[PoC][IR] Generalize interleave/deinterleave intrinsics to factors > 2

[luke]

Summary

This replaces the @llvm.experimental.vector.interleave2
and @llvm.experimental.vector.deinterleave2 intrinsics with the more
general @llvm.experimental.vector.interleave
@llvm.experimental.vector.deinterleave intrinsics that can
interleave/deinterleave an arbitrary number of lanes.

This also extends the vector_interleave/vector_deinterleave SelectionDAG
nodes to match.

Rather than creating N different intrinsics for
@llvm.experimental.vector.interleaveN, this changes the type to accept a
variadic number of arguments, which determines the interleave factor.
Conversely, the interleave factor for the deinterleave intrinsics is
determined by the number of return types.

This does not add support for code generation for factors > 2 yet, which
will be added in a later patch.

[luke]

llvm/docs/LangRef.rst

17791

Even though there is really only overloaded type in this intrinsic, I've suffixed the result type as well to disambiguate the various interleave factors:
e.g. a deinterleave of <vscale x 8 x i32> could either decompose to 2 x <vscale x 4 x i32> or 4 x <vscale x 2 x i32>, and we need separate declarations for them.

[luke]

Update ISDOpcodes documentation and fix integer conversion

[luke]

llvm/include/llvm/IR/Intrinsics.td

2120–2128

This is the main disadvantage of using just one intrinsic to represent all factors: We have to use variadic arguments which complicates the type signature, and we need to do the verification ourselves in Verifier.cpp.

I also considered just creating separate intrinsics for each interleave factor, but didn't like the duplication that would be required in Legalise*Types.cpp/SelectionDAGBuilder.cpp.

[luke]

Fix deinterleave mask on fixed length vectors with NF>2

[luke]

Add tests for fixed length vectors on RISC-V

[luke]

llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll

371

I was aiming to improve the generated code for deinterleaves in a follow up patch, but can do it in this patch if preferred.
I would have expected it to have loaded a gather mask from memory here like in the interleave case.

[paulwalker-arm]

llvm/include/llvm/IR/Intrinsics.td

2120–2128

I don't like this change because I feel it makes the intrinsics cumbersome to work with due to them being so open-ended when compare to the current form.

That said, based on the rational I don't think the change is necessary because when designing the initial support we concluded there was no need for the instrinsics and ISD nodes to follow the same interface and in fact good reasons for them to differ. This means it's perfectly acceptable to add more intrinsics (i.e. int_experimental_vector_interleave3, int_experimental_vector_interleave4...) that all lower to the same ISD node. This is why the intrinsic is numbered and the ISD is not.

llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll

405

This is not how the intrinsic will be written because the overloaded types is now a struct. You can see this by passing the test files through opt where you'll see the function name will be llvm.experimental.vector.deinterleave.sl_v2i64v2i64v2i64s.v6i64.

[luke]

llvm/include/llvm/IR/Intrinsics.td

2120–2128

Thanks for the review. I’m not very strongly opinionated on this, and would be happy to rework this to use separate distinct intrinsics.

In RISC-V the maximum number of interleaving fields in a load/store is 8, so as long as we have up to interleave8/deinterleave8 that should be fine. Does adding those intrinsics sound like a good way forward?

llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll

405

Thanks, that explains a lot of what I was seeing. Shouldn’t be a worry any more though if we rework the intrinsic

[paulwalker-arm]

llvm/include/llvm/IR/Intrinsics.td

2120–2128

That would be consistent with the current design but the answer really depends on whether such intrinsics will actually be used. This is why for AArch64 we've started with the 2-way variant only. This allows us to teach loop vectorise how to use them, along with implementing any necessary combines etc.., and thus understand the pitfalls before moving on to other interleaving factors.

[luke]

llvm/include/llvm/IR/Intrinsics.td

2120–2128

One thing I've ran into in D145495 is how you can get non-power-of-two element counts in your types like nxv6i32 quite easily with other factors, which need a little bit of attention since they aren't valid MVTs.

[paulwalker-arm]

llvm/include/llvm/IR/Intrinsics.td

2120–2128

You likely want to use EVTs during the early stages of code generation. Once type legalisation has been carried out, I'd expect MVTs to then be sufficient.

[luke]

llvm/include/llvm/IR/Intrinsics.td

2120–2128

The snag with using EVTs (IIUC) is that we end up introducing illegal types during the LegalizeDAG phase, which throws an assertion.

For the ISD node
t8: nxv2i32,nxv2i32,nxv2i32 = vector_interleave t2, t4, t6
t2,t4 and t6 already come in as legal nxv2i32 types.

When vector_interleave is then lowered during LegalizeDAG, if we just use EVTs and generate the "logical" nxv6i32 type then we emit:
t38: nxv6i32 = RISCVISD::VRGATHEREI16_VV_VL t24, t34, undef:nxv6i32, t36, Register:i64 $x0

Which is now illegal, and asserts at LegalizeDAG.cpp:975.
I presume the design of LegalizeDAG is such that it relies on LegalizeTypes to make sure the types are legal coming in, and presumes that any further legalisation/target lowering will preserve the types.

[craig.topper]

@luke are you still working on this?

[luke]

In D145485#4451085, @craig.topper wrote:

@luke are you still working on this?

Not actively. Is there interest in this now that D145163 is landed? I think the design of the intrinsics in this patch need reworked to be explicit rather than open ended

[luke]

Marking this as abandoned since I'm not actively working on this anymore, but it would be still good to see this someday

A potential design for the intrinsics could be something like:

llvm
def int_experimental_vector_interleave2   : DefaultAttrsIntrinsic<[LLVMNTimesElts<0, 2>],
                                                                  [llvm_anyvector_ty,
                                                                   LLVMMatchType<0>],
                                                                  [IntrNoMem]>;

def int_experimental_vector_interleave3   : DefaultAttrsIntrinsic<[LLVMNTimesElts<0, 3>],
                                                                  [llvm_anyvector_ty,
                                                                   LLVMMatchType<0>,
                                                                   LLVMMatchType<0>],
                                                                  [IntrNoMem]>;

def int_experimental_vector_deinterleave2 : DefaultAttrsIntrinsic<[llvm_anyvector_ty<0>,
                                                                   LLVMMatchType<0>],
                                                                  [LLVMNTimesElts<0, 2>],
                                                                  [IntrNoMem]>;

def int_experimental_vector_deinterleave3   : DefaultAttrsIntrinsic<[llvm_anyvector_ty,
                                                                     LLVMMatchType<0>,
                                                                     LLVMMatchType<0>],
                                                                     [LLVMNTimesElts<0, 3>],
                                                                    [IntrNoMem]>;

Where LLVMNTimesElts<I, N> is a descriptor for vectors that have N times as many elements as the I'th argument

llvm/docs/LangRef.rst

 recommended way to express reverse operations for fixed-width vectors is still
 to use a shufflevector, as that may allow for more optimization opportunities.
 
 Arguments:
 """"""""""
 
 The argument to this intrinsic must be a vector.
 
-'``llvm.experimental.vector.deinterleave2``' Intrinsic
+'``llvm.experimental.vector.deinterleave``' Intrinsic
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
 Syntax:
 """""""
 This is an overloaded intrinsic.
 
 ::
 
-      declare {<2 x double>, <2 x double>} @llvm.experimental.vector.deinterleave2.v4f64(<4 x double> %vec1)
-      declare {<vscale x 4 x i32>, <vscale x 4 x i32>}  @llvm.experimental.vector.deinterleave2.nxv8i32(<vscale x 8 x i32> %vec1)
+      declare {<2 x double>, <2 x double>} @llvm.experimental.vector.deinterleave.v2f64.v4f64(<4 x double> %vec1)
+      declare {<vscale x 4 x i32>, <vscale x 4 x i32>}  @llvm.experimental.vector.deinterleave.nxv4i32.nxv8i32(<vscale x 8 x i32> %vec1)
+      declare {<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>}  @llvm.experimental.vector.deinterleave.nxv2i16.nxv8i16(<vscale x 8 x i32> %vec1)
 
 Overview:
 """""""""
 
-The '``llvm.experimental.vector.deinterleave2``' intrinsic constructs two
-vectors by deinterleaving the even and odd lanes of the input vector.
+The '``llvm.experimental.vector.deinterleave``' intrinsic constructs two or more
+vectors by deinterleaving alternating lanes of the input vector.
 
 This intrinsic works for both fixed and scalable vectors. While this intrinsic
 supports all vector types the recommended way to express this operation for
 fixed-width vectors is still to use a shufflevector, as that may allow for more
 optimization opportunities.
 
 For example:
 
 .. code-block:: text
 
-  {<2 x i64>, <2 x i64>} llvm.experimental.vector.deinterleave2.v4i64(<4 x i64> <i64 0, i64 1, i64 2, i64 3>); ==> {<2 x i64> <i64 0, i64 2>, <2 x i64> <i64 1, i64 3>}
+  {<2 x i64>, <2 x i64>} llvm.experimental.vector.deinterleave.v2i64.v4i64(<4 x i64> <i64 0, i64 1, i64 2, i64 3>); ==> {<2 x i64> <i64 0, i64 2>, <2 x i64> <i64 1, i64 3>}
 
 Arguments:
 """"""""""
 
+The result types must all be the same type.
 The argument is a vector whose type corresponds to the logical concatenation of
-the two result types.
+the result types.
+The number of lanes to deinterleave is determined by the number of result types.
 
-'``llvm.experimental.vector.interleave2``' Intrinsic
+'``llvm.experimental.vector.interleave``' Intrinsic
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
 Syntax:
 """""""
 This is an overloaded intrinsic.
 
 ::
 
-      declare <4 x double> @llvm.experimental.vector.interleave2.v4f64(<2 x double> %vec1, <2 x double> %vec2)
-      declare <vscale x 8 x i32> @llvm.experimental.vector.interleave2.nxv8i32(<vscale x 4 x i32> %vec1, <vscale x 4 x i32> %vec2)
+      declare <4 x double> @llvm.experimental.vector.interleave.v4f64.v2f64(...)
+      declare <vscale x 8 x i32> @llvm.experimental.vector.interleave.nxv8i32.nxv4i32(...)
+      declare <vscale x 8 x i32> @llvm.experimental.vector.interleave.nxv8i32.nxv2i32(...)
 
 Overview:
 """""""""
 
-The '``llvm.experimental.vector.interleave2``' intrinsic constructs a vector
-by interleaving two input vectors.
+The '``llvm.experimental.vector.interleave``' intrinsic constructs a vector
+by interleaving two or more input vectors.
 
 This intrinsic works for both fixed and scalable vectors. While this intrinsic
 supports all vector types the recommended way to express this operation for
 fixed-width vectors is still to use a shufflevector, as that may allow for more
 optimization opportunities.
 
 For example:
 
 .. code-block:: text
 
-   <4 x i64> llvm.experimental.vector.interleave2.v4i64(<2 x i64> <i64 0, i64 2>, <2 x i64> <i64 1, i64 3>); ==> <4 x i64> <i64 0, i64 1, i64 2, i64 3>
+   <4 x i64> llvm.experimental.vector.interleave.v4i64.v2i64(<2 x i64> <i64 0, i64 2>, <2 x i64> <i64 1, i64 3>); ==> <4 x i64> <i64 0, i64 1, i64 2, i64 3>
 
 Arguments:
 """"""""""
-Both arguments must be vectors of the same type whereby their logical
+All arguments must be vectors of the same type whereby their logical
 concatenation matches the result type.
+The number of lanes to interleave is determined by the number of arguments.
 
 '``llvm.experimental.vector.splice``' Intrinsic
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
 Syntax:
 """""""
 This is an overloaded intrinsic.
 

llvm/include/llvm/CodeGen/ISDOpcodes.h

enum NodeType {
   /// condition cannot be determined statically but is false at runtime, then
   /// the result vector is undefined. The IDX parameter must be a vector index
   /// constant type, which for most targets will be an integer pointer type.
   ///
   /// This operation supports extracting a fixed-width vector from a scalable
   /// vector, but not the other way around.
   EXTRACT_SUBVECTOR,
 
-  /// VECTOR_DEINTERLEAVE(VEC1, VEC2) - Returns two vectors with all input and
-  /// output vectors having the same type. The first output contains the even
-  /// indices from CONCAT_VECTORS(VEC1, VEC2), with the second output
-  /// containing the odd indices. The relative order of elements within an
-  /// output match that of the concatenated input.
+  /// VECTOR_DEINTERLEAVE(VEC1, VEC2, ...) - Returns N vectors with all input
+  /// and output vectors having the same type. The first output contains the
+  /// first indices from CONCAT_VECTORS(VEC1, VEC2, ...), with the second output
+  /// containing the second indices, etc. The relative order of elements within
+  /// an output match that of the concatenated input.
   VECTOR_DEINTERLEAVE,
 
-  /// VECTOR_INTERLEAVE(VEC1, VEC2) - Returns two vectors with all input and
-  /// output vectors having the same type. The first output contains the
-  /// result of interleaving the low half of CONCAT_VECTORS(VEC1, VEC2), with
-  /// the second output containing the result of interleaving the high half.
+  /// VECTOR_INTERLEAVE(VEC1, VEC2, ...) - Returns N vectors with all input and
+  /// output vectors having the same type. The first output contains the result
+  /// of interleaving the first X elements of CONCAT_VECTORS(VEC1, VEC2, ...),
+  /// with the second output containing the result of interleaving the next X
+  /// elements, and so on, where X is the number of elements in each input
+  /// vector.
   VECTOR_INTERLEAVE,
 
   /// VECTOR_REVERSE(VECTOR) - Returns a vector, of the same type as VECTOR,
   /// whose elements are shuffled using the following algorithm:
   ///   RESULT[i] = VECTOR[VECTOR.ElementCount - 1 - i]
   VECTOR_REVERSE,
 
   /// VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as

llvm/include/llvm/IR/Intrinsics.td

 def int_vector_insert : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
                                               [LLVMMatchType<0>, llvm_anyvector_ty, llvm_i64_ty],
                                               [IntrNoMem, IntrSpeculatable, ImmArg<ArgIndex<2>>]>;
 
 def int_vector_extract : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
                                                [llvm_anyvector_ty, llvm_i64_ty],
                                                [IntrNoMem, IntrSpeculatable, ImmArg<ArgIndex<1>>]>;
 
-
-def int_experimental_vector_interleave2   : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
-                                                                  [LLVMHalfElementsVectorType<0>,
-                                                                   LLVMHalfElementsVectorType<0>],
+def int_experimental_vector_interleave   : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
+                                                                  [llvm_vararg_ty],
                                                                   [IntrNoMem]>;
 
-def int_experimental_vector_deinterleave2 : DefaultAttrsIntrinsic<[LLVMHalfElementsVectorType<0>,
-                                                                   LLVMHalfElementsVectorType<0>],
-                                                                  [llvm_anyvector_ty],
-                                                                  [IntrNoMem]>;
+def int_experimental_vector_deinterleave : DefaultAttrsIntrinsic<[llvm_any_ty],
 
 //===----------------- Pointer Authentication Intrinsics ------------------===//
 //
 
 // Sign an unauthenticated pointer using the specified key and discriminator,
 // passed in that order.
 // Returns the first argument, with some known bits replaced with a signature.
 def int_ptrauth_sign :

llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_SPLICE(SDNode *N) {
   SDValue V1 = GetPromotedInteger(N->getOperand(1));
   EVT OutVT = V0.getValueType();
 
   return DAG.getNode(ISD::VECTOR_SPLICE, dl, OutVT, V0, V1, N->getOperand(2));
 }
 
 SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_DEINTERLEAVE(SDNode *N) {
   SDLoc dl(N);
+  unsigned NF = N->getNumOperands();
 
-  SDValue V0 = GetPromotedInteger(N->getOperand(0));
-  SDValue V1 = GetPromotedInteger(N->getOperand(1));
-  EVT ResVT = V0.getValueType();
-  SDValue Res = DAG.getNode(ISD::VECTOR_DEINTERLEAVE, dl,
-                            DAG.getVTList(ResVT, ResVT), V0, V1);
-  SetPromotedInteger(SDValue(N, 0), Res.getValue(0));
-  SetPromotedInteger(SDValue(N, 1), Res.getValue(1));
+  SmallVector<SDValue, 8> Ops;
+  for (unsigned i = 0; i < NF; i++)
+    Ops.push_back(GetPromotedInteger(N->getOperand(i)));
+
+  SmallVector<EVT, 8> ResVTs(NF, Ops[0].getValueType());
+  SDValue Res =
+      DAG.getNode(ISD::VECTOR_DEINTERLEAVE, dl, DAG.getVTList(ResVTs), Ops);
+
+  for (unsigned i = 0; i < NF; i++)
+    SetPromotedInteger(SDValue(N, i), Res.getValue(i));
   return SDValue();
 }
 
 SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_INTERLEAVE(SDNode *N) {
   SDLoc dl(N);
+  unsigned NF = N->getNumOperands();
 
-  SDValue V0 = GetPromotedInteger(N->getOperand(0));
-  SDValue V1 = GetPromotedInteger(N->getOperand(1));
+  SmallVector<SDValue, 8> Ops;
+  for (unsigned i = 0; i < NF; i++)
+    Ops.push_back(GetPromotedInteger(N->getOperand(i)));
+
+  SmallVector<EVT, 8> ResVTs(NF, Ops[0].getValueType());
+  SDValue Res =
+      DAG.getNode(ISD::VECTOR_INTERLEAVE, dl, DAG.getVTList(ResVTs), Ops);
 
-  EVT ResVT = V0.getValueType();
-  SDValue Res = DAG.getNode(ISD::VECTOR_INTERLEAVE, dl,
-                            DAG.getVTList(ResVT, ResVT), V0, V1);
-  SetPromotedInteger(SDValue(N, 0), Res.getValue(0));
-  SetPromotedInteger(SDValue(N, 1), Res.getValue(1));
+  for (unsigned i = 0; i < NF; i++)
+    SetPromotedInteger(SDValue(N, i), Res.getValue(i));
   return SDValue();
 }
 
 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_SUBVECTOR(SDNode *N) {
 
   EVT OutVT = N->getValueType(0);
   EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
   assert(NOutVT.isVector() && "This type must be promoted to a vector type");

llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

void DAGTypeLegalizer::SplitVecRes_VECTOR_DEINTERLEAVE(SDNode *N) {
   SDValue ResHi = DAG.getNode(ISD::VECTOR_DEINTERLEAVE, DL,
                               DAG.getVTList(VT, VT), Op1Lo, Op1Hi);
 
   SetSplitVector(SDValue(N, 0), ResLo.getValue(0), ResHi.getValue(0));
   SetSplitVector(SDValue(N, 1), ResLo.getValue(1), ResHi.getValue(1));
 }
 
 void DAGTypeLegalizer::SplitVecRes_VECTOR_INTERLEAVE(SDNode *N) {
-  SDValue Op0Lo, Op0Hi, Op1Lo, Op1Hi;
-  GetSplitVector(N->getOperand(0), Op0Lo, Op0Hi);
-  GetSplitVector(N->getOperand(1), Op1Lo, Op1Hi);
-  EVT VT = Op0Lo.getValueType();
+  unsigned IF = N->getNumOperands();
+  SmallVector<SDValue, 8> Los, His;
+  for (unsigned i = 0; i < IF; i++) {
+    SDValue Lo, Hi;
+    GetSplitVector(N->getOperand(i), Lo, Hi);
+    Los.push_back(Lo);
+    His.push_back(Hi);
+  }
+
+  SmallVector<EVT, 8> VTs(IF, Los[0].getValueType());
   SDLoc DL(N);
-  SDValue Res[] = {DAG.getNode(ISD::VECTOR_INTERLEAVE, DL,
-                               DAG.getVTList(VT, VT), Op0Lo, Op1Lo),
-                   DAG.getNode(ISD::VECTOR_INTERLEAVE, DL,
-                               DAG.getVTList(VT, VT), Op0Hi, Op1Hi)};
 
-  SetSplitVector(SDValue(N, 0), Res[0].getValue(0), Res[0].getValue(1));
-  SetSplitVector(SDValue(N, 1), Res[1].getValue(0), Res[1].getValue(1));
+  SDValue LoRes = DAG.getNode(ISD::VECTOR_INTERLEAVE, DL, VTs, Los);
+  SDValue HiRes = DAG.getNode(ISD::VECTOR_INTERLEAVE, DL, VTs, His);
+
+  SmallVector<SDValue, 16> CombinedRes;
+  for (unsigned i = 0; i < IF; i++)
+    CombinedRes.push_back(LoRes.getValue(i));
+  for (unsigned i = 0; i < IF; i++)
+    CombinedRes.push_back(HiRes.getValue(i));
+
+  for (int i = IF - 1; i >= 0; i--) {
+    SDValue Hi = CombinedRes.pop_back_val();
+    SDValue Lo = CombinedRes.pop_back_val();
+    SetSplitVector(SDValue(N, i), Lo, Hi);
+  }
 }
 
 //===----------------------------------------------------------------------===//
 //  Operand Vector Splitting
 //===----------------------------------------------------------------------===//
 
 /// This method is called when the specified operand of the specified node is
 /// found to need vector splitting. At this point, all of the result types of

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

case Intrinsic::experimental_vector_reverse:
     visitVectorReverse(I);
     return;
   case Intrinsic::experimental_vector_splice:
     visitVectorSplice(I);
     return;
   case Intrinsic::callbr_landingpad:
     visitCallBrLandingPad(I);
     return;
-  case Intrinsic::experimental_vector_interleave2:
+  case Intrinsic::experimental_vector_interleave:
     visitVectorInterleave(I);
     return;
-  case Intrinsic::experimental_vector_deinterleave2:
+  case Intrinsic::experimental_vector_deinterleave:
     visitVectorDeinterleave(I);
     return;
   }
 }
 
 void SelectionDAGBuilder::visitConstrainedFPIntrinsic(
     const ConstrainedFPIntrinsic &FPI) {
   SDLoc sdl = getCurSDLoc();
for (unsigned i = 0; i != NumElts; ++i)
     Mask.push_back(NumElts - 1 - i);
 
   setValue(&I, DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), Mask));
 }
 
 void SelectionDAGBuilder::visitVectorDeinterleave(const CallInst &I) {
   auto DL = getCurSDLoc();
   SDValue InVec = getValue(I.getOperand(0));
+  unsigned IF = cast<StructType>(I.getType())->getNumElements();
+
+  EVT InVT = InVec.getValueType();
   EVT OutVT =
-      InVec.getValueType().getHalfNumVectorElementsVT(*DAG.getContext());
+      EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(),
+                       InVT.getVectorElementCount().divideCoefficientBy(IF));
 
   unsigned OutNumElts = OutVT.getVectorMinNumElements();
 
-  // ISD Node needs the input vectors split into two equal parts
-  SDValue Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OutVT, InVec,
-                           DAG.getVectorIdxConstant(0, DL));
-  SDValue Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OutVT, InVec,
-                           DAG.getVectorIdxConstant(OutNumElts, DL));
-
   // Use VECTOR_SHUFFLE for fixed-length vectors to benefit from existing
   // legalisation and combines.
   if (OutVT.isFixedLengthVector()) {
-    SDValue Even = DAG.getVectorShuffle(OutVT, DL, Lo, Hi,
-                                        createStrideMask(0, 2, OutNumElts));
-    SDValue Odd = DAG.getVectorShuffle(OutVT, DL, Lo, Hi,
-                                       createStrideMask(1, 2, OutNumElts));
-    SDValue Res = DAG.getMergeValues({Even, Odd}, getCurSDLoc());
+    SDValue Res;
+    SmallVector<SDValue, 8> OutVecs;
+
+    // Get the ceiling of a half length vector
+    EVT HalfInVT = InVT;
+    if (!HalfInVT.getVectorElementCount().isKnownEven())
+      HalfInVT = EVT::getVectorVT(
+          *DAG.getContext(), HalfInVT.getVectorElementType(),
+          HalfInVT.getVectorElementCount().getWithIncrement(1));
+    HalfInVT = HalfInVT.getHalfNumVectorElementsVT(*DAG.getContext());
+
+    unsigned HalfNumElts = HalfInVT.getVectorMinNumElements();
+
+    // Rather than (shuffle InVec, undef, Mask), do
+    // (shuffle InVecLo, InVecHi, Mask) since targets rely on the latter pattern
+    // to detect fixed-length vector interleaves
+    SDValue Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfInVT, InVec,
+                             DAG.getVectorIdxConstant(0, DL));
+    SDValue Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfInVT, InVec,
+                             DAG.getVectorIdxConstant(HalfNumElts, DL));
+    for (unsigned i = 0; i < IF; i++) {
+      auto Mask = createStrideMask(i, IF, HalfInVT.getVectorMinNumElements());
+      // Set mask elements might be outside the combined range to undef
+      for (unsigned j = 0; j < Mask.size(); j++) {
+  if (Mask[j] >= (int)HalfInVT.getVectorMinNumElements() * 2)
+    Mask[j] = -1;
+      } 
+      SDValue Deinterleaved = DAG.getVectorShuffle(HalfInVT, DL, Lo, Hi, Mask);
+      Deinterleaved =
+          DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OutVT, Deinterleaved,
+                      DAG.getVectorIdxConstant(0, DL));
+      OutVecs.push_back(Deinterleaved);
+    }
+    Res = DAG.getMergeValues(OutVecs, getCurSDLoc());
     setValue(&I, Res);
     return;
   }
 
-  SDValue Res = DAG.getNode(ISD::VECTOR_DEINTERLEAVE, DL,
-                            DAG.getVTList(OutVT, OutVT), Lo, Hi);
+  // ISD Node needs the input vectors split into IF equal parts
+  SmallVector<SDValue, 8> Ops;
+  for (unsigned i = 0; i < IF; i++) {
+    Ops.push_back(DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OutVT, InVec,
+                              DAG.getVectorIdxConstant(OutNumElts * i, DL)));
+  }
+
+  SmallVector<EVT, 8> VTs(IF, OutVT);
+  SDValue Res =
+      DAG.getNode(ISD::VECTOR_DEINTERLEAVE, DL, DAG.getVTList(VTs), Ops);
   setValue(&I, Res);
   return;
 }
 
 void SelectionDAGBuilder::visitVectorInterleave(const CallInst &I) {
   auto DL = getCurSDLoc();
   EVT InVT = getValue(I.getOperand(0)).getValueType();
-  SDValue InVec0 = getValue(I.getOperand(0));
-  SDValue InVec1 = getValue(I.getOperand(1));
   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
   EVT OutVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
 
+  unsigned IF = I.getNumOperands() - 1;
+  SmallVector<SDValue, 8> Ops;
+  for (unsigned i = 0; i < IF; i++)
+    Ops.push_back(getValue(I.getOperand(i)));
+
   // Use VECTOR_SHUFFLE for fixed-length vectors to benefit from existing
   // legalisation and combines.
   if (OutVT.isFixedLengthVector()) {
     unsigned NumElts = InVT.getVectorMinNumElements();
-    SDValue V = DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, InVec0, InVec1);
+    SDValue V = DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, Ops);
     setValue(&I, DAG.getVectorShuffle(OutVT, DL, V, DAG.getUNDEF(OutVT),
-                                      createInterleaveMask(NumElts, 2)));
+                                      createInterleaveMask(NumElts, IF)));
     return;
   }
 
-  SDValue Res = DAG.getNode(ISD::VECTOR_INTERLEAVE, DL,
-                            DAG.getVTList(InVT, InVT), InVec0, InVec1);
-  Res = DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, Res.getValue(0),
-                    Res.getValue(1));
+  SmallVector<EVT, 8> VTs(IF, InVT);
+  SDValue Res = DAG.getNode(ISD::VECTOR_INTERLEAVE, DL, VTs, Ops);
+  SmallVector<SDValue, 8> Vals;
+  for (unsigned i = 0; i < IF; i++)
+    Vals.push_back(Res.getValue(i));
+
+  Res = DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, Vals);
   setValue(&I, Res);
   return;
 }
 
 void SelectionDAGBuilder::visitFreeze(const FreezeInst &I) {
   SmallVector<EVT, 4> ValueVTs;
   ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(), I.getType(),
                   ValueVTs);

llvm/lib/IR/Verifier.cpp

case Intrinsic::vector_extract: {
     // overrun the parent vector.
     if (VecEC.isScalable() == ResultEC.isScalable()) {
       Check(IdxN < VecEC.getKnownMinValue() &&
                 IdxN + ResultEC.getKnownMinValue() <= VecEC.getKnownMinValue(),
             "vector_extract would overrun.");
     }
     break;
   }
+  case Intrinsic::experimental_vector_interleave: {
+    unsigned IF = Call.getNumOperands() - 1;
+    Check(IF >= 2, "vector.interleave must have two or more input vectors",
+          &Call);
+
+    VectorType *ResultTy = cast<VectorType>(Call.getType());
+    ElementCount ResultCount = ResultTy->getElementCount();
+    Check(ResultCount.isKnownMultipleOf(IF),
+          "vector.interleave result must be a vector with a count that is a "
+          "multiple of the number of operands.",
+          &Call);
+    VectorType *OperandTy = VectorType::get(
+        ResultTy->getElementType(), ResultCount.divideCoefficientBy(IF));
+    for (unsigned i = 0; i < IF; i++) {
+      if (Call.getArgOperand(i)->getType() != OperandTy) {
+        Check(false,
+              "vector.interleave operand types don't match up with the result.",
+              &Call);
+        break;
+      }
+    }
+    break;
+  }
+  case Intrinsic::experimental_vector_deinterleave: {
+    auto *ResultTy = dyn_cast<StructType>(Call.getType());
+    if (!ResultTy) {
+      Check(false, "vector.deinterleave result must be a struct type.", &Call);
+      break;
+    }
+
+    unsigned IF = ResultTy->getNumElements();
+    Check(IF >= 2, "vector.deterleave must have two or more result vectors",
+          &Call);
+
+    VectorType *InputTy = cast<VectorType>(Call.getOperand(0)->getType());
+
+    ElementCount InputCount = InputTy->getElementCount();
+    Check(InputCount.isKnownMultipleOf(IF),
+          "vector.deinterleave input must be a vector with a count that is a "
+          "multiple of the number of result vectors.",
+          &Call);
+    VectorType *OutputVecTy = VectorType::get(
+        InputTy->getElementType(), InputCount.divideCoefficientBy(IF));
+    for (unsigned i = 0; i < IF; i++) {
+      if (ResultTy->getTypeAtIndex(i) != OutputVecTy) {
+        Check(false,
+              "vector.deinterleave result types don't match up with the input.",
+              &Call);
+        break;
+      }
+    }
+    break;
+  }
   case Intrinsic::experimental_noalias_scope_decl: {
     NoAliasScopeDecls.push_back(cast<IntrinsicInst>(&Call));
     break;
   }
   case Intrinsic::preserve_array_access_index:
   case Intrinsic::preserve_struct_access_index:
   case Intrinsic::aarch64_ldaxr:
   case Intrinsic::aarch64_ldxr:

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

 
 SDValue
 AArch64TargetLowering::LowerVECTOR_DEINTERLEAVE(SDValue Op,
                                                 SelectionDAG &DAG) const {
   SDLoc DL(Op);
   EVT OpVT = Op.getValueType();
   assert(OpVT.isScalableVector() &&
          "Expected scalable vector in LowerVECTOR_DEINTERLEAVE.");
+  assert(Op.getNumOperands() == 2 &&
+         "Deinterleaves of more than 2 vectors not supported yet");
   SDValue Even = DAG.getNode(AArch64ISD::UZP1, DL, OpVT, Op.getOperand(0),
                              Op.getOperand(1));
   SDValue Odd = DAG.getNode(AArch64ISD::UZP2, DL, OpVT, Op.getOperand(0),
                             Op.getOperand(1));
   return DAG.getMergeValues({Even, Odd}, DL);
 }
 
 SDValue AArch64TargetLowering::LowerVECTOR_INTERLEAVE(SDValue Op,
                                                       SelectionDAG &DAG) const {
   SDLoc DL(Op);
   EVT OpVT = Op.getValueType();
   assert(OpVT.isScalableVector() &&
          "Expected scalable vector in LowerVECTOR_INTERLEAVE.");
+  assert(Op.getNumOperands() == 2 &&
+         "Interleaves of more than 2 vectors not supported yet");
 
   SDValue Lo = DAG.getNode(AArch64ISD::ZIP1, DL, OpVT, Op.getOperand(0),
                            Op.getOperand(1));
   SDValue Hi = DAG.getNode(AArch64ISD::ZIP2, DL, OpVT, Op.getOperand(0),
                            Op.getOperand(1));
   return DAG.getMergeValues({Lo, Hi}, DL);
 }
 

llvm/test/CodeGen/AArch64/fixed-vector-deinterleave.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=aarch64-linux-gnu | FileCheck %s
 
 define {<2 x half>, <2 x half>} @vector_deinterleave_v2f16_v4f16(<4 x half> %vec) {
 ; CHECK-LABEL: vector_deinterleave_v2f16_v4f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; CHECK-NEXT:    dup v2.2s, v0.s[1]
 ; CHECK-NEXT:    mov v1.16b, v2.16b
 ; CHECK-NEXT:    mov v1.h[0], v0.h[1]
 ; CHECK-NEXT:    mov v0.h[1], v2.h[0]
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 killed $q1
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
 ; CHECK-NEXT:    ret
-  %retval = call {<2 x half>, <2 x half>} @llvm.experimental.vector.deinterleave2.v4f16(<4 x half> %vec)
+  %retval = call {<2 x half>, <2 x half>} @llvm.experimental.vector.deinterleave.v2f16.v4f16(<4 x half> %vec)
   ret {<2 x half>, <2 x half>}   %retval
 }
 
 define {<4 x half>, <4 x half>} @vector_deinterleave_v4f16_v8f16(<8 x half> %vec) {
 ; CHECK-LABEL: vector_deinterleave_v4f16_v8f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
 ; CHECK-NEXT:    uzp1 v2.4h, v0.4h, v1.4h
 ; CHECK-NEXT:    uzp2 v1.4h, v0.4h, v1.4h
 ; CHECK-NEXT:    fmov d0, d2
 ; CHECK-NEXT:    ret
-  %retval = call {<4 x half>, <4 x half>} @llvm.experimental.vector.deinterleave2.v8f16(<8 x half> %vec)
+  %retval = call {<4 x half>, <4 x half>} @llvm.experimental.vector.deinterleave.v4f16.v8f16(<8 x half> %vec)
   ret {<4 x half>, <4 x half>}   %retval
 }
 
 define {<8 x half>, <8 x half>} @vector_deinterleave_v8f16_v16f16(<16 x half> %vec) {
 ; CHECK-LABEL: vector_deinterleave_v8f16_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    uzp1 v2.8h, v0.8h, v1.8h
 ; CHECK-NEXT:    uzp2 v1.8h, v0.8h, v1.8h
 ; CHECK-NEXT:    mov v0.16b, v2.16b
 ; CHECK-NEXT:    ret
-  %retval = call {<8 x half>, <8 x half>} @llvm.experimental.vector.deinterleave2.v16f16(<16 x half> %vec)
+  %retval = call {<8 x half>, <8 x half>} @llvm.experimental.vector.deinterleave.v8f16.v16f16(<16 x half> %vec)
   ret {<8 x half>, <8 x half>}   %retval
 }
 
 define {<2 x float>, <2 x float>} @vector_deinterleave_v2f32_v4f32(<4 x float> %vec) {
 ; CHECK-LABEL: vector_deinterleave_v2f32_v4f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
 ; CHECK-NEXT:    zip1 v2.2s, v0.2s, v1.2s
 ; CHECK-NEXT:    zip2 v1.2s, v0.2s, v1.2s
 ; CHECK-NEXT:    fmov d0, d2
 ; CHECK-NEXT:    ret
-  %retval = call {<2 x float>, <2 x float>} @llvm.experimental.vector.deinterleave2.v4f32(<4 x float> %vec)
+  %retval = call {<2 x float>, <2 x float>} @llvm.experimental.vector.deinterleave.v2f32.v4f32(<4 x float> %vec)
   ret {<2 x float>, <2 x float>}   %retval
 }
 
 define {<4 x float>, <4 x float>} @vector_deinterleave_v4f32_v8f32(<8 x float> %vec) {
 ; CHECK-LABEL: vector_deinterleave_v4f32_v8f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    uzp1 v2.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    uzp2 v1.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    mov v0.16b, v2.16b
 ; CHECK-NEXT:    ret
-  %retval = call {<4 x float>, <4 x float>} @llvm.experimental.vector.deinterleave2.v8f32(<8 x float> %vec)
+  %retval = call {<4 x float>, <4 x float>} @llvm.experimental.vector.deinterleave.v4f32.v8f32(<8 x float> %vec)
 ret  {<4 x float>, <4 x float>}   %retval
 }
 
 define {<2 x double>, <2 x double>} @vector_deinterleave_v2f64_v4f64(<4 x double> %vec) {
 ; CHECK-LABEL: vector_deinterleave_v2f64_v4f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    zip1 v2.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    zip2 v1.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    mov v0.16b, v2.16b
 ; CHECK-NEXT:    ret
-  %retval = call {<2 x double>, <2 x double>} @llvm.experimental.vector.deinterleave2.v4f64(<4 x double> %vec)
+  %retval = call {<2 x double>, <2 x double>} @llvm.experimental.vector.deinterleave.v2f64.v4f64(<4 x double> %vec)
   ret {<2 x double>, <2 x double>}   %retval
 }
 
 ; Integers
 
 define {<16 x i8>, <16 x i8>} @vector_deinterleave_v16i8_v32i8(<32 x i8> %vec) {
 ; CHECK-LABEL: vector_deinterleave_v16i8_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    uzp1 v2.16b, v0.16b, v1.16b
 ; CHECK-NEXT:    uzp2 v1.16b, v0.16b, v1.16b
 ; CHECK-NEXT:    mov v0.16b, v2.16b
 ; CHECK-NEXT:    ret
-  %retval = call {<16 x i8>, <16 x i8>} @llvm.experimental.vector.deinterleave2.v32i8(<32 x i8> %vec)
+  %retval = call {<16 x i8>, <16 x i8>} @llvm.experimental.vector.deinterleave.v16i8.v32i8(<32 x i8> %vec)
   ret {<16 x i8>, <16 x i8>}   %retval
 }
 
 define {<8 x i16>, <8 x i16>} @vector_deinterleave_v8i16_v16i16(<16 x i16> %vec) {
 ; CHECK-LABEL: vector_deinterleave_v8i16_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    uzp1 v2.8h, v0.8h, v1.8h
 ; CHECK-NEXT:    uzp2 v1.8h, v0.8h, v1.8h
 ; CHECK-NEXT:    mov v0.16b, v2.16b
 ; CHECK-NEXT:    ret
-  %retval = call {<8 x i16>, <8 x i16>} @llvm.experimental.vector.deinterleave2.v16i16(<16 x i16> %vec)
+  %retval = call {<8 x i16>, <8 x i16>} @llvm.experimental.vector.deinterleave.v8i16.v16i16(<16 x i16> %vec)
   ret {<8 x i16>, <8 x i16>}   %retval
 }
 
 define {<4 x i32>, <4 x i32>} @vector_deinterleave_v4i32_v8i32(<8 x i32> %vec) {
 ; CHECK-LABEL: vector_deinterleave_v4i32_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    uzp1 v2.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    uzp2 v1.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    mov v0.16b, v2.16b
 ; CHECK-NEXT:    ret
-  %retval = call {<4 x i32>, <4 x i32>} @llvm.experimental.vector.deinterleave2.v8i32(<8 x i32> %vec)
+  %retval = call {<4 x i32>, <4 x i32>} @llvm.experimental.vector.deinterleave.v4i32.v8i32(<8 x i32> %vec)
   ret {<4 x i32>, <4 x i32>}   %retval
 }
 
 define {<2 x i64>, <2 x i64>} @vector_deinterleave_v2i64_v4i64(<4 x i64> %vec) {
 ; CHECK-LABEL: vector_deinterleave_v2i64_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    zip1 v2.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    zip2 v1.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    mov v0.16b, v2.16b
 ; CHECK-NEXT:    ret
-  %retval = call {<2 x i64>, <2 x i64>} @llvm.experimental.vector.deinterleave2.v4i64(<4 x i64> %vec)
+  %retval = call {<2 x i64>, <2 x i64>} @llvm.experimental.vector.deinterleave.v2i64.v4i64(<4 x i64> %vec)
   ret {<2 x i64>, <2 x i64>}   %retval
 }
 
 
 ; Floating declarations
-declare {<2 x half>,<2 x half>} @llvm.experimental.vector.deinterleave2.v4f16(<4 x half>)
-declare {<4 x half>, <4 x half>} @llvm.experimental.vector.deinterleave2.v8f16(<8 x half>)
-declare {<2 x float>, <2 x float>} @llvm.experimental.vector.deinterleave2.v4f32(<4 x float>)
-declare {<8 x half>, <8 x half>} @llvm.experimental.vector.deinterleave2.v16f16(<16 x half>)
-declare {<4 x float>, <4 x float>} @llvm.experimental.vector.deinterleave2.v8f32(<8 x float>)
-declare {<2 x double>, <2 x double>} @llvm.experimental.vector.deinterleave2.v4f64(<4 x double>)
+declare {<2 x half>, <2 x half>} @llvm.experimental.vector.deinterleave.v2f16.v4f16(<4 x half>)
+declare {<4 x half>, <4 x half>} @llvm.experimental.vector.deinterleave.v4f16.v8f16(<8 x half>)
+declare {<2 x float>, <2 x float>} @llvm.experimental.vector.deinterleave.v2f32.v4f32(<4 x float>)
+declare {<8 x half>, <8 x half>} @llvm.experimental.vector.deinterleave.v8f16.v16f16(<16 x half>)
+declare {<4 x float>, <4 x float>} @llvm.experimental.vector.deinterleave.v4f32.v8f32(<8 x float>)
+declare {<2 x double>, <2 x double>} @llvm.experimental.vector.deinterleave.v2f64.v4f64(<4 x double>)
 
 ; Integer declarations
-declare {<16 x i8>, <16 x i8>} @llvm.experimental.vector.deinterleave2.v32i8(<32 x i8>)
-declare {<8 x i16>, <8 x i16>} @llvm.experimental.vector.deinterleave2.v16i16(<16 x i16>)
-declare {<4 x i32>, <4 x i32>} @llvm.experimental.vector.deinterleave2.v8i32(<8 x i32>)
-declare {<2 x i64>, <2 x i64>} @llvm.experimental.vector.deinterleave2.v4i64(<4 x i64>)
+declare {<16 x i8>, <16 x i8>} @llvm.experimental.vector.deinterleave.v16i8.v32i8(<32 x i8>)
+declare {<8 x i16>, <8 x i16>} @llvm.experimental.vector.deinterleave.v8i16.v16i16(<16 x i16>)
+declare {<4 x i32>, <4 x i32>} @llvm.experimental.vector.deinterleave.v4i32.v8i32(<8 x i32>)
+declare {<2 x i64>, <2 x i64>} @llvm.experimental.vector.deinterleave.v2i64.v4i64(<4 x i64>)
 

llvm/test/CodeGen/AArch64/fixed-vector-interleave.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=aarch64-linux-gnu | FileCheck %s
 
 define <4 x half> @interleave2_v4f16(<2 x half> %vec0, <2 x half> %vec1) {
 ; CHECK-LABEL: interleave2_v4f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    zip1 v0.4h, v0.4h, v1.4h
 ; CHECK-NEXT:    ret
-  %retval = call <4 x half> @llvm.experimental.vector.interleave2.v4f16(<2 x half> %vec0, <2 x half> %vec1)
+  %retval = call <4 x half>(...) @llvm.experimental.vector.interleave.v4f16.v2f16(<2 x half> %vec0, <2 x half> %vec1)
   ret <4 x half> %retval
 }
 
 define <8 x half> @interleave2_v8f16(<4 x half> %vec0, <4 x half> %vec1) {
 ; CHECK-LABEL: interleave2_v8f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    adrp x8, .LCPI1_0
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $q1
 ; CHECK-NEXT:    mov v0.d[1], v1.d[0]
 ; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI1_0]
 ; CHECK-NEXT:    tbl v0.16b, { v0.16b }, v1.16b
 ; CHECK-NEXT:    ret
-  %retval = call <8 x half> @llvm.experimental.vector.interleave2.v8f16(<4 x half> %vec0, <4 x half> %vec1)
+  %retval = call <8 x half>(...) @llvm.experimental.vector.interleave.v8f16.v4f16(<4 x half> %vec0, <4 x half> %vec1)
   ret <8 x half> %retval
 }
 
 define <16 x half> @interleave2_v16f16(<8 x half> %vec0, <8 x half> %vec1) {
 ; CHECK-LABEL: interleave2_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    zip1 v2.8h, v0.8h, v1.8h
 ; CHECK-NEXT:    zip2 v1.8h, v0.8h, v1.8h
 ; CHECK-NEXT:    mov v0.16b, v2.16b
 ; CHECK-NEXT:    ret
-  %retval = call <16 x half> @llvm.experimental.vector.interleave2.v16f16(<8 x half> %vec0, <8 x half> %vec1)
+  %retval = call <16 x half>(...) @llvm.experimental.vector.interleave.v16f16.v8f16(<8 x half> %vec0, <8 x half> %vec1)
   ret <16 x half> %retval
 }
 
 define <4 x float> @interleave2_v4f32(<2 x float> %vec0, <2 x float> %vec1) {
 ; CHECK-LABEL: interleave2_v4f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $q1
 ; CHECK-NEXT:    mov v0.d[1], v1.d[0]
 ; CHECK-NEXT:    rev64 v1.4s, v0.4s
 ; CHECK-NEXT:    uzp1 v0.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    ret
-  %retval = call <4 x float> @llvm.experimental.vector.interleave2.v4f32(<2 x float> %vec0, <2 x float> %vec1)
+  %retval = call <4 x float>(...) @llvm.experimental.vector.interleave.v4f32.v2f32(<2 x float> %vec0, <2 x float> %vec1)
   ret <4 x float> %retval
 }
 
 define <8 x float> @interleave2_v8f32(<4 x float> %vec0, <4 x float> %vec1) {
 ; CHECK-LABEL: interleave2_v8f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    zip1 v2.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    zip2 v1.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    mov v0.16b, v2.16b
 ; CHECK-NEXT:    ret
-  %retval = call <8 x float> @llvm.experimental.vector.interleave2.v8f32(<4 x float> %vec0, <4 x float> %vec1)
+  %retval = call <8 x float>(...) @llvm.experimental.vector.interleave.v8f32.v4f32(<4 x float> %vec0, <4 x float> %vec1)
   ret <8 x float> %retval
 }
 
 define <4 x double> @interleave2_v4f64(<2 x double> %vec0, <2 x double> %vec1) {
 ; CHECK-LABEL: interleave2_v4f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    zip1 v2.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    zip2 v1.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    mov v0.16b, v2.16b
 ; CHECK-NEXT:    ret
-  %retval = call <4 x double>@llvm.experimental.vector.interleave2.v4f64(<2 x double> %vec0, <2 x double> %vec1)
+  %retval = call <4 x double>(...) @llvm.experimental.vector.interleave.v4f64.v2f64(<2 x double> %vec0, <2 x double> %vec1)
   ret <4 x double> %retval
 }
 
 ; Integers
 
 define <32 x i8> @interleave2_v32i8(<16 x i8> %vec0, <16 x i8> %vec1) {
 ; CHECK-LABEL: interleave2_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    zip1 v2.16b, v0.16b, v1.16b
 ; CHECK-NEXT:    zip2 v1.16b, v0.16b, v1.16b
 ; CHECK-NEXT:    mov v0.16b, v2.16b
 ; CHECK-NEXT:    ret
- %retval = call <32 x i8> @llvm.experimental.vector.interleave2.v32i8(<16 x i8> %vec0, <16 x i8> %vec1)
+ %retval = call <32 x i8>(...) @llvm.experimental.vector.interleave.v32i8.v16i8(<16 x i8> %vec0, <16 x i8> %vec1)
   ret <32 x i8> %retval
 }
 
 define <16 x i16> @interleave2_v16i16(<8 x i16> %vec0, <8 x i16> %vec1) {
 ; CHECK-LABEL: interleave2_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    zip1 v2.8h, v0.8h, v1.8h
 ; CHECK-NEXT:    zip2 v1.8h, v0.8h, v1.8h
 ; CHECK-NEXT:    mov v0.16b, v2.16b
 ; CHECK-NEXT:    ret
-  %retval = call <16 x i16> @llvm.experimental.vector.interleave2.v16i16(<8 x i16> %vec0, <8 x i16> %vec1)
+  %retval = call <16 x i16>(...) @llvm.experimental.vector.interleave.v16i16.v8i16(<8 x i16> %vec0, <8 x i16> %vec1)
   ret <16 x i16> %retval
 }
 
 define <8 x i32> @interleave2_v8i32(<4 x i32> %vec0, <4 x i32> %vec1) {
 ; CHECK-LABEL: interleave2_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    zip1 v2.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    zip2 v1.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    mov v0.16b, v2.16b
 ; CHECK-NEXT:    ret
-  %retval = call <8 x i32> @llvm.experimental.vector.interleave2.v8i32(<4 x i32> %vec0, <4 x i32> %vec1)
+  %retval = call <8 x i32>(...) @llvm.experimental.vector.interleave.v8i32.v4i32(<4 x i32> %vec0, <4 x i32> %vec1)
   ret <8 x i32> %retval
 }
 
 define <4 x i64> @interleave2_v4i64(<2 x i64> %vec0, <2 x i64> %vec1) {
 ; CHECK-LABEL: interleave2_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    zip1 v2.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    zip2 v1.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    mov v0.16b, v2.16b
 ; CHECK-NEXT:    ret
-  %retval = call <4 x i64> @llvm.experimental.vector.interleave2.v4i64(<2 x i64> %vec0, <2 x i64> %vec1)
+  %retval = call <4 x i64>(...) @llvm.experimental.vector.interleave.v4i64.v2i64(<2 x i64> %vec0, <2 x i64> %vec1)
   ret <4 x i64> %retval
 }
 
 
 ; Float declarations
-declare <4 x half> @llvm.experimental.vector.interleave2.v4f16(<2 x half>, <2 x half>)
-declare <8 x half> @llvm.experimental.vector.interleave2.v8f16(<4 x half>, <4 x half>)
-declare <16 x half> @llvm.experimental.vector.interleave2.v16f16(<8 x half>, <8 x half>)
-declare <4 x float> @llvm.experimental.vector.interleave2.v4f32(<2 x float>, <2 x float>)
-declare <8 x float> @llvm.experimental.vector.interleave2.v8f32(<4 x float>, <4 x float>)
-declare <4 x double> @llvm.experimental.vector.interleave2.v4f64(<2 x double>, <2 x double>)
+declare <4 x half> @llvm.experimental.vector.interleave.v4f16.v2f16(...)
+declare <8 x half> @llvm.experimental.vector.interleave.v8f16.v4f16(...)
+declare <16 x half> @llvm.experimental.vector.interleave.v16f16.v8f16(...)
+declare <4 x float> @llvm.experimental.vector.interleave.v4f32.v2f32(...)
+declare <8 x float> @llvm.experimental.vector.interleave.v8f32.v4f32(...)
+declare <4 x double> @llvm.experimental.vector.interleave.v4f64.v2f64(...)
 
 ; Integer declarations
-declare <32 x i8> @llvm.experimental.vector.interleave2.v32i8(<16 x i8>, <16 x i8>)
-declare <16 x i16> @llvm.experimental.vector.interleave2.v16i16(<8 x i16>, <8 x i16>)
-declare <8 x i32> @llvm.experimental.vector.interleave2.v8i32(<4 x i32>, <4 x i32>)
-declare <4 x i64> @llvm.experimental.vector.interleave2.v4i64(<2 x i64>, <2 x i64>)
-
+declare <32 x i8> @llvm.experimental.vector.interleave.v32i8.v16i8(...)
+declare <16 x i16> @llvm.experimental.vector.interleave.v16i16.v8i16(...)
+declare <8 x i32> @llvm.experimental.vector.interleave.v8i32.v4i32(...)
+declare <4 x i64> @llvm.experimental.vector.interleave.v4i64.v2i64(...)

llvm/test/CodeGen/AArch64/sve-vector-deinterleave.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+sve2 | FileCheck %s
 
 define {<vscale x 2 x half>, <vscale x 2 x half>} @vector_deinterleave_nxv2f16_nxv4f16(<vscale x 4 x half> %vec) {
 ; CHECK-LABEL: vector_deinterleave_nxv2f16_nxv4f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    uunpkhi z1.d, z0.s
 ; CHECK-NEXT:    uunpklo z2.d, z0.s
 ; CHECK-NEXT:    uzp1 z0.d, z2.d, z1.d
 ; CHECK-NEXT:    uzp2 z1.d, z2.d, z1.d
 ; CHECK-NEXT:    ret
-  %retval = call {<vscale x 2 x half>, <vscale x 2 x half>} @llvm.experimental.vector.deinterleave2.nxv4f16(<vscale x 4 x half> %vec)
+  %retval = call {<vscale x 2 x half>, <vscale x 2 x half>} @llvm.experimental.vector.deinterleave.nxv4f16.nxv2f16(<vscale x 4 x half> %vec)
   ret {<vscale x 2 x half>, <vscale x 2 x half>}   %retval
 }
 
 define {<vscale x 4 x half>, <vscale x 4 x half>} @vector_deinterleave_nxv4f16_nxv8f16(<vscale x 8 x half> %vec) {
 ; CHECK-LABEL: vector_deinterleave_nxv4f16_nxv8f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    uunpkhi z1.s, z0.h
 ; CHECK-NEXT:    uunpklo z2.s, z0.h
 ; CHECK-NEXT:    uzp1 z0.s, z2.s, z1.s
 ; CHECK-NEXT:    uzp2 z1.s, z2.s, z1.s
 ; CHECK-NEXT:    ret
-  %retval = call {<vscale x 4 x half>, <vscale x 4 x half>} @llvm.experimental.vector.deinterleave2.nxv8f16(<vscale x 8 x half> %vec)
+  %retval = call {<vscale x 4 x half>, <vscale x 4 x half>} @llvm.experimental.vector.deinterleave.nxv8f16.nxv4f16(<vscale x 8 x half> %vec)
   ret {<vscale x 4 x half>, <vscale x 4 x half>}   %retval
 }
 
 define {<vscale x 8 x half>, <vscale x 8 x half>} @vector_deinterleave_nxv8f16_nxv16f16(<vscale x 16 x half> %vec) {
 ; CHECK-LABEL: vector_deinterleave_nxv8f16_nxv16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    uzp1 z2.h, z0.h, z1.h
 ; CHECK-NEXT:    uzp2 z1.h, z0.h, z1.h
 ; CHECK-NEXT:    mov z0.d, z2.d
 ; CHECK-NEXT:    ret
-  %retval = call {<vscale x 8 x half>, <vscale x 8 x half>} @llvm.experimental.vector.deinterleave2.nxv16f16(<vscale x 16 x half> %vec)
+  %retval = call {<vscale x 8 x half>, <vscale x 8 x half>} @llvm.experimental.vector.deinterleave.nxv16f16.nxv8f16(<vscale x 16 x half> %vec)
   ret {<vscale x 8 x half>, <vscale x 8 x half>}   %retval
 }
 
 define {<vscale x 2 x float>, <vscale x 2 x float>} @vector_deinterleave_nxv2f32_nxv4f32(<vscale x 4 x float> %vec) {
 ; CHECK-LABEL: vector_deinterleave_nxv2f32_nxv4f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    uunpkhi z1.d, z0.s
 ; CHECK-NEXT:    uunpklo z2.d, z0.s
 ; CHECK-NEXT:    uzp1 z0.d, z2.d, z1.d
 ; CHECK-NEXT:    uzp2 z1.d, z2.d, z1.d
 ; CHECK-NEXT:    ret
-  %retval = call {<vscale x 2 x float>, <vscale x 2 x float>} @llvm.experimental.vector.deinterleave2.nxv4f32(<vscale x 4 x float> %vec)
+  %retval = call {<vscale x 2 x float>, <vscale x 2 x float>} @llvm.experimental.vector.deinterleave.nxv4f32.nxv2f32(<vscale x 4 x float> %vec)
   ret {<vscale x 2 x float>, <vscale x 2 x float>}   %retval
 }
 
 define {<vscale x 4 x float>, <vscale x 4 x float>} @vector_deinterleave_nxv4f32_nxv8f32(<vscale x 8 x float> %vec) {
 ; CHECK-LABEL: vector_deinterleave_nxv4f32_nxv8f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    uzp1 z2.s, z0.s, z1.s
 ; CHECK-NEXT:    uzp2 z1.s, z0.s, z1.s
 ; CHECK-NEXT:    mov z0.d, z2.d
 ; CHECK-NEXT:    ret
-  %retval = call {<vscale x 4 x float>, <vscale x 4 x float>} @llvm.experimental.vector.deinterleave2.nxv8f32(<vscale x 8 x float> %vec)
+  %retval = call {<vscale x 4 x float>, <vscale x 4 x float>} @llvm.experimental.vector.deinterleave.nxv8f32.nxv4f32(<vscale x 8 x float> %vec)
 ret  {<vscale x 4 x float>, <vscale x 4 x float>}   %retval
 }
 
 define {<vscale x 2 x double>, <vscale x 2 x double>} @vector_deinterleave_nxv2f64_nxv4f64(<vscale x 4 x double> %vec) {
 ; CHECK-LABEL: vector_deinterleave_nxv2f64_nxv4f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    uzp1 z2.d, z0.d, z1.d
 ; CHECK-NEXT:    uzp2 z1.d, z0.d, z1.d
 ; CHECK-NEXT:    mov z0.d, z2.d
 ; CHECK-NEXT:    ret
-  %retval = call {<vscale x 2 x double>, <vscale x 2 x double>} @llvm.experimental.vector.deinterleave2.nxv4f64(<vscale x 4 x double> %vec)
+  %retval = call {<vscale x 2 x double>, <vscale x 2 x double>} @llvm.experimental.vector.deinterleave.nxv4f64.nxv2f64(<vscale x 4 x double> %vec)
   ret {<vscale x 2 x double>, <vscale x 2 x double>}   %retval
 }
 
 ; Integers
 
 define {<vscale x 16 x i8>, <vscale x 16 x i8>} @vector_deinterleave_nxv16i8_nxv32i8(<vscale x 32 x i8> %vec) {
 ; CHECK-LABEL: vector_deinterleave_nxv16i8_nxv32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    uzp1 z2.b, z0.b, z1.b
 ; CHECK-NEXT:    uzp2 z1.b, z0.b, z1.b
 ; CHECK-NEXT:    mov z0.d, z2.d
 ; CHECK-NEXT:    ret
-  %retval = call {<vscale x 16 x i8>, <vscale x 16 x i8>} @llvm.experimental.vector.deinterleave2.nxv32i8(<vscale x 32 x i8> %vec)
+  %retval = call {<vscale x 16 x i8>, <vscale x 16 x i8>} @llvm.experimental.vector.deinterleave.nxv32i8.nxv16i8(<vscale x 32 x i8> %vec)
   ret {<vscale x 16 x i8>, <vscale x 16 x i8>}   %retval
 }
 
 define {<vscale x 8 x i16>, <vscale x 8 x i16>} @vector_deinterleave_nxv8i16_nxv16i16(<vscale x 16 x i16> %vec) {
 ; CHECK-LABEL: vector_deinterleave_nxv8i16_nxv16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    uzp1 z2.h, z0.h, z1.h
 ; CHECK-NEXT:    uzp2 z1.h, z0.h, z1.h
 ; CHECK-NEXT:    mov z0.d, z2.d
 ; CHECK-NEXT:    ret
-  %retval = call {<vscale x 8 x i16>, <vscale x 8 x i16>} @llvm.experimental.vector.deinterleave2.nxv16i16(<vscale x 16 x i16> %vec)
+  %retval = call {<vscale x 8 x i16>, <vscale x 8 x i16>} @llvm.experimental.vector.deinterleave.nxv16i16.nxv8i16(<vscale x 16 x i16> %vec)
   ret {<vscale x 8 x i16>, <vscale x 8 x i16>}   %retval
 }
 
 define {<vscale x 4 x i32>, <vscale x 4 x i32>} @vector_deinterleave_nxv4i32_nxvv8i32(<vscale x 8 x i32> %vec) {
 ; CHECK-LABEL: vector_deinterleave_nxv4i32_nxvv8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    uzp1 z2.s, z0.s, z1.s
 ; CHECK-NEXT:    uzp2 z1.s, z0.s, z1.s
 ; CHECK-NEXT:    mov z0.d, z2.d
 ; CHECK-NEXT:    ret
-  %retval = call {<vscale x 4 x i32>, <vscale x 4 x i32>} @llvm.experimental.vector.deinterleave2.nxv8i32(<vscale x 8 x i32> %vec)
+  %retval = call {<vscale x 4 x i32>, <vscale x 4 x i32>} @llvm.experimental.vector.deinterleave.nxv8i32.nxv4i32(<vscale x 8 x i32> %vec)
   ret {<vscale x 4 x i32>, <vscale x 4 x i32>}   %retval
 }
 
 define {<vscale x 2 x i64>, <vscale x 2 x i64>} @vector_deinterleave_nxv2i64_nxv4i64(<vscale x 4 x i64> %vec) {
 ; CHECK-LABEL: vector_deinterleave_nxv2i64_nxv4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    uzp1 z2.d, z0.d, z1.d
 ; CHECK-NEXT:    uzp2 z1.d, z0.d, z1.d
 ; CHECK-NEXT:    mov z0.d, z2.d
 ; CHECK-NEXT:    ret
-  %retval = call {<vscale x 2 x i64>, <vscale x 2 x i64>} @llvm.experimental.vector.deinterleave2.nxv4i64(<vscale x 4 x i64> %vec)
+  %retval = call {<vscale x 2 x i64>, <vscale x 2 x i64>} @llvm.experimental.vector.deinterleave.nxv4i64.nxv2i64(<vscale x 4 x i64> %vec)
   ret {<vscale x 2 x i64>, <vscale x 2 x i64>}   %retval
 }
 
 ; Predicated
 define {<vscale x 16 x i1>, <vscale x 16 x i1>} @vector_deinterleave_nxv16i1_nxv32i1(<vscale x 32 x i1> %vec) {
 ; CHECK-LABEL: vector_deinterleave_nxv16i1_nxv32i1:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    uzp1 p2.b, p0.b, p1.b
 ; CHECK-NEXT:    uzp2 p1.b, p0.b, p1.b
 ; CHECK-NEXT:    mov p0.b, p2.b
 ; CHECK-NEXT:    ret
-  %retval = call {<vscale x 16 x i1>, <vscale x 16 x i1>} @llvm.experimental.vector.deinterleave2.nxv32i1(<vscale x 32 x i1> %vec)
+  %retval = call {<vscale x 16 x i1>, <vscale x 16 x i1>} @llvm.experimental.vector.deinterleave.nxv32i1.nxv16i1(<vscale x 32 x i1> %vec)
   ret {<vscale x 16 x i1>, <vscale x 16 x i1>}   %retval
 }
 
 define {<vscale x 8 x i1>, <vscale x 8 x i1>} @vector_deinterleave_nxv8i1_nxv16i1(<vscale x 16 x i1> %vec) {
 ; CHECK-LABEL: vector_deinterleave_nxv8i1_nxv16i1:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    punpkhi p1.h, p0.b
 ; CHECK-NEXT:    punpklo p2.h, p0.b
 ; CHECK-NEXT:    uzp1 p0.h, p2.h, p1.h
 ; CHECK-NEXT:    uzp2 p1.h, p2.h, p1.h
 ; CHECK-NEXT:    ret
-  %retval = call {<vscale x 8 x i1>, <vscale x 8 x i1>} @llvm.experimental.vector.deinterleave2.nxv16i1(<vscale x 16 x i1> %vec)
+  %retval = call {<vscale x 8 x i1>, <vscale x 8 x i1>} @llvm.experimental.vector.deinterleave.nxv16i1.nxv8i1(<vscale x 16 x i1> %vec)
   ret {<vscale x 8 x i1>, <vscale x 8 x i1>}   %retval
 }
 
 define {<vscale x 4 x i1>, <vscale x 4 x i1>} @vector_deinterleave_nxv4i1_nxv8i1(<vscale x 8 x i1> %vec) {
 ; CHECK-LABEL: vector_deinterleave_nxv4i1_nxv8i1:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    punpkhi p1.h, p0.b
 ; CHECK-NEXT:    punpklo p2.h, p0.b
 ; CHECK-NEXT:    uzp1 p0.s, p2.s, p1.s
 ; CHECK-NEXT:    uzp2 p1.s, p2.s, p1.s
 ; CHECK-NEXT:    ret
-  %retval = call {<vscale x 4 x i1>, <vscale x 4 x i1>} @llvm.experimental.vector.deinterleave2.nxv8i1(<vscale x 8 x i1> %vec)
+  %retval = call {<vscale x 4 x i1>, <vscale x 4 x i1>} @llvm.experimental.vector.deinterleave.nxv8i1.nxv4i1(<vscale x 8 x i1> %vec)
   ret {<vscale x 4 x i1>, <vscale x 4 x i1>}   %retval
 }
 
 define {<vscale x 2 x i1>, <vscale x 2 x i1>} @vector_deinterleave_nxv2i1_nxv4i1(<vscale x 4 x i1> %vec) {
 ; CHECK-LABEL: vector_deinterleave_nxv2i1_nxv4i1:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    punpkhi p1.h, p0.b
 ; CHECK-NEXT:    punpklo p2.h, p0.b
 ; CHECK-NEXT:    uzp1 p0.d, p2.d, p1.d
 ; CHECK-NEXT:    uzp2 p1.d, p2.d, p1.d
 ; CHECK-NEXT:    ret
-  %retval = call {<vscale x 2 x i1>, <vscale x 2 x i1>} @llvm.experimental.vector.deinterleave2.nxv4i1(<vscale x 4 x i1> %vec)
+  %retval = call {<vscale x 2 x i1>, <vscale x 2 x i1>} @llvm.experimental.vector.deinterleave.nxv4i1.nxv2i1(<vscale x 4 x i1> %vec)
   ret {<vscale x 2 x i1>, <vscale x 2 x i1>}   %retval
 }
 
 
 ; Split illegal types
 
 define {<vscale x 4 x i64>, <vscale x 4 x i64>} @vector_deinterleave_nxv4i64_nxv8i64(<vscale x 8 x i64> %vec) {
 ; CHECK-LABEL: vector_deinterleave_nxv4i64_nxv8i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    uzp1 z4.d, z2.d, z3.d
 ; CHECK-NEXT:    uzp1 z5.d, z0.d, z1.d
 ; CHECK-NEXT:    uzp2 z6.d, z0.d, z1.d
 ; CHECK-NEXT:    uzp2 z3.d, z2.d, z3.d
 ; CHECK-NEXT:    mov z0.d, z5.d
 ; CHECK-NEXT:    mov z1.d, z4.d
 ; CHECK-NEXT:    mov z2.d, z6.d
 ; CHECK-NEXT:    ret
-%retval = call {<vscale x 4 x i64>, <vscale x 4 x i64>} @llvm.experimental.vector.deinterleave2.nxv8i64(<vscale x 8 x i64> %vec)
+%retval = call {<vscale x 4 x i64>, <vscale x 4 x i64>} @llvm.experimental.vector.deinterleave.nxv8i64.nxv4i64(<vscale x 8 x i64> %vec)
 ret {<vscale x 4 x i64>, <vscale x 4 x i64>} %retval
 }
 
 define {<vscale x 8 x i64>, <vscale x 8 x i64>}  @vector_deinterleave_nxv8i64_nxv16i64(<vscale x 16 x i64> %vec) {
 ; CHECK-LABEL: vector_deinterleave_nxv8i64_nxv16i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    uzp1 z24.d, z4.d, z5.d
 ; CHECK-NEXT:    uzp1 z25.d, z2.d, z3.d
 ; CHECK-NEXT:    uzp1 z26.d, z0.d, z1.d
 ; CHECK-NEXT:    uzp1 z27.d, z6.d, z7.d
 ; CHECK-NEXT:    uzp2 z28.d, z0.d, z1.d
 ; CHECK-NEXT:    uzp2 z29.d, z2.d, z3.d
 ; CHECK-NEXT:    uzp2 z30.d, z4.d, z5.d
 ; CHECK-NEXT:    uzp2 z7.d, z6.d, z7.d
 ; CHECK-NEXT:    mov z0.d, z26.d
 ; CHECK-NEXT:    mov z1.d, z25.d
 ; CHECK-NEXT:    mov z2.d, z24.d
 ; CHECK-NEXT:    mov z3.d, z27.d
 ; CHECK-NEXT:    mov z4.d, z28.d
 ; CHECK-NEXT:    mov z5.d, z29.d
 ; CHECK-NEXT:    mov z6.d, z30.d
 ; CHECK-NEXT:    ret
-%retval = call {<vscale x 8 x i64>, <vscale x 8 x i64>} @llvm.experimental.vector.deinterleave2.nxv16i64(<vscale x 16 x i64> %vec)
+%retval = call {<vscale x 8 x i64>, <vscale x 8 x i64>} @llvm.experimental.vector.deinterleave.nxv16i64.nxv8i64(<vscale x 16 x i64> %vec)
 ret {<vscale x 8 x i64>, <vscale x 8 x i64>}  %retval
 }
 
 
 ; Promote illegal type size
 
 define {<vscale x 8 x i8>, <vscale x 8 x i8>} @vector_deinterleave_nxv8i8_nxv16i8(<vscale x 16 x i8> %vec) {
 ; CHECK-LABEL: vector_deinterleave_nxv8i8_nxv16i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    uunpkhi z1.h, z0.b
 ; CHECK-NEXT:    uunpklo z2.h, z0.b
 ; CHECK-NEXT:    uzp1 z0.h, z2.h, z1.h
 ; CHECK-NEXT:    uzp2 z1.h, z2.h, z1.h
 ; CHECK-NEXT:    ret
-%retval = call {<vscale x 8 x i8>, <vscale x 8 x i8>} @llvm.experimental.vector.deinterleave2.nxv16i8(<vscale x 16 x i8> %vec)
+%retval = call {<vscale x 8 x i8>, <vscale x 8 x i8>} @llvm.experimental.vector.deinterleave.nxv16i8.nxv8i8(<vscale x 16 x i8> %vec)
 ret {<vscale x 8 x i8>, <vscale x 8 x i8>} %retval
 }
 
 define {<vscale x 4 x i16>, <vscale x 4 x i16>} @vector_deinterleave_nxv4i16_nxv8i16(<vscale x 8 x i16> %vec) {
 ; CHECK-LABEL: vector_deinterleave_nxv4i16_nxv8i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    uunpkhi z1.s, z0.h
 ; CHECK-NEXT:    uunpklo z2.s, z0.h
 ; CHECK-NEXT:    uzp1 z0.s, z2.s, z1.s
 ; CHECK-NEXT:    uzp2 z1.s, z2.s, z1.s
 ; CHECK-NEXT:    ret
-%retval = call {<vscale x 4 x i16>, <vscale x 4 x i16>} @llvm.experimental.vector.deinterleave2.nxv8i16(<vscale x 8 x i16> %vec)
+%retval = call {<vscale x 4 x i16>, <vscale x 4 x i16>} @llvm.experimental.vector.deinterleave.nxv8i16.nxv4i16(<vscale x 8 x i16> %vec)
 ret {<vscale x 4 x i16>, <vscale x 4 x i16>} %retval
 }
 
 define {<vscale x 2 x i32>, <vscale x 2 x i32>} @vector_deinterleave_nxv2i32_nxv4i32(<vscale x 4 x i32> %vec) {
 ; CHECK-LABEL: vector_deinterleave_nxv2i32_nxv4i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    uunpkhi z1.d, z0.s
 ; CHECK-NEXT:    uunpklo z2.d, z0.s
 ; CHECK-NEXT:    uzp1 z0.d, z2.d, z1.d
 ; CHECK-NEXT:    uzp2 z1.d, z2.d, z1.d
 ; CHECK-NEXT:    ret
-%retval = call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.experimental.vector.deinterleave2.nxv4i32(<vscale x 4 x i32> %vec)
+%retval = call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.experimental.vector.deinterleave.nxv4i32.nxv2i32(<vscale x 4 x i32> %vec)
 ret {<vscale x 2 x i32>, <vscale x 2 x i32>} %retval
 }
 
 
 ; Floating declarations
-declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.experimental.vector.deinterleave2.nxv4f16(<vscale x 4 x half>)
-declare {<vscale x 4 x half>, <vscale x 4 x half>} @llvm.experimental.vector.deinterleave2.nxv8f16(<vscale x 8 x half>)
-declare {<vscale x 2 x float>, <vscale x 2 x float>} @llvm.experimental.vector.deinterleave2.nxv4f32(<vscale x 4 x float>)
-declare {<vscale x 8 x half>, <vscale x 8 x half>} @llvm.experimental.vector.deinterleave2.nxv16f16(<vscale x 16 x half>)
-declare {<vscale x 4 x float>, <vscale x 4 x float>} @llvm.experimental.vector.deinterleave2.nxv8f32(<vscale x 8 x float>)
-declare {<vscale x 2 x double>, <vscale x 2 x double>} @llvm.experimental.vector.deinterleave2.nxv4f64(<vscale x 4 x double>)
+declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.experimental.vector.deinterleave.nxv4f16.nxv2f16(<vscale x 4 x half>)
+declare {<vscale x 4 x half>, <vscale x 4 x half>} @llvm.experimental.vector.deinterleave.nxv8f16.nxv4f16(<vscale x 8 x half>)
+declare {<vscale x 2 x float>, <vscale x 2 x float>} @llvm.experimental.vector.deinterleave.nxv4f32.nxv2f32(<vscale x 4 x float>)
+declare {<vscale x 8 x half>, <vscale x 8 x half>} @llvm.experimental.vector.deinterleave.nxv16f16.nxv8f16(<vscale x 16 x half>)
+declare {<vscale x 4 x float>, <vscale x 4 x float>} @llvm.experimental.vector.deinterleave.nxv8f32.nxv4f32(<vscale x 8 x float>)
+declare {<vscale x 2 x double>, <vscale x 2 x double>} @llvm.experimental.vector.deinterleave.nxv4f64.nxv2f64(<vscale x 4 x double>)
 
 ; Integer declarations
-declare {<vscale x 16 x i8>, <vscale x 16 x i8>} @llvm.experimental.vector.deinterleave2.nxv32i8(<vscale x 32 x i8>)
-declare {<vscale x 8 x i16>, <vscale x 8 x i16>} @llvm.experimental.vector.deinterleave2.nxv16i16(<vscale x 16 x i16>)
-declare {<vscale x 4 x i32>, <vscale x 4 x i32>} @llvm.experimental.vector.deinterleave2.nxv8i32(<vscale x 8 x i32>)
-declare {<vscale x 2 x i64>, <vscale x 2 x i64>} @llvm.experimental.vector.deinterleave2.nxv4i64(<vscale x 4 x i64>)
+declare {<vscale x 16 x i8>, <vscale x 16 x i8>} @llvm.experimental.vector.deinterleave.nxv32i8.nxv16i8(<vscale x 32 x i8>)
+declare {<vscale x 8 x i16>, <vscale x 8 x i16>} @llvm.experimental.vector.deinterleave.nxv16i16.nxv8i16(<vscale x 16 x i16>)
+declare {<vscale x 4 x i32>, <vscale x 4 x i32>} @llvm.experimental.vector.deinterleave.nxv8i32.nxv4i32(<vscale x 8 x i32>)
+declare {<vscale x 2 x i64>, <vscale x 2 x i64>} @llvm.experimental.vector.deinterleave.nxv4i64.nxv2i64(<vscale x 4 x i64>)
 
 ; Predicated declarations
-declare {<vscale x 16 x i1>, <vscale x 16 x i1>} @llvm.experimental.vector.deinterleave2.nxv32i1(<vscale x 32 x i1>)
-declare {<vscale x 8 x i1>, <vscale x 8 x i1>} @llvm.experimental.vector.deinterleave2.nxv16i1(<vscale x 16 x i1>)
-declare {<vscale x 4 x i1>, <vscale x 4 x i1>} @llvm.experimental.vector.deinterleave2.nxv8i1(<vscale x 8 x i1>)
-declare {<vscale x 2 x i1>, <vscale x 2 x i1>} @llvm.experimental.vector.deinterleave2.nxv4i1(<vscale x 4 x i1>)
+declare {<vscale x 16 x i1>, <vscale x 16 x i1>} @llvm.experimental.vector.deinterleave.nxv32i1.nxv16i1(<vscale x 32 x i1>)
+declare {<vscale x 8 x i1>, <vscale x 8 x i1>} @llvm.experimental.vector.deinterleave.nxv16i1.nxv8i1(<vscale x 16 x i1>)
+declare {<vscale x 4 x i1>, <vscale x 4 x i1>} @llvm.experimental.vector.deinterleave.nxv8i1.nxv4i1(<vscale x 8 x i1>)
+declare {<vscale x 2 x i1>, <vscale x 2 x i1>} @llvm.experimental.vector.deinterleave.nxv4i1.nxv2i1(<vscale x 4 x i1>)
 
 ; Illegal size type
-declare {<vscale x 4 x i64>, <vscale x 4 x i64>} @llvm.experimental.vector.deinterleave2.nxv8i64(<vscale x 8 x i64>)
-declare {<vscale x 8 x i64>, <vscale x 8 x i64>} @llvm.experimental.vector.deinterleave2.nxv16i64(<vscale x 16 x i64>)
+declare {<vscale x 4 x i64>, <vscale x 4 x i64>} @llvm.experimental.vector.deinterleave.nxv8i64.nxv4i64(<vscale x 8 x i64>)
+declare {<vscale x 8 x i64>, <vscale x 8 x i64>} @llvm.experimental.vector.deinterleave.nxv16i64.nxv8i64(<vscale x 16 x i64>)
 
-declare {<vscale x 8 x i8>, <vscale x 8 x i8>} @llvm.experimental.vector.deinterleave2.nxv16i8(<vscale x 16 x i8>)
-declare {<vscale x 4 x i16>, <vscale x 4 x i16>} @llvm.experimental.vector.deinterleave2.nxv8i16(<vscale x 8 x i16>)
-declare {<vscale x 2 x i32>, <vscale x 2 x i32>} @llvm.experimental.vector.deinterleave2.nxv4i32(<vscale x 4 x i32>)
+declare {<vscale x 8 x i8>, <vscale x 8 x i8>} @llvm.experimental.vector.deinterleave.nxv16i8.nxv8i8(<vscale x 16 x i8>)
+declare {<vscale x 4 x i16>, <vscale x 4 x i16>} @llvm.experimental.vector.deinterleave.nxv8i16.nxv4i16(<vscale x 8 x i16>)
+declare {<vscale x 2 x i32>, <vscale x 2 x i32>} @llvm.experimental.vector.deinterleave.nxv4i32.nxv2i32(<vscale x 4 x i32>)

llvm/test/CodeGen/AArch64/sve-vector-interleave.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+sve | FileCheck %s
 
 define <vscale x 4 x half> @interleave2_nxv4f16(<vscale x 2 x half> %vec0, <vscale x 2 x half> %vec1) {
 ; CHECK-LABEL: interleave2_nxv4f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    zip2 z2.d, z0.d, z1.d
 ; CHECK-NEXT:    zip1 z0.d, z0.d, z1.d
 ; CHECK-NEXT:    uzp1 z0.s, z0.s, z2.s
 ; CHECK-NEXT:    ret
-  %retval = call <vscale x 4 x half> @llvm.experimental.vector.interleave2.nxv4f16(<vscale x 2 x half> %vec0, <vscale x 2 x half> %vec1)
+  %retval = call <vscale x 4 x half>(...) @llvm.experimental.vector.interleave.nxv4f16.nxv2f16(<vscale x 2 x half> %vec0, <vscale x 2 x half> %vec1)
   ret  <vscale x 4 x half>   %retval
 }
 
 define <vscale x 8 x half> @interleave2_nxv8f16(<vscale x 4 x half> %vec0, <vscale x 4 x half> %vec1) {
 ; CHECK-LABEL: interleave2_nxv8f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    zip2 z2.s, z0.s, z1.s
 ; CHECK-NEXT:    zip1 z0.s, z0.s, z1.s
 ; CHECK-NEXT:    uzp1 z0.h, z0.h, z2.h
 ; CHECK-NEXT:    ret
-  %retval = call <vscale x 8 x half> @llvm.experimental.vector.interleave2.nxv8f16(<vscale x 4 x half> %vec0, <vscale x 4 x half> %vec1)
+  %retval = call <vscale x 8 x half>(...) @llvm.experimental.vector.interleave.nxv8f16.nxv4f16(<vscale x 4 x half> %vec0, <vscale x 4 x half> %vec1)
   ret  <vscale x 8 x half>   %retval
 }
 
 define <vscale x 16 x half> @interleave2_nxv16f16(<vscale x 8 x half> %vec0, <vscale x 8 x half> %vec1) {
 ; CHECK-LABEL: interleave2_nxv16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    zip1 z2.h, z0.h, z1.h
 ; CHECK-NEXT:    zip2 z1.h, z0.h, z1.h
 ; CHECK-NEXT:    mov z0.d, z2.d
 ; CHECK-NEXT:    ret
-  %retval = call <vscale x 16 x half> @llvm.experimental.vector.interleave2.nxv16f16(<vscale x 8 x half> %vec0, <vscale x 8 x half> %vec1)
+  %retval = call <vscale x 16 x half>(...) @llvm.experimental.vector.interleave.nxv16f16.nxv8f16(<vscale x 8 x half> %vec0, <vscale x 8 x half> %vec1)
   ret  <vscale x 16 x half>   %retval
 }
 
 define <vscale x 4 x float> @interleave2_nxv4f32(<vscale x 2 x float> %vec0, <vscale x 2 x float> %vec1) {
 ; CHECK-LABEL: interleave2_nxv4f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    zip2 z2.d, z0.d, z1.d
 ; CHECK-NEXT:    zip1 z0.d, z0.d, z1.d
 ; CHECK-NEXT:    uzp1 z0.s, z0.s, z2.s
 ; CHECK-NEXT:    ret
-  %retval = call <vscale x 4 x float> @llvm.experimental.vector.interleave2.nxv4f32(<vscale x 2 x float> %vec0, <vscale x 2 x float> %vec1)
+  %retval = call <vscale x 4 x float>(...) @llvm.experimental.vector.interleave.nxv4f32.nxv2f32(<vscale x 2 x float> %vec0, <vscale x 2 x float> %vec1)
   ret  <vscale x 4 x float>   %retval
 }
 
 define <vscale x 8 x float> @interleave2_nxv8f32(<vscale x 4 x float> %vec0, <vscale x 4 x float> %vec1) {
 ; CHECK-LABEL: interleave2_nxv8f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    zip1 z2.s, z0.s, z1.s
 ; CHECK-NEXT:    zip2 z1.s, z0.s, z1.s
 ; CHECK-NEXT:    mov z0.d, z2.d
 ; CHECK-NEXT:    ret
-  %retval = call <vscale x 8 x float> @llvm.experimental.vector.interleave2.nxv8f32(<vscale x 4 x float> %vec0, <vscale x 4 x float> %vec1)
+  %retval = call <vscale x 8 x float>(...) @llvm.experimental.vector.interleave.nxv8f32.nxv4f32(<vscale x 4 x float> %vec0, <vscale x 4 x float> %vec1)
   ret  <vscale x 8 x float>   %retval
 }
 
 define <vscale x 4 x double> @interleave2_nxv4f64(<vscale x 2 x double> %vec0, <vscale x 2 x double> %vec1) {
 ; CHECK-LABEL: interleave2_nxv4f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    zip1 z2.d, z0.d, z1.d
 ; CHECK-NEXT:    zip2 z1.d, z0.d, z1.d
 ; CHECK-NEXT:    mov z0.d, z2.d
 ; CHECK-NEXT:    ret
-  %retval = call <vscale x 4 x double>@llvm.experimental.vector.interleave2.nxv4f64(<vscale x 2 x double> %vec0, <vscale x 2 x double> %vec1)
+  %retval = call <vscale x 4 x double>(...) @llvm.experimental.vector.interleave.nxv4f64.nxv2f64(<vscale x 2 x double> %vec0, <vscale x 2 x double> %vec1)
   ret  <vscale x 4 x double>   %retval
 }
 
 ; Integers
 
 define <vscale x 32 x i8> @interleave2_nxv32i8(<vscale x 16 x i8> %vec0, <vscale x 16 x i8> %vec1) {
 ; CHECK-LABEL: interleave2_nxv32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    zip1 z2.b, z0.b, z1.b
 ; CHECK-NEXT:    zip2 z1.b, z0.b, z1.b
 ; CHECK-NEXT:    mov z0.d, z2.d
 ; CHECK-NEXT:    ret
-   %retval = call <vscale x 32 x i8> @llvm.experimental.vector.interleave2.nxv32i8(<vscale x 16 x i8> %vec0, <vscale x 16 x i8> %vec1)
+   %retval = call <vscale x 32 x i8>(...) @llvm.experimental.vector.interleave.nxv32i8.nxv16i8(<vscale x 16 x i8> %vec0, <vscale x 16 x i8> %vec1)
   ret  <vscale x 32 x i8>   %retval
 }
 
 define <vscale x 16 x i16> @interleave2_nxv16i16(<vscale x 8 x i16> %vec0, <vscale x 8 x i16> %vec1) {
 ; CHECK-LABEL: interleave2_nxv16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    zip1 z2.h, z0.h, z1.h
 ; CHECK-NEXT:    zip2 z1.h, z0.h, z1.h
 ; CHECK-NEXT:    mov z0.d, z2.d
 ; CHECK-NEXT:    ret
-  %retval = call <vscale x 16 x i16> @llvm.experimental.vector.interleave2.nxv16i16(<vscale x 8 x i16> %vec0, <vscale x 8 x i16> %vec1)
+  %retval = call <vscale x 16 x i16>(...) @llvm.experimental.vector.interleave.nxv16i16.nxv8i16(<vscale x 8 x i16> %vec0, <vscale x 8 x i16> %vec1)
   ret  <vscale x 16 x i16>   %retval
 }
 
 define <vscale x 8 x i32> @interleave2_nxv8i32(<vscale x 4 x i32> %vec0, <vscale x 4 x i32> %vec1) {
 ; CHECK-LABEL: interleave2_nxv8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    zip1 z2.s, z0.s, z1.s
 ; CHECK-NEXT:    zip2 z1.s, z0.s, z1.s
 ; CHECK-NEXT:    mov z0.d, z2.d
 ; CHECK-NEXT:    ret
-  %retval = call <vscale x 8 x i32> @llvm.experimental.vector.interleave2.nxv8i32(<vscale x 4 x i32> %vec0, <vscale x 4 x i32> %vec1)
+  %retval = call <vscale x 8 x i32>(...) @llvm.experimental.vector.interleave.nxv8i32.nxv4i32(<vscale x 4 x i32> %vec0, <vscale x 4 x i32> %vec1)
   ret  <vscale x 8 x i32>   %retval
 }
 
 define <vscale x 4 x i64> @interleave2_nxv4i64(<vscale x 2 x i64> %vec0, <vscale x 2 x i64> %vec1) {
 ; CHECK-LABEL: interleave2_nxv4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    zip1 z2.d, z0.d, z1.d
 ; CHECK-NEXT:    zip2 z1.d, z0.d, z1.d
 ; CHECK-NEXT:    mov z0.d, z2.d
 ; CHECK-NEXT:    ret
-  %retval = call <vscale x 4 x i64> @llvm.experimental.vector.interleave2.nxv4i64(<vscale x 2 x i64> %vec0, <vscale x 2 x i64> %vec1)
+  %retval = call <vscale x 4 x i64>(...) @llvm.experimental.vector.interleave.nxv4i64.nxv2i64(<vscale x 2 x i64> %vec0, <vscale x 2 x i64> %vec1)
   ret  <vscale x 4 x i64>   %retval
 }
 
 ; Predicated
 
 define <vscale x 32 x i1> @interleave2_nxv32i1(<vscale x 16 x i1> %vec0, <vscale x 16 x i1> %vec1) {
 ; CHECK-LABEL: interleave2_nxv32i1:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    zip1 p2.b, p0.b, p1.b
 ; CHECK-NEXT:    zip2 p1.b, p0.b, p1.b
 ; CHECK-NEXT:    mov p0.b, p2.b
 ; CHECK-NEXT:    ret
-   %retval = call <vscale x 32 x i1> @llvm.experimental.vector.interleave2.nxv32i1(<vscale x 16 x i1> %vec0, <vscale x 16 x i1> %vec1)
+   %retval = call <vscale x 32 x i1>(...) @llvm.experimental.vector.interleave.nxv32i1.nxv16i1(<vscale x 16 x i1> %vec0, <vscale x 16 x i1> %vec1)
   ret  <vscale x 32 x i1>   %retval
 }
 
 define <vscale x 16 x i1> @interleave2_nxv16i1(<vscale x 8 x i1> %vec0, <vscale x 8 x i1> %vec1) {
 ; CHECK-LABEL: interleave2_nxv16i1:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    zip2 p2.h, p0.h, p1.h
 ; CHECK-NEXT:    zip1 p0.h, p0.h, p1.h
 ; CHECK-NEXT:    uzp1 p0.b, p0.b, p2.b
 ; CHECK-NEXT:    ret
-  %retval = call <vscale x 16 x i1> @llvm.experimental.vector.interleave2.nxv16i1(<vscale x 8 x i1> %vec0, <vscale x 8 x i1> %vec1)
+  %retval = call <vscale x 16 x i1>(...) @llvm.experimental.vector.interleave.nxv16i1.nxv8i1(<vscale x 8 x i1> %vec0, <vscale x 8 x i1> %vec1)
   ret  <vscale x 16 x i1>   %retval
 }
 
 define <vscale x 8 x i1> @interleave2_nxv8i1(<vscale x 4 x i1> %vec0, <vscale x 4 x i1> %vec1) {
 ; CHECK-LABEL: interleave2_nxv8i1:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    zip2 p2.s, p0.s, p1.s
 ; CHECK-NEXT:    zip1 p0.s, p0.s, p1.s
 ; CHECK-NEXT:    uzp1 p0.h, p0.h, p2.h
 ; CHECK-NEXT:    ret
-  %retval = call <vscale x 8 x i1> @llvm.experimental.vector.interleave2.nxv8i1(<vscale x 4 x i1> %vec0, <vscale x 4 x i1> %vec1)
+  %retval = call <vscale x 8 x i1>(...) @llvm.experimental.vector.interleave.nxv8i1.nxv4i1(<vscale x 4 x i1> %vec0, <vscale x 4 x i1> %vec1)
   ret  <vscale x 8 x i1>   %retval
 }
 
 define <vscale x 4 x i1> @interleave2_nxv4i1(<vscale x 2 x i1> %vec0, <vscale x 2 x i1> %vec1) {
 ; CHECK-LABEL: interleave2_nxv4i1:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    zip2 p2.d, p0.d, p1.d
 ; CHECK-NEXT:    zip1 p0.d, p0.d, p1.d
 ; CHECK-NEXT:    uzp1 p0.s, p0.s, p2.s
 ; CHECK-NEXT:    ret
-  %retval = call <vscale x 4 x i1> @llvm.experimental.vector.interleave2.nxv4i1(<vscale x 2 x i1> %vec0, <vscale x 2 x i1> %vec1)
+  %retval = call <vscale x 4 x i1>(...) @llvm.experimental.vector.interleave.nxv4i1.nxv2i1(<vscale x 2 x i1> %vec0, <vscale x 2 x i1> %vec1)
   ret  <vscale x 4 x i1>   %retval
 }
 
 ; Split illegal type size
 
 define <vscale x 16 x i32> @interleave2_nxv16i32(<vscale x 8 x i32> %vec0, <vscale x 8 x i32> %vec1) {
 ; CHECK-LABEL: interleave2_nxv16i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    zip1 z4.s, z0.s, z2.s
 ; CHECK-NEXT:    zip2 z5.s, z0.s, z2.s
 ; CHECK-NEXT:    zip1 z2.s, z1.s, z3.s
 ; CHECK-NEXT:    zip2 z3.s, z1.s, z3.s
 ; CHECK-NEXT:    mov z0.d, z4.d
 ; CHECK-NEXT:    mov z1.d, z5.d
 ; CHECK-NEXT:    ret
-  %retval = call <vscale x 16 x i32>@llvm.experimental.vector.interleave2.nxv16i32(<vscale x 8 x i32> %vec0, <vscale x 8 x i32> %vec1)
+  %retval = call <vscale x 16 x i32>(...) @llvm.experimental.vector.interleave.nxv16i32.nxv8i32(<vscale x 8 x i32> %vec0, <vscale x 8 x i32> %vec1)
   ret <vscale x 16 x i32> %retval
 }
 
 define <vscale x 8 x i64> @interleave2_nxv8i64(<vscale x 4 x i64> %vec0, <vscale x 4 x i64> %vec1) {
 ; CHECK-LABEL: interleave2_nxv8i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    zip1 z4.d, z0.d, z2.d
 ; CHECK-NEXT:    zip2 z5.d, z0.d, z2.d
 ; CHECK-NEXT:    zip1 z2.d, z1.d, z3.d
 ; CHECK-NEXT:    zip2 z3.d, z1.d, z3.d
 ; CHECK-NEXT:    mov z0.d, z4.d
 ; CHECK-NEXT:    mov z1.d, z5.d
 ; CHECK-NEXT:    ret
-  %retval = call <vscale x 8 x i64> @llvm.experimental.vector.interleave2.nxv8i64(<vscale x 4 x i64> %vec0, <vscale x 4 x i64> %vec1)
+  %retval = call <vscale x 8 x i64>(...) @llvm.experimental.vector.interleave.nxv8i64.nxv4i64(<vscale x 4 x i64> %vec0, <vscale x 4 x i64> %vec1)
   ret <vscale x 8 x i64> %retval
 }
 
 ; Promote illegal type size
 
 define <vscale x 16 x i8> @interleave2_nxv8i8(<vscale x 8 x i8> %vec0, <vscale x 8 x i8> %vec1) {
 ; CHECK-LABEL: interleave2_nxv8i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    zip2 z2.h, z0.h, z1.h
 ; CHECK-NEXT:    zip1 z0.h, z0.h, z1.h
 ; CHECK-NEXT:    uzp1 z0.b, z0.b, z2.b
 ; CHECK-NEXT:    ret
-  %retval = call <vscale x 16 x i8> @llvm.experimental.vector.interleave2.nxv16i8(<vscale x 8 x i8> %vec0, <vscale x 8 x i8> %vec1)
+  %retval = call <vscale x 16 x i8>(...) @llvm.experimental.vector.interleave.nxv16i8.nxv8i8(<vscale x 8 x i8> %vec0, <vscale x 8 x i8> %vec1)
   ret <vscale x 16 x i8> %retval
 }
 
 define <vscale x 8 x i16> @interleave2_nxv4i16(<vscale x 4 x i16> %vec0, <vscale x 4 x i16> %vec1) {
 ; CHECK-LABEL: interleave2_nxv4i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    zip2 z2.s, z0.s, z1.s
 ; CHECK-NEXT:    zip1 z0.s, z0.s, z1.s
 ; CHECK-NEXT:    uzp1 z0.h, z0.h, z2.h
 ; CHECK-NEXT:    ret
-  %retval = call <vscale x 8 x i16> @llvm.experimental.vector.interleave2.nxv8i16(<vscale x 4 x i16> %vec0, <vscale x 4 x i16> %vec1)
+  %retval = call <vscale x 8 x i16>(...) @llvm.experimental.vector.interleave.nxv8i16.nxv4i16(<vscale x 4 x i16> %vec0, <vscale x 4 x i16> %vec1)
   ret <vscale x 8 x i16> %retval
 }
 
 define <vscale x 4 x i32> @interleave2_nxv2i32(<vscale x 2 x i32> %vec0, <vscale x 2 x i32> %vec1) {
 ; CHECK-LABEL: interleave2_nxv2i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    zip2 z2.d, z0.d, z1.d
 ; CHECK-NEXT:    zip1 z0.d, z0.d, z1.d
 ; CHECK-NEXT:    uzp1 z0.s, z0.s, z2.s
 ; CHECK-NEXT:    ret
-  %retval = call <vscale x 4 x i32> @llvm.experimental.vector.interleave2.nxv4i32(<vscale x 2 x i32> %vec0, <vscale x 2 x i32> %vec1)
+  %retval = call <vscale x 4 x i32>(...) @llvm.experimental.vector.interleave.nxv4i32.nxv2i32(<vscale x 2 x i32> %vec0, <vscale x 2 x i32> %vec1)
   ret <vscale x 4 x i32> %retval
 }
 
 ; Float declarations
-declare <vscale x 4 x half> @llvm.experimental.vector.interleave2.nxv4f16(<vscale x 2 x half>, <vscale x 2 x half>)
-declare <vscale x 8 x half> @llvm.experimental.vector.interleave2.nxv8f16(<vscale x 4 x half>, <vscale x 4 x half>)
-declare <vscale x 16 x half> @llvm.experimental.vector.interleave2.nxv16f16(<vscale x 8 x half>, <vscale x 8 x half>)
-declare <vscale x 4 x float> @llvm.experimental.vector.interleave2.nxv4f32(<vscale x 2 x float>, <vscale x 2 x float>)
-declare <vscale x 8 x float> @llvm.experimental.vector.interleave2.nxv8f32(<vscale x 4 x float>, <vscale x 4 x float>)
-declare <vscale x 4 x double> @llvm.experimental.vector.interleave2.nxv4f64(<vscale x 2 x double>, <vscale x 2 x double>)
+declare <vscale x 4 x half> @llvm.experimental.vector.interleave.nxv4f16.nxv2f16(...)
+declare <vscale x 8 x half> @llvm.experimental.vector.interleave.nxv8f16.nxv4f16(...)
+declare <vscale x 16 x half> @llvm.experimental.vector.interleave.nxv16f16.nxv8f16(...)
+declare <vscale x 4 x float> @llvm.experimental.vector.interleave.nxv4f32.nxv2f32(...)
+declare <vscale x 8 x float> @llvm.experimental.vector.interleave.nxv8f32.nxv4f32(...)
+declare <vscale x 4 x double> @llvm.experimental.vector.interleave.nxv4f64.nxv2f64(...)
 
 ; Integer declarations
-declare <vscale x 32 x i8> @llvm.experimental.vector.interleave2.nxv32i8(<vscale x 16 x i8>, <vscale x 16 x i8>)
-declare <vscale x 16 x i16> @llvm.experimental.vector.interleave2.nxv16i16(<vscale x 8 x i16>, <vscale x 8 x i16>)
-declare <vscale x 8 x i32> @llvm.experimental.vector.interleave2.nxv8i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
-declare <vscale x 4 x i64> @llvm.experimental.vector.interleave2.nxv4i64(<vscale x 2 x i64>, <vscale x 2 x i64>)
+declare <vscale x 32 x i8> @llvm.experimental.vector.interleave.nxv32i8.nxv16i8(...)
+declare <vscale x 16 x i16> @llvm.experimental.vector.interleave.nxv16i16.nxv8i16(...)
+declare <vscale x 8 x i32> @llvm.experimental.vector.interleave.nxv8i32.nxv4i32(...)
+declare <vscale x 4 x i64> @llvm.experimental.vector.interleave.nxv4i64.nxv2i64(...)
 
 ; Predicated
-declare <vscale x 32 x i1> @llvm.experimental.vector.interleave2.nxv32i1(<vscale x 16 x i1>, <vscale x 16 x i1>)
-declare <vscale x 16 x i1> @llvm.experimental.vector.interleave2.nxv16i1(<vscale x 8 x i1>, <vscale x 8 x i1>)
-declare <vscale x 8 x i1> @llvm.experimental.vector.interleave2.nxv8i1(<vscale x 4 x i1>, <vscale x 4 x i1>)
-declare <vscale x 4 x i1> @llvm.experimental.vector.interleave2.nxv4i1(<vscale x 2 x i1>, <vscale x 2 x i1>)
+declare <vscale x 32 x i1> @llvm.experimental.vector.interleave.nxv32i1.nxv16i1(...)
+declare <vscale x 16 x i1> @llvm.experimental.vector.interleave.nxv16i1.nxv8i1(...)
+declare <vscale x 8 x i1> @llvm.experimental.vector.interleave.nxv8i1.nxv4i1(...)
+declare <vscale x 4 x i1> @llvm.experimental.vector.interleave.nxv4i1.nxv2i1(...)
 
 ; Illegal type size
-declare <vscale x 16 x i32> @llvm.experimental.vector.interleave2.nxv16i32(<vscale x 8 x i32>, <vscale x 8 x i32>)
-declare <vscale x 8 x i64> @llvm.experimental.vector.interleave2.nxv8i64(<vscale x 4 x i64>, <vscale x 4 x i64>)
+declare <vscale x 16 x i32> @llvm.experimental.vector.interleave.nxv16i32.nxv8i32(...)
+declare <vscale x 8 x i64> @llvm.experimental.vector.interleave.nxv8i64.nxv4i64(...)
 
-declare <vscale x 16 x i8> @llvm.experimental.vector.interleave2.nxv16i8(<vscale x 8 x i8>, <vscale x 8 x i8>)
-declare <vscale x 8 x i16> @llvm.experimental.vector.interleave2.nxv8i16(<vscale x 4 x i16>, <vscale x 4 x i16>)
-declare <vscale x 4 x i32> @llvm.experimental.vector.interleave2.nxv4i32(<vscale x 2 x i32>, <vscale x 2 x i32>)
+declare <vscale x 16 x i8> @llvm.experimental.vector.interleave.nxv16i8.nxv8i8(...)
+declare <vscale x 8 x i16> @llvm.experimental.vector.interleave.nxv8i16.nxv4i16(...)
+declare <vscale x 4 x i32> @llvm.experimental.vector.interleave.nxv4i32.nxv2i32(...)

llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll

 ; RV64-NEXT:    mv a0, sp
 ; RV64-NEXT:    vle8.v v9, (a0)
 ; RV64-NEXT:    vand.vi v8, v8, 1
 ; RV64-NEXT:    vmsne.vi v0, v8, 0
 ; RV64-NEXT:    vand.vi v8, v9, 1
 ; RV64-NEXT:    vmsne.vi v8, v8, 0
 ; RV64-NEXT:    addi sp, sp, 32
 ; RV64-NEXT:    ret
-%retval = call {<16 x i1>, <16 x i1>} @llvm.experimental.vector.deinterleave2.v32i1(<32 x i1> %vec)
+%retval = call {<16 x i1>, <16 x i1>} @llvm.experimental.vector.deinterleave.v16i1.v32i1(<32 x i1> %vec)
 ret {<16 x i1>, <16 x i1>} %retval
 }
 
 define {<16 x i8>, <16 x i8>} @vector_deinterleave_v16i8_v32i8(<32 x i8> %vec) {
 ; CHECK-LABEL: vector_deinterleave_v16i8_v32i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
 ; CHECK-NEXT:    vnsrl.wi v10, v8, 0
 ; CHECK-NEXT:    vnsrl.wi v11, v8, 8
 ; CHECK-NEXT:    vmv.v.v v8, v10
 ; CHECK-NEXT:    vmv.v.v v9, v11
 ; CHECK-NEXT:    ret
-%retval = call {<16 x i8>, <16 x i8>} @llvm.experimental.vector.deinterleave2.v32i8(<32 x i8> %vec)
+%retval = call {<16 x i8>, <16 x i8>} @llvm.experimental.vector.deinterleave.v16i8.v32i8(<32 x i8> %vec)
 ret {<16 x i8>, <16 x i8>} %retval
 }
 
 define {<8 x i16>, <8 x i16>} @vector_deinterleave_v8i16_v16i16(<16 x i16> %vec) {
 ; CHECK-LABEL: vector_deinterleave_v8i16_v16i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
 ; CHECK-NEXT:    vnsrl.wi v10, v8, 0
 ; CHECK-NEXT:    vnsrl.wi v11, v8, 16
 ; CHECK-NEXT:    vmv.v.v v8, v10
 ; CHECK-NEXT:    vmv.v.v v9, v11
 ; CHECK-NEXT:    ret
-%retval = call {<8 x i16>, <8 x i16>} @llvm.experimental.vector.deinterleave2.v16i16(<16 x i16> %vec)
+%retval = call {<8 x i16>, <8 x i16>} @llvm.experimental.vector.deinterleave.v8i16.v16i16(<16 x i16> %vec)
 ret {<8 x i16>, <8 x i16>} %retval
 }
 
 define {<4 x i32>, <4 x i32>} @vector_deinterleave_v4i32_vv8i32(<8 x i32> %vec) {
 ; CHECK-LABEL: vector_deinterleave_v4i32_vv8i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    li a0, 32
 ; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
 ; CHECK-NEXT:    vnsrl.wx v10, v8, a0
 ; CHECK-NEXT:    vnsrl.wi v11, v8, 0
 ; CHECK-NEXT:    vmv.v.v v8, v11
 ; CHECK-NEXT:    vmv.v.v v9, v10
 ; CHECK-NEXT:    ret
-%retval = call {<4 x i32>, <4 x i32>} @llvm.experimental.vector.deinterleave2.v8i32(<8 x i32> %vec)
+%retval = call {<4 x i32>, <4 x i32>} @llvm.experimental.vector.deinterleave.v4i32.v8i32(<8 x i32> %vec)
 ret {<4 x i32>, <4 x i32>} %retval
 }
 
 define {<2 x i64>, <2 x i64>} @vector_deinterleave_v2i64_v4i64(<4 x i64> %vec) {
 ; CHECK-LABEL: vector_deinterleave_v2i64_v4i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 2, e64, m2, ta, ma
 ; CHECK-NEXT:    vslidedown.vi v12, v8, 2
 ; CHECK-NEXT:    li a0, 2
 ; CHECK-NEXT:    vmv.s.x v0, a0
 ; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, mu
 ; CHECK-NEXT:    vrgather.vi v10, v8, 0
 ; CHECK-NEXT:    vrgather.vi v10, v12, 0, v0.t
 ; CHECK-NEXT:    vrgather.vi v11, v8, 1
 ; CHECK-NEXT:    vrgather.vi v11, v12, 1, v0.t
 ; CHECK-NEXT:    vmv.v.v v8, v10
 ; CHECK-NEXT:    vmv.v.v v9, v11
 ; CHECK-NEXT:    ret
-%retval = call {<2 x i64>, <2 x i64>} @llvm.experimental.vector.deinterleave2.v4i64(<4 x i64> %vec)
+%retval = call {<2 x i64>, <2 x i64>} @llvm.experimental.vector.deinterleave.v2i64.v4i64(<4 x i64> %vec)
 ret {<2 x i64>, <2 x i64>} %retval
 }
 
-declare {<16 x i1>, <16 x i1>} @llvm.experimental.vector.deinterleave2.v32i1(<32 x i1>)
-declare {<16 x i8>, <16 x i8>} @llvm.experimental.vector.deinterleave2.v32i8(<32 x i8>)
-declare {<8 x i16>, <8 x i16>} @llvm.experimental.vector.deinterleave2.v16i16(<16 x i16>)
-declare {<4 x i32>, <4 x i32>} @llvm.experimental.vector.deinterleave2.v8i32(<8 x i32>)
-declare {<2 x i64>, <2 x i64>} @llvm.experimental.vector.deinterleave2.v4i64(<4 x i64>)
+define {<2 x i64>, <2 x i64>, <2 x i64>} @vector_deinterleave_v2i64_v6i64(<6 x i64> %vec) {
+; RV32-LABEL: vector_deinterleave_v2i64_v6i64:
+; RV32:       # %bb.0:
+; RV32-NEXT:    addi sp, sp, -96
+; RV32-NEXT:    .cfi_def_cfa_offset 96
+; RV32-NEXT:    sw ra, 92(sp) # 4-byte Folded Spill
+; RV32-NEXT:    sw s0, 88(sp) # 4-byte Folded Spill
+; RV32-NEXT:    .cfi_offset ra, -4
+; RV32-NEXT:    .cfi_offset s0, -8
+; RV32-NEXT:    addi s0, sp, 96
+; RV32-NEXT:    .cfi_def_cfa s0, 0
+; RV32-NEXT:    andi sp, sp, -32
+; RV32-NEXT:    vsetivli zero, 1, e64, m4, ta, ma
+; RV32-NEXT:    vslidedown.vi v12, v8, 4
+; RV32-NEXT:    vmv.x.s a0, v12
+; RV32-NEXT:    sw a0, 24(sp)
+; RV32-NEXT:    vslidedown.vi v16, v8, 3
+; RV32-NEXT:    vmv.x.s a1, v16
+; RV32-NEXT:    sw a1, 16(sp)
+; RV32-NEXT:    li a2, 32
+; RV32-NEXT:    vsrl.vx v12, v12, a2
+; RV32-NEXT:    vmv.x.s a3, v12
+; RV32-NEXT:    sw a3, 28(sp)
+; RV32-NEXT:    vsrl.vx v12, v16, a2
+; RV32-NEXT:    vmv.x.s a4, v12
+; RV32-NEXT:    sw a4, 20(sp)
+; RV32-NEXT:    vslidedown.vi v12, v8, 5
+; RV32-NEXT:    vmv.x.s a5, v12
+; RV32-NEXT:    sw a5, 48(sp)
+; RV32-NEXT:    sw a0, 40(sp)
+; RV32-NEXT:    sw a1, 32(sp)
+; RV32-NEXT:    vsrl.vx v12, v12, a2
+; RV32-NEXT:    vmv.x.s a0, v12
+; RV32-NEXT:    sw a0, 52(sp)
+; RV32-NEXT:    sw a3, 44(sp)
+; RV32-NEXT:    sw a4, 36(sp)
+; RV32-NEXT:    li a0, 2
+; RV32-NEXT:    vmv.s.x v0, a0
+; RV32-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
+; RV32-NEXT:    vrgather.vi v12, v8, 0
+; RV32-NEXT:    addi a0, sp, 16
+; RV32-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
+; RV32-NEXT:    vle32.v v14, (a0)
+; RV32-NEXT:    vsetivli zero, 2, e64, m1, ta, mu
+; RV32-NEXT:    vrgather.vi v12, v14, 0, v0.t
+; RV32-NEXT:    vrgather.vi v13, v8, 1
+; RV32-NEXT:    vrgather.vi v13, v14, 1, v0.t
+; RV32-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
+; RV32-NEXT:    vrgather.vi v14, v8, 2
+; RV32-NEXT:    addi a0, sp, 32
+; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
+; RV32-NEXT:    vle32.v v8, (a0)
+; RV32-NEXT:    vsetivli zero, 4, e64, m2, ta, mu
+; RV32-NEXT:    vrgather.vi v14, v8, 2, v0.t
+; RV32-NEXT:    vmv1r.v v8, v12
+; RV32-NEXT:    vmv1r.v v9, v13
+; RV32-NEXT:    vmv1r.v v10, v14
+; RV32-NEXT:    addi sp, s0, -96
+; RV32-NEXT:    lw ra, 92(sp) # 4-byte Folded Reload
+; RV32-NEXT:    lw s0, 88(sp) # 4-byte Folded Reload
+; RV32-NEXT:    addi sp, sp, 96
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vector_deinterleave_v2i64_v6i64:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vsetivli zero, 1, e64, m4, ta, ma
+; RV64-NEXT:    vslidedown.vi v12, v8, 3
+; RV64-NEXT:    vmv.x.s a0, v12
+; RV64-NEXT:    vsetivli zero, 2, e64, m1, ta, mu
+; RV64-NEXT:    vmv.v.x v13, a0
+; RV64-NEXT:    li a0, 2
+; RV64-NEXT:    vmv.s.x v0, a0
+; RV64-NEXT:    vrgather.vi v12, v8, 0
+; RV64-NEXT:    vrgather.vi v12, v13, 0, v0.t
+; RV64-NEXT:    vsetivli zero, 1, e64, m4, ta, ma
+; RV64-NEXT:    vslidedown.vi v16, v8, 4
+; RV64-NEXT:    vmv.x.s a0, v16
+; RV64-NEXT:    vsetivli zero, 2, e64, m1, ta, mu
+; RV64-NEXT:    vmv.v.x v14, a0
+; RV64-NEXT:    vrgather.vi v13, v8, 1
+; RV64-NEXT:    vrgather.vi v13, v14, 1, v0.t
+; RV64-NEXT:    li a0, 1
+; RV64-NEXT:    vmv.s.x v0, a0
+; RV64-NEXT:    vsetivli zero, 4, e64, m4, ta, ma
+; RV64-NEXT:    vslidedown.vi v16, v8, 4
+; RV64-NEXT:    vsetivli zero, 1, e64, m2, ta, ma
+; RV64-NEXT:    vslidedown.vi v14, v16, 1
+; RV64-NEXT:    vmv.x.s a0, v14
+; RV64-NEXT:    vsetivli zero, 4, e64, m2, ta, mu
+; RV64-NEXT:    vmv.v.x v14, a0
+; RV64-NEXT:    vrgather.vi v14, v8, 2, v0.t
+; RV64-NEXT:    vmv1r.v v8, v12
+; RV64-NEXT:    vmv1r.v v9, v13
+; RV64-NEXT:    vmv1r.v v10, v14
+; RV64-NEXT:    ret
+%retval = call {<2 x i64>, <2 x i64>, <2 x i64>} @llvm.experimental.vector.deinterleave.v2i64.v6i64(<6 x i64> %vec)
+ret {<2 x i64>, <2 x i64>, <2 x i64>} %retval
+}
+
+declare {<16 x i1>, <16 x i1>} @llvm.experimental.vector.deinterleave.v16i1.v32i1(<32 x i1>)
+declare {<16 x i8>, <16 x i8>} @llvm.experimental.vector.deinterleave.v16i8.v32i8(<32 x i8>)
+declare {<8 x i16>, <8 x i16>} @llvm.experimental.vector.deinterleave.v8i16.v16i16(<16 x i16>)
+declare {<4 x i32>, <4 x i32>} @llvm.experimental.vector.deinterleave.v4i32.v8i32(<8 x i32>)
+declare {<2 x i64>, <2 x i64>} @llvm.experimental.vector.deinterleave.v2i64.v4i64(<4 x i64>)
+declare {<2 x i64>, <2 x i64>, <2 x i64>} @llvm.experimental.vector.deinterleave.v2i64.v6i64(<6 x i64>)
 
 ; Floats
 
 define {<2 x half>, <2 x half>} @vector_deinterleave_v2f16_v4f16(<4 x half> %vec) {
 ; CHECK-LABEL: vector_deinterleave_v2f16_v4f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
 ; CHECK-NEXT:    vnsrl.wi v10, v8, 0
 ; CHECK-NEXT:    vnsrl.wi v9, v8, 16
 ; CHECK-NEXT:    vmv1r.v v8, v10
 ; CHECK-NEXT:    ret
-%retval = call {<2 x half>, <2 x half>} @llvm.experimental.vector.deinterleave2.v4f16(<4 x half> %vec)
+%retval = call {<2 x half>, <2 x half>} @llvm.experimental.vector.deinterleave.v2f16.v4f16(<4 x half> %vec)
 ret {<2 x half>, <2 x half>} %retval
 }
 
 define {<4 x half>, <4 x half>} @vector_deinterleave_v4f16_v8f16(<8 x half> %vec) {
 ; CHECK-LABEL: vector_deinterleave_v4f16_v8f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
 ; CHECK-NEXT:    vnsrl.wi v10, v8, 0
 ; CHECK-NEXT:    vnsrl.wi v9, v8, 16
 ; CHECK-NEXT:    vmv1r.v v8, v10
 ; CHECK-NEXT:    ret
-%retval = call {<4 x half>, <4 x half>} @llvm.experimental.vector.deinterleave2.v8f16(<8 x half> %vec)
+%retval = call {<4 x half>, <4 x half>} @llvm.experimental.vector.deinterleave.v4f16.v8f16(<8 x half> %vec)
 ret {<4 x half>, <4 x half>} %retval
 }
 
 define {<2 x float>, <2 x float>} @vector_deinterleave_v2f32_v4f32(<4 x float> %vec) {
 ; CHECK-LABEL: vector_deinterleave_v2f32_v4f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    li a0, 32
 ; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
 ; CHECK-NEXT:    vnsrl.wx v9, v8, a0
 ; CHECK-NEXT:    vnsrl.wi v8, v8, 0
 ; CHECK-NEXT:    ret
-%retval = call {<2 x float>, <2 x float>} @llvm.experimental.vector.deinterleave2.v4f32(<4 x float> %vec)
+%retval = call {<2 x float>, <2 x float>} @llvm.experimental.vector.deinterleave.v2f32.v4f32(<4 x float> %vec)
 ret {<2 x float>, <2 x float>} %retval
 }
 
 define {<8 x half>, <8 x half>} @vector_deinterleave_v8f16_v16f16(<16 x half> %vec) {
 ; CHECK-LABEL: vector_deinterleave_v8f16_v16f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
 ; CHECK-NEXT:    vnsrl.wi v10, v8, 0
 ; CHECK-NEXT:    vnsrl.wi v11, v8, 16
 ; CHECK-NEXT:    vmv.v.v v8, v10
 ; CHECK-NEXT:    vmv.v.v v9, v11
 ; CHECK-NEXT:    ret
-%retval = call {<8 x half>, <8 x half>} @llvm.experimental.vector.deinterleave2.v16f16(<16 x half> %vec)
+%retval = call {<8 x half>, <8 x half>} @llvm.experimental.vector.deinterleave.v8f16.v16f16(<16 x half> %vec)
 ret {<8 x half>, <8 x half>} %retval
 }
 
 define {<4 x float>, <4 x float>} @vector_deinterleave_v4f32_v8f32(<8 x float> %vec) {
 ; CHECK-LABEL: vector_deinterleave_v4f32_v8f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    li a0, 32
 ; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
 ; CHECK-NEXT:    vnsrl.wx v10, v8, a0
 ; CHECK-NEXT:    vnsrl.wi v11, v8, 0
 ; CHECK-NEXT:    vmv.v.v v8, v11
 ; CHECK-NEXT:    vmv.v.v v9, v10
 ; CHECK-NEXT:    ret
-%retval = call {<4 x float>, <4 x float>} @llvm.experimental.vector.deinterleave2.v8f32(<8 x float> %vec)
+%retval = call {<4 x float>, <4 x float>} @llvm.experimental.vector.deinterleave.v4f32.v8f32(<8 x float> %vec)
 ret  {<4 x float>, <4 x float>} %retval
 }
 
 define {<2 x double>, <2 x double>} @vector_deinterleave_v2f64_v4f64(<4 x double> %vec) {
 ; CHECK-LABEL: vector_deinterleave_v2f64_v4f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 2, e64, m2, ta, ma
 ; CHECK-NEXT:    vslidedown.vi v12, v8, 2
 ; CHECK-NEXT:    li a0, 2
 ; CHECK-NEXT:    vmv.s.x v0, a0
 ; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, mu
 ; CHECK-NEXT:    vrgather.vi v10, v8, 0
 ; CHECK-NEXT:    vrgather.vi v10, v12, 0, v0.t
 ; CHECK-NEXT:    vrgather.vi v11, v8, 1
 ; CHECK-NEXT:    vrgather.vi v11, v12, 1, v0.t
 ; CHECK-NEXT:    vmv.v.v v8, v10
 ; CHECK-NEXT:    vmv.v.v v9, v11
 ; CHECK-NEXT:    ret
-%retval = call {<2 x double>, <2 x double>} @llvm.experimental.vector.deinterleave2.v4f64(<4 x double> %vec)
+%retval = call {<2 x double>, <2 x double>} @llvm.experimental.vector.deinterleave.v2f64.v4f64(<4 x double> %vec)
 ret {<2 x double>, <2 x double>} %retval
 }
 
-declare {<2 x half>,<2 x half>} @llvm.experimental.vector.deinterleave2.v4f16(<4 x half>)
-declare {<4 x half>, <4 x half>} @llvm.experimental.vector.deinterleave2.v8f16(<8 x half>)
-declare {<2 x float>, <2 x float>} @llvm.experimental.vector.deinterleave2.v4f32(<4 x float>)
-declare {<8 x half>, <8 x half>} @llvm.experimental.vector.deinterleave2.v16f16(<16 x half>)
-declare {<4 x float>, <4 x float>} @llvm.experimental.vector.deinterleave2.v8f32(<8 x float>)
-declare {<2 x double>, <2 x double>} @llvm.experimental.vector.deinterleave2.v4f64(<4 x double>)
+declare {<2 x half>,<2 x half>} @llvm.experimental.vector.deinterleave.v2f16.v4f16(<4 x half>)
+declare {<4 x half>, <4 x half>} @llvm.experimental.vector.deinterleave.v4f16.v8f16(<8 x half>)
+declare {<2 x float>, <2 x float>} @llvm.experimental.vector.deinterleave.v2f32.v4f32(<4 x float>)
+declare {<8 x half>, <8 x half>} @llvm.experimental.vector.deinterleave.v8f16.v16f16(<16 x half>)
+declare {<4 x float>, <4 x float>} @llvm.experimental.vector.deinterleave.v4f32.v8f32(<8 x float>)
+declare {<2 x double>, <2 x double>} @llvm.experimental.vector.deinterleave.v2f64.v4f64(<4 x double>)

llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll

 ; CHECK-NEXT:    vmerge.vim v12, v10, 1, v0
 ; CHECK-NEXT:    vnsrl.wi v8, v12, 0
 ; CHECK-NEXT:    vand.vi v8, v8, 1
 ; CHECK-NEXT:    vmsne.vi v0, v8, 0
 ; CHECK-NEXT:    vnsrl.wi v8, v12, 8
 ; CHECK-NEXT:    vand.vi v10, v8, 1
 ; CHECK-NEXT:    vmsne.vi v8, v10, 0
 ; CHECK-NEXT:    ret
-%retval = call {<vscale x 16 x i1>, <vscale x 16 x i1>} @llvm.experimental.vector.deinterleave2.nxv32i1(<vscale x 32 x i1> %vec)
+%retval = call {<vscale x 16 x i1>, <vscale x 16 x i1>} @llvm.experimental.vector.deinterleave.nxv16i1.nxv32i1(<vscale x 32 x i1> %vec)
 ret {<vscale x 16 x i1>, <vscale x 16 x i1>} %retval
 }
 
 define {<vscale x 16 x i8>, <vscale x 16 x i8>} @vector_deinterleave_nxv16i8_nxv32i8(<vscale x 32 x i8> %vec) {
 ; CHECK-LABEL: vector_deinterleave_nxv16i8_nxv32i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, ma
 ; CHECK-NEXT:    vnsrl.wi v12, v8, 0
 ; CHECK-NEXT:    vnsrl.wi v14, v8, 8
 ; CHECK-NEXT:    vmv.v.v v8, v12
 ; CHECK-NEXT:    vmv.v.v v10, v14
 ; CHECK-NEXT:    ret
-%retval = call {<vscale x 16 x i8>, <vscale x 16 x i8>} @llvm.experimental.vector.deinterleave2.nxv32i8(<vscale x 32 x i8> %vec)
+%retval = call {<vscale x 16 x i8>, <vscale x 16 x i8>} @llvm.experimental.vector.deinterleave.nxv16i8.nxv32i8(<vscale x 32 x i8> %vec)
 ret {<vscale x 16 x i8>, <vscale x 16 x i8>} %retval
 }
 
 define {<vscale x 8 x i16>, <vscale x 8 x i16>} @vector_deinterleave_nxv8i16_nxv16i16(<vscale x 16 x i16> %vec) {
 ; CHECK-LABEL: vector_deinterleave_nxv8i16_nxv16i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
 ; CHECK-NEXT:    vnsrl.wi v12, v8, 0
 ; CHECK-NEXT:    vnsrl.wi v14, v8, 16
 ; CHECK-NEXT:    vmv.v.v v8, v12
 ; CHECK-NEXT:    vmv.v.v v10, v14
 ; CHECK-NEXT:    ret
-%retval = call {<vscale x 8 x i16>, <vscale x 8 x i16>} @llvm.experimental.vector.deinterleave2.nxv16i16(<vscale x 16 x i16> %vec)
+%retval = call {<vscale x 8 x i16>, <vscale x 8 x i16>} @llvm.experimental.vector.deinterleave.nxv8i16.nxv16i16(<vscale x 16 x i16> %vec)
 ret {<vscale x 8 x i16>, <vscale x 8 x i16>} %retval
 }
 
 define {<vscale x 4 x i32>, <vscale x 4 x i32>} @vector_deinterleave_nxv4i32_nxvv8i32(<vscale x 8 x i32> %vec) {
 ; CHECK-LABEL: vector_deinterleave_nxv4i32_nxvv8i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    li a0, 32
 ; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
 ; CHECK-NEXT:    vnsrl.wx v12, v8, a0
 ; CHECK-NEXT:    vnsrl.wi v14, v8, 0
 ; CHECK-NEXT:    vmv.v.v v8, v14
 ; CHECK-NEXT:    vmv.v.v v10, v12
 ; CHECK-NEXT:    ret
-%retval = call {<vscale x 4 x i32>, <vscale x 4 x i32>} @llvm.experimental.vector.deinterleave2.nxv8i32(<vscale x 8 x i32> %vec)
+%retval = call {<vscale x 4 x i32>, <vscale x 4 x i32>} @llvm.experimental.vector.deinterleave.nxv4i32.nxv8i32(<vscale x 8 x i32> %vec)
 ret {<vscale x 4 x i32>, <vscale x 4 x i32>} %retval
 }
 
 define {<vscale x 2 x i64>, <vscale x 2 x i64>} @vector_deinterleave_nxv2i64_nxv4i64(<vscale x 4 x i64> %vec) {
 ; CHECK-LABEL: vector_deinterleave_nxv2i64_nxv4i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
 ; CHECK-NEXT:    vid.v v12
 ; CHECK-NEXT:    vadd.vv v16, v12, v12
 ; CHECK-NEXT:    vrgather.vv v12, v8, v16
 ; CHECK-NEXT:    vadd.vi v16, v16, 1
 ; CHECK-NEXT:    vrgather.vv v20, v8, v16
 ; CHECK-NEXT:    vmv2r.v v8, v12
 ; CHECK-NEXT:    vmv2r.v v10, v20
 ; CHECK-NEXT:    ret
-%retval = call {<vscale x 2 x i64>, <vscale x 2 x i64>} @llvm.experimental.vector.deinterleave2.nxv4i64(<vscale x 4 x i64> %vec)
+%retval = call {<vscale x 2 x i64>, <vscale x 2 x i64>} @llvm.experimental.vector.deinterleave.nxv2i64.nxv4i64(<vscale x 4 x i64> %vec)
 ret {<vscale x 2 x i64>, <vscale x 2 x i64>} %retval
 }
 
-declare {<vscale x 16 x i1>, <vscale x 16 x i1>} @llvm.experimental.vector.deinterleave2.nxv32i1(<vscale x 32 x i1>)
-declare {<vscale x 16 x i8>, <vscale x 16 x i8>} @llvm.experimental.vector.deinterleave2.nxv32i8(<vscale x 32 x i8>)
-declare {<vscale x 8 x i16>, <vscale x 8 x i16>} @llvm.experimental.vector.deinterleave2.nxv16i16(<vscale x 16 x i16>)
-declare {<vscale x 4 x i32>, <vscale x 4 x i32>} @llvm.experimental.vector.deinterleave2.nxv8i32(<vscale x 8 x i32>)
-declare {<vscale x 2 x i64>, <vscale x 2 x i64>} @llvm.experimental.vector.deinterleave2.nxv4i64(<vscale x 4 x i64>)
+declare {<vscale x 16 x i1>, <vscale x 16 x i1>} @llvm.experimental.vector.deinterleave.nxv16i1.nxv32i1(<vscale x 32 x i1>)
+declare {<vscale x 16 x i8>, <vscale x 16 x i8>} @llvm.experimental.vector.deinterleave.nxv16i8.nxv32i8(<vscale x 32 x i8>)
+declare {<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>} @llvm.experimental.vector.deinterleave.nxv4i8.nxv12i8(<vscale x 12 x i8>)
+declare {<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>} @llvm.experimental.vector.deinterleave.nxv1i8.nxv5i8(<vscale x 5 x i8>)
+declare {<vscale x 8 x i16>, <vscale x 8 x i16>} @llvm.experimental.vector.deinterleave.nxv8i16.nxv16i16(<vscale x 16 x i16>)
+declare {<vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>} @llvm.experimental.vector.deinterleave.nxv4i16.nxv16i16(<vscale x 16 x i16>)
+declare {<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>} @llvm.experimental.vector.deinterleave.nxv2i32.nxv6i32(<vscale x 6 x i32>)
+declare {<vscale x 4 x i32>, <vscale x 4 x i32>} @llvm.experimental.vector.deinterleave.nxv4i32.nxv8i32(<vscale x 8 x i32>)
+declare {<vscale x 2 x i64>, <vscale x 2 x i64>} @llvm.experimental.vector.deinterleave.nxv2i64.nxv4i64(<vscale x 4 x i64>)
 
 ; Floats
 
 define {<vscale x 2 x half>, <vscale x 2 x half>} @vector_deinterleave_nxv2f16_nxv4f16(<vscale x 4 x half> %vec) {
 ; CHECK-LABEL: vector_deinterleave_nxv2f16_nxv4f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
 ; CHECK-NEXT:    vnsrl.wi v10, v8, 0
 ; CHECK-NEXT:    vnsrl.wi v9, v8, 16
 ; CHECK-NEXT:    vmv1r.v v8, v10
 ; CHECK-NEXT:    ret
-%retval = call {<vscale x 2 x half>, <vscale x 2 x half>} @llvm.experimental.vector.deinterleave2.nxv4f16(<vscale x 4 x half> %vec)
+%retval = call {<vscale x 2 x half>, <vscale x 2 x half>} @llvm.experimental.vector.deinterleave.nxv2f16.nxv4f16(<vscale x 4 x half> %vec)
 ret {<vscale x 2 x half>, <vscale x 2 x half>} %retval
 }
 
 define {<vscale x 4 x half>, <vscale x 4 x half>} @vector_deinterleave_nxv4f16_nxv8f16(<vscale x 8 x half> %vec) {
 ; CHECK-LABEL: vector_deinterleave_nxv4f16_nxv8f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
 ; CHECK-NEXT:    vnsrl.wi v10, v8, 0
 ; CHECK-NEXT:    vnsrl.wi v11, v8, 16
 ; CHECK-NEXT:    vmv.v.v v8, v10
 ; CHECK-NEXT:    vmv.v.v v9, v11
 ; CHECK-NEXT:    ret
-%retval = call {<vscale x 4 x half>, <vscale x 4 x half>} @llvm.experimental.vector.deinterleave2.nxv8f16(<vscale x 8 x half> %vec)
+%retval = call {<vscale x 4 x half>, <vscale x 4 x half>} @llvm.experimental.vector.deinterleave.nxv4f16.nxv8f16(<vscale x 8 x half> %vec)
 ret {<vscale x 4 x half>, <vscale x 4 x half>} %retval
 }
 
 define {<vscale x 2 x float>, <vscale x 2 x float>} @vector_deinterleave_nxv2f32_nxv4f32(<vscale x 4 x float> %vec) {
 ; CHECK-LABEL: vector_deinterleave_nxv2f32_nxv4f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    li a0, 32
 ; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
 ; CHECK-NEXT:    vnsrl.wx v10, v8, a0
 ; CHECK-NEXT:    vnsrl.wi v11, v8, 0
 ; CHECK-NEXT:    vmv.v.v v8, v11
 ; CHECK-NEXT:    vmv.v.v v9, v10
 ; CHECK-NEXT:    ret
-%retval = call {<vscale x 2 x float>, <vscale x 2 x float>} @llvm.experimental.vector.deinterleave2.nxv4f32(<vscale x 4 x float> %vec)
+%retval = call {<vscale x 2 x float>, <vscale x 2 x float>} @llvm.experimental.vector.deinterleave.nxv2f32.nxv4f32(<vscale x 4 x float> %vec)
 ret {<vscale x 2 x float>, <vscale x 2 x float>} %retval
 }
 
 define {<vscale x 8 x half>, <vscale x 8 x half>} @vector_deinterleave_nxv8f16_nxv16f16(<vscale x 16 x half> %vec) {
 ; CHECK-LABEL: vector_deinterleave_nxv8f16_nxv16f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
 ; CHECK-NEXT:    vnsrl.wi v12, v8, 0
 ; CHECK-NEXT:    vnsrl.wi v14, v8, 16
 ; CHECK-NEXT:    vmv.v.v v8, v12
 ; CHECK-NEXT:    vmv.v.v v10, v14
 ; CHECK-NEXT:    ret
-%retval = call {<vscale x 8 x half>, <vscale x 8 x half>} @llvm.experimental.vector.deinterleave2.nxv16f16(<vscale x 16 x half> %vec)
+%retval = call {<vscale x 8 x half>, <vscale x 8 x half>} @llvm.experimental.vector.deinterleave.nxv8f16.nxv16f16(<vscale x 16 x half> %vec)
 ret {<vscale x 8 x half>, <vscale x 8 x half>} %retval
 }
 
 define {<vscale x 4 x float>, <vscale x 4 x float>} @vector_deinterleave_nxv4f32_nxv8f32(<vscale x 8 x float> %vec) {
 ; CHECK-LABEL: vector_deinterleave_nxv4f32_nxv8f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    li a0, 32
 ; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
 ; CHECK-NEXT:    vnsrl.wx v12, v8, a0
 ; CHECK-NEXT:    vnsrl.wi v14, v8, 0
 ; CHECK-NEXT:    vmv.v.v v8, v14
 ; CHECK-NEXT:    vmv.v.v v10, v12
 ; CHECK-NEXT:    ret
-%retval = call {<vscale x 4 x float>, <vscale x 4 x float>} @llvm.experimental.vector.deinterleave2.nxv8f32(<vscale x 8 x float> %vec)
+%retval = call {<vscale x 4 x float>, <vscale x 4 x float>} @llvm.experimental.vector.deinterleave.nxv4f32.nxv8f32(<vscale x 8 x float> %vec)
 ret  {<vscale x 4 x float>, <vscale x 4 x float>} %retval
 }
 
 define {<vscale x 2 x double>, <vscale x 2 x double>} @vector_deinterleave_nxv2f64_nxv4f64(<vscale x 4 x double> %vec) {
 ; CHECK-LABEL: vector_deinterleave_nxv2f64_nxv4f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
 ; CHECK-NEXT:    vid.v v12
 ; CHECK-NEXT:    vadd.vv v16, v12, v12
 ; CHECK-NEXT:    vrgather.vv v12, v8, v16
 ; CHECK-NEXT:    vadd.vi v16, v16, 1
 ; CHECK-NEXT:    vrgather.vv v20, v8, v16
 ; CHECK-NEXT:    vmv2r.v v8, v12
 ; CHECK-NEXT:    vmv2r.v v10, v20
 ; CHECK-NEXT:    ret
-%retval = call {<vscale x 2 x double>, <vscale x 2 x double>} @llvm.experimental.vector.deinterleave2.nxv4f64(<vscale x 4 x double> %vec)
+%retval = call {<vscale x 2 x double>, <vscale x 2 x double>} @llvm.experimental.vector.deinterleave.nxv2f64.nxv4f64(<vscale x 4 x double> %vec)
 ret {<vscale x 2 x double>, <vscale x 2 x double>} %retval
 }
 
-declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.experimental.vector.deinterleave2.nxv4f16(<vscale x 4 x half>)
-declare {<vscale x 4 x half>, <vscale x 4 x half>} @llvm.experimental.vector.deinterleave2.nxv8f16(<vscale x 8 x half>)
-declare {<vscale x 2 x float>, <vscale x 2 x float>} @llvm.experimental.vector.deinterleave2.nxv4f32(<vscale x 4 x float>)
-declare {<vscale x 8 x half>, <vscale x 8 x half>} @llvm.experimental.vector.deinterleave2.nxv16f16(<vscale x 16 x half>)
-declare {<vscale x 4 x float>, <vscale x 4 x float>} @llvm.experimental.vector.deinterleave2.nxv8f32(<vscale x 8 x float>)
-declare {<vscale x 2 x double>, <vscale x 2 x double>} @llvm.experimental.vector.deinterleave2.nxv4f64(<vscale x 4 x double>)
+declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.experimental.vector.deinterleave.nxv2f16.nxv4f16(<vscale x 4 x half>)
+declare {<vscale x 4 x half>, <vscale x 4 x half>} @llvm.experimental.vector.deinterleave.nxv4f16.nxv8f16(<vscale x 8 x half>)
+declare {<vscale x 2 x float>, <vscale x 2 x float>} @llvm.experimental.vector.deinterleave.nxv2f32.nxv4f32(<vscale x 4 x float>)
+declare {<vscale x 8 x half>, <vscale x 8 x half>} @llvm.experimental.vector.deinterleave.nxv8f16.nxv16f16(<vscale x 16 x half>)
+declare {<vscale x 4 x float>, <vscale x 4 x float>} @llvm.experimental.vector.deinterleave.nxv4f32.nxv8f32(<vscale x 8 x float>)
+declare {<vscale x 2 x double>, <vscale x 2 x double>} @llvm.experimental.vector.deinterleave.nxv2f64.nxv4f64(<vscale x 4 x double>)

llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll

 ; RV64-NEXT:    vle8.v v8, (a1)
 ; RV64-NEXT:    vand.vi v8, v8, 1
 ; RV64-NEXT:    vmsne.vi v0, v8, 0
 ; RV64-NEXT:    addi sp, s0, -64
 ; RV64-NEXT:    ld ra, 56(sp) # 8-byte Folded Reload
 ; RV64-NEXT:    ld s0, 48(sp) # 8-byte Folded Reload
 ; RV64-NEXT:    addi sp, sp, 64
 ; RV64-NEXT:    ret
-     %res = call <32 x i1> @llvm.experimental.vector.interleave2.v32i1(<16 x i1> %a, <16 x i1> %b)
+     %res = call <32 x i1>(...) @llvm.experimental.vector.interleave.v32i1.v16i1(<16 x i1> %a, <16 x i1> %b)
      ret <32 x i1> %res
 }
 
 define <16 x i16> @vector_interleave_v16i16_v8i16(<8 x i16> %a, <8 x i16> %b) {
 ; CHECK-LABEL: vector_interleave_v16i16_v8i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
 ; CHECK-NEXT:    vwaddu.vv v10, v8, v9
 ; CHECK-NEXT:    li a0, -1
 ; CHECK-NEXT:    vwmaccu.vx v10, a0, v9
 ; CHECK-NEXT:    vmv2r.v v8, v10
 ; CHECK-NEXT:    ret
-     %res = call <16 x i16> @llvm.experimental.vector.interleave2.v16i16(<8 x i16> %a, <8 x i16> %b)
+     %res = call <16 x i16>(...) @llvm.experimental.vector.interleave.v16i16.v8i16(<8 x i16> %a, <8 x i16> %b)
      ret <16 x i16> %res
 }
 
+define <6 x i32> @vector_interleave_v6i32_v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) {
+; RV32-LABEL: vector_interleave_v6i32_v2i32:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v12, v9
+; RV32-NEXT:    # kill: def $v8 killed $v8 def $v8m2
+; RV32-NEXT:    vsetivli zero, 4, e32, m2, tu, ma
+; RV32-NEXT:    vslideup.vi v8, v12, 2
+; RV32-NEXT:    lui a0, %hi(.LCPI2_0)
+; RV32-NEXT:    addi a0, a0, %lo(.LCPI2_0)
+; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
+; RV32-NEXT:    vle32.v v14, (a0)
+; RV32-NEXT:    # kill: def $v10 killed $v10 def $v10m2
+; RV32-NEXT:    vrgather.vv v12, v8, v14
+; RV32-NEXT:    vmv.s.x v8, zero
+; RV32-NEXT:    vmv.v.i v14, 1
+; RV32-NEXT:    vsetivli zero, 3, e32, m2, tu, ma
+; RV32-NEXT:    vslideup.vi v14, v8, 2
+; RV32-NEXT:    li a0, 36
+; RV32-NEXT:    vmv.s.x v0, a0
+; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, mu
+; RV32-NEXT:    vrgather.vv v12, v10, v14, v0.t
+; RV32-NEXT:    vmv.v.v v8, v12
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vector_interleave_v6i32_v2i32:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v12, v9
+; RV64-NEXT:    # kill: def $v8 killed $v8 def $v8m2
+; RV64-NEXT:    vsetivli zero, 4, e32, m2, tu, ma
+; RV64-NEXT:    vslideup.vi v8, v12, 2
+; RV64-NEXT:    lui a0, %hi(.LCPI2_0)
+; RV64-NEXT:    addi a0, a0, %lo(.LCPI2_0)
+; RV64-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
+; RV64-NEXT:    vle32.v v14, (a0)
+; RV64-NEXT:    # kill: def $v10 killed $v10 def $v10m2
+; RV64-NEXT:    vrgather.vv v12, v8, v14
+; RV64-NEXT:    li a0, 36
+; RV64-NEXT:    vmv.s.x v0, a0
+; RV64-NEXT:    li a0, 1
+; RV64-NEXT:    slli a0, a0, 32
+; RV64-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
+; RV64-NEXT:    vmv.v.x v8, a0
+; RV64-NEXT:    vsetivli zero, 8, e32, m2, ta, mu
+; RV64-NEXT:    vrgather.vv v12, v10, v8, v0.t
+; RV64-NEXT:    vmv.v.v v8, v12
+; RV64-NEXT:    ret
+     %res = call <6 x i32>(...) @llvm.experimental.vector.interleave.v6i32.v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32 >%c)
+     ret <6 x i32> %res
+}
+
 define <8 x i32> @vector_interleave_v8i32_v4i32(<4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LABEL: vector_interleave_v8i32_v4i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
 ; CHECK-NEXT:    vwaddu.vv v10, v8, v9
 ; CHECK-NEXT:    li a0, -1
 ; CHECK-NEXT:    vwmaccu.vx v10, a0, v9
 ; CHECK-NEXT:    vmv2r.v v8, v10
 ; CHECK-NEXT:    ret
-     %res = call <8 x i32> @llvm.experimental.vector.interleave2.v8i32(<4 x i32> %a, <4 x i32> %b)
+     %res = call <8 x i32>(...) @llvm.experimental.vector.interleave.v8i32.v4i32(<4 x i32> %a, <4 x i32> %b)
      ret <8 x i32> %res
 }
 
 define <4 x i64> @vector_interleave_v4i64_v2i64(<2 x i64> %a, <2 x i64> %b) {
 ; RV32-LABEL: vector_interleave_v4i64_v2i64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vmv1r.v v10, v9
 ; RV32-NEXT:    # kill: def $v8 killed $v8 def $v8m2
 ; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
 ; RV32-NEXT:    vmv.v.i v12, 0
 ; RV32-NEXT:    vsetivli zero, 2, e64, m2, tu, ma
 ; RV32-NEXT:    vslideup.vi v12, v8, 0
 ; RV32-NEXT:    vsetivli zero, 4, e64, m2, tu, ma
 ; RV32-NEXT:    vslideup.vi v12, v10, 2
-; RV32-NEXT:    lui a0, %hi(.LCPI3_0)
-; RV32-NEXT:    addi a0, a0, %lo(.LCPI3_0)
+; RV32-NEXT:    lui a0, %hi(.LCPI4_0)
+; RV32-NEXT:    addi a0, a0, %lo(.LCPI4_0)
 ; RV32-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
 ; RV32-NEXT:    vle16.v v10, (a0)
 ; RV32-NEXT:    vrgatherei16.vv v8, v12, v10
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vector_interleave_v4i64_v2i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vmv1r.v v10, v9
 ; RV64-NEXT:    # kill: def $v8 killed $v8 def $v8m2
 ; RV64-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
 ; RV64-NEXT:    vmv.v.i v12, 0
 ; RV64-NEXT:    vsetivli zero, 2, e64, m2, tu, ma
 ; RV64-NEXT:    vslideup.vi v12, v8, 0
 ; RV64-NEXT:    vsetivli zero, 4, e64, m2, tu, ma
 ; RV64-NEXT:    vslideup.vi v12, v10, 2
-; RV64-NEXT:    lui a0, %hi(.LCPI3_0)
-; RV64-NEXT:    addi a0, a0, %lo(.LCPI3_0)
+; RV64-NEXT:    lui a0, %hi(.LCPI4_0)
+; RV64-NEXT:    addi a0, a0, %lo(.LCPI4_0)
 ; RV64-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
 ; RV64-NEXT:    vle64.v v10, (a0)
 ; RV64-NEXT:    vrgather.vv v8, v12, v10
 ; RV64-NEXT:    ret
-     %res = call <4 x i64> @llvm.experimental.vector.interleave2.v4i64(<2 x i64> %a, <2 x i64> %b)
+     %res = call <4 x i64>(...) @llvm.experimental.vector.interleave.v4i64.v2i64(<2 x i64> %a, <2 x i64> %b)
      ret <4 x i64> %res
 }
 
-declare <32 x i1> @llvm.experimental.vector.interleave2.v32i1(<16 x i1>, <16 x i1>)
-declare <16 x i16> @llvm.experimental.vector.interleave2.v16i16(<8 x i16>, <8 x i16>)
-declare <8 x i32> @llvm.experimental.vector.interleave2.v8i32(<4 x i32>, <4 x i32>)
-declare <4 x i64> @llvm.experimental.vector.interleave2.v4i64(<2 x i64>, <2 x i64>)
+declare <32 x i1> @llvm.experimental.vector.interleave.v32i1.v16i1(...)
+declare <16 x i16> @llvm.experimental.vector.interleave.v16i16.v8i16(...)
+declare <6 x i32> @llvm.experimental.vector.interleave.v6i32.v2i32(...)
+declare <8 x i32> @llvm.experimental.vector.interleave.v8i32.v4i32(...)
+declare <4 x i64> @llvm.experimental.vector.interleave.v4i64.v2i64(...)
 
 ; Floats
 
 define <4 x half> @vector_interleave_v4f16_v2f16(<2 x half> %a, <2 x half> %b) {
 ; CHECK-LABEL: vector_interleave_v4f16_v2f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
 ; CHECK-NEXT:    vwaddu.vv v10, v8, v9
 ; CHECK-NEXT:    li a0, -1
 ; CHECK-NEXT:    vwmaccu.vx v10, a0, v9
 ; CHECK-NEXT:    vmv1r.v v8, v10
 ; CHECK-NEXT:    ret
-     %res = call <4 x half> @llvm.experimental.vector.interleave2.v4f16(<2 x half> %a, <2 x half> %b)
+     %res = call <4 x half>(...) @llvm.experimental.vector.interleave.v4f16.v2f16(<2 x half> %a, <2 x half> %b)
      ret <4 x half> %res
 }
 
 define <8 x half> @vector_interleave_v8f16_v4f16(<4 x half> %a, <4 x half> %b) {
 ; CHECK-LABEL: vector_interleave_v8f16_v4f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
 ; CHECK-NEXT:    vwaddu.vv v10, v8, v9
 ; CHECK-NEXT:    li a0, -1
 ; CHECK-NEXT:    vwmaccu.vx v10, a0, v9
 ; CHECK-NEXT:    vmv1r.v v8, v10
 ; CHECK-NEXT:    ret
-     %res = call <8 x half> @llvm.experimental.vector.interleave2.v8f16(<4 x half> %a, <4 x half> %b)
+     %res = call <8 x half>(...) @llvm.experimental.vector.interleave.v8f16.v4f16(<4 x half> %a, <4 x half> %b)
      ret <8 x half> %res
 }
 
 define <4 x float> @vector_interleave_v4f32_v2f32(<2 x float> %a, <2 x float> %b) {
 ; CHECK-LABEL: vector_interleave_v4f32_v2f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
 ; CHECK-NEXT:    vwaddu.vv v10, v8, v9
 ; CHECK-NEXT:    li a0, -1
 ; CHECK-NEXT:    vwmaccu.vx v10, a0, v9
 ; CHECK-NEXT:    vmv1r.v v8, v10
 ; CHECK-NEXT:    ret
-     %res = call <4 x float> @llvm.experimental.vector.interleave2.v4f32(<2 x float> %a, <2 x float> %b)
+     %res = call <4 x float>(...) @llvm.experimental.vector.interleave.v4f32.v2f32(<2 x float> %a, <2 x float> %b)
      ret <4 x float> %res
 }
 
 define <16 x half> @vector_interleave_v16f16_v8f16(<8 x half> %a, <8 x half> %b) {
 ; CHECK-LABEL: vector_interleave_v16f16_v8f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
 ; CHECK-NEXT:    vwaddu.vv v10, v8, v9
 ; CHECK-NEXT:    li a0, -1
 ; CHECK-NEXT:    vwmaccu.vx v10, a0, v9
 ; CHECK-NEXT:    vmv2r.v v8, v10
 ; CHECK-NEXT:    ret
-     %res = call <16 x half> @llvm.experimental.vector.interleave2.v16f16(<8 x half> %a, <8 x half> %b)
+     %res = call <16 x half>(...) @llvm.experimental.vector.interleave.v16f16.v8f16(<8 x half> %a, <8 x half> %b)
      ret <16 x half> %res
 }
 
 define <8 x float> @vector_interleave_v8f32_v4f32(<4 x float> %a, <4 x float> %b) {
 ; CHECK-LABEL: vector_interleave_v8f32_v4f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
 ; CHECK-NEXT:    vwaddu.vv v10, v8, v9
 ; CHECK-NEXT:    li a0, -1
 ; CHECK-NEXT:    vwmaccu.vx v10, a0, v9
 ; CHECK-NEXT:    vmv2r.v v8, v10
 ; CHECK-NEXT:    ret
-     %res = call <8 x float> @llvm.experimental.vector.interleave2.v8f32(<4 x float> %a, <4 x float> %b)
+     %res = call <8 x float>(...) @llvm.experimental.vector.interleave.v8f32.v4f32(<4 x float> %a, <4 x float> %b)
      ret <8 x float> %res
 }
 
 define <4 x double> @vector_interleave_v4f64_v2f64(<2 x double> %a, <2 x double> %b) {
 ; RV32-LABEL: vector_interleave_v4f64_v2f64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vmv1r.v v10, v9
 ; RV32-NEXT:    # kill: def $v8 killed $v8 def $v8m2
 ; RV32-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
 ; RV32-NEXT:    vmv.v.i v12, 0
 ; RV32-NEXT:    vsetivli zero, 2, e64, m2, tu, ma
 ; RV32-NEXT:    vslideup.vi v12, v8, 0
 ; RV32-NEXT:    vsetivli zero, 4, e64, m2, tu, ma
 ; RV32-NEXT:    vslideup.vi v12, v10, 2
-; RV32-NEXT:    lui a0, %hi(.LCPI9_0)
-; RV32-NEXT:    addi a0, a0, %lo(.LCPI9_0)
+; RV32-NEXT:    lui a0, %hi(.LCPI10_0)
+; RV32-NEXT:    addi a0, a0, %lo(.LCPI10_0)
 ; RV32-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
 ; RV32-NEXT:    vle16.v v10, (a0)
 ; RV32-NEXT:    vrgatherei16.vv v8, v12, v10
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vector_interleave_v4f64_v2f64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vmv1r.v v10, v9
 ; RV64-NEXT:    # kill: def $v8 killed $v8 def $v8m2
 ; RV64-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
 ; RV64-NEXT:    vmv.v.i v12, 0
 ; RV64-NEXT:    vsetivli zero, 2, e64, m2, tu, ma
 ; RV64-NEXT:    vslideup.vi v12, v8, 0
 ; RV64-NEXT:    vsetivli zero, 4, e64, m2, tu, ma
 ; RV64-NEXT:    vslideup.vi v12, v10, 2
-; RV64-NEXT:    lui a0, %hi(.LCPI9_0)
-; RV64-NEXT:    addi a0, a0, %lo(.LCPI9_0)
+; RV64-NEXT:    lui a0, %hi(.LCPI10_0)
+; RV64-NEXT:    addi a0, a0, %lo(.LCPI10_0)
 ; RV64-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
 ; RV64-NEXT:    vle64.v v10, (a0)
 ; RV64-NEXT:    vrgather.vv v8, v12, v10
 ; RV64-NEXT:    ret
-     %res = call <4 x double> @llvm.experimental.vector.interleave2.v4f64(<2 x double> %a, <2 x double> %b)
+     %res = call <4 x double>(...) @llvm.experimental.vector.interleave.v4f64.v2f64(<2 x double> %a, <2 x double> %b)
      ret <4 x double> %res
 }
 
 
-declare <4 x half> @llvm.experimental.vector.interleave2.v4f16(<2 x half>, <2 x half>)
-declare <8 x half> @llvm.experimental.vector.interleave2.v8f16(<4 x half>, <4 x half>)
-declare <4 x float> @llvm.experimental.vector.interleave2.v4f32(<2 x float>, <2 x float>)
-declare <16 x half> @llvm.experimental.vector.interleave2.v16f16(<8 x half>, <8 x half>)
-declare <8 x float> @llvm.experimental.vector.interleave2.v8f32(<4 x float>, <4 x float>)
-declare <4 x double> @llvm.experimental.vector.interleave2.v4f64(<2 x double>, <2 x double>)
+declare <4 x half> @llvm.experimental.vector.interleave.v4f16.v2f16(...)
+declare <8 x half> @llvm.experimental.vector.interleave.v8f16.v4f16(...)
+declare <4 x float> @llvm.experimental.vector.interleave.v4f32.v2f32(...)
+declare <16 x half> @llvm.experimental.vector.interleave.v16f16.v8f16(...)
+declare <8 x float> @llvm.experimental.vector.interleave.v8f32.v4f32(...)
+declare <4 x double> @llvm.experimental.vector.interleave.v4f64.v2f64(...)

llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll

 ; CHECK-NEXT:    vand.vi v8, v16, 1
 ; CHECK-NEXT:    vmsne.vi v0, v8, 0
 ; CHECK-NEXT:    csrr a0, vlenb
 ; CHECK-NEXT:    srli a0, a0, 2
 ; CHECK-NEXT:    add a1, a0, a0
 ; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, tu, ma
 ; CHECK-NEXT:    vslideup.vx v0, v10, a0
 ; CHECK-NEXT:    ret
-     %res = call <vscale x 32 x i1> @llvm.experimental.vector.interleave2.nxv32i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b)
+     %res = call <vscale x 32 x i1>(...) @llvm.experimental.vector.interleave.nxv32i1.nxv16i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b)
      ret <vscale x 32 x i1> %res
 }
 
 define <vscale x 16 x i16> @vector_interleave_nxv16i16_nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
 ; CHECK-LABEL: vector_interleave_nxv16i16_nxv8i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
 ; CHECK-NEXT:    vwaddu.vv v12, v8, v10
 ; CHECK-NEXT:    li a0, -1
 ; CHECK-NEXT:    vwmaccu.vx v12, a0, v10
 ; CHECK-NEXT:    vmv4r.v v8, v12
 ; CHECK-NEXT:    ret
-     %res = call <vscale x 16 x i16> @llvm.experimental.vector.interleave2.nxv16i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b)
+     %res = call <vscale x 16 x i16>(...) @llvm.experimental.vector.interleave.nxv16i16.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b)
      ret <vscale x 16 x i16> %res
 }
 
 define <vscale x 8 x i32> @vector_interleave_nxv8i32_nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
 ; CHECK-LABEL: vector_interleave_nxv8i32_nxv4i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
 ; CHECK-NEXT:    vwaddu.vv v12, v8, v10
 ; CHECK-NEXT:    li a0, -1
 ; CHECK-NEXT:    vwmaccu.vx v12, a0, v10
 ; CHECK-NEXT:    vmv4r.v v8, v12
 ; CHECK-NEXT:    ret
-     %res = call <vscale x 8 x i32> @llvm.experimental.vector.interleave2.nxv8i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b)
+     %res = call <vscale x 8 x i32>(...) @llvm.experimental.vector.interleave.nxv8i32.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b)
      ret <vscale x 8 x i32> %res
 }
 
 define <vscale x 4 x i64> @vector_interleave_nxv4i64_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
 ; CHECK-LABEL: vector_interleave_nxv4i64_nxv2i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    # kill: def $v10m2 killed $v10m2 killed $v8m4 def $v8m4
 ; CHECK-NEXT:    csrr a0, vlenb
 ; CHECK-NEXT:    srli a0, a0, 2
 ; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
 ; CHECK-NEXT:    vid.v v12
 ; CHECK-NEXT:    vand.vi v13, v12, 1
 ; CHECK-NEXT:    vmsne.vi v0, v13, 0
 ; CHECK-NEXT:    vsrl.vi v16, v12, 1
 ; CHECK-NEXT:    vadd.vx v16, v16, a0, v0.t
 ; CHECK-NEXT:    vsetvli zero, zero, e64, m4, ta, ma
 ; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m4 def $v8m4
 ; CHECK-NEXT:    vrgatherei16.vv v12, v8, v16, v0.t
 ; CHECK-NEXT:    vmv.v.v v8, v12
 ; CHECK-NEXT:    ret
-     %res = call <vscale x 4 x i64> @llvm.experimental.vector.interleave2.nxv4i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b)
+     %res = call <vscale x 4 x i64>(...) @llvm.experimental.vector.interleave.nxv4i64.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b)
      ret <vscale x 4 x i64> %res
 }
 
-declare <vscale x 32 x i1> @llvm.experimental.vector.interleave2.nxv32i1(<vscale x 16 x i1>, <vscale x 16 x i1>)
-declare <vscale x 16 x i16> @llvm.experimental.vector.interleave2.nxv16i16(<vscale x 8 x i16>, <vscale x 8 x i16>)
-declare <vscale x 8 x i32> @llvm.experimental.vector.interleave2.nxv8i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
-declare <vscale x 4 x i64> @llvm.experimental.vector.interleave2.nxv4i64(<vscale x 2 x i64>, <vscale x 2 x i64>)
+declare <vscale x 32 x i1> @llvm.experimental.vector.interleave.nxv32i1.nxv16i1(...)
+declare <vscale x 16 x i16> @llvm.experimental.vector.interleave.nxv16i16.nxv8i16(...)
+declare <vscale x 8 x i32> @llvm.experimental.vector.interleave.nxv8i32.nxv4i32(...)
+declare <vscale x 6 x i32> @llvm.experimental.vector.interleave.nxv6i32.nxv2i32(...)
+declare <vscale x 4 x i64> @llvm.experimental.vector.interleave.nxv4i64.nxv2i64(...)
 
 ; Floats
 
 define <vscale x 4 x half> @vector_interleave_nxv4f16_nxv2f16(<vscale x 2 x half> %a, <vscale x 2 x half> %b) {
 ; CHECK-LABEL: vector_interleave_nxv4f16_nxv2f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
 ; CHECK-NEXT:    vwaddu.vv v10, v8, v9
 ; CHECK-NEXT:    li a0, -1
 ; CHECK-NEXT:    vwmaccu.vx v10, a0, v9
 ; CHECK-NEXT:    csrr a0, vlenb
 ; CHECK-NEXT:    srli a0, a0, 2
 ; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
 ; CHECK-NEXT:    vslidedown.vx v8, v10, a0
 ; CHECK-NEXT:    add a1, a0, a0
 ; CHECK-NEXT:    vsetvli zero, a1, e16, m1, tu, ma
 ; CHECK-NEXT:    vslideup.vx v10, v8, a0
 ; CHECK-NEXT:    vmv1r.v v8, v10
 ; CHECK-NEXT:    ret
-     %res = call <vscale x 4 x half> @llvm.experimental.vector.interleave2.nxv4f16(<vscale x 2 x half> %a, <vscale x 2 x half> %b)
+     %res = call <vscale x 4 x half>(...) @llvm.experimental.vector.interleave.nxv4f16.nxv2f16(<vscale x 2 x half> %a, <vscale x 2 x half> %b)
      ret <vscale x 4 x half> %res
 }
 
 define <vscale x 8 x half> @vector_interleave_nxv8f16_nxv4f16(<vscale x 4 x half> %a, <vscale x 4 x half> %b) {
 ; CHECK-LABEL: vector_interleave_nxv8f16_nxv4f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
 ; CHECK-NEXT:    vwaddu.vv v10, v8, v9
 ; CHECK-NEXT:    li a0, -1
 ; CHECK-NEXT:    vwmaccu.vx v10, a0, v9
 ; CHECK-NEXT:    vmv2r.v v8, v10
 ; CHECK-NEXT:    ret
-     %res = call <vscale x 8 x half> @llvm.experimental.vector.interleave2.nxv8f16(<vscale x 4 x half> %a, <vscale x 4 x half> %b)
+     %res = call <vscale x 8 x half>(...) @llvm.experimental.vector.interleave.nxv8f16.nxv4f16(<vscale x 4 x half> %a, <vscale x 4 x half> %b)
      ret <vscale x 8 x half> %res
 }
 
 define <vscale x 4 x float> @vector_interleave_nxv4f32_nxv2f32(<vscale x 2 x float> %a, <vscale x 2 x float> %b) {
 ; CHECK-LABEL: vector_interleave_nxv4f32_nxv2f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
 ; CHECK-NEXT:    vwaddu.vv v10, v8, v9
 ; CHECK-NEXT:    li a0, -1
 ; CHECK-NEXT:    vwmaccu.vx v10, a0, v9
 ; CHECK-NEXT:    vmv2r.v v8, v10
 ; CHECK-NEXT:    ret
-     %res = call <vscale x 4 x float> @llvm.experimental.vector.interleave2.nxv4f32(<vscale x 2 x float> %a, <vscale x 2 x float> %b)
+     %res = call <vscale x 4 x float>(...) @llvm.experimental.vector.interleave.nxv4f32.nxv2f32(<vscale x 2 x float> %a, <vscale x 2 x float> %b)
      ret <vscale x 4 x float> %res
 }
 
 define <vscale x 16 x half> @vector_interleave_nxv16f16_nxv8f16(<vscale x 8 x half> %a, <vscale x 8 x half> %b) {
 ; CHECK-LABEL: vector_interleave_nxv16f16_nxv8f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
 ; CHECK-NEXT:    vwaddu.vv v12, v8, v10
 ; CHECK-NEXT:    li a0, -1
 ; CHECK-NEXT:    vwmaccu.vx v12, a0, v10
 ; CHECK-NEXT:    vmv4r.v v8, v12
 ; CHECK-NEXT:    ret
-     %res = call <vscale x 16 x half> @llvm.experimental.vector.interleave2.nxv16f16(<vscale x 8 x half> %a, <vscale x 8 x half> %b)
+     %res = call <vscale x 16 x half>(...) @llvm.experimental.vector.interleave.nxv16f16.nxv8f16(<vscale x 8 x half> %a, <vscale x 8 x half> %b)
      ret <vscale x 16 x half> %res
 }
 
 define <vscale x 8 x float> @vector_interleave_nxv8f32_nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b) {
 ; CHECK-LABEL: vector_interleave_nxv8f32_nxv4f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
 ; CHECK-NEXT:    vwaddu.vv v12, v8, v10
 ; CHECK-NEXT:    li a0, -1
 ; CHECK-NEXT:    vwmaccu.vx v12, a0, v10
 ; CHECK-NEXT:    vmv4r.v v8, v12
 ; CHECK-NEXT:    ret
-     %res = call <vscale x 8 x float> @llvm.experimental.vector.interleave2.nxv8f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b)
+     %res = call <vscale x 8 x float>(...) @llvm.experimental.vector.interleave.nxv8f32.nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b)
      ret <vscale x 8 x float> %res
 }
 
 define <vscale x 4 x double> @vector_interleave_nxv4f64_nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b) {
 ; CHECK-LABEL: vector_interleave_nxv4f64_nxv2f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    # kill: def $v10m2 killed $v10m2 killed $v8m4 def $v8m4
 ; CHECK-NEXT:    csrr a0, vlenb
 ; CHECK-NEXT:    srli a0, a0, 2
 ; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
 ; CHECK-NEXT:    vid.v v12
 ; CHECK-NEXT:    vand.vi v13, v12, 1
 ; CHECK-NEXT:    vmsne.vi v0, v13, 0
 ; CHECK-NEXT:    vsrl.vi v16, v12, 1
 ; CHECK-NEXT:    vadd.vx v16, v16, a0, v0.t
 ; CHECK-NEXT:    vsetvli zero, zero, e64, m4, ta, ma
 ; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m4 def $v8m4
 ; CHECK-NEXT:    vrgatherei16.vv v12, v8, v16, v0.t
 ; CHECK-NEXT:    vmv.v.v v8, v12
 ; CHECK-NEXT:    ret
-     %res = call <vscale x 4 x double> @llvm.experimental.vector.interleave2.nxv4f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b)
+     %res = call <vscale x 4 x double>(...) @llvm.experimental.vector.interleave.nxv4f64.nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b)
      ret <vscale x 4 x double> %res
 }
 
 
-declare <vscale x 4 x half> @llvm.experimental.vector.interleave2.nxv4f16(<vscale x 2 x half>, <vscale x 2 x half>)
-declare <vscale x 8 x half> @llvm.experimental.vector.interleave2.nxv8f16(<vscale x 4 x half>, <vscale x 4 x half>)
-declare <vscale x 4 x float> @llvm.experimental.vector.interleave2.nxv4f32(<vscale x 2 x float>, <vscale x 2 x float>)
-declare <vscale x 16 x half> @llvm.experimental.vector.interleave2.nxv16f16(<vscale x 8 x half>, <vscale x 8 x half>)
-declare <vscale x 8 x float> @llvm.experimental.vector.interleave2.nxv8f32(<vscale x 4 x float>, <vscale x 4 x float>)
-declare <vscale x 4 x double> @llvm.experimental.vector.interleave2.nxv4f64(<vscale x 2 x double>, <vscale x 2 x double>)
+declare <vscale x 4 x half> @llvm.experimental.vector.interleave.nxv4f16.nxv2f16(...)
+declare <vscale x 8 x half> @llvm.experimental.vector.interleave.nxv8f16.nxv4f16(...)
+declare <vscale x 4 x float> @llvm.experimental.vector.interleave.nxv4f32.nxv2f32(...)
+declare <vscale x 16 x half> @llvm.experimental.vector.interleave.nxv16f16.nxv8f16(...)
+declare <vscale x 8 x float> @llvm.experimental.vector.interleave.nxv8f32.nxv4f32(...)
+declare <vscale x 4 x double> @llvm.experimental.vector.interleave.nxv4f64.nxv2f64(...)

llvm/test/Verifier/vector-deinterleave-intrinsic.ll

+; RUN: not opt -S -passes=verify < %s 2>&1 | FileCheck %s
+
+declare i32 @llvm.experimental.vector.deinterleave.nxv2i32(<vscale x 2 x i32>)
+define i32 @non_struct_return_type(<vscale x 2 x i32> %a) {
+; CHECK: vector.deinterleave result must be a struct type. 
+  %1 = call i32 @llvm.experimental.vector.deinterleave.nxv2i32(<vscale x 2 x i32> %a)
+  ret i32 %1
+}
+
+declare {<vscale x 2 x i32>, <vscale x 2 x i32>} @llvm.experimental.vector.deinterleave.nxv9i32(<vscale x 9 x i32>)
+define {<vscale x 2 x i32>, <vscale x 2 x i32>} @non_multiple_return_type(<vscale x 9 x i32> %a) {
+; CHECK: vector.deinterleave input must be a vector with a count that is a multiple of the number of result vectors. 
+  %1 = call {<vscale x 2 x i32>, <vscale x 2 x i32>} @llvm.experimental.vector.deinterleave.nxv9i32(<vscale x 9 x i32> %a)
+  ret {<vscale x 2 x i32>, <vscale x 2 x i32>} %1
+}
+
+declare {<vscale x 2 x i32>, <vscale x 3 x i32>} @llvm.experimental.vector.deinterleave.nxv2i32.nxv4i32(<vscale x 4 x i32>)
+define {<vscale x 2 x i32>, <vscale x 3 x i32>} @incorrect_result_type_count(<vscale x 4 x i32> %a) {
+; vector.deinterleave result types don't match up with the input.
+  %1 = call {<vscale x 2 x i32>, <vscale x 3 x i32>} @llvm.experimental.vector.deinterleave.nxv2i32.nxv4i32(<vscale x 4 x i32> %a)
+  ret {<vscale x 2 x i32>, <vscale x 3 x i32>} %1
+}
+
+declare {<vscale x 2 x i64>, <vscale x 2 x i32>} @llvm.experimental.vector.deinterleave.nxv2i64.nxv4i32(<vscale x 4 x i32>)
+define {<vscale x 2 x i64>, <vscale x 2 x i32>} @incorrect_result_type_element(<vscale x 4 x i32> %a) {
+; vector.deinterleave result types don't match up with the input.
+  %1 = call {<vscale x 2 x i64>, <vscale x 2 x i32>} @llvm.experimental.vector.deinterleave.nxv2i64.nxv4i32(<vscale x 4 x i32> %a)
+  ret {<vscale x 2 x i64>, <vscale x 2 x i32>} %1
+}
+

llvm/test/Verifier/vector-interleave-intrinsic.ll

+; RUN: not opt -S -passes=verify < %s 2>&1 | FileCheck %s
+
+declare <vscale x 9 x i32> @llvm.experimental.vector.interleave.nxv9i32.nxv2i32(...)
+define <vscale x 9 x i32> @non_multiple_return_type(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) {
+; CHECK: vector.interleave result must be a vector with a count that is a multiple of the number of operands.
+  %1 = call <vscale x 9 x i32>(...) @llvm.experimental.vector.interleave.nxv9i32.nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b)
+  ret <vscale x 9 x i32> %1
+}
+
+declare <vscale x 4 x i32> @llvm.experimental.vector.interleave.nxv4i32.nxv2i32(...)
+define <vscale x 4 x i32> @incorrect_operand_type_count(<vscale x 2 x i32> %a, <vscale x 3 x i32> %b) {
+; CHECK: vector.interleave operand types don't match up with the result.
+  %1 = call <vscale x 4 x i32>(...) @llvm.experimental.vector.interleave.nxv4i32.nxv2i32(<vscale x 2 x i32> %a, <vscale x 3 x i32> %b)
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @incorrect_operand_type_element(<vscale x 2 x i64> %a, <vscale x 2 x i32> %b) {
+; CHECK: vector.interleave operand types don't match up with the result.
+  %1 = call <vscale x 4 x i32>(...) @llvm.experimental.vector.interleave.nxv4i32.nxv2i32(<vscale x 2 x i64> %a, <vscale x 2 x i32> %b)
+  ret <vscale x 4 x i32> %1
+}