Improve and enable folding of conditional branches with tail calls.

[goldstein.w.n]

Summary

Improve and enable folding of conditional branches with tail calls.

1. Make it so that conditional tail calls can be emitted even when there are multiple predecessors.

2. Don't guard the transformation behind -Os. The rationale for guarding it was static-prediction can be affected by whether the branch is forward of backward. This is no longer true for almost any X86 cpus (anything newer than SnB) so is no longer a meaningful concern.

[goldstein.w.n]

@hans Added you b.c you seem to the original author. I didn't quite understand the rationale behind leaving this off given that:

1. replaceBranchWithTailCall already keep the condition constant L3020: if (CC != BranchCond[0].getImm())
2. The entire transform is guarded behind MBB == TBB.

[pengfei]

I'm not sure if we can arbitrarily replace jmp foo with jcc foo. At least jmp has a large range (64-bit) scope which supports code size > 2GB. Maybe we should limit it to kernel/small code model?

llvm/lib/Target/X86/X86InstrInfo.cpp

3018–3019 ↗

(On Diff #486118)

We do we need to add it if it's unused? Do not put unrelated/useless code in the same patch. It obstructs people to understand the patch.

[goldstein.w.n]

In D140931#4025075, @pengfei wrote:

I'm not sure if we can arbitrarily replace jmp foo with jcc foo. At least jmp has a large range (64-bit) scope which supports code size > 2GB. Maybe we should limit it to kernel/small code model?

Can it? https://www.felixcloutier.com/x86/jmp I though rel32 was maximum imm encoding.

But in canMakeTailCallConditional we have:

if (TailCall.getOpcode() != X86::TCRETURNdi &&
    TailCall.getOpcode() != X86::TCRETURNdi64) {
  // Only direct calls can be done with a conditional branch.
  return false;
}

We could limit X86::TCRETURNdi64 with kernel/small-code model. Although this is done after
reg alloc and only within function so we could only do if function has less than 2^32 / 16 instructions
and be safe.

Edit:
The stuff about in function is wrong.

[goldstein.w.n]

llvm/lib/Target/X86/X86InstrInfo.cpp

3018–3019 ↗

(On Diff #486118)

Its not needed. The reason I added it was b.c the rationale previously for keeping this optimization guarded behind -Os was that if it changed branch direction + reordered CFG it could be a de-optimization. That seems like a reasonable concern so thought it would be good to have in the generic API.

A more appropriate comment might have been: "At the moment never change branch direction".

Can drop if your prefer. Let me know for V2.

[pengfei]

In D140931#4025158, @goldstein.w.n wrote:

In D140931#4025075, @pengfei wrote:

I'm not sure if we can arbitrarily replace jmp foo with jcc foo. At least jmp has a large range (64-bit) scope which supports code size > 2GB. Maybe we should limit it to kernel/small code model?

Can it? https://www.felixcloutier.com/x86/jmp I though rel32 was maximum imm encoding.

But in canMakeTailCallConditional we have:

if (TailCall.getOpcode() != X86::TCRETURNdi &&
    TailCall.getOpcode() != X86::TCRETURNdi64) {
  // Only direct calls can be done with a conditional branch.
  return false;
}

We could limit X86::TCRETURNdi64 with kernel/small-code model. Although this is done after
reg alloc and only within function so we could only do if function has less than 2^32 / 16 instructions
and be safe.

Edit:
The stuff about in function is wrong.

I didn't look into the details in canMakeTailCallConditional. Seems we have checked for several cases. So this is not a fresh question, or maybe even not a problem. At least, it's not specific to this patch.

llvm/lib/Target/X86/X86InstrInfo.cpp

3018–3019 ↗

(On Diff #486118)

I'm still confused by the intention of this flag. If you believe it's a reasonable concern, why can we do it by default in this patch? The flag doesn't prevent from doing it.
OTOH, if we want make target specific decision, should we simply add the code

if (MayChangeDirection)
  return false;

to other targets (if they override it)? So we don't need to pass MayChangeDirection again to replaceBranchWithTailCall, right?

Regarding de-optimization, I had the same concern at the beginning. But test cases show that in most cases both branches are terminators, either jmp or ret. So the change of the layout should have negligible affect to performance?

[goldstein.w.n]

llvm/lib/Target/X86/X86InstrInfo.cpp

3018–3019 ↗

(On Diff #486118)

I'm still confused by the intention of this flag. If you believe it's a reasonable concern, why can we do it by default in this patch? The flag doesn't prevent from doing it.

Oh man...

The comment is wrong. We assume MayChangeDirection is false (I.e we only find branch if CC matches, not also able to find matches inverse). Sorry for the confusion.

OTOH, if we want make target specific decision, should we simply add the code

if (MayChangeDirection)
  return false;

to other targets (if they override it)? So we don't need to pass MayChangeDirection again to replaceBranchWithTailCall, right?

So at the moment MayChangeDirection is unused in both X86InstrInfo::canMakeTailCallConditional and X86InstrInfo::replaceBranchWithTailCall (assumed false). X86InstrInfo::replaceBranchWithTailCall needs to find the branch we are replacing which may rely on MayChangeDirection. Also we have the sanity tests:

assert(canMakeTailCallConditional(BranchCond, TailCall, MayChangeDirection));

sitting at the top.

Regarding de-optimization, I had the same concern at the beginning. But test cases show that in most cases both branches are terminators, either jmp or ret. So the change of the layout should have negligible affect to performance?

This is because the entire case is guarded behind:

// Only eliminate if MBB == TBB (Taken Basic Block)
if (PredAnalyzable && !PredCond.empty() && PredTBB == MBB &&
    PredTBB != PredFBB) {

So we really are only ever doing this opt if it won't cause CFG reordering already. The MayChangeDirection AFAICT is redundant in the current implementation. Would you prefer me to just turn it into a comment at the call site?

Note we do see the final condition switch but from what I can tell that is b.c eliminating this edge in the CFG affects future calls to BranchFolder::OptimizeBlock. At the time this transformation takes place it only matches the same taken condition.

[goldstein.w.n]

Fix wrong comment about MayChangeDirection

[goldstein.w.n]

llvm/lib/Target/X86/X86InstrInfo.cpp

3018–3019 ↗

(On Diff #486118)

I'm still confused by the intention of this flag. If you believe it's a reasonable concern, why can we do it by default in this patch? The flag doesn't prevent from doing it.

Oh man...

The comment is wrong. We assume MayChangeDirection is false (I.e we only find branch if CC matches, not also able to find matches inverse). Sorry for the confusion.

I fixed the wrong comment in V2. Let me know your decision about dropping MayChangeDirection entirely for V3.

OTOH, if we want make target specific decision, should we simply add the code

if (MayChangeDirection)
  return false;

to other targets (if they override it)? So we don't need to pass MayChangeDirection again to replaceBranchWithTailCall, right?

So at the moment MayChangeDirection is unused in both X86InstrInfo::canMakeTailCallConditional and X86InstrInfo::replaceBranchWithTailCall (assumed false). X86InstrInfo::replaceBranchWithTailCall needs to find the branch we are replacing which may rely on MayChangeDirection. Also we have the sanity tests:

assert(canMakeTailCallConditional(BranchCond, TailCall, MayChangeDirection));

sitting at the top.

Regarding de-optimization, I had the same concern at the beginning. But test cases show that in most cases both branches are terminators, either jmp or ret. So the change of the layout should have negligible affect to performance?

This is because the entire case is guarded behind:

// Only eliminate if MBB == TBB (Taken Basic Block)
if (PredAnalyzable && !PredCond.empty() && PredTBB == MBB &&
    PredTBB != PredFBB) {

So we really are only ever doing this opt if it won't cause CFG reordering already. The MayChangeDirection AFAICT is redundant in the current implementation. Would you prefer me to just turn it into a comment at the call site?

Note we do see the final condition switch but from what I can tell that is b.c eliminating this edge in the CFG affects future calls to BranchFolder::OptimizeBlock. At the time this transformation takes place it only matches the same taken condition.

[pengfei]

llvm/lib/Target/X86/X86InstrInfo.cpp

3018–3019 ↗

(On Diff #486118)

Thanks! The flag is clear to me now. But it's still not clear to me why it is conservative.
According to the old comments in BranchFolding.cpp, the true conservative action is to do replaceBranchWithTailCall only when OptForSize or MayChangeDirection is true. But this change always does replaceBranchWithTailCall now. So it looks to me like aggressive rather than conservative.

[goldstein.w.n]

llvm/lib/Target/X86/X86InstrInfo.cpp

3018–3019 ↗

(On Diff #486118)

Thanks! The flag is clear to me now. But it's still not clear to me why it is conservative.
According to the old comments in BranchFolding.cpp, the true conservative action is to do replaceBranchWithTailCall only when OptForSize or MayChangeDirection is true. But this change always does replaceBranchWithTailCall now. So it looks to me like aggressive rather than conservative.

Thats not how I read it. How I read it was only do replaceBranchWithTailCall when OptForSize because we may change branch direction and mess up other CFG optimizations. AFAICT from the code, however, we never actually change branch direction (at the moment). I added the flag so that in the future if someone wants to make this more aggressive, the original intent, to not change branch direction unless OptForSize it would be clear.

[pengfei]

llvm/lib/Target/X86/X86InstrInfo.cpp

3018–3019 ↗

(On Diff #486118)

Seems we have opposite understanding in the sentences. cc @hans who wrote it in D29856.
My understanding is the "branch direction" means the BB layout that the BPU may take it as taken or not taken. The layout is usually calculated according to the branch possibility. Changing the order may regress performance.

[goldstein.w.n]

llvm/lib/Target/X86/X86InstrInfo.cpp

3018–3019 ↗

(On Diff #486118)

Seems we have opposite understanding in the sentences. cc @hans who wrote it in D29856.
My understanding is the "branch direction" means the BB layout that the BPU may take it as taken or not taken. The layout is usually calculated according to the branch possibility. Changing the order may regress performance.

That can't change either.

// Only eliminate if MBB == TBB (Taken Basic Block)
 if (PredAnalyzable && !PredCond.empty() && PredTBB == MBB &&
     PredTBB != PredFBB) {

I think it defacto ends up changing things later on b.c once an MBB has no preds it gets killed and that can re-order (more opportunistic optimization than forced changes) but we never explicitly swap fallthrough/taken. (Just as an reference, bolt now does this unconditionally in SimplifyConditionalTailCalls::fixTailCalls)

3018–3019 ↗

(On Diff #486118)

Seems we have opposite understanding in the sentences. cc @hans who wrote it in D29856.
My understanding is the "branch direction" means the BB layout that the BPU may take it as taken or not taken. The layout is usually calculated according to the branch possibility. Changing the order may regress performance.

The comment at the end:

// If the predecessor is falling through to this block, we could reverse
  // the branch condition and fold the tail call into that. However, after
  // that we might have to re-arrange the CFG to fall through to the other
  // block and there is a high risk of regressing code size rather than
  // improving it.

I think is more in line with what you're saying.

[hans]

llvm/lib/Target/X86/X86InstrInfo.cpp

3018–3019 ↗

(On Diff #486118)

I didn't look at the current patch so I don't have the full context, but when I wrote that comment, it was referring to branch direction as in whether it's branching to a higher or lower address. For example changing "Jcc foo; foo: jmp bar;" into "Jcc bar;" might be changing Jcc from a forwards branch (to foo) to a backwards branch to bar (if it's at a lower address).

Someone had expressed concerns about this, which is why we limited it to optsize functions.

[goldstein.w.n]

llvm/lib/Target/X86/X86InstrInfo.cpp

3018–3019 ↗

(On Diff #486118)

I didn't look at the current patch so I don't have the full context, but when I wrote that comment, it was referring to branch direction as in whether it's branching to a higher or lower address. For example changing "Jcc foo; foo: jmp bar;" into "Jcc bar;" might be changing Jcc from a forwards branch (to foo) to a backwards branch to bar (if it's at a lower address).

Someone had expressed concerns about this, which is why we limited it to optsize functions.

What was the rationale? Static prediction? If so we can could probably limit this to haswell and never where static prediction was changed.

[goldstein.w.n]

ping.

[goldstein.w.n]

ping2.

[pengfei]

Make it so that conditional tail calls can be emitted even when there are multiple predecessors.

Do you notice a test case to reflect this target? Otherwise we may need to add one for it.

llvm/lib/CodeGen/BranchFolding.cpp

1513–1539

I think this flags turns to meaningless now. Either we leave code as was to match with SOM or we totally ignore it.

llvm/lib/Target/X86/X86InstrInfo.cpp

3018–3019 ↗

(On Diff #486118)

Yeah, it looks like Assembly/Compiler Coding Rule 3 in SOM. It suggests to maintain for consistency although Core microarchitecture does not use the static prediction heuristic.

llvm/test/CodeGen/X86/tail-opts.ll

866–867

This looks like increasing size some time. Is this caused by the change of checking for all predecessors?

[goldstein.w.n]

Remove MayChangeDirection flag

[goldstein.w.n]

In D140931#4088632, @pengfei wrote:

Make it so that conditional tail calls can be emitted even when there are multiple predecessors.

Do you notice a test case to reflect this target? Otherwise we may need to add one for it.

Yes the following tests rely on it:

LLVM :: CodeGen/X86/jump_sign.ll
LLVM :: CodeGen/X86/or-branch.ll
LLVM :: CodeGen/X86/segmented-stacks.ll
LLVM :: CodeGen/X86/tailcall-extract.ll

llvm/lib/CodeGen/BranchFolding.cpp

1513–1539

I think this flags turns to meaningless now. Either we leave code as was to match with SOM or we totally ignore it.

Dropped the flag, LMK if you want me to replace with a CPU newer than SnB check.

llvm/lib/Target/X86/X86InstrInfo.cpp

3018–3019 ↗

(On Diff #486118)

Yeah, it looks like Assembly/Compiler Coding Rule 3 in SOM. It suggests to maintain for consistency although Core microarchitecture does not use the static prediction heuristic.

IMO the comment is quite outdated and just because it did exist it shouldn't get in the way of improvements for nearly ALL modern machines.

We could add a flag to may it only SnB and newer (I think starts at SnB but might be IVB).

llvm/test/CodeGen/X86/tail-opts.ll

866–867

This looks like increasing size some time. Is this caused by the change of checking for all predecessors?

Is this increasing size? Seems to be one less basic-block to me and -1 instruction. I think the numbering just gets weird and it jumps from bb.2 -> bb.5.

[pengfei]

llvm/lib/Target/X86/X86InstrInfo.cpp

3030–3032 ↗

(On Diff #493109)

Revert the format change in this file.

llvm/test/CodeGen/X86/segmented-stacks.ll

1725

It doesn't look like multi predecessors.

1729

This looks like dead code?

llvm/test/CodeGen/X86/tail-opts.ll

866–867

jne rel8 vs. jne rel32. 3 bytes longer and no instruction reduced.

[goldstein.w.n]

llvm/lib/Target/X86/X86InstrInfo.cpp

3030–3032 ↗

(On Diff #493109)

Revert the format change in this file.

Will do for v4.

llvm/test/CodeGen/X86/segmented-stacks.ll

1725

It doesn't look like multi predecessors.

Hmm?

1729

This looks like dead code?

Appears to be. Not sure whats causing that. Is __morestack doing something tricky?

llvm/test/CodeGen/X86/tail-opts.ll

866–867

jne rel8 vs. jne rel32. 3 bytes longer and no instruction reduced.

Yeah, you're right, its because the tail call MBB is used by multiple branches, some of which can be dropped, but not all.

We could make it so that for -Os removing the tail calls is all or nothing (on the assumption that the MBB is more likely to be imm8 encodable than the jmp, although the alternative is also possible).

What do you think?

[goldstein.w.n]

Fix fmt issues.

[pengfei]

llvm/test/CodeGen/X86/switch-bt.ll

56–63

Just noticed this. The manual written CHECK has gone, but no corresponding new check generated. Should we still use the old format with a bit twist?

[goldstein.w.n]

llvm/test/CodeGen/X86/switch-bt.ll

56–63

Just noticed this. The manual written CHECK has gone, but no corresponding new check generated. Should we still use the old format with a bit twist?

We can also just remove the:
-asm-verbose=false and then autogenerate. That Okay?

[goldstein.w.n]

Rebase

[goldstein.w.n]

llvm/test/CodeGen/X86/switch-bt.ll

56–63

Just noticed this. The manual written CHECK has gone, but no corresponding new check generated. Should we still use the old format with a bit twist?

Made D142860 to autogenerate tests for switch-bt.ll, then this one just updates.

[goldstein.w.n]

Rebase

[pengfei]

LGTM, thanks!

[hctim]

Hey, looks like this probably broke the ASan buildbot: https://lab.llvm.org/buildbot/#/builders/5/builds/31141/steps/13/logs/stdio

I'm running a bisect now just to double check.

Instructions on how to reproduce the bots can be found here: https://github.com/google/sanitizers/wiki/SanitizerBotReproduceBuild. You're probably looking for buildbot_fast.sh, the same one that's referenced in the instructions.

Testing:  0.. 10.. 20.. 30.. 40.. 50..
FAIL: LLVM :: CodeGen/X86/tailcall-extract.ll (42751 of 72693)
******************** TEST 'LLVM :: CodeGen/X86/tailcall-extract.ll' FAILED ********************
Script:
--
: 'RUN: at line 1';   /b/sanitizer-x86_64-linux-fast/build/llvm_build_asan/bin/llc -opaque-pointers=0 -mtriple=x86_64-linux < /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/test/CodeGen/X86/tailcall-extract.ll | /b/sanitizer-x86_64-linux-fast/build/llvm_build_asan/bin/FileCheck /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/test/CodeGen/X86/tailcall-extract.ll
: 'RUN: at line 2';   /b/sanitizer-x86_64-linux-fast/build/llvm_build_asan/bin/opt -opaque-pointers=0 -codegenprepare -S -mtriple=x86_64-linux < /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/test/CodeGen/X86/tailcall-extract.ll | /b/sanitizer-x86_64-linux-fast/build/llvm_build_asan/bin/FileCheck /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/test/CodeGen/X86/tailcall-extract.ll --check-prefix OPT
--
Exit Code: 2
Command Output (stderr):
--
=================================================================
==1490386==ERROR: AddressSanitizer: container-overflow on address 0x602000006718 at pc 0x55bf6065a91e bp 0x7ffc1fdaeed0 sp 0x7ffc1fdaeec8
READ of size 8 at 0x602000006718 thread T0
    #0 0x55bf6065a91d in llvm::BranchFolder::OptimizeBlock(llvm::MachineBasicBlock*) /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/lib/CodeGen/BranchFolding.cpp:1517:34
    #1 0x55bf60649db4 in llvm::BranchFolder::OptimizeBranches(llvm::MachineFunction&) /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/lib/CodeGen/BranchFolding.cpp:1207:19
    #2 0x55bf606465b7 in llvm::BranchFolder::OptimizeFunction(llvm::MachineFunction&, llvm::TargetInstrInfo const*, llvm::TargetRegisterInfo const*, llvm::MachineLoopInfo*, bool) /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/lib/CodeGen/BranchFolding.cpp:212:34
    #3 0x55bf60660955 in (anonymous namespace)::BranchFolderPass::runOnMachineFunction(llvm::MachineFunction&) /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/lib/CodeGen/BranchFolding.cpp:137:17
    #4 0x55bf60b3be12 in llvm::MachineFunctionPass::runOnFunction(llvm::Function&) /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/lib/CodeGen/MachineFunctionPass.cpp:91:13
    #5 0x55bf61a80e73 in llvm::FPPassManager::runOnFunction(llvm::Function&) /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/lib/IR/LegacyPassManager.cpp:1430:27
    #6 0x55bf61a9aa70 in llvm::FPPassManager::runOnModule(llvm::Module&) /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/lib/IR/LegacyPassManager.cpp:1476:16
    #7 0x55bf61a82ce2 in runOnModule /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/lib/IR/LegacyPassManager.cpp:1545:27
    #8 0x55bf61a82ce2 in llvm::legacy::PassManagerImpl::run(llvm::Module&) /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/lib/IR/LegacyPassManager.cpp:535:44
    #9 0x55bf5b7d7904 in compileModule /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/tools/llc/llc.cpp:733:8
    #10 0x55bf5b7d7904 in main /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/tools/llc/llc.cpp:420:22
    #11 0x7f6384b17d8f  (/lib/x86_64-linux-gnu/libc.so.6+0x29d8f) (BuildId: 69389d485a9793dbe873f0ea2c93e02efaa9aa3d)
    #12 0x7f6384b17e3f in __libc_start_main (/lib/x86_64-linux-gnu/libc.so.6+0x29e3f) (BuildId: 69389d485a9793dbe873f0ea2c93e02efaa9aa3d)
    #13 0x55bf5b704064 in _start (/b/sanitizer-x86_64-linux-fast/build/llvm_build_asan/bin/llc+0x751c064)
0x602000006718 is located 8 bytes inside of 16-byte region [0x602000006710,0x602000006720)
allocated by thread T0 here:
    #0 0x55bf5b7c3bcd in operator new(unsigned long) /b/sanitizer-x86_64-linux-fast/build/llvm-project/compiler-rt/lib/asan/asan_new_delete.cpp:95:3
    #1 0x55bf5c95c847 in __libcpp_operator_new<unsigned long> /b/sanitizer-x86_64-linux-fast/build/libcxx_build_asan/include/c++/v1/new:266:10
    #2 0x55bf5c95c847 in __libcpp_allocate /b/sanitizer-x86_64-linux-fast/build/libcxx_build_asan/include/c++/v1/new:292:10
    #3 0x55bf5c95c847 in allocate /b/sanitizer-x86_64-linux-fast/build/libcxx_build_asan/include/c++/v1/__memory/allocator.h:115:38
    #4 0x55bf5c95c847 in __allocate_at_least<std::__1::allocator<llvm::MachineBasicBlock *> > /b/sanitizer-x86_64-linux-fast/build/libcxx_build_asan/include/c++/v1/__memory/allocate_at_least.h:55:19
    #5 0x55bf5c95c847 in __split_buffer /b/sanitizer-x86_64-linux-fast/build/libcxx_build_asan/include/c++/v1/__split_buffer:323:29
    #6 0x55bf5c95c847 in void std::__1::vector<llvm::MachineBasicBlock*, std::__1::allocator<llvm::MachineBasicBlock*>>::__push_back_slow_path<llvm::MachineBasicBlock* const&>(llvm::MachineBasicBlock* const&) /b/sanitizer-x86_64-linux-fast/build/libcxx_build_asan/include/c++/v1/vector:1538:49
    #7 0x55bf609e858b in push_back /b/sanitizer-x86_64-linux-fast/build/libcxx_build_asan/include/c++/v1/vector:1556:9
    #8 0x55bf609e858b in addPredecessor /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/lib/CodeGen/MachineBasicBlock.cpp:882:16
    #9 0x55bf609e858b in llvm::MachineBasicBlock::addSuccessor(llvm::MachineBasicBlock*, llvm::BranchProbability) /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/lib/CodeGen/MachineBasicBlock.cpp:779:9
    #10 0x55bf62e4b401 in addSuccessorWithProb /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:2196:10
    #11 0x55bf62e4b401 in llvm::SelectionDAGBuilder::visitSwitchCase(llvm::SwitchCG::CaseBlock&, llvm::MachineBasicBlock*) /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:2576:3
    #12 0x55bf63063ffe in llvm::SelectionDAGISel::FinishBasicBlock() /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1876:10
    #13 0x55bf630506c3 in llvm::SelectionDAGISel::SelectAllBasicBlocks(llvm::Function const&) /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1644:5
    #14 0x55bf630464c4 in llvm::SelectionDAGISel::runOnMachineFunction(llvm::MachineFunction&) /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:480:3
    #15 0x55bf5f5032f9 in (anonymous namespace)::X86DAGToDAGISel::runOnMachineFunction(llvm::MachineFunction&) /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:191:25
    #16 0x55bf60b3be12 in llvm::MachineFunctionPass::runOnFunction(llvm::Function&) /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/lib/CodeGen/MachineFunctionPass.cpp:91:13
    #17 0x55bf61a80e73 in llvm::FPPassManager::runOnFunction(llvm::Function&) /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/lib/IR/LegacyPassManager.cpp:1430:27
    #18 0x55bf61a9aa70 in llvm::FPPassManager::runOnModule(llvm::Module&) /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/lib/IR/LegacyPassManager.cpp:1476:16
    #19 0x55bf61a82ce2 in runOnModule /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/lib/IR/LegacyPassManager.cpp:1545:27
    #20 0x55bf61a82ce2 in llvm::legacy::PassManagerImpl::run(llvm::Module&) /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/lib/IR/LegacyPassManager.cpp:535:44
    #21 0x55bf5b7d7904 in compileModule /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/tools/llc/llc.cpp:733:8
    #22 0x55bf5b7d7904 in main /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/tools/llc/llc.cpp:420:22
    #23 0x7f6384b17d8f  (/lib/x86_64-linux-gnu/libc.so.6+0x29d8f) (BuildId: 69389d485a9793dbe873f0ea2c93e02efaa9aa3d)
HINT: if you don't care about these errors you may set ASAN_OPTIONS=detect_container_overflow=0.
If you suspect a false positive see also: https://github.com/google/sanitizers/wiki/AddressSanitizerContainerOverflow.
SUMMARY: AddressSanitizer: container-overflow /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/lib/CodeGen/BranchFolding.cpp:1517:34 in llvm::BranchFolder::OptimizeBlock(llvm::MachineBasicBlock*)
Shadow bytes around the buggy address:
  0x0c047fff8c90: fa fa fd fd fa fa fd fd fa fa fd fd fa fa fd fd
  0x0c047fff8ca0: fa fa fd fa fa fa fd fd fa fa fd fa fa fa fd fd
  0x0c047fff8cb0: fa fa 00 fa fa fa fd fa fa fa fd fa fa fa fd fa
  0x0c047fff8cc0: fa fa 04 fa fa fa 00 fc fa fa 00 fa fa fa fd fd
  0x0c047fff8cd0: fa fa fd fa fa fa fd fd fa fa fd fa fa fa fd fa
=>0x0c047fff8ce0: fa fa 00[fc]fa fa 00 fa fa fa 00 00 fa fa 00 fa
  0x0c047fff8cf0: fa fa fd fd fa fa fd fd fa fa fd fa fa fa fd fd
  0x0c047fff8d00: fa fa fd fa fa fa fd fa fa fa fd fd fa fa fd fd
  0x0c047fff8d10: fa fa fd fa fa fa fd fa fa fa fd fd fa fa 00 00
  0x0c047fff8d20: fa fa 00 00 fa fa fd fa fa fa fd fd fa fa fd fd
  0x0c047fff8d30: fa fa 00 00 fa fa 00 00 fa fa 00 00 fa fa fd fd
Shadow byte legend (one shadow byte represents 8 application bytes):
  Addressable:           00
  Partially addressable: 01 02 03 04 05 06 07 
  Heap left redzone:       fa
  Freed heap region:       fd
  Stack left redzone:      f1
  Stack mid redzone:       f2
  Stack right redzone:     f3
  Stack after return:      f5
  Stack use after scope:   f8
  Global redzone:          f9
  Global init order:       f6
  Poisoned by user:        f7
  Container overflow:      fc
  Array cookie:            ac
  Intra object redzone:    bb
  ASan internal:           fe
  Left alloca redzone:     ca
  Right alloca redzone:    cb
==1490386==ABORTING
FileCheck error: '<stdin>' is empty.
FileCheck command line:  /b/sanitizer-x86_64-linux-fast/build/llvm_build_asan/bin/FileCheck /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/test/CodeGen/X86/tailcall-extract.ll
--

[hctim]

Ah, looks like you beat me to it. Thanks for reverting early :).

[goldstein.w.n]

In D140931#4097141, @hctim wrote:

Ah, looks like you beat me to it. Thanks for reverting early :).

Not me, thanks are to @goncharov for catching it almost immediately.

Thanks for the reproduction instructions :)

[goldstein.w.n]

Fix ASAN issues

[pengfei]

llvm/lib/CodeGen/BranchFolding.cpp

1547

return true;

[goldstein.w.n]

Fix return

llvm/lib/CodeGen/BranchFolding.cpp

if (MBB->succ_empty() && !PriorCond.empty() && !PriorFBB &&
           MadeChange = true;
           ++NumBranchOpts;
           return MadeChange;
         }
       }
     }
   }
 
-  bool OptForSize =
-      MF.getFunction().hasOptSize() ||
-      llvm::shouldOptimizeForSize(MBB, PSI, &MBBFreqInfo);
-  if (!IsEmptyBlock(MBB) && MBB->pred_size() == 1 && OptForSize) {
-    // Changing "Jcc foo; foo: jmp bar;" into "Jcc bar;" might change the branch
-    // direction, thereby defeating careful block placement and regressing
-    // performance. Therefore, only consider this for optsize functions.
+  if (!IsEmptyBlock(MBB)) {
     MachineInstr &TailCall = *MBB->getFirstNonDebugInstr();
     if (TII->isUnconditionalTailCall(TailCall)) {
-      MachineBasicBlock *Pred = *MBB->pred_begin();
+      for (auto &Pred : MBB->predecessors()) {
         MachineBasicBlock *PredTBB = nullptr, *PredFBB = nullptr;
         SmallVector<MachineOperand, 4> PredCond;
         bool PredAnalyzable =
             !TII->analyzeBranch(*Pred, PredTBB, PredFBB, PredCond, true);
 
+        // Only eliminate if MBB == TBB (Taken Basic Block)
         if (PredAnalyzable && !PredCond.empty() && PredTBB == MBB &&
             PredTBB != PredFBB) {
-        // The predecessor has a conditional branch to this block which consists
-        // of only a tail call. Try to fold the tail call into the conditional
-        // branch.
+          // The predecessor has a conditional branch to this block which
+          // consists of only a tail call. Try to fold the tail call into the
+          // conditional branch.
           if (TII->canMakeTailCallConditional(PredCond, TailCall)) {
             // TODO: It would be nice if analyzeBranch() could provide a pointer
             // to the branch instruction so replaceBranchWithTailCall() doesn't
             // have to search for it.
             TII->replaceBranchWithTailCall(*Pred, PredCond, TailCall);
             ++NumTailCalls;
-          Pred->removeSuccessor(MBB);
             MadeChange = true;
-          return MadeChange;
+            Pred->removeSuccessor(MBB);
           }
         }
         // If the predecessor is falling through to this block, we could reverse
         // the branch condition and fold the tail call into that. However, after
         // that we might have to re-arrange the CFG to fall through to the other
         // block and there is a high risk of regressing code size rather than
         // improving it.
       }
+      if (MadeChange)
+        return MadeChange;
+    }
   }
 
   if (!CurUnAnalyzable) {
     // If this is a two-way branch, and the FBB branches to this block, reverse
     // the condition so the single-basic-block loop is faster.  Instead of:
     //    Loop: xxx; jcc Out; jmp Loop
     // we want:
     //    Loop: xxx; jncc Loop; jmp Out
     if (CurTBB && CurFBB && CurFBB == MBB && CurTBB != MBB) {
       SmallVector<MachineOperand, 4> NewCond(CurCond);
       if (!TII->reverseBranchCondition(NewCond)) {
         DebugLoc dl = getBranchDebugLoc(*MBB);

llvm/test/CodeGen/X86/add.ll

 ; X86-NEXT:    addl $4, %esp
 ; X86-NEXT:    .cfi_adjust_cfa_offset -4
 ; X86-NEXT:  .LBB19_2: # %if.end
 ; X86-NEXT:    retl
 ;
 ; X64-LINUX-LABEL: add_i32_128_flag:
 ; X64-LINUX:       # %bb.0: # %entry
 ; X64-LINUX-NEXT:    subl $-128, %edi
-; X64-LINUX-NEXT:    je .LBB19_1
-; X64-LINUX-NEXT:  # %bb.2: # %if.then
-; X64-LINUX-NEXT:    jmp bar_i32 # TAILCALL
-; X64-LINUX-NEXT:  .LBB19_1: # %if.end
+; X64-LINUX-NEXT:    jne bar_i32 # TAILCALL
+; X64-LINUX-NEXT:  # %bb.1: # %if.end
 ; X64-LINUX-NEXT:    retq
 ;
 ; X64-WIN32-LABEL: add_i32_128_flag:
 ; X64-WIN32:       # %bb.0: # %entry
 ; X64-WIN32-NEXT:    subl $-128, %ecx
-; X64-WIN32-NEXT:    je .LBB19_1
-; X64-WIN32-NEXT:  # %bb.2: # %if.then
-; X64-WIN32-NEXT:    jmp bar_i32 # TAILCALL
-; X64-WIN32-NEXT:  .LBB19_1: # %if.end
+; X64-WIN32-NEXT:    jne bar_i32 # TAILCALL
+; X64-WIN32-NEXT:  # %bb.1: # %if.end
 ; X64-WIN32-NEXT:    retq
 entry:
   %add = add i32 %x, 128
   %tobool = icmp eq i32 %add, 0
   br i1 %tobool, label %if.end, label %if.then
 
 if.then:
   tail call void @bar_i32(i32 %add)

 ; X86-NEXT:    addl $8, %esp
 ; X86-NEXT:    .cfi_adjust_cfa_offset -8
 ; X86-NEXT:  .LBB20_2: # %if.end
 ; X86-NEXT:    retl
 ;
 ; X64-LINUX-LABEL: add_i64_128_flag:
 ; X64-LINUX:       # %bb.0: # %entry
 ; X64-LINUX-NEXT:    subq $-128, %rdi
-; X64-LINUX-NEXT:    je .LBB20_1
-; X64-LINUX-NEXT:  # %bb.2: # %if.then
-; X64-LINUX-NEXT:    jmp bar_i64 # TAILCALL
-; X64-LINUX-NEXT:  .LBB20_1: # %if.end
+; X64-LINUX-NEXT:    jne bar_i64 # TAILCALL
+; X64-LINUX-NEXT:  # %bb.1: # %if.end
 ; X64-LINUX-NEXT:    retq
 ;
 ; X64-WIN32-LABEL: add_i64_128_flag:
 ; X64-WIN32:       # %bb.0: # %entry
 ; X64-WIN32-NEXT:    subq $-128, %rcx
-; X64-WIN32-NEXT:    je .LBB20_1
-; X64-WIN32-NEXT:  # %bb.2: # %if.then
-; X64-WIN32-NEXT:    jmp bar_i64 # TAILCALL
-; X64-WIN32-NEXT:  .LBB20_1: # %if.end
+; X64-WIN32-NEXT:    jne bar_i64 # TAILCALL
+; X64-WIN32-NEXT:  # %bb.1: # %if.end
 ; X64-WIN32-NEXT:    retq
 entry:
   %add = add i64 %x, 128
   %tobool = icmp eq i64 %add, 0
   br i1 %tobool, label %if.end, label %if.then
 
 if.then:
   tail call void @bar_i64(i64 %add)

 ; X86-NEXT:    addl $8, %esp
 ; X86-NEXT:    .cfi_adjust_cfa_offset -8
 ; X86-NEXT:  .LBB21_2: # %if.end
 ; X86-NEXT:    retl
 ;
 ; X64-LINUX-LABEL: add_i64_2147483648_flag:
 ; X64-LINUX:       # %bb.0: # %entry
 ; X64-LINUX-NEXT:    subq $-2147483648, %rdi # imm = 0x80000000
-; X64-LINUX-NEXT:    je .LBB21_1
-; X64-LINUX-NEXT:  # %bb.2: # %if.then
-; X64-LINUX-NEXT:    jmp bar_i64 # TAILCALL
-; X64-LINUX-NEXT:  .LBB21_1: # %if.end
+; X64-LINUX-NEXT:    jne bar_i64 # TAILCALL
+; X64-LINUX-NEXT:  # %bb.1: # %if.end
 ; X64-LINUX-NEXT:    retq
 ;
 ; X64-WIN32-LABEL: add_i64_2147483648_flag:
 ; X64-WIN32:       # %bb.0: # %entry
 ; X64-WIN32-NEXT:    subq $-2147483648, %rcx # imm = 0x80000000
-; X64-WIN32-NEXT:    je .LBB21_1
-; X64-WIN32-NEXT:  # %bb.2: # %if.then
-; X64-WIN32-NEXT:    jmp bar_i64 # TAILCALL
-; X64-WIN32-NEXT:  .LBB21_1: # %if.end
+; X64-WIN32-NEXT:    jne bar_i64 # TAILCALL
+; X64-WIN32-NEXT:  # %bb.1: # %if.end
 ; X64-WIN32-NEXT:    retq
 entry:
   %add = add i64 %x, 2147483648
   %tobool = icmp eq i64 %add, 0
   br i1 %tobool, label %if.end, label %if.then
 
 if.then:
   tail call void @bar_i64(i64 %add)
   br label %if.end
 
 if.end:
   ret void
 }

llvm/test/CodeGen/X86/atom-pad-short-functions.ll

 bb2:
   ret i32 %b
 }
 
 define void @test_call_others(i32 %x) nounwind {
 ; CHECK-LABEL: test_call_others:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    cmpl $0, {{[0-9]+}}(%esp)
-; CHECK-NEXT:    je .LBB6_1
-; CHECK-NEXT:  # %bb.2: # %true.case
-; CHECK-NEXT:    jmp external_function@PLT # TAILCALL
-; CHECK-NEXT:  .LBB6_1: # %if.end
+; CHECK-NEXT:    jne external_function@PLT # TAILCALL
+; CHECK-NEXT:  # %bb.1: # %if.end
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    retl
   %tobool = icmp eq i32 %x, 0
   br i1 %tobool, label %if.end, label %true.case
 

llvm/test/CodeGen/X86/avx512-i1test.ll

 }
 
 ; The following test generates suboptimal code on AVX-512
 ; PR 28175
 define i64 @func2(i1 zeroext %i, i32 %j) {
 ; CHECK-LABEL: func2:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    testl %esi, %esi
-; CHECK-NEXT:    je .LBB1_1
-; CHECK-NEXT:  # %bb.2: # %if.then
-; CHECK-NEXT:    jmp bar # TAILCALL
-; CHECK-NEXT:  .LBB1_1: # %if.end
+; CHECK-NEXT:    jne bar # TAILCALL
+; CHECK-NEXT:  # %bb.1: # %if.end
 ; CHECK-NEXT:    movzbl %dil, %eax
 ; CHECK-NEXT:    orq $-2, %rax
 ; CHECK-NEXT:    retq
 entry:
   %tobool = icmp eq i32 %j, 0
   br i1 %tobool, label %if.end, label %if.then
 
 if.then:                                          ; preds = %entry

llvm/test/CodeGen/X86/bmi.ll

 }
 
 define void @pr40060(i32, i32) {
 ; X86-LABEL: pr40060:
 ; X86:       # %bb.0:
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    bextrl %eax, {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    testl %eax, %eax
-; X86-NEXT:    js .LBB52_1
-; X86-NEXT:  # %bb.2:
-; X86-NEXT:    jmp bar # TAILCALL
-; X86-NEXT:  .LBB52_1:
+; X86-NEXT:    jns bar # TAILCALL
+; X86-NEXT:  # %bb.1:
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: pr40060:
 ; X64:       # %bb.0:
 ; X64-NEXT:    bextrl %esi, %edi, %eax
 ; X64-NEXT:    testl %eax, %eax
-; X64-NEXT:    js .LBB52_1
-; X64-NEXT:  # %bb.2:
-; X64-NEXT:    jmp bar # TAILCALL
-; X64-NEXT:  .LBB52_1:
+; X64-NEXT:    jns bar # TAILCALL
+; X64-NEXT:  # %bb.1:
 ; X64-NEXT:    retq
   %3 = tail call i32 @llvm.x86.bmi.bextr.32(i32 %0, i32 %1)
   %4 = icmp sgt i32 %3, -1
   br i1 %4, label %5, label %6
 
   tail call void @bar()
   br label %6
 

 }
 
 declare dso_local void @bar()
 
 define void @pr42118_i32(i32 %x) {
 ; X86-LABEL: pr42118_i32:
 ; X86:       # %bb.0:
 ; X86-NEXT:    blsrl {{[0-9]+}}(%esp), %eax
-; X86-NEXT:    jne .LBB57_1
-; X86-NEXT:  # %bb.2:
-; X86-NEXT:    jmp bar # TAILCALL
-; X86-NEXT:  .LBB57_1:
+; X86-NEXT:    je bar # TAILCALL
+; X86-NEXT:  # %bb.1:
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: pr42118_i32:
 ; X64:       # %bb.0:
 ; X64-NEXT:    blsrl %edi, %eax
-; X64-NEXT:    jne .LBB57_1
-; X64-NEXT:  # %bb.2:
-; X64-NEXT:    jmp bar # TAILCALL
-; X64-NEXT:  .LBB57_1:
+; X64-NEXT:    je bar # TAILCALL
+; X64-NEXT:  # %bb.1:
 ; X64-NEXT:    retq
   %tmp = sub i32 0, %x
   %tmp1 = and i32 %tmp, %x
   %cmp = icmp eq i32 %tmp1, %x
   br i1 %cmp, label %1, label %2
 
   tail call void @bar()
   br label %2

 ; X86-NEXT:    .cfi_def_cfa_offset 8
 ; X86-NEXT:    popl %esi
 ; X86-NEXT:    .cfi_def_cfa_offset 4
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: pr42118_i64:
 ; X64:       # %bb.0:
 ; X64-NEXT:    blsrq %rdi, %rax
-; X64-NEXT:    jne .LBB58_1
-; X64-NEXT:  # %bb.2:
-; X64-NEXT:    jmp bar # TAILCALL
-; X64-NEXT:  .LBB58_1:
+; X64-NEXT:    je bar # TAILCALL
+; X64-NEXT:  # %bb.1:
 ; X64-NEXT:    retq
   %tmp = sub i64 0, %x
   %tmp1 = and i64 %tmp, %x
   %cmp = icmp eq i64 %tmp1, %x
   br i1 %cmp, label %1, label %2
 
   tail call void @bar()
   br label %2

llvm/test/CodeGen/X86/brcond.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=i386-apple-darwin10 -mcpu=penryn | FileCheck %s
 
 ; rdar://7475489
 
 define i32 @test1(i32 %a, i32 %b) nounwind ssp {
 ; CHECK-LABEL: test1:
 ; CHECK:       ## %bb.0: ## %entry
 ; CHECK-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
 ; CHECK-NEXT:    xorb {{[0-9]+}}(%esp), %al
 ; CHECK-NEXT:    testb $64, %al
-; CHECK-NEXT:    je LBB0_1
-; CHECK-NEXT:  ## %bb.2: ## %bb1
-; CHECK-NEXT:    jmp _bar ## TAILCALL
-; CHECK-NEXT:  LBB0_1: ## %bb
+; CHECK-NEXT:    jne _bar ## TAILCALL
+; CHECK-NEXT:  ## %bb.1: ## %bb
 ; CHECK-NEXT:    jmp _foo ## TAILCALL
 entry:
   %0 = and i32 %a, 16384
   %1 = icmp ne i32 %0, 0
   %2 = and i32 %b, 16384
   %3 = icmp ne i32 %2, 0
   %4 = xor i1 %1, %3
   br i1 %4, label %bb1, label %bb

llvm/test/CodeGen/X86/btq.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
 
 declare dso_local void @bar()
 
 define void @test1(i64 %foo) nounwind {
 ; CHECK-LABEL: test1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    btq $32, %rdi
-; CHECK-NEXT:    jb .LBB0_2
+; CHECK-NEXT:    jb bar # TAILCALL
 ; CHECK-NEXT:  # %bb.1: # %if.end
 ; CHECK-NEXT:    retq
-; CHECK-NEXT:  .LBB0_2: # %if.then
-; CHECK-NEXT:    jmp bar # TAILCALL
   %and = and i64 %foo, 4294967296
   %tobool = icmp eq i64 %and, 0
   br i1 %tobool, label %if.end, label %if.then
 
 if.then:
   tail call void @bar() nounwind
   br label %if.end
 
 if.end:
   ret void
 }
 
 define void @test2(i64 %foo) nounwind {
 ; CHECK-LABEL: test2:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    testl %edi, %edi
-; CHECK-NEXT:    js .LBB1_2
+; CHECK-NEXT:    js bar # TAILCALL
 ; CHECK-NEXT:  # %bb.1: # %if.end
 ; CHECK-NEXT:    retq
-; CHECK-NEXT:  .LBB1_2: # %if.then
-; CHECK-NEXT:    jmp bar # TAILCALL
   %and = and i64 %foo, 2147483648
   %tobool = icmp eq i64 %and, 0
   br i1 %tobool, label %if.end, label %if.then
 
 if.then:
   tail call void @bar() nounwind
   br label %if.end
 
 if.end:
   ret void
 }

llvm/test/CodeGen/X86/cmp-merge.ll

 declare void @on_equal()
 declare void @on_greater()
 
 define void @eq_first(i32 %0, i32 %1) {
 ; X86-LABEL: eq_first:
 ; X86:       # %bb.0:
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    cmpl %eax, {{[0-9]+}}(%esp)
-; X86-NEXT:    jge .LBB0_1
-; X86-NEXT:  # %bb.3:
-; X86-NEXT:    jmp on_less@PLT # TAILCALL
-; X86-NEXT:  .LBB0_1:
-; X86-NEXT:    jne .LBB0_2
-; X86-NEXT:  # %bb.4:
-; X86-NEXT:    jmp on_equal@PLT # TAILCALL
-; X86-NEXT:  .LBB0_2:
+; X86-NEXT:    jl on_less@PLT # TAILCALL
+; X86-NEXT:  # %bb.1:
+; X86-NEXT:    je on_equal@PLT # TAILCALL
+; X86-NEXT:  # %bb.2:
 ; X86-NEXT:    jmp on_greater@PLT # TAILCALL
 ;
 ; X64-LABEL: eq_first:
 ; X64:       # %bb.0:
 ; X64-NEXT:    cmpl %esi, %edi
-; X64-NEXT:    jge .LBB0_1
-; X64-NEXT:  # %bb.3:
-; X64-NEXT:    jmp on_less@PLT # TAILCALL
-; X64-NEXT:  .LBB0_1:
-; X64-NEXT:    jne .LBB0_2
-; X64-NEXT:  # %bb.4:
-; X64-NEXT:    jmp on_equal@PLT # TAILCALL
-; X64-NEXT:  .LBB0_2:
+; X64-NEXT:    jl on_less@PLT # TAILCALL
+; X64-NEXT:  # %bb.1:
+; X64-NEXT:    je on_equal@PLT # TAILCALL
+; X64-NEXT:  # %bb.2:
 ; X64-NEXT:    jmp on_greater@PLT # TAILCALL
   %3 = icmp slt i32 %0, %1
   br i1 %3, label %4, label %5
 4:
   tail call void @on_less()
   br label %9
 5:
   %6 = icmp eq i32 %0, %1

 }
 
 define void @gt_first(i32 %0, i32 %1) {
 ; X86-LABEL: gt_first:
 ; X86:       # %bb.0:
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X86-NEXT:    cmpl %eax, %ecx
-; X86-NEXT:    jge .LBB1_1
-; X86-NEXT:  # %bb.3:
-; X86-NEXT:    jmp on_less@PLT # TAILCALL
-; X86-NEXT:  .LBB1_1:
-; X86-NEXT:    jle .LBB1_2
-; X86-NEXT:  # %bb.4:
-; X86-NEXT:    jmp on_greater@PLT # TAILCALL
-; X86-NEXT:  .LBB1_2:
+; X86-NEXT:    jl on_less@PLT # TAILCALL
+; X86-NEXT:  # %bb.1:
+; X86-NEXT:    jg on_greater@PLT # TAILCALL
+; X86-NEXT:  # %bb.2:
 ; X86-NEXT:    jmp on_equal@PLT # TAILCALL
 ;
 ; X64-LABEL: gt_first:
 ; X64:       # %bb.0:
 ; X64-NEXT:    cmpl %esi, %edi
-; X64-NEXT:    jge .LBB1_1
-; X64-NEXT:  # %bb.3:
-; X64-NEXT:    jmp on_less@PLT # TAILCALL
-; X64-NEXT:  .LBB1_1:
-; X64-NEXT:    jle .LBB1_2
-; X64-NEXT:  # %bb.4:
-; X64-NEXT:    jmp on_greater@PLT # TAILCALL
-; X64-NEXT:  .LBB1_2:
+; X64-NEXT:    jl on_less@PLT # TAILCALL
+; X64-NEXT:  # %bb.1:
+; X64-NEXT:    jg on_greater@PLT # TAILCALL
+; X64-NEXT:  # %bb.2:
 ; X64-NEXT:    jmp on_equal@PLT # TAILCALL
   %3 = icmp slt i32 %0, %1
   br i1 %3, label %4, label %5
 4:
   tail call void @on_less()
   br label %9
 5:
   %6 = icmp slt i32 %1, %0

llvm/test/CodeGen/X86/cmp.ll

 
 ; Make sure we use a 32-bit comparison without an extend based on the input
 ; being pre-sign extended by caller.
 define i32 @pr42189(i16 signext %c) {
 ; CHECK-LABEL: pr42189:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpl $32767, %edi # encoding: [0x81,0xff,0xff,0x7f,0x00,0x00]
 ; CHECK-NEXT:    # imm = 0x7FFF
-; CHECK-NEXT:    jne .LBB45_2 # encoding: [0x75,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB45_2-1, kind: FK_PCRel_1
+; CHECK-NEXT:    jne f@PLT # TAILCALL
+; CHECK-NEXT:    # encoding: [0x75,A]
+; CHECK-NEXT:    # fixup A - offset: 1, value: f@PLT-1, kind: FK_PCRel_1
 ; CHECK-NEXT:  # %bb.1: # %if.then
 ; CHECK-NEXT:    jmp g@PLT # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: g@PLT-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB45_2: # %if.end
-; CHECK-NEXT:    jmp f@PLT # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: f@PLT-1, kind: FK_PCRel_1
 entry:
   %cmp = icmp eq i16 %c, 32767
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
   %call = tail call i32 @g()
   br label %return
 

llvm/test/CodeGen/X86/comi-flags.ll

 
 define void @PR38960_eq(<4 x float> %A, <4 x float> %B) {
 ; SSE-LABEL: PR38960_eq:
 ; SSE:       # %bb.0: # %entry
 ; SSE-NEXT:    comiss %xmm1, %xmm0
 ; SSE-NEXT:    setnp %al
 ; SSE-NEXT:    sete %cl
 ; SSE-NEXT:    testb %al, %cl
-; SSE-NEXT:    je .LBB24_1
-; SSE-NEXT:  # %bb.2: # %if.then
-; SSE-NEXT:    jmp foo@PLT # TAILCALL
-; SSE-NEXT:  .LBB24_1: # %if.end
+; SSE-NEXT:    jne foo@PLT # TAILCALL
+; SSE-NEXT:  # %bb.1: # %if.end
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: PR38960_eq:
 ; AVX:       # %bb.0: # %entry
 ; AVX-NEXT:    vcomiss %xmm1, %xmm0
 ; AVX-NEXT:    setnp %al
 ; AVX-NEXT:    sete %cl
 ; AVX-NEXT:    testb %al, %cl
-; AVX-NEXT:    je .LBB24_1
-; AVX-NEXT:  # %bb.2: # %if.then
-; AVX-NEXT:    jmp foo@PLT # TAILCALL
-; AVX-NEXT:  .LBB24_1: # %if.end
+; AVX-NEXT:    jne foo@PLT # TAILCALL
+; AVX-NEXT:  # %bb.1: # %if.end
 ; AVX-NEXT:    retq
 entry:
   %call = tail call i32 @llvm.x86.sse.comieq.ss(<4 x float> %A, <4 x float> %B) #3
   %cmp = icmp eq i32 %call, 0
   br i1 %cmp, label %if.end, label %if.then
 
 if.then:
   tail call void @foo()
   br label %if.end
 
 if.end:
   ret void
 }
 
 define void @PR38960_neq(<4 x float> %A, <4 x float> %B) {
 ; SSE-LABEL: PR38960_neq:
 ; SSE:       # %bb.0: # %entry
 ; SSE-NEXT:    comiss %xmm1, %xmm0
 ; SSE-NEXT:    setp %al
 ; SSE-NEXT:    setne %cl
 ; SSE-NEXT:    orb %al, %cl
-; SSE-NEXT:    je .LBB25_1
-; SSE-NEXT:  # %bb.2: # %if.then
-; SSE-NEXT:    jmp foo@PLT # TAILCALL
-; SSE-NEXT:  .LBB25_1: # %if.end
+; SSE-NEXT:    jne foo@PLT # TAILCALL
+; SSE-NEXT:  # %bb.1: # %if.end
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: PR38960_neq:
 ; AVX:       # %bb.0: # %entry
 ; AVX-NEXT:    vcomiss %xmm1, %xmm0
 ; AVX-NEXT:    setp %al
 ; AVX-NEXT:    setne %cl
 ; AVX-NEXT:    orb %al, %cl
-; AVX-NEXT:    je .LBB25_1
-; AVX-NEXT:  # %bb.2: # %if.then
-; AVX-NEXT:    jmp foo@PLT # TAILCALL
-; AVX-NEXT:  .LBB25_1: # %if.end
+; AVX-NEXT:    jne foo@PLT # TAILCALL
+; AVX-NEXT:  # %bb.1: # %if.end
 ; AVX-NEXT:    retq
 entry:
   %call = tail call i32 @llvm.x86.sse.comineq.ss(<4 x float> %A, <4 x float> %B) #3
   %cmp = icmp eq i32 %call, 0
   br i1 %cmp, label %if.end, label %if.then
 
 if.then:
   tail call void @foo()
   br label %if.end
 
 if.end:
   ret void
 }
 declare void @foo()

llvm/test/CodeGen/X86/extern_weak.ll

if.then:
   ret void
 
 if.end:
   ret void
 }
 
 ; DARWIN-LABEL: _bar:
 ; DARWIN: cmpl $0, L_foo$non_lazy_ptr
-; DARWIN: jmp _foo ## TAILCALL
+; DARWIN: jne _foo ## TAILCALL
 
 ; WIN32-LABEL: _bar:
 ; WIN32: cmpl $0, .refptr._foo
 ; WIN32: jmpl *.refptr._foo
 
 ; WIN64-LABEL: bar:
 ; WIN64: cmpq $0, .refptr.foo(%rip)
 ; WIN64: jmpq *.refptr.foo

llvm/test/CodeGen/X86/fold-rmw-ops.ll

 declare dso_local void @b()
 
 define void @add64_imm32_br() nounwind {
 ; CHECK-LABEL: add64_imm32_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addq $16777214, g64(%rip) # encoding: [0x48,0x81,0x05,A,A,A,A,0xfe,0xff,0xff,0x00]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: g64-8, kind: reloc_riprel_4byte
 ; CHECK-NEXT:    # imm = 0xFFFFFE
-; CHECK-NEXT:    js .LBB0_1 # encoding: [0x78,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB0_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jns b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x79,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB0_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i64, ptr @g64
   ; Add 0x00FFFFFE, a positive immediate requiring 24-bits.
   %add = add i64 %load1, 16777214
   store i64 %add, ptr @g64

 }
 
 define void @add64_sext_imm32_br() nounwind {
 ; CHECK-LABEL: add64_sext_imm32_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addq $-2147483648, g64(%rip) # encoding: [0x48,0x81,0x05,A,A,A,A,0x00,0x00,0x00,0x80]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: g64-8, kind: reloc_riprel_4byte
 ; CHECK-NEXT:    # imm = 0x80000000
-; CHECK-NEXT:    js .LBB1_1 # encoding: [0x78,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB1_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jns b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x79,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB1_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i64, ptr @g64
   ; Add -0x80000000, which requires sign-extended 32 bits.
   %add = add i64 %load1, -2147483648
   store i64 %add, ptr @g64

 }
 
 define void @add64_imm32_via_sub_br() nounwind {
 ; CHECK-LABEL: add64_imm32_via_sub_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    subq $-2147483648, g64(%rip) # encoding: [0x48,0x81,0x2d,A,A,A,A,0x00,0x00,0x00,0x80]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: g64-8, kind: reloc_riprel_4byte
 ; CHECK-NEXT:    # imm = 0x80000000
-; CHECK-NEXT:    js .LBB2_1 # encoding: [0x78,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB2_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jns b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x79,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB2_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i64, ptr @g64
   ; Add 0x80000000, which cannot fit in a sign extended 32-bit immediate. This
   ; get's folded because we can instead subtract -0x80000000.
   %add = add i64 %load1, 2147483648

 
 define void @add64_no_imm32_via_sub_due_to_cf_br() nounwind {
 ; CHECK-LABEL: add64_no_imm32_via_sub_due_to_cf_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    movl $2147483648, %eax # encoding: [0xb8,0x00,0x00,0x00,0x80]
 ; CHECK-NEXT:    # imm = 0x80000000
 ; CHECK-NEXT:    addq %rax, g64(%rip) # encoding: [0x48,0x01,0x05,A,A,A,A]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: g64-4, kind: reloc_riprel_4byte
-; CHECK-NEXT:    jae .LBB3_2 # encoding: [0x73,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB3_2-1, kind: FK_PCRel_1
+; CHECK-NEXT:    jae b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x73,A]
+; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
 ; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB3_2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
 entry:
   %load1 = load i64, ptr @g64
   ; Add 0x80000000, which cannot fit in a sign extended 32-bit immediate, but
   ; could in theory be folded into an immediate operand of a sub. However, we
   ; use the CF flag here and so shouldn't make that transformation.
   %add = add i64 %load1, 2147483648
   store i64 %add, ptr @g64
   %cond = icmp ult i64 %add, 2147483648

 
 define void @add64_too_large_imm32_br() nounwind {
 ; CHECK-LABEL: add64_too_large_imm32_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    movl $2147483649, %eax # encoding: [0xb8,0x01,0x00,0x00,0x80]
 ; CHECK-NEXT:    # imm = 0x80000001
 ; CHECK-NEXT:    addq %rax, g64(%rip) # encoding: [0x48,0x01,0x05,A,A,A,A]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: g64-4, kind: reloc_riprel_4byte
-; CHECK-NEXT:    js .LBB4_1 # encoding: [0x78,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB4_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jns b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x79,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB4_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i64, ptr @g64
   ; Add 0x80000001, which cannot fit in a sign extended 32-bit immediate. This
   ; should not get folded into an immediate.
   %add = add i64 %load1, 2147483649
b:
   ret void
 }
 
 define void @add64_imm8_via_sub_br() nounwind {
 ; CHECK-LABEL: add64_imm8_via_sub_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    subq $-128, g64(%rip) # encoding: [0x48,0x83,0x2d,A,A,A,A,0x80]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: g64-5, kind: reloc_riprel_4byte
-; CHECK-NEXT:    js .LBB5_1 # encoding: [0x78,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB5_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jns b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x79,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB5_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i64, ptr @g64
   ; Add 0x80 which can't quite fit into an imm8 because it would be sign
   ; extended, but which can fit if we convert to a sub and negate the value.
   %add = add i64 %load1, 128
b:
   ret void
 }
 
 define void @add64_imm8_br() nounwind {
 ; CHECK-LABEL: add64_imm8_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addq $42, g64(%rip) # encoding: [0x48,0x83,0x05,A,A,A,A,0x2a]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: g64-5, kind: reloc_riprel_4byte
-; CHECK-NEXT:    js .LBB6_1 # encoding: [0x78,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB6_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jns b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x79,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB6_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i64, ptr @g64
   %add = add i64 %load1, 42
   store i64 %add, ptr @g64
   %cond = icmp slt i64 %add, 0
   br i1 %cond, label %a, label %b
 
 a:
   tail call void @a()
   ret void
 
 b:
   tail call void @b()
   ret void
 }
 
 define void @add64_imm8_neg_br() nounwind {
 ; CHECK-LABEL: add64_imm8_neg_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addq $-42, g64(%rip) # encoding: [0x48,0x83,0x05,A,A,A,A,0xd6]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: g64-5, kind: reloc_riprel_4byte
-; CHECK-NEXT:    js .LBB7_1 # encoding: [0x78,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB7_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jns b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x79,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB7_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i64, ptr @g64
   %add = add i64 %load1, -42
   store i64 %add, ptr @g64
   %cond = icmp slt i64 %add, 0

 }
 
 define void @add32_imm_br() nounwind {
 ; CHECK-LABEL: add32_imm_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addl $-2147483648, g32(%rip) # encoding: [0x81,0x05,A,A,A,A,0x00,0x00,0x00,0x80]
 ; CHECK-NEXT:    # fixup A - offset: 2, value: g32-8, kind: reloc_riprel_4byte
 ; CHECK-NEXT:    # imm = 0x80000000
-; CHECK-NEXT:    js .LBB8_1 # encoding: [0x78,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB8_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jns b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x79,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB8_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i32, ptr @g32
   ; Add 0x80000000, a positive number requiring 32 bits of immediate.
   %add = add i32 %load1, 2147483648
   store i32 %add, ptr @g32
b:
   ret void
 }
 
 define void @add32_imm8_br() nounwind {
 ; CHECK-LABEL: add32_imm8_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addl $42, g32(%rip) # encoding: [0x83,0x05,A,A,A,A,0x2a]
 ; CHECK-NEXT:    # fixup A - offset: 2, value: g32-5, kind: reloc_riprel_4byte
-; CHECK-NEXT:    js .LBB9_1 # encoding: [0x78,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB9_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jns b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x79,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB9_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i32, ptr @g32
   %add = add i32 %load1, 42
   store i32 %add, ptr @g32
   %cond = icmp slt i32 %add, 0
   br i1 %cond, label %a, label %b
 
 a:
   tail call void @a()
   ret void
 
 b:
   tail call void @b()
   ret void
 }
 
 define void @add32_imm8_neg_br() nounwind {
 ; CHECK-LABEL: add32_imm8_neg_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addl $-42, g32(%rip) # encoding: [0x83,0x05,A,A,A,A,0xd6]
 ; CHECK-NEXT:    # fixup A - offset: 2, value: g32-5, kind: reloc_riprel_4byte
-; CHECK-NEXT:    js .LBB10_1 # encoding: [0x78,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB10_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jns b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x79,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB10_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i32, ptr @g32
   %add = add i32 %load1, -42
   store i32 %add, ptr @g32
   %cond = icmp slt i32 %add, 0

 }
 
 define void @add16_imm_br() nounwind {
 ; CHECK-LABEL: add16_imm_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addw $-32768, g16(%rip) # encoding: [0x66,0x81,0x05,A,A,A,A,0x00,0x80]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: g16-6, kind: reloc_riprel_4byte
 ; CHECK-NEXT:    # imm = 0x8000
-; CHECK-NEXT:    js .LBB11_1 # encoding: [0x78,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB11_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jns b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x79,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB11_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i16, ptr @g16
   ; Add 0x8000, a positive number requiring 16 bits of immediate.
   %add = add i16 %load1, 32768
   store i16 %add, ptr @g16
b:
   ret void
 }
 
 define void @add16_imm8_br() nounwind {
 ; CHECK-LABEL: add16_imm8_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addw $42, g16(%rip) # encoding: [0x66,0x83,0x05,A,A,A,A,0x2a]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: g16-5, kind: reloc_riprel_4byte
-; CHECK-NEXT:    js .LBB12_1 # encoding: [0x78,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB12_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jns b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x79,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB12_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i16, ptr @g16
   %add = add i16 %load1, 42
   store i16 %add, ptr @g16
   %cond = icmp slt i16 %add, 0
   br i1 %cond, label %a, label %b
 
 a:
   tail call void @a()
   ret void
 
 b:
   tail call void @b()
   ret void
 }
 
 define void @add16_imm8_neg_br() nounwind {
 ; CHECK-LABEL: add16_imm8_neg_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addw $-42, g16(%rip) # encoding: [0x66,0x83,0x05,A,A,A,A,0xd6]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: g16-5, kind: reloc_riprel_4byte
-; CHECK-NEXT:    js .LBB13_1 # encoding: [0x78,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB13_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jns b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x79,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB13_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i16, ptr @g16
   %add = add i16 %load1, -42
   store i16 %add, ptr @g16
   %cond = icmp slt i16 %add, 0
   br i1 %cond, label %a, label %b
 
 a:
   tail call void @a()
   ret void
 
 b:
   tail call void @b()
   ret void
 }
 
 define void @add8_imm_br() nounwind {
 ; CHECK-LABEL: add8_imm_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addb $-2, g8(%rip) # encoding: [0x80,0x05,A,A,A,A,0xfe]
 ; CHECK-NEXT:    # fixup A - offset: 2, value: g8-5, kind: reloc_riprel_4byte
-; CHECK-NEXT:    js .LBB14_1 # encoding: [0x78,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB14_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jns b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x79,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB14_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i8, ptr @g8
   %add = add i8 %load1, -2
   store i8 %add, ptr @g8
   %cond = icmp slt i8 %add, 0
   br i1 %cond, label %a, label %b
 
 a:
   tail call void @a()
   ret void
 
 b:
   tail call void @b()
   ret void
 }
 
 define void @add64_reg_br(i64 %arg) nounwind {
 ; CHECK-LABEL: add64_reg_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addq %rdi, g64(%rip) # encoding: [0x48,0x01,0x3d,A,A,A,A]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: g64-4, kind: reloc_riprel_4byte
-; CHECK-NEXT:    js .LBB15_1 # encoding: [0x78,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB15_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jns b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x79,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB15_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i64, ptr @g64
   %add = add i64 %load1, %arg
   store i64 %add, ptr @g64
   %cond = icmp slt i64 %add, 0
   br i1 %cond, label %a, label %b
 
 a:
   tail call void @a()
   ret void
 
 b:
   tail call void @b()
   ret void
 }
 
 define void @add32_reg_br(i32 %arg) nounwind {
 ; CHECK-LABEL: add32_reg_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addl %edi, g32(%rip) # encoding: [0x01,0x3d,A,A,A,A]
 ; CHECK-NEXT:    # fixup A - offset: 2, value: g32-4, kind: reloc_riprel_4byte
-; CHECK-NEXT:    js .LBB16_1 # encoding: [0x78,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB16_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jns b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x79,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB16_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i32, ptr @g32
   %add = add i32 %load1, %arg
   store i32 %add, ptr @g32
   %cond = icmp slt i32 %add, 0
   br i1 %cond, label %a, label %b
 
 a:
   tail call void @a()
   ret void
 
 b:
   tail call void @b()
   ret void
 }
 
 define void @add16_reg_br(i16 %arg) nounwind {
 ; CHECK-LABEL: add16_reg_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addw %di, g16(%rip) # encoding: [0x66,0x01,0x3d,A,A,A,A]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: g16-4, kind: reloc_riprel_4byte
-; CHECK-NEXT:    js .LBB17_1 # encoding: [0x78,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB17_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jns b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x79,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB17_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i16, ptr @g16
   %add = add i16 %load1, %arg
   store i16 %add, ptr @g16
   %cond = icmp slt i16 %add, 0
   br i1 %cond, label %a, label %b
 
 a:
   tail call void @a()
   ret void
 
 b:
   tail call void @b()
   ret void
 }
 
 define void @add8_reg_br(i8 %arg) nounwind {
 ; CHECK-LABEL: add8_reg_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addb %dil, g8(%rip) # encoding: [0x40,0x00,0x3d,A,A,A,A]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: g8-4, kind: reloc_riprel_4byte
-; CHECK-NEXT:    js .LBB18_1 # encoding: [0x78,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB18_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jns b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x79,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB18_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i8, ptr @g8
   %add = add i8 %load1, %arg
   store i8 %add, ptr @g8
   %cond = icmp slt i8 %add, 0

 }
 
 define void @sub64_imm32_br() nounwind {
 ; CHECK-LABEL: sub64_imm32_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    subq $-2147483648, g64(%rip) # encoding: [0x48,0x81,0x2d,A,A,A,A,0x00,0x00,0x00,0x80]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: g64-8, kind: reloc_riprel_4byte
 ; CHECK-NEXT:    # imm = 0x80000000
-; CHECK-NEXT:    js .LBB19_1 # encoding: [0x78,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB19_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jns b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x79,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB19_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i64, ptr @g64
   ; Subtract -0x80000000, which can't be negated into a sign-extended 32-bit
   ; immediate, so that we have to select sub here.
   %sub = sub i64 %load1, -2147483648

 
 define void @sub64_too_large_imm32_br() nounwind {
 ; CHECK-LABEL: sub64_too_large_imm32_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    movabsq $-4294967295, %rax # encoding: [0x48,0xb8,0x01,0x00,0x00,0x00,0xff,0xff,0xff,0xff]
 ; CHECK-NEXT:    # imm = 0xFFFFFFFF00000001
 ; CHECK-NEXT:    addq %rax, g64(%rip) # encoding: [0x48,0x01,0x05,A,A,A,A]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: g64-4, kind: reloc_riprel_4byte
-; CHECK-NEXT:    js .LBB20_1 # encoding: [0x78,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB20_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jns b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x79,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB20_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i64, ptr @g64
   ; Subtract 0xFFFFFFFF, which cannot fit in a sign extended 32-bit immediate,
   ; even if negated and sign extended as an add.
   %sub = sub i64 %load1, 4294967295
b:
   ret void
 }
 
 define void @sub64_imm8_br() nounwind {
 ; CHECK-LABEL: sub64_imm8_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    subq $-128, g64(%rip) # encoding: [0x48,0x83,0x2d,A,A,A,A,0x80]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: g64-5, kind: reloc_riprel_4byte
-; CHECK-NEXT:    js .LBB21_1 # encoding: [0x78,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB21_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jns b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x79,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB21_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i64, ptr @g64
   ; Subtract -0x80, which can be done with an 8-bit immediate but only as
   ; a subtract where that immediate can be negative.
   %sub = sub i64 %load1, -128

 }
 
 define void @sub32_imm_br() nounwind {
 ; CHECK-LABEL: sub32_imm_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addl $-2147483648, g32(%rip) # encoding: [0x81,0x05,A,A,A,A,0x00,0x00,0x00,0x80]
 ; CHECK-NEXT:    # fixup A - offset: 2, value: g32-8, kind: reloc_riprel_4byte
 ; CHECK-NEXT:    # imm = 0x80000000
-; CHECK-NEXT:    js .LBB22_1 # encoding: [0x78,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB22_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jns b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x79,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB22_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i32, ptr @g32
   ; Subtract -0x80000000, which requires 32 bits of immediate but still gets
   ; lowered as an add.
   %sub = sub i32 %load1, -2147483648
b:
   ret void
 }
 
 define void @sub32_imm8_br() nounwind {
 ; CHECK-LABEL: sub32_imm8_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    subl $-128, g32(%rip) # encoding: [0x83,0x2d,A,A,A,A,0x80]
 ; CHECK-NEXT:    # fixup A - offset: 2, value: g32-5, kind: reloc_riprel_4byte
-; CHECK-NEXT:    js .LBB23_1 # encoding: [0x78,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB23_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jns b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x79,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB23_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i32, ptr @g32
   ; Subtract -0x80, which can be done with an 8-bit immediate but only as
   ; a subtract where that immediate can be negative.
   %sub = sub i32 %load1, -128

 }
 
 define void @sub16_imm_br() nounwind {
 ; CHECK-LABEL: sub16_imm_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addw $-32768, g16(%rip) # encoding: [0x66,0x81,0x05,A,A,A,A,0x00,0x80]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: g16-6, kind: reloc_riprel_4byte
 ; CHECK-NEXT:    # imm = 0x8000
-; CHECK-NEXT:    js .LBB24_1 # encoding: [0x78,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB24_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jns b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x79,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB24_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i16, ptr @g16
   ; Subtract -0x8000, which requires a 16 bits of immediate but still gets
   ; lowered as an add.
   %sub = sub i16 %load1, -32768
b:
   ret void
 }
 
 define void @sub16_imm8_br() nounwind {
 ; CHECK-LABEL: sub16_imm8_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    subw $-128, g16(%rip) # encoding: [0x66,0x83,0x2d,A,A,A,A,0x80]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: g16-5, kind: reloc_riprel_4byte
-; CHECK-NEXT:    js .LBB25_1 # encoding: [0x78,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB25_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jns b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x79,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB25_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i16, ptr @g16
   ; Subtract -0x80, which can be done with an 8-bit immediate but only as
   ; a subtract where that immediate can be negative.
   %sub = sub i16 %load1, -128
b:
   ret void
 }
 
 define void @sub8_imm_br() nounwind {
 ; CHECK-LABEL: sub8_imm_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addb $-128, g8(%rip) # encoding: [0x80,0x05,A,A,A,A,0x80]
 ; CHECK-NEXT:    # fixup A - offset: 2, value: g8-5, kind: reloc_riprel_4byte
-; CHECK-NEXT:    js .LBB26_1 # encoding: [0x78,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB26_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jns b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x79,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB26_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i8, ptr @g8
   ; Subtract -0x80, which requires an 8-bit immediate but still gets lowered as
   ; an add.
   %sub = sub i8 %load1, -128
b:
   ret void
 }
 
 define void @sub64_reg_br(i64 %arg) nounwind {
 ; CHECK-LABEL: sub64_reg_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    subq %rdi, g64(%rip) # encoding: [0x48,0x29,0x3d,A,A,A,A]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: g64-4, kind: reloc_riprel_4byte
-; CHECK-NEXT:    js .LBB27_1 # encoding: [0x78,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB27_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jns b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x79,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB27_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i64, ptr @g64
   %sub = sub i64 %load1, %arg
   store i64 %sub, ptr @g64
   %cond = icmp slt i64 %sub, 0
   br i1 %cond, label %a, label %b
 
 a:
   tail call void @a()
   ret void
 
 b:
   tail call void @b()
   ret void
 }
 
 define void @sub32_reg_br(i32 %arg) nounwind {
 ; CHECK-LABEL: sub32_reg_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    subl %edi, g32(%rip) # encoding: [0x29,0x3d,A,A,A,A]
 ; CHECK-NEXT:    # fixup A - offset: 2, value: g32-4, kind: reloc_riprel_4byte
-; CHECK-NEXT:    js .LBB28_1 # encoding: [0x78,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB28_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jns b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x79,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB28_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i32, ptr @g32
   %sub = sub i32 %load1, %arg
   store i32 %sub, ptr @g32
   %cond = icmp slt i32 %sub, 0
   br i1 %cond, label %a, label %b
 
 a:
   tail call void @a()
   ret void
 
 b:
   tail call void @b()
   ret void
 }
 
 define void @sub16_reg_br(i16 %arg) nounwind {
 ; CHECK-LABEL: sub16_reg_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    subw %di, g16(%rip) # encoding: [0x66,0x29,0x3d,A,A,A,A]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: g16-4, kind: reloc_riprel_4byte
-; CHECK-NEXT:    js .LBB29_1 # encoding: [0x78,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB29_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jns b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x79,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB29_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i16, ptr @g16
   %sub = sub i16 %load1, %arg
   store i16 %sub, ptr @g16
   %cond = icmp slt i16 %sub, 0
   br i1 %cond, label %a, label %b
 
 a:
   tail call void @a()
   ret void
 
 b:
   tail call void @b()
   ret void
 }
 
 define void @sub8_reg_br(i8 %arg) nounwind {
 ; CHECK-LABEL: sub8_reg_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    subb %dil, g8(%rip) # encoding: [0x40,0x28,0x3d,A,A,A,A]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: g8-4, kind: reloc_riprel_4byte
-; CHECK-NEXT:    js .LBB30_1 # encoding: [0x78,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB30_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jns b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x79,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB30_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i8, ptr @g8
   %sub = sub i8 %load1, %arg
   store i8 %sub, ptr @g8
   %cond = icmp slt i8 %sub, 0

 }
 
 define void @and64_imm32_br() nounwind {
 ; CHECK-LABEL: and64_imm32_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    andq $16777215, g64(%rip) # encoding: [0x48,0x81,0x25,A,A,A,A,0xff,0xff,0xff,0x00]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: g64-8, kind: reloc_riprel_4byte
 ; CHECK-NEXT:    # imm = 0xFFFFFF
-; CHECK-NEXT:    je .LBB31_1 # encoding: [0x74,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB31_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jne b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x75,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB31_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i64, ptr @g64
   ; And 0x00FFFFFF, a positive immediate requiring 24-bits.
   %and = and i64 %load1, 16777215
   store i64 %and, ptr @g64

 }
 
 define void @and64_sext_imm32_br() nounwind {
 ; CHECK-LABEL: and64_sext_imm32_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    andq $-2147483648, g64(%rip) # encoding: [0x48,0x81,0x25,A,A,A,A,0x00,0x00,0x00,0x80]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: g64-8, kind: reloc_riprel_4byte
 ; CHECK-NEXT:    # imm = 0x80000000
-; CHECK-NEXT:    je .LBB32_1 # encoding: [0x74,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB32_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jne b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x75,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB32_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i64, ptr @g64
   ; And -0x80000000, which requires sign-extended 32 bits.
   %and = and i64 %load1, -2147483648
   store i64 %and, ptr @g64
b:
   ret void
 }
 
 define void @and64_imm8_br() nounwind {
 ; CHECK-LABEL: and64_imm8_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    andq $15, g64(%rip) # encoding: [0x48,0x83,0x25,A,A,A,A,0x0f]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: g64-5, kind: reloc_riprel_4byte
-; CHECK-NEXT:    je .LBB33_1 # encoding: [0x74,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB33_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jne b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x75,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB33_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i64, ptr @g64
   %and = and i64 %load1, 15
   store i64 %and, ptr @g64
   %cond = icmp eq i64 %and, 0
   br i1 %cond, label %a, label %b
 
 a:
   tail call void @a()
   ret void
 
 b:
   tail call void @b()
   ret void
 }
 
 define void @and64_imm8_neg_br() nounwind {
 ; CHECK-LABEL: and64_imm8_neg_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    andq $-4, g64(%rip) # encoding: [0x48,0x83,0x25,A,A,A,A,0xfc]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: g64-5, kind: reloc_riprel_4byte
-; CHECK-NEXT:    je .LBB34_1 # encoding: [0x74,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB34_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jne b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x75,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB34_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i64, ptr @g64
   %and = and i64 %load1, -4
   store i64 %and, ptr @g64
   %cond = icmp eq i64 %and, 0

 }
 
 define void @and32_imm_br() nounwind {
 ; CHECK-LABEL: and32_imm_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    andl $-2147483648, g32(%rip) # encoding: [0x81,0x25,A,A,A,A,0x00,0x00,0x00,0x80]
 ; CHECK-NEXT:    # fixup A - offset: 2, value: g32-8, kind: reloc_riprel_4byte
 ; CHECK-NEXT:    # imm = 0x80000000
-; CHECK-NEXT:    jne .LBB35_2 # encoding: [0x75,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB35_2-1, kind: FK_PCRel_1
+; CHECK-NEXT:    jne b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x75,A]
+; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
 ; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB35_2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
 entry:
   %load1 = load i32, ptr @g32
   ; And 0x80000000, a positive number requiring 32 bits of immediate.
   %and = and i32 %load1, 2147483648
   store i32 %and, ptr @g32
   %cond = icmp eq i32 %and, 0
   br i1 %cond, label %a, label %b
 
 a:
   tail call void @a()
   ret void
 
 b:
   tail call void @b()
   ret void
 }
 
 define void @and32_imm8_br() nounwind {
 ; CHECK-LABEL: and32_imm8_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    andl $15, g32(%rip) # encoding: [0x83,0x25,A,A,A,A,0x0f]
 ; CHECK-NEXT:    # fixup A - offset: 2, value: g32-5, kind: reloc_riprel_4byte
-; CHECK-NEXT:    je .LBB36_1 # encoding: [0x74,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB36_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jne b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x75,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB36_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i32, ptr @g32
   %and = and i32 %load1, 15
   store i32 %and, ptr @g32
   %cond = icmp eq i32 %and, 0
   br i1 %cond, label %a, label %b
 
 a:
   tail call void @a()
   ret void
 
 b:
   tail call void @b()
   ret void
 }
 
 define void @and32_imm8_neg_br() nounwind {
 ; CHECK-LABEL: and32_imm8_neg_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    andl $-4, g32(%rip) # encoding: [0x83,0x25,A,A,A,A,0xfc]
 ; CHECK-NEXT:    # fixup A - offset: 2, value: g32-5, kind: reloc_riprel_4byte
-; CHECK-NEXT:    je .LBB37_1 # encoding: [0x74,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB37_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jne b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x75,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB37_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i32, ptr @g32
   %and = and i32 %load1, -4
   store i32 %and, ptr @g32
   %cond = icmp eq i32 %and, 0

 }
 
 define void @and16_imm_br() nounwind {
 ; CHECK-LABEL: and16_imm_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    andw $-32768, g16(%rip) # encoding: [0x66,0x81,0x25,A,A,A,A,0x00,0x80]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: g16-6, kind: reloc_riprel_4byte
 ; CHECK-NEXT:    # imm = 0x8000
-; CHECK-NEXT:    jne .LBB38_2 # encoding: [0x75,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB38_2-1, kind: FK_PCRel_1
+; CHECK-NEXT:    jne b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x75,A]
+; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
 ; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB38_2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
 entry:
   %load1 = load i16, ptr @g16
   %and = and i16 %load1, 32768
   store i16 %and, ptr @g16
   %cond = icmp eq i16 %and, 0
   br i1 %cond, label %a, label %b
 
 a:
   tail call void @a()
   ret void
 
 b:
   tail call void @b()
   ret void
 }
 
 define void @and16_imm8_br() nounwind {
 ; CHECK-LABEL: and16_imm8_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    andw $15, g16(%rip) # encoding: [0x66,0x83,0x25,A,A,A,A,0x0f]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: g16-5, kind: reloc_riprel_4byte
-; CHECK-NEXT:    je .LBB39_1 # encoding: [0x74,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB39_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jne b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x75,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB39_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i16, ptr @g16
   %and = and i16 %load1, 15
   store i16 %and, ptr @g16
   %cond = icmp eq i16 %and, 0
   br i1 %cond, label %a, label %b
 
 a:
   tail call void @a()
   ret void
 
 b:
   tail call void @b()
   ret void
 }
 
 define void @and16_imm8_neg_br() nounwind {
 ; CHECK-LABEL: and16_imm8_neg_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    andw $-4, g16(%rip) # encoding: [0x66,0x83,0x25,A,A,A,A,0xfc]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: g16-5, kind: reloc_riprel_4byte
-; CHECK-NEXT:    je .LBB40_1 # encoding: [0x74,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB40_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jne b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x75,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB40_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i16, ptr @g16
   %and = and i16 %load1, -4
   store i16 %and, ptr @g16
   %cond = icmp eq i16 %and, 0
   br i1 %cond, label %a, label %b
 
 a:
   tail call void @a()
   ret void
 
 b:
   tail call void @b()
   ret void
 }
 
 define void @and8_imm_br() nounwind {
 ; CHECK-LABEL: and8_imm_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    andb $-4, g8(%rip) # encoding: [0x80,0x25,A,A,A,A,0xfc]
 ; CHECK-NEXT:    # fixup A - offset: 2, value: g8-5, kind: reloc_riprel_4byte
-; CHECK-NEXT:    je .LBB41_1 # encoding: [0x74,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB41_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jne b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x75,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB41_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i8, ptr @g8
   %and = and i8 %load1, -4
   store i8 %and, ptr @g8
   %cond = icmp eq i8 %and, 0
   br i1 %cond, label %a, label %b
 
 a:
   tail call void @a()
   ret void
 
 b:
   tail call void @b()
   ret void
 }
 
 define void @and64_reg_br(i64 %arg) nounwind {
 ; CHECK-LABEL: and64_reg_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    andq %rdi, g64(%rip) # encoding: [0x48,0x21,0x3d,A,A,A,A]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: g64-4, kind: reloc_riprel_4byte
-; CHECK-NEXT:    je .LBB42_1 # encoding: [0x74,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB42_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jne b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x75,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB42_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i64, ptr @g64
   %and = and i64 %load1, %arg
   store i64 %and, ptr @g64
   %cond = icmp eq i64 %and, 0
   br i1 %cond, label %a, label %b
 
 a:
   tail call void @a()
   ret void
 
 b:
   tail call void @b()
   ret void
 }
 
 define void @and32_reg_br(i32 %arg) nounwind {
 ; CHECK-LABEL: and32_reg_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    andl %edi, g32(%rip) # encoding: [0x21,0x3d,A,A,A,A]
 ; CHECK-NEXT:    # fixup A - offset: 2, value: g32-4, kind: reloc_riprel_4byte
-; CHECK-NEXT:    je .LBB43_1 # encoding: [0x74,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB43_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jne b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x75,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB43_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i32, ptr @g32
   %and = and i32 %load1, %arg
   store i32 %and, ptr @g32
   %cond = icmp eq i32 %and, 0
   br i1 %cond, label %a, label %b
 
 a:
   tail call void @a()
   ret void
 
 b:
   tail call void @b()
   ret void
 }
 
 define void @and16_reg_br(i16 %arg) nounwind {
 ; CHECK-LABEL: and16_reg_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    andw %di, g16(%rip) # encoding: [0x66,0x21,0x3d,A,A,A,A]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: g16-4, kind: reloc_riprel_4byte
-; CHECK-NEXT:    je .LBB44_1 # encoding: [0x74,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB44_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jne b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x75,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB44_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i16, ptr @g16
   %and = and i16 %load1, %arg
   store i16 %and, ptr @g16
   %cond = icmp eq i16 %and, 0
   br i1 %cond, label %a, label %b
 
 a:
   tail call void @a()
   ret void
 
 b:
   tail call void @b()
   ret void
 }
 
 define void @and8_reg_br(i8 %arg) nounwind {
 ; CHECK-LABEL: and8_reg_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    andb %dil, g8(%rip) # encoding: [0x40,0x20,0x3d,A,A,A,A]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: g8-4, kind: reloc_riprel_4byte
-; CHECK-NEXT:    je .LBB45_1 # encoding: [0x74,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB45_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jne b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x75,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB45_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i8, ptr @g8
   %and = and i8 %load1, %arg
   store i8 %and, ptr @g8
   %cond = icmp eq i8 %and, 0

 }
 
 define void @or64_imm32_br() nounwind {
 ; CHECK-LABEL: or64_imm32_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    orq $16777215, g64(%rip) # encoding: [0x48,0x81,0x0d,A,A,A,A,0xff,0xff,0xff,0x00]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: g64-8, kind: reloc_riprel_4byte
 ; CHECK-NEXT:    # imm = 0xFFFFFF
-; CHECK-NEXT:    je .LBB46_1 # encoding: [0x74,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB46_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jne b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x75,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB46_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i64, ptr @g64
   ; Or 0x00FFFFFF, a positive immediate requiring 24-bits.
   %or = or i64 %load1, 16777215
   store i64 %or, ptr @g64

 }
 
 define void @or64_sext_imm32_br() nounwind {
 ; CHECK-LABEL: or64_sext_imm32_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    orq $-2147483648, g64(%rip) # encoding: [0x48,0x81,0x0d,A,A,A,A,0x00,0x00,0x00,0x80]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: g64-8, kind: reloc_riprel_4byte
 ; CHECK-NEXT:    # imm = 0x80000000
-; CHECK-NEXT:    je .LBB47_1 # encoding: [0x74,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB47_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jne b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x75,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB47_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i64, ptr @g64
   ; Or -0x80000000, which requires sign-extended 32 bits.
   %or = or i64 %load1, -2147483648
   store i64 %or, ptr @g64
b:
   ret void
 }
 
 define void @or64_imm8_br() nounwind {
 ; CHECK-LABEL: or64_imm8_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    orq $15, g64(%rip) # encoding: [0x48,0x83,0x0d,A,A,A,A,0x0f]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: g64-5, kind: reloc_riprel_4byte
-; CHECK-NEXT:    je .LBB48_1 # encoding: [0x74,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB48_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jne b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x75,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB48_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i64, ptr @g64
   %or = or i64 %load1, 15
   store i64 %or, ptr @g64
   %cond = icmp eq i64 %or, 0
   br i1 %cond, label %a, label %b
 
 a:
   tail call void @a()
   ret void
 
 b:
   tail call void @b()
   ret void
 }
 
 define void @or64_imm8_neg_br() nounwind {
 ; CHECK-LABEL: or64_imm8_neg_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    orq $-4, g64(%rip) # encoding: [0x48,0x83,0x0d,A,A,A,A,0xfc]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: g64-5, kind: reloc_riprel_4byte
-; CHECK-NEXT:    je .LBB49_1 # encoding: [0x74,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB49_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jne b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x75,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB49_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i64, ptr @g64
   %or = or i64 %load1, -4
   store i64 %or, ptr @g64
   %cond = icmp eq i64 %or, 0

 }
 
 define void @or32_imm_br() nounwind {
 ; CHECK-LABEL: or32_imm_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    orl $-2147483648, g32(%rip) # encoding: [0x81,0x0d,A,A,A,A,0x00,0x00,0x00,0x80]
 ; CHECK-NEXT:    # fixup A - offset: 2, value: g32-8, kind: reloc_riprel_4byte
 ; CHECK-NEXT:    # imm = 0x80000000
-; CHECK-NEXT:    je .LBB50_1 # encoding: [0x74,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB50_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jne b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x75,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB50_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i32, ptr @g32
   ; Or 0x80000000, a positive number requiring 32 bits of immediate.
   %or = or i32 %load1, 2147483648
   store i32 %or, ptr @g32
b:
   ret void
 }
 
 define void @or32_imm8_br() nounwind {
 ; CHECK-LABEL: or32_imm8_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    orl $15, g32(%rip) # encoding: [0x83,0x0d,A,A,A,A,0x0f]
 ; CHECK-NEXT:    # fixup A - offset: 2, value: g32-5, kind: reloc_riprel_4byte
-; CHECK-NEXT:    je .LBB51_1 # encoding: [0x74,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB51_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jne b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x75,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB51_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i32, ptr @g32
   %or = or i32 %load1, 15
   store i32 %or, ptr @g32
   %cond = icmp eq i32 %or, 0
   br i1 %cond, label %a, label %b
 
 a:
   tail call void @a()
   ret void
 
 b:
   tail call void @b()
   ret void
 }
 
 define void @or32_imm8_neg_br() nounwind {
 ; CHECK-LABEL: or32_imm8_neg_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    orl $-4, g32(%rip) # encoding: [0x83,0x0d,A,A,A,A,0xfc]
 ; CHECK-NEXT:    # fixup A - offset: 2, value: g32-5, kind: reloc_riprel_4byte
-; CHECK-NEXT:    je .LBB52_1 # encoding: [0x74,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB52_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jne b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x75,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB52_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i32, ptr @g32
   %or = or i32 %load1, -4
   store i32 %or, ptr @g32
   %cond = icmp eq i32 %or, 0

 }
 
 define void @or16_imm_br() nounwind {
 ; CHECK-LABEL: or16_imm_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    orw $-32768, g16(%rip) # encoding: [0x66,0x81,0x0d,A,A,A,A,0x00,0x80]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: g16-6, kind: reloc_riprel_4byte
 ; CHECK-NEXT:    # imm = 0x8000
-; CHECK-NEXT:    je .LBB53_1 # encoding: [0x74,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB53_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jne b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x75,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB53_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i16, ptr @g16
   %or = or i16 %load1, 32768
   store i16 %or, ptr @g16
   %cond = icmp eq i16 %or, 0
   br i1 %cond, label %a, label %b
 
 a:
   tail call void @a()
   ret void
 
 b:
   tail call void @b()
   ret void
 }
 
 define void @or16_imm8_br() nounwind {
 ; CHECK-LABEL: or16_imm8_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    orw $15, g16(%rip) # encoding: [0x66,0x83,0x0d,A,A,A,A,0x0f]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: g16-5, kind: reloc_riprel_4byte
-; CHECK-NEXT:    je .LBB54_1 # encoding: [0x74,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB54_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jne b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x75,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB54_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i16, ptr @g16
   %or = or i16 %load1, 15
   store i16 %or, ptr @g16
   %cond = icmp eq i16 %or, 0
   br i1 %cond, label %a, label %b
 
 a:
   tail call void @a()
   ret void
 
 b:
   tail call void @b()
   ret void
 }
 
 define void @or16_imm8_neg_br() nounwind {
 ; CHECK-LABEL: or16_imm8_neg_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    orw $-4, g16(%rip) # encoding: [0x66,0x83,0x0d,A,A,A,A,0xfc]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: g16-5, kind: reloc_riprel_4byte
-; CHECK-NEXT:    je .LBB55_1 # encoding: [0x74,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB55_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jne b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x75,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB55_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i16, ptr @g16
   %or = or i16 %load1, -4
   store i16 %or, ptr @g16
   %cond = icmp eq i16 %or, 0
   br i1 %cond, label %a, label %b
 
 a:
   tail call void @a()
   ret void
 
 b:
   tail call void @b()
   ret void
 }
 
 define void @or8_imm_br() nounwind {
 ; CHECK-LABEL: or8_imm_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    orb $-4, g8(%rip) # encoding: [0x80,0x0d,A,A,A,A,0xfc]
 ; CHECK-NEXT:    # fixup A - offset: 2, value: g8-5, kind: reloc_riprel_4byte
-; CHECK-NEXT:    je .LBB56_1 # encoding: [0x74,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB56_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jne b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x75,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB56_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i8, ptr @g8
   %or = or i8 %load1, -4
   store i8 %or, ptr @g8
   %cond = icmp eq i8 %or, 0
   br i1 %cond, label %a, label %b
 
 a:
   tail call void @a()
   ret void
 
 b:
   tail call void @b()
   ret void
 }
 
 define void @or64_reg_br(i64 %arg) nounwind {
 ; CHECK-LABEL: or64_reg_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    orq %rdi, g64(%rip) # encoding: [0x48,0x09,0x3d,A,A,A,A]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: g64-4, kind: reloc_riprel_4byte
-; CHECK-NEXT:    je .LBB57_1 # encoding: [0x74,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB57_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jne b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x75,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB57_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i64, ptr @g64
   %or = or i64 %load1, %arg
   store i64 %or, ptr @g64
   %cond = icmp eq i64 %or, 0
   br i1 %cond, label %a, label %b
 
 a:
   tail call void @a()
   ret void
 
 b:
   tail call void @b()
   ret void
 }
 
 define void @or32_reg_br(i32 %arg) nounwind {
 ; CHECK-LABEL: or32_reg_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    orl %edi, g32(%rip) # encoding: [0x09,0x3d,A,A,A,A]
 ; CHECK-NEXT:    # fixup A - offset: 2, value: g32-4, kind: reloc_riprel_4byte
-; CHECK-NEXT:    je .LBB58_1 # encoding: [0x74,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB58_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jne b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x75,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB58_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i32, ptr @g32
   %or = or i32 %load1, %arg
   store i32 %or, ptr @g32
   %cond = icmp eq i32 %or, 0
   br i1 %cond, label %a, label %b
 
 a:
   tail call void @a()
   ret void
 
 b:
   tail call void @b()
   ret void
 }
 
 define void @or16_reg_br(i16 %arg) nounwind {
 ; CHECK-LABEL: or16_reg_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    orw %di, g16(%rip) # encoding: [0x66,0x09,0x3d,A,A,A,A]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: g16-4, kind: reloc_riprel_4byte
-; CHECK-NEXT:    je .LBB59_1 # encoding: [0x74,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB59_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jne b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x75,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB59_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i16, ptr @g16
   %or = or i16 %load1, %arg
   store i16 %or, ptr @g16
   %cond = icmp eq i16 %or, 0
   br i1 %cond, label %a, label %b
 
 a:
   tail call void @a()
   ret void
 
 b:
   tail call void @b()
   ret void
 }
 
 define void @or8_reg_br(i8 %arg) nounwind {
 ; CHECK-LABEL: or8_reg_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    orb %dil, g8(%rip) # encoding: [0x40,0x08,0x3d,A,A,A,A]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: g8-4, kind: reloc_riprel_4byte
-; CHECK-NEXT:    je .LBB60_1 # encoding: [0x74,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB60_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jne b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x75,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB60_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i8, ptr @g8
   %or = or i8 %load1, %arg
   store i8 %or, ptr @g8
   %cond = icmp eq i8 %or, 0

 }
 
 define void @xor64_imm32_br() nounwind {
 ; CHECK-LABEL: xor64_imm32_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xorq $16777215, g64(%rip) # encoding: [0x48,0x81,0x35,A,A,A,A,0xff,0xff,0xff,0x00]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: g64-8, kind: reloc_riprel_4byte
 ; CHECK-NEXT:    # imm = 0xFFFFFF
-; CHECK-NEXT:    je .LBB61_1 # encoding: [0x74,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB61_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jne b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x75,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB61_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i64, ptr @g64
   ; Xor 0x00FFFFFF, a positive immediate requiring 24-bits.
   %xor = xor i64 %load1, 16777215
   store i64 %xor, ptr @g64

 }
 
 define void @xor64_sext_imm32_br() nounwind {
 ; CHECK-LABEL: xor64_sext_imm32_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xorq $-2147483648, g64(%rip) # encoding: [0x48,0x81,0x35,A,A,A,A,0x00,0x00,0x00,0x80]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: g64-8, kind: reloc_riprel_4byte
 ; CHECK-NEXT:    # imm = 0x80000000
-; CHECK-NEXT:    je .LBB62_1 # encoding: [0x74,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB62_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jne b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x75,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB62_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i64, ptr @g64
   ; Xor -0x80000000, which requires sign-extended 32 bits.
   %xor = xor i64 %load1, -2147483648
   store i64 %xor, ptr @g64
b:
   ret void
 }
 
 define void @xor64_imm8_br() nounwind {
 ; CHECK-LABEL: xor64_imm8_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xorq $15, g64(%rip) # encoding: [0x48,0x83,0x35,A,A,A,A,0x0f]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: g64-5, kind: reloc_riprel_4byte
-; CHECK-NEXT:    je .LBB63_1 # encoding: [0x74,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB63_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jne b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x75,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB63_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i64, ptr @g64
   %xor = xor i64 %load1, 15
   store i64 %xor, ptr @g64
   %cond = icmp eq i64 %xor, 0
   br i1 %cond, label %a, label %b
 
 a:
   tail call void @a()
   ret void
 
 b:
   tail call void @b()
   ret void
 }
 
 define void @xor64_imm8_neg_br() nounwind {
 ; CHECK-LABEL: xor64_imm8_neg_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xorq $-4, g64(%rip) # encoding: [0x48,0x83,0x35,A,A,A,A,0xfc]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: g64-5, kind: reloc_riprel_4byte
-; CHECK-NEXT:    je .LBB64_1 # encoding: [0x74,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB64_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jne b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x75,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB64_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i64, ptr @g64
   %xor = xor i64 %load1, -4
   store i64 %xor, ptr @g64
   %cond = icmp eq i64 %xor, 0

 }
 
 define void @xor32_imm_br() nounwind {
 ; CHECK-LABEL: xor32_imm_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xorl $-2147483648, g32(%rip) # encoding: [0x81,0x35,A,A,A,A,0x00,0x00,0x00,0x80]
 ; CHECK-NEXT:    # fixup A - offset: 2, value: g32-8, kind: reloc_riprel_4byte
 ; CHECK-NEXT:    # imm = 0x80000000
-; CHECK-NEXT:    je .LBB65_1 # encoding: [0x74,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB65_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jne b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x75,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB65_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i32, ptr @g32
   ; Xor 0x80000000, a positive number requiring 32 bits of immediate.
   %xor = xor i32 %load1, 2147483648
   store i32 %xor, ptr @g32
b:
   ret void
 }
 
 define void @xor32_imm8_br() nounwind {
 ; CHECK-LABEL: xor32_imm8_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xorl $15, g32(%rip) # encoding: [0x83,0x35,A,A,A,A,0x0f]
 ; CHECK-NEXT:    # fixup A - offset: 2, value: g32-5, kind: reloc_riprel_4byte
-; CHECK-NEXT:    je .LBB66_1 # encoding: [0x74,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB66_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jne b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x75,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB66_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i32, ptr @g32
   %xor = xor i32 %load1, 15
   store i32 %xor, ptr @g32
   %cond = icmp eq i32 %xor, 0
   br i1 %cond, label %a, label %b
 
 a:
   tail call void @a()
   ret void
 
 b:
   tail call void @b()
   ret void
 }
 
 define void @xor32_imm8_neg_br() nounwind {
 ; CHECK-LABEL: xor32_imm8_neg_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xorl $-4, g32(%rip) # encoding: [0x83,0x35,A,A,A,A,0xfc]
 ; CHECK-NEXT:    # fixup A - offset: 2, value: g32-5, kind: reloc_riprel_4byte
-; CHECK-NEXT:    je .LBB67_1 # encoding: [0x74,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB67_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jne b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x75,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB67_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i32, ptr @g32
   %xor = xor i32 %load1, -4
   store i32 %xor, ptr @g32
   %cond = icmp eq i32 %xor, 0

 }
 
 define void @xor16_imm_br() nounwind {
 ; CHECK-LABEL: xor16_imm_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xorw $-32768, g16(%rip) # encoding: [0x66,0x81,0x35,A,A,A,A,0x00,0x80]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: g16-6, kind: reloc_riprel_4byte
 ; CHECK-NEXT:    # imm = 0x8000
-; CHECK-NEXT:    je .LBB68_1 # encoding: [0x74,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB68_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jne b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x75,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB68_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i16, ptr @g16
   %xor = xor i16 %load1, 32768
   store i16 %xor, ptr @g16
   %cond = icmp eq i16 %xor, 0
   br i1 %cond, label %a, label %b
 
 a:
   tail call void @a()
   ret void
 
 b:
   tail call void @b()
   ret void
 }
 
 define void @xor16_imm8_br() nounwind {
 ; CHECK-LABEL: xor16_imm8_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xorw $15, g16(%rip) # encoding: [0x66,0x83,0x35,A,A,A,A,0x0f]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: g16-5, kind: reloc_riprel_4byte
-; CHECK-NEXT:    je .LBB69_1 # encoding: [0x74,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB69_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jne b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x75,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB69_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i16, ptr @g16
   %xor = xor i16 %load1, 15
   store i16 %xor, ptr @g16
   %cond = icmp eq i16 %xor, 0
   br i1 %cond, label %a, label %b
 
 a:
   tail call void @a()
   ret void
 
 b:
   tail call void @b()
   ret void
 }
 
 define void @xor16_imm8_neg_br() nounwind {
 ; CHECK-LABEL: xor16_imm8_neg_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xorw $-4, g16(%rip) # encoding: [0x66,0x83,0x35,A,A,A,A,0xfc]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: g16-5, kind: reloc_riprel_4byte
-; CHECK-NEXT:    je .LBB70_1 # encoding: [0x74,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB70_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jne b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x75,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB70_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i16, ptr @g16
   %xor = xor i16 %load1, -4
   store i16 %xor, ptr @g16
   %cond = icmp eq i16 %xor, 0
   br i1 %cond, label %a, label %b
 
 a:
   tail call void @a()
   ret void
 
 b:
   tail call void @b()
   ret void
 }
 
 define void @xor8_imm_br() nounwind {
 ; CHECK-LABEL: xor8_imm_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xorb $-4, g8(%rip) # encoding: [0x80,0x35,A,A,A,A,0xfc]
 ; CHECK-NEXT:    # fixup A - offset: 2, value: g8-5, kind: reloc_riprel_4byte
-; CHECK-NEXT:    je .LBB71_1 # encoding: [0x74,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB71_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jne b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x75,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB71_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i8, ptr @g8
   %xor = xor i8 %load1, -4
   store i8 %xor, ptr @g8
   %cond = icmp eq i8 %xor, 0
   br i1 %cond, label %a, label %b
 
 a:
   tail call void @a()
   ret void
 
 b:
   tail call void @b()
   ret void
 }
 
 define void @xor64_reg_br(i64 %arg) nounwind {
 ; CHECK-LABEL: xor64_reg_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xorq %rdi, g64(%rip) # encoding: [0x48,0x31,0x3d,A,A,A,A]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: g64-4, kind: reloc_riprel_4byte
-; CHECK-NEXT:    je .LBB72_1 # encoding: [0x74,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB72_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jne b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x75,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB72_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i64, ptr @g64
   %xor = xor i64 %load1, %arg
   store i64 %xor, ptr @g64
   %cond = icmp eq i64 %xor, 0
   br i1 %cond, label %a, label %b
 
 a:
   tail call void @a()
   ret void
 
 b:
   tail call void @b()
   ret void
 }
 
 define void @xor32_reg_br(i32 %arg) nounwind {
 ; CHECK-LABEL: xor32_reg_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xorl %edi, g32(%rip) # encoding: [0x31,0x3d,A,A,A,A]
 ; CHECK-NEXT:    # fixup A - offset: 2, value: g32-4, kind: reloc_riprel_4byte
-; CHECK-NEXT:    je .LBB73_1 # encoding: [0x74,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB73_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jne b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x75,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB73_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i32, ptr @g32
   %xor = xor i32 %load1, %arg
   store i32 %xor, ptr @g32
   %cond = icmp eq i32 %xor, 0
   br i1 %cond, label %a, label %b
 
 a:
   tail call void @a()
   ret void
 
 b:
   tail call void @b()
   ret void
 }
 
 define void @xor16_reg_br(i16 %arg) nounwind {
 ; CHECK-LABEL: xor16_reg_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xorw %di, g16(%rip) # encoding: [0x66,0x31,0x3d,A,A,A,A]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: g16-4, kind: reloc_riprel_4byte
-; CHECK-NEXT:    je .LBB74_1 # encoding: [0x74,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB74_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jne b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x75,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB74_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i16, ptr @g16
   %xor = xor i16 %load1, %arg
   store i16 %xor, ptr @g16
   %cond = icmp eq i16 %xor, 0
   br i1 %cond, label %a, label %b
 
 a:
   tail call void @a()
   ret void
 
 b:
   tail call void @b()
   ret void
 }
 
 define void @xor8_reg_br(i8 %arg) nounwind {
 ; CHECK-LABEL: xor8_reg_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xorb %dil, g8(%rip) # encoding: [0x40,0x30,0x3d,A,A,A,A]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: g8-4, kind: reloc_riprel_4byte
-; CHECK-NEXT:    je .LBB75_1 # encoding: [0x74,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB75_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jne b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x75,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB75_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i8, ptr @g8
   %xor = xor i8 %load1, %arg
   store i8 %xor, ptr @g8
   %cond = icmp eq i8 %xor, 0
   br i1 %cond, label %a, label %b
 
 a:
   tail call void @a()
   ret void
 
 b:
   tail call void @b()
   ret void
 }
 
 define void @neg64_br() nounwind {
 ; CHECK-LABEL: neg64_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    negq g64(%rip) # encoding: [0x48,0xf7,0x1d,A,A,A,A]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: g64-4, kind: reloc_riprel_4byte
-; CHECK-NEXT:    js .LBB76_1 # encoding: [0x78,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB76_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jns b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x79,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB76_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i64, ptr @g64
   %sub = sub i64 0, %load1
   store i64 %sub, ptr @g64
   %cond = icmp slt i64 %sub, 0
   br i1 %cond, label %a, label %b
 
 a:
   tail call void @a()
   ret void
 
 b:
   tail call void @b()
   ret void
 }
 
 define void @neg32_br() nounwind {
 ; CHECK-LABEL: neg32_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    negl g32(%rip) # encoding: [0xf7,0x1d,A,A,A,A]
 ; CHECK-NEXT:    # fixup A - offset: 2, value: g32-4, kind: reloc_riprel_4byte
-; CHECK-NEXT:    js .LBB77_1 # encoding: [0x78,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB77_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jns b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x79,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB77_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i32, ptr @g32
   %sub = sub i32 0, %load1
   store i32 %sub, ptr @g32
   %cond = icmp slt i32 %sub, 0
   br i1 %cond, label %a, label %b
 
 a:
   tail call void @a()
   ret void
 
 b:
   tail call void @b()
   ret void
 }
 
 define void @neg16_br() nounwind {
 ; CHECK-LABEL: neg16_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    negw g16(%rip) # encoding: [0x66,0xf7,0x1d,A,A,A,A]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: g16-4, kind: reloc_riprel_4byte
-; CHECK-NEXT:    js .LBB78_1 # encoding: [0x78,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB78_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jns b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x79,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB78_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i16, ptr @g16
   %sub = sub i16 0, %load1
   store i16 %sub, ptr @g16
   %cond = icmp slt i16 %sub, 0
   br i1 %cond, label %a, label %b
 
 a:
   tail call void @a()
   ret void
 
 b:
   tail call void @b()
   ret void
 }
 
 define void @neg8_br() nounwind {
 ; CHECK-LABEL: neg8_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    negb g8(%rip) # encoding: [0xf6,0x1d,A,A,A,A]
 ; CHECK-NEXT:    # fixup A - offset: 2, value: g8-4, kind: reloc_riprel_4byte
-; CHECK-NEXT:    js .LBB79_1 # encoding: [0x78,A]
-; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB79_1-1, kind: FK_PCRel_1
-; CHECK-NEXT:  # %bb.2: # %b
-; CHECK-NEXT:    jmp b # TAILCALL
-; CHECK-NEXT:    # encoding: [0xeb,A]
+; CHECK-NEXT:    jns b # TAILCALL
+; CHECK-NEXT:    # encoding: [0x79,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
-; CHECK-NEXT:  .LBB79_1: # %a
+; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i8, ptr @g8
   %sub = sub i8 0, %load1
   store i8 %sub, ptr @g8
   %cond = icmp slt i8 %sub, 0

llvm/test/CodeGen/X86/fp-strict-scalar-cmp-fp16.ll

 ; AVX-NEXT:    vpextrw $0, %xmm1, %ecx
 ; AVX-NEXT:    movzwl %cx, %ecx
 ; AVX-NEXT:    vmovd %ecx, %xmm0
 ; AVX-NEXT:    vcvtph2ps %xmm0, %xmm0
 ; AVX-NEXT:    movzwl %ax, %eax
 ; AVX-NEXT:    vmovd %eax, %xmm1
 ; AVX-NEXT:    vcvtph2ps %xmm1, %xmm1
 ; AVX-NEXT:    vucomiss %xmm0, %xmm1
-; AVX-NEXT:    jbe .LBB28_1
-; AVX-NEXT:  # %bb.2:
-; AVX-NEXT:    jmp bar@PLT # TAILCALL
-; AVX-NEXT:  .LBB28_1:
+; AVX-NEXT:    ja bar@PLT # TAILCALL
+; AVX-NEXT:  # %bb.1:
 ; AVX-NEXT:    retq
 ;
 ; CHECK-32-LABEL: foo:
 ; CHECK-32:       # %bb.0:
 ; CHECK-32-NEXT:    vmovsh {{[0-9]+}}(%esp), %xmm0
 ; CHECK-32-NEXT:    vucomish {{[0-9]+}}(%esp), %xmm0
-; CHECK-32-NEXT:    jbe .LBB28_1
-; CHECK-32-NEXT:  # %bb.2:
-; CHECK-32-NEXT:    jmp bar@PLT # TAILCALL
-; CHECK-32-NEXT:  .LBB28_1:
+; CHECK-32-NEXT:    ja bar@PLT # TAILCALL
+; CHECK-32-NEXT:  # %bb.1:
 ; CHECK-32-NEXT:    retl
 ;
 ; CHECK-64-LABEL: foo:
 ; CHECK-64:       # %bb.0:
 ; CHECK-64-NEXT:    vucomish %xmm1, %xmm0
-; CHECK-64-NEXT:    jbe .LBB28_1
-; CHECK-64-NEXT:  # %bb.2:
-; CHECK-64-NEXT:    jmp bar@PLT # TAILCALL
-; CHECK-64-NEXT:  .LBB28_1:
+; CHECK-64-NEXT:    ja bar@PLT # TAILCALL
+; CHECK-64-NEXT:  # %bb.1:
 ; CHECK-64-NEXT:    retq
   %3 = call i1 @llvm.experimental.constrained.fcmp.f16( half %0, half %1, metadata !"ogt", metadata !"fpexcept.strict") #0
   br i1 %3, label %4, label %5
 
 4:                                                ; preds = %2
   tail call void @bar() #0
   br label %5
 

llvm/test/CodeGen/X86/fp-strict-scalar-cmp.ll

; X87-CMOV-NEXT:    retl
   ret i32 %res
 }
 
 define void @foo(float %0, float %1) #0 {
 ; SSE-32-LABEL: foo:
 ; SSE-32:       # %bb.0:
 ; SSE-32-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; SSE-32-NEXT:    ucomiss {{[0-9]+}}(%esp), %xmm0
-; SSE-32-NEXT:    jbe .LBB56_1
-; SSE-32-NEXT:  # %bb.2:
-; SSE-32-NEXT:    jmp bar # TAILCALL
-; SSE-32-NEXT:  .LBB56_1:
+; SSE-32-NEXT:    ja bar # TAILCALL
+; SSE-32-NEXT:  # %bb.1:
 ; SSE-32-NEXT:    retl
 ;
 ; SSE-64-LABEL: foo:
 ; SSE-64:       # %bb.0:
 ; SSE-64-NEXT:    ucomiss %xmm1, %xmm0
-; SSE-64-NEXT:    jbe .LBB56_1
-; SSE-64-NEXT:  # %bb.2:
-; SSE-64-NEXT:    jmp bar # TAILCALL
-; SSE-64-NEXT:  .LBB56_1:
+; SSE-64-NEXT:    ja bar # TAILCALL
+; SSE-64-NEXT:  # %bb.1:
 ; SSE-64-NEXT:    retq
 ;
 ; AVX-32-LABEL: foo:
 ; AVX-32:       # %bb.0:
 ; AVX-32-NEXT:    vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; AVX-32-NEXT:    vucomiss {{[0-9]+}}(%esp), %xmm0
-; AVX-32-NEXT:    jbe .LBB56_1
-; AVX-32-NEXT:  # %bb.2:
-; AVX-32-NEXT:    jmp bar # TAILCALL
-; AVX-32-NEXT:  .LBB56_1:
+; AVX-32-NEXT:    ja bar # TAILCALL
+; AVX-32-NEXT:  # %bb.1:
 ; AVX-32-NEXT:    retl
 ;
 ; AVX-64-LABEL: foo:
 ; AVX-64:       # %bb.0:
 ; AVX-64-NEXT:    vucomiss %xmm1, %xmm0
-; AVX-64-NEXT:    jbe .LBB56_1
-; AVX-64-NEXT:  # %bb.2:
-; AVX-64-NEXT:    jmp bar # TAILCALL
-; AVX-64-NEXT:  .LBB56_1:
+; AVX-64-NEXT:    ja bar # TAILCALL
+; AVX-64-NEXT:  # %bb.1:
 ; AVX-64-NEXT:    retq
 ;
 ; X87-LABEL: foo:
 ; X87:       # %bb.0:
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    fucompp
 ; X87-NEXT:    wait
 ; X87-NEXT:    fnstsw %ax
 ; X87-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-NEXT:    sahf
-; X87-NEXT:    jbe .LBB56_1
-; X87-NEXT:  # %bb.2:
-; X87-NEXT:    jmp bar # TAILCALL
-; X87-NEXT:  .LBB56_1:
+; X87-NEXT:    ja bar # TAILCALL
+; X87-NEXT:  # %bb.1:
 ; X87-NEXT:    retl
 ;
 ; X87-CMOV-LABEL: foo:
 ; X87-CMOV:       # %bb.0:
 ; X87-CMOV-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fucompi %st(1), %st
 ; X87-CMOV-NEXT:    fstp %st(0)
 ; X87-CMOV-NEXT:    wait
-; X87-CMOV-NEXT:    jbe .LBB56_1
-; X87-CMOV-NEXT:  # %bb.2:
-; X87-CMOV-NEXT:    jmp bar # TAILCALL
-; X87-CMOV-NEXT:  .LBB56_1:
+; X87-CMOV-NEXT:    ja bar # TAILCALL
+; X87-CMOV-NEXT:  # %bb.1:
 ; X87-CMOV-NEXT:    retl
   %3 = call i1 @llvm.experimental.constrained.fcmp.f32( float %0, float %1, metadata !"ogt", metadata !"fpexcept.strict") #0
   br i1 %3, label %4, label %5
 
 4:                                                ; preds = %2
   tail call void @bar() #0
   br label %5
 

llvm/test/CodeGen/X86/funnel-shift.ll

 ; X64-AVX2-NEXT:    leaq (%rax,%rax,2), %rcx
 ; X64-AVX2-NEXT:    movsbq 10(%rsi,%rcx,4), %rdx
 ; X64-AVX2-NEXT:    shlq $16, %rdx
 ; X64-AVX2-NEXT:    movzwl 8(%rsi,%rcx,4), %edi
 ; X64-AVX2-NEXT:    orq %rdx, %rdi
 ; X64-AVX2-NEXT:    movq (%rsi,%rcx,4), %rcx
 ; X64-AVX2-NEXT:    shrdq $40, %rdi, %rcx
 ; X64-AVX2-NEXT:    cmpq %rax, %rcx
-; X64-AVX2-NEXT:    jne .LBB46_1
-; X64-AVX2-NEXT:  # %bb.2:
-; X64-AVX2-NEXT:    jmp _Z3foov # TAILCALL
-; X64-AVX2-NEXT:  .LBB46_1:
+; X64-AVX2-NEXT:    je _Z3foov # TAILCALL
+; X64-AVX2-NEXT:  # %bb.1:
 ; X64-AVX2-NEXT:    retq
   %3 = sext i32 %0 to i64
   %4 = getelementptr inbounds %struct.S, %struct.S* %1, i64 %3
   %5 = bitcast %struct.S* %4 to i88*
   %6 = load i88, i88* %5, align 1
   %7 = ashr i88 %6, 40
   %8 = trunc i88 %7 to i64
   %9 = icmp eq i64 %8, %3

llvm/test/CodeGen/X86/jump_sign.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=cmov -verify-machineinstrs | FileCheck %s
 
 define i32 @func_f(i32 %X) {
 ; CHECK-LABEL: func_f:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; CHECK-NEXT:    incl %eax
-; CHECK-NEXT:    jns .LBB0_2
+; CHECK-NEXT:    jns baz@PLT # TAILCALL
 ; CHECK-NEXT:  # %bb.1: # %cond_true
 ; CHECK-NEXT:    calll bar@PLT
-; CHECK-NEXT:  .LBB0_2: # %cond_next
 ; CHECK-NEXT:    jmp baz@PLT # TAILCALL
 entry:
   %tmp1 = add i32 %X, 1
   %tmp = icmp slt i32 %tmp1, 0
   br i1 %tmp, label %cond_true, label %cond_next, !prof !1
 
 cond_true:    ; preds = %entry
   %tmp2 = tail call i32 (...) @bar( )

llvm/test/CodeGen/X86/neg_cmp.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
 
 ; rdar://11245199
 ; PR12545
 
 declare dso_local void @g()
 
 define void @neg_cmp(i32 %x, i32 %y) nounwind {
 ; CHECK-LABEL: neg_cmp:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addl %esi, %edi
-; CHECK-NEXT:    jne .LBB0_1
-; CHECK-NEXT:  # %bb.2: # %if.then
-; CHECK-NEXT:    jmp g # TAILCALL
-; CHECK-NEXT:  .LBB0_1: # %if.end
+; CHECK-NEXT:    je g # TAILCALL
+; CHECK-NEXT:  # %bb.1: # %if.end
 ; CHECK-NEXT:    retq
   %sub = sub i32 0, %y
   %cmp = icmp eq i32 %x, %sub
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:
   tail call void @g() nounwind
   br label %if.end
 
 if.end:
   ret void
 }
 
 define void @neg_cmp_commuted(i32 %x, i32 %y) nounwind {
 ; CHECK-LABEL: neg_cmp_commuted:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addl %esi, %edi
-; CHECK-NEXT:    jne .LBB1_1
-; CHECK-NEXT:  # %bb.2: # %if.then
-; CHECK-NEXT:    jmp g # TAILCALL
-; CHECK-NEXT:  .LBB1_1: # %if.end
+; CHECK-NEXT:    je g # TAILCALL
+; CHECK-NEXT:  # %bb.1: # %if.end
 ; CHECK-NEXT:    retq
   %sub = sub i32 0, %y
   %cmp = icmp eq i32 %sub, %x
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:
   tail call void @g() nounwind
   br label %if.end
 
 if.end:
   ret void
 }
 

llvm/test/CodeGen/X86/or-branch.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=i386-unknown-unknown -jump-is-expensive=0 | FileCheck %s --check-prefix=JUMP2
 ; RUN: llc < %s -mtriple=i386-unknown-unknown -jump-is-expensive=1 | FileCheck %s --check-prefix=JUMP1
 
 define void @foo(i32 %X, i32 %Y, i32 %Z) nounwind {
 ; JUMP2-LABEL: foo:
 ; JUMP2:       # %bb.0: # %entry
 ; JUMP2-NEXT:    cmpl $5, {{[0-9]+}}(%esp)
-; JUMP2-NEXT:    jl .LBB0_3
+; JUMP2-NEXT:    jl bar@PLT # TAILCALL
 ; JUMP2-NEXT:  # %bb.1: # %entry
 ; JUMP2-NEXT:    cmpl $0, {{[0-9]+}}(%esp)
-; JUMP2-NEXT:    je .LBB0_3
+; JUMP2-NEXT:    je bar@PLT # TAILCALL
 ; JUMP2-NEXT:  # %bb.2: # %UnifiedReturnBlock
 ; JUMP2-NEXT:    retl
-; JUMP2-NEXT:  .LBB0_3: # %cond_true
-; JUMP2-NEXT:    jmp bar@PLT # TAILCALL
 ;
 ; JUMP1-LABEL: foo:
 ; JUMP1:       # %bb.0: # %entry
 ; JUMP1-NEXT:    cmpl $0, {{[0-9]+}}(%esp)
 ; JUMP1-NEXT:    setne %al
 ; JUMP1-NEXT:    cmpl $5, {{[0-9]+}}(%esp)
 ; JUMP1-NEXT:    setge %cl
 ; JUMP1-NEXT:    testb %al, %cl
-; JUMP1-NEXT:    jne .LBB0_1
-; JUMP1-NEXT:  # %bb.2: # %cond_true
-; JUMP1-NEXT:    jmp bar@PLT # TAILCALL
-; JUMP1-NEXT:  .LBB0_1: # %UnifiedReturnBlock
+; JUMP1-NEXT:    je bar@PLT # TAILCALL
+; JUMP1-NEXT:  # %bb.1: # %UnifiedReturnBlock
 ; JUMP1-NEXT:    retl
 entry:
   %tmp1 = icmp eq i32 %X, 0
   %tmp3 = icmp slt i32 %Y, 5
   %tmp4 = or i1 %tmp3, %tmp1
   br i1 %tmp4, label %cond_true, label %UnifiedReturnBlock
 
 cond_true:

 define void @unpredictable(i32 %X, i32 %Y, i32 %Z) nounwind {
 ; JUMP2-LABEL: unpredictable:
 ; JUMP2:       # %bb.0: # %entry
 ; JUMP2-NEXT:    cmpl $0, {{[0-9]+}}(%esp)
 ; JUMP2-NEXT:    setne %al
 ; JUMP2-NEXT:    cmpl $5, {{[0-9]+}}(%esp)
 ; JUMP2-NEXT:    setge %cl
 ; JUMP2-NEXT:    testb %al, %cl
-; JUMP2-NEXT:    jne .LBB1_1
-; JUMP2-NEXT:  # %bb.2: # %cond_true
-; JUMP2-NEXT:    jmp bar@PLT # TAILCALL
-; JUMP2-NEXT:  .LBB1_1: # %UnifiedReturnBlock
+; JUMP2-NEXT:    je bar@PLT # TAILCALL
+; JUMP2-NEXT:  # %bb.1: # %UnifiedReturnBlock
 ; JUMP2-NEXT:    retl
 ;
 ; JUMP1-LABEL: unpredictable:
 ; JUMP1:       # %bb.0: # %entry
 ; JUMP1-NEXT:    cmpl $0, {{[0-9]+}}(%esp)
 ; JUMP1-NEXT:    setne %al
 ; JUMP1-NEXT:    cmpl $5, {{[0-9]+}}(%esp)
 ; JUMP1-NEXT:    setge %cl
 ; JUMP1-NEXT:    testb %al, %cl
-; JUMP1-NEXT:    jne .LBB1_1
-; JUMP1-NEXT:  # %bb.2: # %cond_true
-; JUMP1-NEXT:    jmp bar@PLT # TAILCALL
-; JUMP1-NEXT:  .LBB1_1: # %UnifiedReturnBlock
+; JUMP1-NEXT:    je bar@PLT # TAILCALL
+; JUMP1-NEXT:  # %bb.1: # %UnifiedReturnBlock
 ; JUMP1-NEXT:    retl
 entry:
   %tmp1 = icmp eq i32 %X, 0
   %tmp3 = icmp slt i32 %Y, 5
   %tmp4 = or i1 %tmp3, %tmp1
   br i1 %tmp4, label %cond_true, label %UnifiedReturnBlock, !unpredictable !0
 
 cond_true:

llvm/test/CodeGen/X86/peep-test-4.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-pc-linux -mattr=+bmi,+bmi2,+popcnt,+lzcnt | FileCheck %s
 declare dso_local void @foo(i32)
 declare dso_local void @foo32(i32)
 declare dso_local void @foo64(i64)
 
 define void @neg(i32 %x) nounwind {
 ; CHECK-LABEL: neg:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    negl %edi
-; CHECK-NEXT:    je .LBB0_1
-; CHECK-NEXT:  # %bb.2: # %bb
-; CHECK-NEXT:    jmp foo # TAILCALL
-; CHECK-NEXT:  .LBB0_1: # %return
+; CHECK-NEXT:    jne foo # TAILCALL
+; CHECK-NEXT:  # %bb.1: # %return
 ; CHECK-NEXT:    retq
   %sub = sub i32 0, %x
   %cmp = icmp eq i32 %sub, 0
   br i1 %cmp, label %return, label %bb
 
 bb:
   tail call void @foo(i32 %sub)
   br label %return
 
 return:
   ret void
 }
 
 define void @sar(i32 %x) nounwind {
 ; CHECK-LABEL: sar:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    sarl %edi
-; CHECK-NEXT:    je .LBB1_1
-; CHECK-NEXT:  # %bb.2: # %bb
-; CHECK-NEXT:    jmp foo # TAILCALL
-; CHECK-NEXT:  .LBB1_1: # %return
+; CHECK-NEXT:    jne foo # TAILCALL
+; CHECK-NEXT:  # %bb.1: # %return
 ; CHECK-NEXT:    retq
   %ashr = ashr i32 %x, 1
   %cmp = icmp eq i32 %ashr, 0
   br i1 %cmp, label %return, label %bb
 
 bb:
   tail call void @foo(i32 %ashr)
   br label %return
 
 return:
   ret void
 }
 
 define void @shr(i32 %x) nounwind {
 ; CHECK-LABEL: shr:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    shrl %edi
-; CHECK-NEXT:    je .LBB2_1
-; CHECK-NEXT:  # %bb.2: # %bb
-; CHECK-NEXT:    jmp foo # TAILCALL
-; CHECK-NEXT:  .LBB2_1: # %return
+; CHECK-NEXT:    jne foo # TAILCALL
+; CHECK-NEXT:  # %bb.1: # %return
 ; CHECK-NEXT:    retq
   %ashr = lshr i32 %x, 1
   %cmp = icmp eq i32 %ashr, 0
   br i1 %cmp, label %return, label %bb
 
 bb:
   tail call void @foo(i32 %ashr)
   br label %return
 
 return:
   ret void
 }
 
 define void @shri(i32 %x) nounwind {
 ; CHECK-LABEL: shri:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    shrl $3, %edi
-; CHECK-NEXT:    je .LBB3_1
-; CHECK-NEXT:  # %bb.2: # %bb
-; CHECK-NEXT:    jmp foo # TAILCALL
-; CHECK-NEXT:  .LBB3_1: # %return
+; CHECK-NEXT:    jne foo # TAILCALL
+; CHECK-NEXT:  # %bb.1: # %return
 ; CHECK-NEXT:    retq
   %ashr = lshr i32 %x, 3
   %cmp = icmp eq i32 %ashr, 0
   br i1 %cmp, label %return, label %bb
 
 bb:
   tail call void @foo(i32 %ashr)
   br label %return
 
 return:
   ret void
 }
 
 define void @shl(i32 %x) nounwind {
 ; CHECK-LABEL: shl:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addl %edi, %edi
-; CHECK-NEXT:    je .LBB4_1
-; CHECK-NEXT:  # %bb.2: # %bb
-; CHECK-NEXT:    jmp foo # TAILCALL
-; CHECK-NEXT:  .LBB4_1: # %return
+; CHECK-NEXT:    jne foo # TAILCALL
+; CHECK-NEXT:  # %bb.1: # %return
 ; CHECK-NEXT:    retq
   %shl = shl i32 %x, 1
   %cmp = icmp eq i32 %shl, 0
   br i1 %cmp, label %return, label %bb
 
 bb:
   tail call void @foo(i32 %shl)
   br label %return
 
 return:
   ret void
 }
 
 define void @shli(i32 %x) nounwind {
 ; CHECK-LABEL: shli:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    shll $4, %edi
-; CHECK-NEXT:    je .LBB5_1
-; CHECK-NEXT:  # %bb.2: # %bb
-; CHECK-NEXT:    jmp foo # TAILCALL
-; CHECK-NEXT:  .LBB5_1: # %return
+; CHECK-NEXT:    jne foo # TAILCALL
+; CHECK-NEXT:  # %bb.1: # %return
 ; CHECK-NEXT:    retq
   %shl = shl i32 %x, 4
   %cmp = icmp eq i32 %shl, 0
   br i1 %cmp, label %return, label %bb
 
 bb:
   tail call void @foo(i32 %shl)
   br label %return
; CHECK-NEXT:    retq
   %cmp = icmp sge i128 %sub, 0
   ret i1 %cmp
 }
 
 define void @andn(i32 %x, i32 %y) nounwind {
 ; CHECK-LABEL: andn:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    andnl %esi, %edi, %edi
-; CHECK-NEXT:    je .LBB8_1
-; CHECK-NEXT:  # %bb.2: # %bb
-; CHECK-NEXT:    jmp foo # TAILCALL
-; CHECK-NEXT:  .LBB8_1: # %return
+; CHECK-NEXT:    jne foo # TAILCALL
+; CHECK-NEXT:  # %bb.1: # %return
 ; CHECK-NEXT:    retq
   %not = xor i32 %x, -1
   %andn = and i32 %y, %not
   %cmp = icmp eq i32 %andn, 0
   br i1 %cmp, label %return, label %bb
 
 bb:
   tail call void @foo(i32 %andn)
   br label %return
 
 return:
   ret void
 }
 
 declare i32 @llvm.x86.bmi.bextr.32(i32, i32) nounwind readnone
 define void @bextr(i32 %x, i32 %y) nounwind {
 ; CHECK-LABEL: bextr:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    bextrl %esi, %edi, %edi
-; CHECK-NEXT:    je .LBB9_1
-; CHECK-NEXT:  # %bb.2: # %bb
-; CHECK-NEXT:    jmp foo # TAILCALL
-; CHECK-NEXT:  .LBB9_1: # %return
+; CHECK-NEXT:    jne foo # TAILCALL
+; CHECK-NEXT:  # %bb.1: # %return
 ; CHECK-NEXT:    retq
   %bextr = tail call i32 @llvm.x86.bmi.bextr.32(i32 %x, i32 %y)
   %cmp = icmp eq i32 %bextr, 0
   br i1 %cmp, label %return, label %bb
 
 bb:
   tail call void @foo(i32 %bextr)
   br label %return
 
 return:
   ret void
 }
 
 declare i32 @llvm.ctpop.i32(i32) nounwind readnone
 define void @popcnt(i32 %x) nounwind {
 ; CHECK-LABEL: popcnt:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    popcntl %edi, %edi
-; CHECK-NEXT:    je .LBB10_1
-; CHECK-NEXT:  # %bb.2: # %bb
-; CHECK-NEXT:    jmp foo # TAILCALL
-; CHECK-NEXT:  .LBB10_1: # %return
+; CHECK-NEXT:    jne foo # TAILCALL
+; CHECK-NEXT:  # %bb.1: # %return
 ; CHECK-NEXT:    retq
   %popcnt = tail call i32 @llvm.ctpop.i32(i32 %x)
   %cmp = icmp eq i32 %popcnt, 0
   br i1 %cmp, label %return, label %bb
 bb:
   tail call void @foo(i32 %popcnt)
   br label %return
 return:

llvm/test/CodeGen/X86/pr37025.ll

 
 define void @test_dec_select(ptr nocapture %0, ptr readnone %1) {
 ; CHECK-LABEL: test_dec_select:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lock decq (%rdi)
 ; CHECK-NEXT:    jne .LBB0_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    testq %rsi, %rsi
-; CHECK-NEXT:    je .LBB0_2
-; CHECK-NEXT:  # %bb.3:
-; CHECK-NEXT:    jmp func2 # TAILCALL
+; CHECK-NEXT:    jne func2 # TAILCALL
 ; CHECK-NEXT:  .LBB0_2:
 ; CHECK-NEXT:    retq
   %3 = atomicrmw sub ptr %0, i64 1 seq_cst
   %4 = icmp eq i64 %3, 1
   %5 = icmp ne ptr %1, null
   %6 = select i1 %4, i1 %5, i1 false
   br i1 %6, label %7, label %8
 

 ; CHECK-LABEL: test_dec_select_commute:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lock decq (%rdi)
 ; CHECK-NEXT:    sete %al
 ; CHECK-NEXT:    testq %rsi, %rsi
 ; CHECK-NEXT:    je .LBB1_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    testb %al, %al
-; CHECK-NEXT:    je .LBB1_2
-; CHECK-NEXT:  # %bb.3:
-; CHECK-NEXT:    jmp func2 # TAILCALL
+; CHECK-NEXT:    jne func2 # TAILCALL
 ; CHECK-NEXT:  .LBB1_2:
 ; CHECK-NEXT:    retq
   %3 = atomicrmw sub ptr %0, i64 1 seq_cst
   %4 = icmp eq i64 %3, 1
   %5 = icmp ne ptr %1, null
   %6 = select i1 %5, i1 %4, i1 false
   br i1 %6, label %7, label %8
 

 ; CHECK-LABEL: test_dec_and:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lock decq (%rdi)
 ; CHECK-NEXT:    sete %al
 ; CHECK-NEXT:    testq %rsi, %rsi
 ; CHECK-NEXT:    je .LBB2_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    testb %al, %al
-; CHECK-NEXT:    je .LBB2_2
-; CHECK-NEXT:  # %bb.3:
-; CHECK-NEXT:    jmp func2 # TAILCALL
+; CHECK-NEXT:    jne func2 # TAILCALL
 ; CHECK-NEXT:  .LBB2_2:
 ; CHECK-NEXT:    retq
   %3 = atomicrmw sub ptr %0, i64 1 seq_cst
   %4 = icmp eq i64 %3, 1
   %5 = icmp ne ptr %1, null
   %6 = and i1 %5, %4
   br i1 %6, label %7, label %8
 
 7: ; preds = %2
   tail call void @func2()
   br label %8
 
 8: ; preds = %7, %2
   ret void
 }
 
 define void @test_dec_and_commute(ptr nocapture %0, ptr readnone %1) {
 ; CHECK-LABEL: test_dec_and_commute:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lock decq (%rdi)
 ; CHECK-NEXT:    jne .LBB3_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    testq %rsi, %rsi
-; CHECK-NEXT:    je .LBB3_2
-; CHECK-NEXT:  # %bb.3:
-; CHECK-NEXT:    jmp func2 # TAILCALL
+; CHECK-NEXT:    jne func2 # TAILCALL
 ; CHECK-NEXT:  .LBB3_2:
 ; CHECK-NEXT:    retq
   %3 = atomicrmw sub ptr %0, i64 1 seq_cst
   %4 = icmp eq i64 %3, 1
   %5 = icmp ne ptr %1, null
   %6 = and i1 %4, %5
   br i1 %6, label %7, label %8
 

llvm/test/CodeGen/X86/pr37063.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
 
 declare dso_local void @bar()
 
 define void @foo(ptr) {
 ; CHECK-LABEL: foo:
 ; CHECK:       # %bb.0: # %start
 ; CHECK-NEXT:    movl (%rdi), %eax
 ; CHECK-NEXT:    andl $6, %eax
 ; CHECK-NEXT:    cmpl $4, %eax
-; CHECK-NEXT:    jne .LBB0_2
+; CHECK-NEXT:    jne bar # TAILCALL
 ; CHECK-NEXT:  # %bb.1: # %bb1
 ; CHECK-NEXT:    retq
-; CHECK-NEXT:  .LBB0_2: # %bb2.i
-; CHECK-NEXT:    jmp bar # TAILCALL
 start:
   %1 = load i64, ptr %0, align 8, !range !0
   %2 = and i64 %1, 6
   %3 = icmp eq i64 %2, 4
   br i1 %3, label %bb1, label %bb2.i
 
 bb1:                                              ; preds = %bb2.i, %start
   ret void
 
 bb2.i:                                            ; preds = %start
   tail call fastcc void @bar()
   br label %bb1
 }
 
 !0 = !{i64 0, i64 6}

llvm/test/CodeGen/X86/rd-mod-wr-eflags.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
 
 %struct.obj = type { i64 }
 
 define dso_local void @_Z7releaseP3obj(ptr nocapture %o) nounwind uwtable ssp {
 ; CHECK-LABEL: _Z7releaseP3obj:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    decq (%rdi)
-; CHECK-NEXT:    je .LBB0_2
+; CHECK-NEXT:    je free # TAILCALL
 ; CHECK-NEXT:  # %bb.1: # %return
 ; CHECK-NEXT:    retq
-; CHECK-NEXT:  .LBB0_2: # %if.end
-; CHECK-NEXT:    jmp free # TAILCALL
 entry:
   %0 = load i64, ptr %o, align 8
   %dec = add i64 %0, -1
   store i64 %dec, ptr %o, align 8
   %tobool = icmp eq i64 %dec, 0
   br i1 %tobool, label %if.end, label %return
 
 if.end:                                           ; preds = %entry

 ; CHECK-NEXT:  # %bb.1: # %if.end
 ; CHECK-NEXT:    decl 8(%rdi)
 ; CHECK-NEXT:    jne .LBB3_4
 ; CHECK-NEXT:  # %bb.2: # %if.end1
 ; CHECK-NEXT:    decw 12(%rdi)
 ; CHECK-NEXT:    jne .LBB3_4
 ; CHECK-NEXT:  # %bb.3: # %if.end2
 ; CHECK-NEXT:    decb 14(%rdi)
-; CHECK-NEXT:    je .LBB3_5
+; CHECK-NEXT:    je other # TAILCALL
 ; CHECK-NEXT:  .LBB3_4: # %return
 ; CHECK-NEXT:    retq
-; CHECK-NEXT:  .LBB3_5: # %if.end4
-; CHECK-NEXT:    jmp other # TAILCALL
 entry:
   %0 = load i64, ptr %o, align 8
   %dec = add i64 %0, -1
   store i64 %dec, ptr %o, align 8
   %tobool = icmp eq i64 %dec, 0
   br i1 %tobool, label %if.end, label %return
 
 ; 32 bit dec

 ; CHECK-NEXT:  # %bb.1: # %if.end
 ; CHECK-NEXT:    incl 8(%rdi)
 ; CHECK-NEXT:    jne .LBB4_4
 ; CHECK-NEXT:  # %bb.2: # %if.end1
 ; CHECK-NEXT:    incw 12(%rdi)
 ; CHECK-NEXT:    jne .LBB4_4
 ; CHECK-NEXT:  # %bb.3: # %if.end2
 ; CHECK-NEXT:    incb 14(%rdi)
-; CHECK-NEXT:    jne .LBB4_4
-; CHECK-NEXT:  # %bb.5: # %if.end4
-; CHECK-NEXT:    jmp other # TAILCALL
+; CHECK-NEXT:    je other # TAILCALL
 ; CHECK-NEXT:  .LBB4_4: # %return
 ; CHECK-NEXT:    retq
 entry:
   %0 = load i64, ptr %o, align 8
   %inc = add i64 %0, 1
   store i64 %inc, ptr %o, align 8
   %tobool = icmp eq i64 %inc, 0
   br i1 %tobool, label %if.end, label %return

 ; rdar://11236106
 @foo = external dso_local global ptr, align 8
 
 define dso_local void @test3() nounwind ssp {
 ; CHECK-LABEL: test3:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    movq foo(%rip), %rax
 ; CHECK-NEXT:    decq 16(%rax)
-; CHECK-NEXT:    je .LBB5_2
+; CHECK-NEXT:    je baz # TAILCALL
 ; CHECK-NEXT:  # %bb.1: # %if.end
 ; CHECK-NEXT:    retq
-; CHECK-NEXT:  .LBB5_2: # %if.then
-; CHECK-NEXT:    jmp baz # TAILCALL
 entry:
   %0 = load ptr, ptr @foo, align 8
   %arrayidx = getelementptr inbounds i64, ptr %0, i64 2
   %1 = load i64, ptr %arrayidx, align 8
   %dec = add i64 %1, -1
   store i64 %dec, ptr %arrayidx, align 8
   %cmp = icmp eq i64 %dec, 0
   br i1 %cmp, label %if.then, label %if.end

llvm/test/CodeGen/X86/segmented-stacks.ll

 ; (PR37807).
 
 declare i32 @callee(i32)
 
 define i32 @test_sibling_call_empty_frame(i32 %x) #0 {
 ; X86-Linux-LABEL: test_sibling_call_empty_frame:
 ; X86-Linux:       # %bb.0:
 ; X86-Linux-NEXT:    cmpl %gs:48, %esp
-; X86-Linux-NEXT:    jbe .LBB8_1
-; X86-Linux-NEXT:  # %bb.2:
-; X86-Linux-NEXT:    jmp callee@PLT # TAILCALL
-; X86-Linux-NEXT:  .LBB8_1:
+; X86-Linux-NEXT:    ja callee@PLT # TAILCALL
+; X86-Linux-NEXT:  # %bb.1:
 ; X86-Linux-NEXT:    pushl $4
 ; X86-Linux-NEXT:    pushl $0
 ; X86-Linux-NEXT:    calll __morestack
 ; X86-Linux-NEXT:    retl
 ; X86-Linux-NEXT:    jmp callee@PLT # TAILCALL
 ;
 ; X64-Linux-LABEL: test_sibling_call_empty_frame:
 ; X64-Linux:       # %bb.0:
 ; X64-Linux-NEXT:    cmpq %fs:112, %rsp
-; X64-Linux-NEXT:    jbe .LBB8_1
-; X64-Linux-NEXT:  # %bb.2:
-; X64-Linux-NEXT:    jmp callee@PLT # TAILCALL
-; X64-Linux-NEXT:  .LBB8_1:
+; X64-Linux-NEXT:    ja callee@PLT # TAILCALL
+; X64-Linux-NEXT:  # %bb.1:
 ; X64-Linux-NEXT:    movl $0, %r10d
 ; X64-Linux-NEXT:    movl $0, %r11d
 ; X64-Linux-NEXT:    callq __morestack
 ; X64-Linux-NEXT:    retq
 ; X64-Linux-NEXT:    jmp callee@PLT # TAILCALL
 ;
 ; X64-Linux-Large-LABEL: test_sibling_call_empty_frame:
 ; X64-Linux-Large:       # %bb.0:
 ; X64-Linux-Large-NEXT:    cmpq %fs:112, %rsp
 ; X64-Linux-Large-NEXT:    jbe .LBB8_1
 ; X64-Linux-Large-NEXT:  # %bb.2:
 ; X64-Linux-Large-NEXT:    movabsq $callee, %rax
 ; X64-Linux-Large-NEXT:    jmpq *%rax # TAILCALL
 ; X64-Linux-Large-NEXT:  .LBB8_1:
 ; X64-Linux-Large-NEXT:    movl $0, %r10d
 ; X64-Linux-Large-NEXT:    movl $0, %r11d
 ; X64-Linux-Large-NEXT:    callq *__morestack_addr(%rip)
 ; X64-Linux-Large-NEXT:    retq
 ; X64-Linux-Large-NEXT:    movabsq $callee, %rax
 ; X64-Linux-Large-NEXT:    jmpq *%rax # TAILCALL
 ;
 ; X32ABI-LABEL: test_sibling_call_empty_frame:
 ; X32ABI:       # %bb.0:
 ; X32ABI-NEXT:    cmpl %fs:64, %esp
-; X32ABI-NEXT:    jbe .LBB8_1
-; X32ABI-NEXT:  # %bb.2:
-; X32ABI-NEXT:    jmp callee@PLT # TAILCALL
-; X32ABI-NEXT:  .LBB8_1:
+; X32ABI-NEXT:    ja callee@PLT # TAILCALL
+; X32ABI-NEXT:  # %bb.1:
 ; X32ABI-NEXT:    movl $0, %r10d
 ; X32ABI-NEXT:    movl $0, %r11d
 ; X32ABI-NEXT:    callq __morestack
 ; X32ABI-NEXT:    retq
 ; X32ABI-NEXT:    jmp callee@PLT # TAILCALL
 ;
 ; X86-Darwin-LABEL: test_sibling_call_empty_frame:
 ; X86-Darwin:       ## %bb.0:
 ; X86-Darwin-NEXT:    movl $432, %ecx ## imm = 0x1B0
 ; X86-Darwin-NEXT:    cmpl %gs:(%ecx), %esp
-; X86-Darwin-NEXT:    jbe LBB8_1
-; X86-Darwin-NEXT:  ## %bb.2:
-; X86-Darwin-NEXT:    jmp _callee ## TAILCALL
-; X86-Darwin-NEXT:  LBB8_1:
+; X86-Darwin-NEXT:    ja _callee ## TAILCALL
+; X86-Darwin-NEXT:  ## %bb.1:
 ; X86-Darwin-NEXT:    pushl $4
 ; X86-Darwin-NEXT:    pushl $0
 ; X86-Darwin-NEXT:    calll ___morestack
 ; X86-Darwin-NEXT:    retl
 ; X86-Darwin-NEXT:    jmp _callee ## TAILCALL
 ;
 ; X64-Darwin-LABEL: test_sibling_call_empty_frame:
 ; X64-Darwin:       ## %bb.0:
 ; X64-Darwin-NEXT:    cmpq %gs:816, %rsp
-; X64-Darwin-NEXT:    jbe LBB8_1
-; X64-Darwin-NEXT:  ## %bb.2:
-; X64-Darwin-NEXT:    jmp _callee ## TAILCALL
-; X64-Darwin-NEXT:  LBB8_1:
+; X64-Darwin-NEXT:    ja _callee ## TAILCALL
+; X64-Darwin-NEXT:  ## %bb.1:
 ; X64-Darwin-NEXT:    movl $0, %r10d
 ; X64-Darwin-NEXT:    movl $0, %r11d
 ; X64-Darwin-NEXT:    callq ___morestack
 ; X64-Darwin-NEXT:    retq
 ; X64-Darwin-NEXT:    jmp _callee ## TAILCALL
 ;
 ; X86-MinGW-LABEL: test_sibling_call_empty_frame:
 ; X86-MinGW:       # %bb.0:
 ; X86-MinGW-NEXT:    cmpl %fs:20, %esp
-; X86-MinGW-NEXT:    jbe LBB8_1
-; X86-MinGW-NEXT:  # %bb.2:
-; X86-MinGW-NEXT:    jmp _callee # TAILCALL
-; X86-MinGW-NEXT:  LBB8_1:
+; X86-MinGW-NEXT:    ja _callee # TAILCALL
+; X86-MinGW-NEXT:  # %bb.1:
 ; X86-MinGW-NEXT:    pushl $4
 ; X86-MinGW-NEXT:    pushl $0
 ; X86-MinGW-NEXT:    calll ___morestack
 ; X86-MinGW-NEXT:    retl
 ; X86-MinGW-NEXT:    jmp _callee # TAILCALL
 ;
 ; X64-FreeBSD-LABEL: test_sibling_call_empty_frame:
 ; X64-FreeBSD:       # %bb.0:
 ; X64-FreeBSD-NEXT:    cmpq %fs:24, %rsp
-; X64-FreeBSD-NEXT:    jbe .LBB8_1
-; X64-FreeBSD-NEXT:  # %bb.2:
-; X64-FreeBSD-NEXT:    jmp callee@PLT # TAILCALL
-; X64-FreeBSD-NEXT:  .LBB8_1:
+; X64-FreeBSD-NEXT:    ja callee@PLT # TAILCALL
+; X64-FreeBSD-NEXT:  # %bb.1:
 ; X64-FreeBSD-NEXT:    movl $0, %r10d
 ; X64-FreeBSD-NEXT:    movl $0, %r11d
 ; X64-FreeBSD-NEXT:    callq __morestack
 ; X64-FreeBSD-NEXT:    retq
 ; X64-FreeBSD-NEXT:    jmp callee@PLT # TAILCALL
 ;
 ; X86-DFlyBSD-LABEL: test_sibling_call_empty_frame:
 ; X86-DFlyBSD:       # %bb.0:
 ; X86-DFlyBSD-NEXT:    cmpl %fs:16, %esp
-; X86-DFlyBSD-NEXT:    jbe .LBB8_1
-; X86-DFlyBSD-NEXT:  # %bb.2:
-; X86-DFlyBSD-NEXT:    jmp callee@PLT # TAILCALL
-; X86-DFlyBSD-NEXT:  .LBB8_1:
+; X86-DFlyBSD-NEXT:    ja callee@PLT # TAILCALL
+; X86-DFlyBSD-NEXT:  # %bb.1:
 ; X86-DFlyBSD-NEXT:    pushl $4
 ; X86-DFlyBSD-NEXT:    pushl $0
 ; X86-DFlyBSD-NEXT:    calll __morestack
 ; X86-DFlyBSD-NEXT:    retl
 ; X86-DFlyBSD-NEXT:    jmp callee@PLT # TAILCALL
 ;
 ; X64-DFlyBSD-LABEL: test_sibling_call_empty_frame:
 ; X64-DFlyBSD:       # %bb.0:
 ; X64-DFlyBSD-NEXT:    cmpq %fs:32, %rsp
-; X64-DFlyBSD-NEXT:    jbe .LBB8_1
-; X64-DFlyBSD-NEXT:  # %bb.2:
-; X64-DFlyBSD-NEXT:    jmp callee@PLT # TAILCALL
-; X64-DFlyBSD-NEXT:  .LBB8_1:
+; X64-DFlyBSD-NEXT:    ja callee@PLT # TAILCALL
+; X64-DFlyBSD-NEXT:  # %bb.1:
 ; X64-DFlyBSD-NEXT:    movl $0, %r10d
 ; X64-DFlyBSD-NEXT:    movl $0, %r11d
 ; X64-DFlyBSD-NEXT:    callq __morestack
 ; X64-DFlyBSD-NEXT:    retq
 ; X64-DFlyBSD-NEXT:    jmp callee@PLT # TAILCALL
 ;
 ; X64-MinGW-LABEL: test_sibling_call_empty_frame:
 ; X64-MinGW:       # %bb.0:
 ; X64-MinGW-NEXT:    cmpq %gs:40, %rsp
-; X64-MinGW-NEXT:    jbe .LBB8_1
-; X64-MinGW-NEXT:  # %bb.2:
-; X64-MinGW-NEXT:    jmp callee # TAILCALL
-; X64-MinGW-NEXT:  .LBB8_1:
+; X64-MinGW-NEXT:    ja callee # TAILCALL
+; X64-MinGW-NEXT:  # %bb.1:
 ; X64-MinGW-NEXT:    movl $0, %r10d
 ; X64-MinGW-NEXT:    movl $32, %r11d
 ; X64-MinGW-NEXT:    callq __morestack
 ; X64-MinGW-NEXT:    retq
 ; X64-MinGW-NEXT:    jmp callee # TAILCALL
   %call = tail call i32 @callee(i32 %x) #0
   ret i32 %call
 }

llvm/test/CodeGen/X86/sibcall.ll

 ; X86-NEXT:    retl
 ; X86-NEXT:  .LBB6_2: # %bb1
 ; X86-NEXT:    addl $12, %esp
 ; X86-NEXT:    jmp bar # TAILCALL
 ;
 ; X64-LABEL: t6:
 ; X64:       # %bb.0:
 ; X64-NEXT:    cmpl $9, %edi
-; X64-NEXT:    jg .LBB6_2
+; X64-NEXT:    jg bar # TAILCALL
 ; X64-NEXT:  # %bb.1: # %bb
 ; X64-NEXT:    decl %edi
 ; X64-NEXT:    jmp t6 # TAILCALL
-; X64-NEXT:  .LBB6_2: # %bb1
-; X64-NEXT:    jmp bar # TAILCALL
 ;
 ; X32-LABEL: t6:
 ; X32:       # %bb.0:
 ; X32-NEXT:    cmpl $9, %edi
-; X32-NEXT:    jg .LBB6_2
+; X32-NEXT:    jg bar # TAILCALL
 ; X32-NEXT:  # %bb.1: # %bb
 ; X32-NEXT:    decl %edi
 ; X32-NEXT:    jmp t6 # TAILCALL
-; X32-NEXT:  .LBB6_2: # %bb1
-; X32-NEXT:    jmp bar # TAILCALL
   %t0 = icmp slt i32 %x, 10
   br i1 %t0, label %bb, label %bb1
 
 bb:
   %t1 = add nsw i32 %x, -1
   %t2 = tail call i32 @t6(i32 %t1) nounwind ssp
   ret i32 %t2
 

 
 ; In 32-bit mode, it's emitting a bunch of dead loads that are not being
 ; eliminated currently.
 
 define dso_local i32 @t11(i32 %x, i32 %y, i32 %z.0, i32 %z.1, i32 %z.2) nounwind ssp {
 ; X86-LABEL: t11:
 ; X86:       # %bb.0: # %entry
 ; X86-NEXT:    cmpl $0, {{[0-9]+}}(%esp)
-; X86-NEXT:    je .LBB11_1
-; X86-NEXT:  # %bb.2: # %bb
-; X86-NEXT:    jmp foo5 # TAILCALL
-; X86-NEXT:  .LBB11_1: # %bb6
+; X86-NEXT:    jne foo5 # TAILCALL
+; X86-NEXT:  # %bb.1: # %bb6
 ; X86-NEXT:    xorl %eax, %eax
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: t11:
 ; X64:       # %bb.0: # %entry
 ; X64-NEXT:    testl %edi, %edi
-; X64-NEXT:    je .LBB11_1
-; X64-NEXT:  # %bb.2: # %bb
-; X64-NEXT:    jmp foo5 # TAILCALL
-; X64-NEXT:  .LBB11_1: # %bb6
+; X64-NEXT:    jne foo5 # TAILCALL
+; X64-NEXT:  # %bb.1: # %bb6
 ; X64-NEXT:    xorl %eax, %eax
 ; X64-NEXT:    retq
 ;
 ; X32-LABEL: t11:
 ; X32:       # %bb.0: # %entry
 ; X32-NEXT:    testl %edi, %edi
-; X32-NEXT:    je .LBB11_1
-; X32-NEXT:  # %bb.2: # %bb
-; X32-NEXT:    jmp foo5 # TAILCALL
-; X32-NEXT:  .LBB11_1: # %bb6
+; X32-NEXT:    jne foo5 # TAILCALL
+; X32-NEXT:  # %bb.1: # %bb6
 ; X32-NEXT:    xorl %eax, %eax
 ; X32-NEXT:    retq
 entry:
   %0 = icmp eq i32 %x, 0
   br i1 %0, label %bb6, label %bb
 
 bb:
   %1 = tail call i32 @foo5(i32 %x, i32 %y, i32 %z.0, i32 %z.1, i32 %z.2) nounwind
   ret i32 %1
 
 bb6:
   ret i32 0
 }
 
 declare dso_local i32 @foo5(i32, i32, i32, i32, i32)
 
 %struct.t = type { i32, i32, i32, i32, i32 }
 
 define dso_local i32 @t12(i32 %x, i32 %y, ptr byval(%struct.t) align 4 %z) nounwind ssp {
 ; X86-LABEL: t12:
 ; X86:       # %bb.0: # %entry
 ; X86-NEXT:    cmpl $0, {{[0-9]+}}(%esp)
-; X86-NEXT:    je .LBB12_1
-; X86-NEXT:  # %bb.2: # %bb
-; X86-NEXT:    jmp foo6 # TAILCALL
-; X86-NEXT:  .LBB12_1: # %bb2
+; X86-NEXT:    jne foo6 # TAILCALL
+; X86-NEXT:  # %bb.1: # %bb2
 ; X86-NEXT:    xorl %eax, %eax
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: t12:
 ; X64:       # %bb.0: # %entry
 ; X64-NEXT:    testl %edi, %edi
-; X64-NEXT:    je .LBB12_1
-; X64-NEXT:  # %bb.2: # %bb
-; X64-NEXT:    jmp foo6 # TAILCALL
-; X64-NEXT:  .LBB12_1: # %bb2
+; X64-NEXT:    jne foo6 # TAILCALL
+; X64-NEXT:  # %bb.1: # %bb2
 ; X64-NEXT:    xorl %eax, %eax
 ; X64-NEXT:    retq
 ;
 ; X32-LABEL: t12:
 ; X32:       # %bb.0: # %entry
 ; X32-NEXT:    testl %edi, %edi
-; X32-NEXT:    je .LBB12_1
-; X32-NEXT:  # %bb.2: # %bb
-; X32-NEXT:    jmp foo6 # TAILCALL
-; X32-NEXT:  .LBB12_1: # %bb2
+; X32-NEXT:    jne foo6 # TAILCALL
+; X32-NEXT:  # %bb.1: # %bb2
 ; X32-NEXT:    xorl %eax, %eax
 ; X32-NEXT:    retq
 entry:
   %0 = icmp eq i32 %x, 0
   br i1 %0, label %bb2, label %bb
 
 bb:
   %1 = tail call i32 @foo6(i32 %x, i32 %y, ptr byval(%struct.t) align 4 %z) nounwind

 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    movl %eax, (%esp)
 ; X86-NEXT:    calll t22_f_sret@PLT
 ; X86-NEXT:    addl $8, %esp
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: t22_non_sret_to_sret:
 ; X64:       # %bb.0:
-; X64-NEXT:    jmp  t22_f_sret@PLT                  # TAILCALL
+; X64-NEXT:    jmp t22_f_sret@PLT # TAILCALL
 ;
 ; X32-LABEL: t22_non_sret_to_sret:
 ; X32:       # %bb.0:
-; X32-NEXT:    jmp  t22_f_sret@PLT                  # TAILCALL
+; X32-NEXT:    jmp t22_f_sret@PLT # TAILCALL
   tail call ccc void @t22_f_sret(ptr noalias sret(%struct.foo) %agg.result) nounwind
   ret void
 }
 
 declare dso_local fastcc void @t21_f_sret(ptr noalias sret(%struct.foo)) nounwind
 declare dso_local fastcc void @t21_f_sret2(ptr noalias sret(%struct.foo), ptr noalias) nounwind
 declare dso_local fastcc void @t21_f_non_sret(ptr) nounwind
 
 declare ccc void @t22_f_sret(ptr noalias sret(%struct.foo)) nounwind
 
 declare ccc void @f_sret(ptr noalias sret(%struct.foo), i32, i32) nounwind

llvm/test/CodeGen/X86/slow-incdec.ll

 declare {i32, i1} @llvm.uadd.with.overflow.i32(i32, i32)
 declare void @other(ptr ) nounwind;
 
 define void @cond_ae_to_cond_ne(ptr %p) nounwind {
 ; INCDEC-LABEL: cond_ae_to_cond_ne:
 ; INCDEC:       # %bb.0: # %entry
 ; INCDEC-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; INCDEC-NEXT:    incl (%eax)
-; INCDEC-NEXT:    jne .LBB6_1
-; INCDEC-NEXT:  # %bb.2: # %if.end4
-; INCDEC-NEXT:    jmp other@PLT # TAILCALL
-; INCDEC-NEXT:  .LBB6_1: # %return
+; INCDEC-NEXT:    je other@PLT # TAILCALL
+; INCDEC-NEXT:  # %bb.1: # %return
 ; INCDEC-NEXT:    retl
 ;
 ; ADD-LABEL: cond_ae_to_cond_ne:
 ; ADD:       # %bb.0: # %entry
 ; ADD-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; ADD-NEXT:    addl $1, (%eax)
-; ADD-NEXT:    jne .LBB6_1
-; ADD-NEXT:  # %bb.2: # %if.end4
-; ADD-NEXT:    jmp other@PLT # TAILCALL
-; ADD-NEXT:  .LBB6_1: # %return
+; ADD-NEXT:    je other@PLT # TAILCALL
+; ADD-NEXT:  # %bb.1: # %return
 ; ADD-NEXT:    retl
 entry:
   %t0 = load i32, ptr %p, align 8
   %add_ov = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %t0, i32 1)
   %inc = extractvalue { i32, i1 } %add_ov, 0
   store i32 %inc, ptr %p, align 8
   %ov = extractvalue { i32, i1 } %add_ov, 1
   br i1 %ov, label %if.end4, label %return

 ; INCDEC-LABEL: test_tail_call:
 ; INCDEC:       # %bb.0: # %entry
 ; INCDEC-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; INCDEC-NEXT:    incl (%eax)
 ; INCDEC-NEXT:    setne %al
 ; INCDEC-NEXT:    incb a
 ; INCDEC-NEXT:    sete d
 ; INCDEC-NEXT:    testb %al, %al
-; INCDEC-NEXT:    jne .LBB7_2
+; INCDEC-NEXT:    jne external_b@PLT # TAILCALL
 ; INCDEC-NEXT:  # %bb.1: # %then
 ; INCDEC-NEXT:    jmp external_a@PLT # TAILCALL
-; INCDEC-NEXT:  .LBB7_2: # %else
-; INCDEC-NEXT:    jmp external_b@PLT # TAILCALL
 ;
 ; ADD-LABEL: test_tail_call:
 ; ADD:       # %bb.0: # %entry
 ; ADD-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; ADD-NEXT:    addl $1, (%eax)
 ; ADD-NEXT:    setne %al
 ; ADD-NEXT:    addb $1, a
 ; ADD-NEXT:    sete d
 ; ADD-NEXT:    testb %al, %al
-; ADD-NEXT:    jne .LBB7_2
+; ADD-NEXT:    jne external_b@PLT # TAILCALL
 ; ADD-NEXT:  # %bb.1: # %then
 ; ADD-NEXT:    jmp external_a@PLT # TAILCALL
-; ADD-NEXT:  .LBB7_2: # %else
-; ADD-NEXT:    jmp external_b@PLT # TAILCALL
 entry:
   %val = load i32, ptr %ptr
   %add_ov = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %val, i32 1)
   %inc = extractvalue { i32, i1 } %add_ov, 0
   store i32 %inc, ptr %ptr
   %cmp = extractvalue { i32, i1 } %add_ov, 1
   %aval = load volatile i8, ptr @a
   %add_ov2 = call {i8, i1} @llvm.uadd.with.overflow.i8(i8 %aval, i8 1)

llvm/test/CodeGen/X86/sqrt-partial.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=SSE
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX
 
 ; PR31455 - https://bugs.llvm.org/show_bug.cgi?id=31455
 ; We have to assume that errno can be set, so we have to make a libcall in that case.
 ; But it's better for perf to check that the argument is valid rather than the result of
 ; sqrtss/sqrtsd.
 ; Note: This is really a test of the -partially-inline-libcalls IR pass (and we have an IR test
 ; for that), but we're checking the final asm to make sure that comes out as expected too.
 
 define float @f(float %val) nounwind {
 ; SSE-LABEL: f:
 ; SSE:       # %bb.0:
 ; SSE-NEXT:    xorps %xmm1, %xmm1
 ; SSE-NEXT:    ucomiss %xmm1, %xmm0
-; SSE-NEXT:    jb .LBB0_2
+; SSE-NEXT:    jb sqrtf # TAILCALL
 ; SSE-NEXT:  # %bb.1: # %.split
 ; SSE-NEXT:    sqrtss %xmm0, %xmm0
 ; SSE-NEXT:    retq
-; SSE-NEXT:  .LBB0_2: # %call.sqrt
-; SSE-NEXT:    jmp sqrtf # TAILCALL
 ;
 ; AVX-LABEL: f:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vxorps %xmm1, %xmm1, %xmm1
 ; AVX-NEXT:    vucomiss %xmm1, %xmm0
-; AVX-NEXT:    jb .LBB0_2
+; AVX-NEXT:    jb sqrtf # TAILCALL
 ; AVX-NEXT:  # %bb.1: # %.split
 ; AVX-NEXT:    vsqrtss %xmm0, %xmm0, %xmm0
 ; AVX-NEXT:    retq
-; AVX-NEXT:  .LBB0_2: # %call.sqrt
-; AVX-NEXT:    jmp sqrtf # TAILCALL
   %res = tail call float @sqrtf(float %val)
   ret float %res
 }
 
 define double @d(double %val) nounwind {
 ; SSE-LABEL: d:
 ; SSE:       # %bb.0:
 ; SSE-NEXT:    xorpd %xmm1, %xmm1
 ; SSE-NEXT:    ucomisd %xmm1, %xmm0
-; SSE-NEXT:    jb .LBB1_2
+; SSE-NEXT:    jb sqrt # TAILCALL
 ; SSE-NEXT:  # %bb.1: # %.split
 ; SSE-NEXT:    sqrtsd %xmm0, %xmm0
 ; SSE-NEXT:    retq
-; SSE-NEXT:  .LBB1_2: # %call.sqrt
-; SSE-NEXT:    jmp sqrt # TAILCALL
 ;
 ; AVX-LABEL: d:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vxorpd %xmm1, %xmm1, %xmm1
 ; AVX-NEXT:    vucomisd %xmm1, %xmm0
-; AVX-NEXT:    jb .LBB1_2
+; AVX-NEXT:    jb sqrt # TAILCALL
 ; AVX-NEXT:  # %bb.1: # %.split
 ; AVX-NEXT:    vsqrtsd %xmm0, %xmm0, %xmm0
 ; AVX-NEXT:    retq
-; AVX-NEXT:  .LBB1_2: # %call.sqrt
-; AVX-NEXT:    jmp sqrt # TAILCALL
   %res = tail call double @sqrt(double %val)
   ret double %res
 }
 
 define double @minsize(double %x, double %y) minsize {
 ; SSE-LABEL: minsize:
 ; SSE:       # %bb.0:
 ; SSE-NEXT:    mulsd %xmm0, %xmm0

llvm/test/CodeGen/X86/switch-bt.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=x86_64-- -asm-verbose=false < %s -jump-table-density=40 -switch-peel-threshold=101 | FileCheck %s
 
 ; This switch should use bit tests, and the third bit test case is just
 ; testing for one possible value, so it doesn't need a bt.
 
 ;      CHECK: movabsq $2305843009482129440, %r
 ; CHECK-NEXT: btq %rax, %r
 ; CHECK-NEXT: jb
sw.epilog:                                        ; preds = %sw.default, %sw.bb4, %sw.bb2, %sw.bb
   ret void
 }
 
 declare void @foo(i32)
 
 ; Don't zero extend the test operands to pointer type if it can be avoided.
 ; rdar://8781238
 define void @test2(i32 %x) nounwind ssp {
-; CHECK-LABEL: test2:
-; CHECK: cmpl $6
-; CHECK: ja
-
-; CHECK-NEXT: movl $91
-; CHECK-NOT: movl
-; CHECK-NEXT: btl
-; CHECK-NEXT: jae
+
 entry:
   switch i32 %x, label %if.end [
     i32 6, label %if.then
     i32 4, label %if.then
     i32 3, label %if.then
     i32 1, label %if.then
     i32 0, label %if.then
   ]
 
 if.then:                                          ; preds = %entry, %entry, %entry, %entry, %entry
   tail call void @bar() nounwind
   ret void
 
 if.end:                                           ; preds = %entry
   ret void
 }
 
 declare void @bar()
 
 define void @test3(i32 %x) nounwind {
-; CHECK-LABEL: test3:
-; CHECK: cmpl $5
-; CHECK: ja
-; CHECK: cmpl $4
-; CHECK: je
   switch i32 %x, label %if.end [
     i32 0, label %if.then
     i32 1, label %if.then
     i32 2, label %if.then
     i32 3, label %if.then
     i32 5, label %if.then
   ]
 if.then:
   tail call void @bar() nounwind
   ret void
 if.end:
   ret void
 }
 
 ; Ensure that optimizing for jump tables doesn't needlessly deteriorate the
 ; created binary tree search. See PR22262.
 define void @test4(i32 %x, ptr %y) {
-; CHECK-LABEL: test4:
 
 entry:
   switch i32 %x, label %sw.default [
     i32 10, label %sw.bb
     i32 20, label %sw.bb1
     i32 30, label %sw.bb2
     i32 40, label %sw.bb3
     i32 50, label %sw.bb4

 sw.default:
   store i32 7, ptr %y
   br label %sw.epilog
 sw.epilog:
   ret void
 
 ; The balanced binary switch here would start with a comparison against 39, but
 ; it is currently starting with 29 because of the density-sum heuristic.
-; CHECK: cmpl $39
-; CHECK: jg
-; CHECK: cmpl $10
-; CHECK: je
-; CHECK: cmpl $20
-; CHECK: je
-; CHECK: cmpl $30
-; CHECK: jne
-; CHECK: cmpl $40
-; CHECK: je
-; CHECK: cmpl $50
-; CHECK: je
-; CHECK: cmpl $60
-; CHECK: jne
 }
 
 
 ; Omit the range check when the default case is unreachable, see PR43129.
 declare void @g(i32)
 define void @test5(i32 %x) {
 
-; CHECK-LABEL: test5
-; CHECK-NOT: cmp
-
 ; 73 = 2^0 + 2^3 + 2^6
-; CHECK:      movl $73
-; CHECK-NEXT: btl
-; CHECK-NEXT: jb
 
 ; 146 = 2^1 + 2^4 + 2^7
-; CHECK-NEXT: movl $146
-; CHECK-NEXT: btl
-; CHECK-NEXT: jae
 
 
 entry:
   switch i32 %x, label %return [
     i32 0, label %bb0
     i32 3, label %bb0
     i32 6, label %bb0
 
     i32 1, label %bb1
     i32 4, label %bb1
     i32 7, label %bb1
 
     i32 2, label %bb2
     i32 5, label %bb2
     i32 8, label %bb2
   ]
 bb0: tail call void @g(i32 0) br label %return
 bb1: tail call void @g(i32 1) br label %return
 bb2: tail call void @g(i32 2) br label %return
 return: unreachable
 }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK: {{.*}}

llvm/test/CodeGen/X86/tail-opts.ll

 
 ; This triggers a situation where a new block (bb4 is split) is created and then
 ; would be passed to the PGSO interface llvm::shouldOptimizeForSize().
 @GV = dso_local global i32 0
 define dso_local void @bfi_new_block_pgso(i32 %c) nounwind {
 ; CHECK-LABEL: bfi_new_block_pgso:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    testl %edi, %edi
-; CHECK-NEXT:    je .LBB14_4
+; CHECK-NEXT:    je .LBB14_6
 ; CHECK-NEXT:  # %bb.1: # %bb1
 ; CHECK-NEXT:    pushq %rax
 ; CHECK-NEXT:    cmpl $16, %edi
-; CHECK-NEXT:    je .LBB14_6
+; CHECK-NEXT:    je .LBB14_3
 ; CHECK-NEXT:  # %bb.2: # %bb1
 ; CHECK-NEXT:    cmpl $17, %edi
-; CHECK-NEXT:    je .LBB14_7
-; CHECK-NEXT:  # %bb.3: # %bb4
+; CHECK-NEXT:    je .LBB14_4
+; CHECK-NEXT:  # %bb.5: # %bb4
 ; CHECK-NEXT:    popq %rax
 ; CHECK-NEXT:    jmp tail_call_me # TAILCALL
-; CHECK-NEXT:  .LBB14_4: # %bb5
+; CHECK-NEXT:  .LBB14_6: # %bb5
 ; CHECK-NEXT:    cmpl $128, %edi
-; CHECK-NEXT:    jne .LBB14_8
-; CHECK-NEXT:  # %bb.5: # %return
+; CHECK-NEXT:    jne tail_call_me # TAILCALL
+; CHECK-NEXT:  # %bb.7: # %return
 ; CHECK-NEXT:    retq
-; CHECK-NEXT:  .LBB14_6: # %bb3
+; CHECK-NEXT:  .LBB14_3: # %bb3
 ; CHECK-NEXT:    movl $0, GV(%rip)
-; CHECK-NEXT:  .LBB14_7: # %bb4
+; CHECK-NEXT:  .LBB14_4: # %bb4
 ; CHECK-NEXT:    callq func
 ; CHECK-NEXT:    popq %rax
-; CHECK-NEXT:  .LBB14_8: # %bb6
 ; CHECK-NEXT:    jmp tail_call_me # TAILCALL
 entry:
   %0 = icmp eq i32 %c, 0
   br i1 %0, label %bb5, label %bb1
 
 bb1:
   switch i32 %c, label %bb4 [
     i32 16, label %bb3

llvm/test/CodeGen/X86/tailcall-cgp-dup.ll

 ; rdar://11958338
 %0 = type opaque
 
 declare ptr @bar(ptr) uwtable optsize noinline ssp
 
 define hidden ptr @thingWithValue(ptr %self) uwtable ssp {
 entry:
 ; CHECK-LABEL: thingWithValue:
-; CHECK: jmp _bar
+; CHECK: je _bar
   br i1 undef, label %if.then.i, label %if.else.i
 
 if.then.i:                                        ; preds = %entry
   br label %someThingWithValue.exit
 
 if.else.i:                                        ; preds = %entry
   %call4.i = tail call ptr @bar(ptr undef) optsize
   br label %someThingWithValue.exit
 
 someThingWithValue.exit:                          ; preds = %if.else.i, %if.then.i
   %retval.0.in.i = phi ptr [ undef, %if.then.i ], [ %call4.i, %if.else.i ]
   ret ptr %retval.0.in.i
 }
 
 
 ; Correctly handle zext returns.
 declare zeroext i1 @foo_i1()
 
 ; CHECK-LABEL: zext_i1
-; CHECK: jmp _foo_i1
+; CHECK: je _foo_i1
 define zeroext i1 @zext_i1(i1 %k) {
 entry:
   br i1 %k, label %land.end, label %land.rhs
 
 land.rhs:                                         ; preds = %entry
   %call1 = tail call zeroext i1 @foo_i1()
   br label %land.end
 

 ; OPT-NEXT:    [[PTR:%.*]] = tail call ptr @g_ret32()
 ; OPT-NEXT:    ret ptr [[PTR]]
 ; OPT:       return:
 ; OPT-NEXT:    ret ptr [[OBJ]]
 ;
 ; CHECK-LABEL: f_ret8:
 ; CHECK:       ## %bb.0: ## %entry
 ; CHECK-NEXT:    testq %rdi, %rdi
-; CHECK-NEXT:    je LBB3_1
-; CHECK-NEXT:  ## %bb.2: ## %if.then
-; CHECK-NEXT:    jmp _g_ret32 ## TAILCALL
-; CHECK-NEXT:  LBB3_1: ## %return
+; CHECK-NEXT:    jne _g_ret32 ## TAILCALL
+; CHECK-NEXT:  ## %bb.1: ## %return
 ; CHECK-NEXT:    movq %rdi, %rax
 ; CHECK-NEXT:    retq
 entry:
   %cmp = icmp eq ptr %obj, null
   br i1 %cmp, label %return, label %if.then
 
 if.then:
   %ptr = tail call ptr @g_ret32()
   br label %return
 
 return:
   %retval = phi ptr [ %ptr, %if.then ], [ %obj, %entry ]
   ret ptr %retval
 }

llvm/test/CodeGen/X86/tailcall-extract.ll

 ; RUN: llc -opaque-pointers=0 -mtriple=x86_64-linux < %s | FileCheck %s
 ; RUN: opt -opaque-pointers=0 -codegenprepare -S -mtriple=x86_64-linux < %s | FileCheck %s --check-prefix OPT
 
 
 ; The exit block containing extractvalue can be duplicated into the BB
 ; containing call. And later tail call can be generated.
 
 ; CHECK-LABEL: test1:
+; CHECK:       je foo # TAILCALL
 ; CHECK:       jmp bar # TAILCALL
-; CHECK:       jmp foo # TAILCALL
 
 ; OPT-LABEL:   test1
 ; OPT:         if.then.i:
 ; OPT-NEXT:    tail call { i8*, i64 } @bar
 ; OPT-NEXT:    extractvalue
 ; OPT-NEXT:    bitcast
 ; OPT-NEXT:    ret
 ;
exit:
   ret i64 %ev
 }
 
 
 ; The extractvalue accesses a nest struct type, the extracted field has zero
 ; offset, so the exit block can still be duplicated, and tail call generated.
 
 ; CHECK-LABEL: test3:
+; CHECK:       je qux # TAILCALL
 ; CHECK:       jmp baz # TAILCALL
-; CHECK:       jmp qux # TAILCALL
 
 ; OPT-LABEL:   test3
 ; OPT:         if.then.i:
 ; OPT-NEXT:    tail call { { i8*, i64 }, i64 } @baz
 ; OPT-NEXT:    extractvalue
 ; OPT-NEXT:    bitcast
 ; OPT-NEXT:    ret
 ;

llvm/test/CodeGen/X86/xor-icmp.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=i686-unknown   | FileCheck %s --check-prefix=X86
 ; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s --check-prefix=X64
 ; rdar://7367229
 
 define i32 @t(i32 %a, i32 %b) nounwind ssp {
 ; X86-LABEL: t:
 ; X86:       # %bb.0: # %entry
 ; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    xorb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    testb $64, %al
-; X86-NEXT:    je .LBB0_1
-; X86-NEXT:  # %bb.2: # %bb1
-; X86-NEXT:    jmp bar # TAILCALL
-; X86-NEXT:  .LBB0_1: # %bb
+; X86-NEXT:    jne bar # TAILCALL
+; X86-NEXT:  # %bb.1: # %bb
 ; X86-NEXT:    jmp foo # TAILCALL
 ;
 ; X64-LABEL: t:
 ; X64:       # %bb.0: # %entry
 ; X64-NEXT:    xorl %esi, %edi
 ; X64-NEXT:    xorl %eax, %eax
 ; X64-NEXT:    testl $16384, %edi # imm = 0x4000
-; X64-NEXT:    je .LBB0_1
-; X64-NEXT:  # %bb.2: # %bb1
-; X64-NEXT:    jmp bar # TAILCALL
-; X64-NEXT:  .LBB0_1: # %bb
+; X64-NEXT:    jne bar # TAILCALL
+; X64-NEXT:  # %bb.1: # %bb
 ; X64-NEXT:    jmp foo # TAILCALL
 entry:
   %0 = and i32 %a, 16384
   %1 = icmp ne i32 %0, 0
   %2 = and i32 %b, 16384
   %3 = icmp ne i32 %2, 0
   %4 = xor i1 %1, %3
   br i1 %4, label %bb1, label %bb

 define i32 @t2(i32 %x, i32 %y) nounwind ssp {
 ; X86-LABEL: t2:
 ; X86:       # %bb.0: # %entry
 ; X86-NEXT:    cmpl $0, {{[0-9]+}}(%esp)
 ; X86-NEXT:    sete %al
 ; X86-NEXT:    cmpl $0, {{[0-9]+}}(%esp)
 ; X86-NEXT:    sete %cl
 ; X86-NEXT:    cmpb %al, %cl
-; X86-NEXT:    je .LBB1_1
-; X86-NEXT:  # %bb.2: # %bb
-; X86-NEXT:    jmp foo # TAILCALL
-; X86-NEXT:  .LBB1_1: # %return
+; X86-NEXT:    jne foo # TAILCALL
+; X86-NEXT:  # %bb.1: # %return
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: t2:
 ; X64:       # %bb.0: # %entry
 ; X64-NEXT:    testl %edi, %edi
 ; X64-NEXT:    sete %al
 ; X64-NEXT:    testl %esi, %esi
 ; X64-NEXT:    sete %cl