This is an archive of the discontinued LLVM Phabricator instance.

Differential D140692

[RISCV] Add Svpbmt extension support.
ClosedPublic

Authored by fakepaper56 on Dec 27 2022, 5:54 AM.

Details

Reviewers
kito-cheng
craig.topper
asb
reames
Commits
rGbd9c0f082b20: [RISCV] Add Svpbmt extension support.
Summary

Spec of Svpbmt: https://github.com/riscv/riscv-isa-manual/blob/master/src/supervisor.tex#L2399

Diff Detail

Event Timeline

fakepaper56 created this revision.Dec 27 2022, 5:54 AM
Herald added a project: Restricted Project. · View Herald TranscriptDec 27 2022, 5:54 AM
Herald added subscribers: sunshaoce, VincentWu, StephenFan and 28 others. · View Herald Transcript
fakepaper56 requested review of this revision.Dec 27 2022, 5:54 AM
Herald added projects: Restricted Project, Restricted Project. · View Herald TranscriptDec 27 2022, 5:54 AM
Herald added subscribers: llvm-commits, cfe-commits, • pcwang-thead and 2 others. · View Herald Transcript
kito-cheng added a comment.Dec 27 2022, 6:05 AM

You are typo on title and commit log, it should be Svpbmt not Svbmpt, but the code changes are right, and you need to update llvm/docs/RISCVUsage.rst too.

Harbormaster completed remote builds in B204981: Diff 485372.Dec 27 2022, 7:27 AM
fakepaper56 retitled this revision from [RISCV] Add Svbmpt extension support. to [RISCV] Add Svpbmt extension support..Dec 27 2022, 6:19 PM
fakepaper56 edited the summary of this revision. (Show Details)
fakepaper56 updated this revision to Diff 485446.Dec 27 2022, 6:23 PM

Fix typoes and add svpbmt into llvm/docs/RISCVUsage.rst.

fakepaper56 updated this revision to Diff 485447.Dec 27 2022, 6:24 PM

Suppress lint warning.

Harbormaster completed remote builds in B205039: Diff 485447.Dec 27 2022, 7:28 PM
kito-cheng accepted this revision.Dec 28 2022, 5:36 PM

LGTM

This revision is now accepted and ready to land.Dec 28 2022, 5:36 PM
This revision was landed with ongoing or failed builds.Dec 28 2022, 11:58 PM
Closed by commit rGbd9c0f082b20: [RISCV] Add Svpbmt extension support. (authored by fakepaper56). · Explain Why
This revision was automatically updated to reflect the committed changes.
fakepaper56 added a commit: rGbd9c0f082b20: [RISCV] Add Svpbmt extension support..

Revision Contents

PathSize
clang/
test/
Preprocessor/
7 lines
llvm/
docs/
1 line
lib/
Target/
RISCV/
4 lines
TargetParser/
1 line
test/
CodeGen/
RISCV/
4 lines

Diff 485585

clang/test/Preprocessor/riscv-target-features.c

Show All 35 Lines
// CHECK-NOT: __riscv_zksh // CHECK-NOT: __riscv_zksh
// CHECK-NOT: __riscv_zksed // CHECK-NOT: __riscv_zksed
// CHECK-NOT: __riscv_zkr // CHECK-NOT: __riscv_zkr
// CHECK-NOT: __riscv_zkt // CHECK-NOT: __riscv_zkt
// CHECK-NOT: __riscv_zk // CHECK-NOT: __riscv_zk
// CHECK-NOT: __riscv_zicbom // CHECK-NOT: __riscv_zicbom
// CHECK-NOT: __riscv_zicboz // CHECK-NOT: __riscv_zicboz
// CHECK-NOT: __riscv_svnapot // CHECK-NOT: __riscv_svnapot
// CHECK-NOT: __riscv_svpbmt
// CHECK-NOT: __riscv_svinval // CHECK-NOT: __riscv_svinval
// CHECK-NOT: __riscv_xventanacondops // CHECK-NOT: __riscv_xventanacondops
// CHECK-NOT: __riscv_zcd // CHECK-NOT: __riscv_zcd
// CHECK-NOT: __riscv_zcf // CHECK-NOT: __riscv_zcf
// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32im -x c -E -dM %s \ // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32im -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-M-EXT %s // RUN: -o - | FileCheck --check-prefix=CHECK-M-EXT %s
// RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64im -x c -E -dM %s \ // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64im -x c -E -dM %s \
▲ Show 20 Lines • Show All 379 Lines • ▼ Show 20 Lines
// CHECK-ZTSO-EXT: __riscv_ztso 1000{{$}} // CHECK-ZTSO-EXT: __riscv_ztso 1000{{$}}
// RUN: %clang -target riscv32 -march=rv32isvnapot -x c -E -dM %s \ // RUN: %clang -target riscv32 -march=rv32isvnapot -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SVNAPOT-EXT %s // RUN: -o - | FileCheck --check-prefix=CHECK-SVNAPOT-EXT %s
// RUN: %clang -target riscv64 -march=rv64isvnapot -x c -E -dM %s \ // RUN: %clang -target riscv64 -march=rv64isvnapot -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SVNAPOT-EXT %s // RUN: -o - | FileCheck --check-prefix=CHECK-SVNAPOT-EXT %s
// CHECK-SVNAPOT-EXT: __riscv_svnapot 1000000{{$}} // CHECK-SVNAPOT-EXT: __riscv_svnapot 1000000{{$}}
// RUN: %clang -target riscv32 -march=rv32isvpbmt -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SVPBMT-EXT %s
// RUN: %clang -target riscv64 -march=rv64isvpbmt -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SVPBMT-EXT %s
// CHECK-SVPBMT-EXT: __riscv_svpbmt 1000000{{$}}
// RUN: %clang -target riscv32 -march=rv32isvinval -x c -E -dM %s \ // RUN: %clang -target riscv32 -march=rv32isvinval -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SVINVAL-EXT %s // RUN: -o - | FileCheck --check-prefix=CHECK-SVINVAL-EXT %s
// RUN: %clang -target riscv64 -march=rv64isvinval -x c -E -dM %s \ // RUN: %clang -target riscv64 -march=rv64isvinval -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SVINVAL-EXT %s // RUN: -o - | FileCheck --check-prefix=CHECK-SVINVAL-EXT %s
// CHECK-SVINVAL-EXT: __riscv_svinval 1000000{{$}} // CHECK-SVINVAL-EXT: __riscv_svinval 1000000{{$}}
// RUN: %clang -target riscv64 -march=rv64ixventanacondops -x c -E -dM %s \ // RUN: %clang -target riscv64 -march=rv64ixventanacondops -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-XVENTANACONDOPS-EXT %s // RUN: -o - | FileCheck --check-prefix=CHECK-XVENTANACONDOPS-EXT %s
Show All 15 Lines

llvm/docs/RISCVUsage.rst

Show First 20 Lines • Show All 47 Lines • ▼ Show 20 Lines .. table:: Ratified Extensions by Status
Extension Status Extension Status
=============== ========================================================= =============== =========================================================
``A`` Supported ``A`` Supported
``C`` Supported ``C`` Supported
``D`` Supported ``D`` Supported
``F`` Supported ``F`` Supported
``M`` Supported ``M`` Supported
``Svinval`` Assembly Support ``Svinval`` Assembly Support
``Svpbmt`` Supported
``V`` Supported ``V`` Supported
``Zba`` Supported ``Zba`` Supported
``Zbb`` Supported ``Zbb`` Supported
``Zbc`` Supported ``Zbc`` Supported
``Zbkb`` Supported (`See note <#riscv-scalar-crypto-note1>`__) ``Zbkb`` Supported (`See note <#riscv-scalar-crypto-note1>`__)
``Zbkc`` Supported ``Zbkc`` Supported
``Zbkx`` Supported (`See note <#riscv-scalar-crypto-note1>`__) ``Zbkx`` Supported (`See note <#riscv-scalar-crypto-note1>`__)
``Zbs`` Supported ``Zbs`` Supported
▲ Show 20 Lines • Show All 110 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCV.td

Show First 20 Lines • Show All 407 Lines • ▼ Show 20 Lines
def HasStdExtZicbop : Predicate<"Subtarget->hasStdExtZicbop()">, def HasStdExtZicbop : Predicate<"Subtarget->hasStdExtZicbop()">,
AssemblerPredicate<(all_of FeatureStdExtZicbop), AssemblerPredicate<(all_of FeatureStdExtZicbop),
"'Zicbop' (Cache-Block Prefetch Instructions)">; "'Zicbop' (Cache-Block Prefetch Instructions)">;
def FeatureStdExtSvnapot def FeatureStdExtSvnapot
: SubtargetFeature<"svnapot", "HasStdExtSvnapot", "true", : SubtargetFeature<"svnapot", "HasStdExtSvnapot", "true",
"'Svnapot' (NAPOT Translation Contiguity)">; "'Svnapot' (NAPOT Translation Contiguity)">;
def FeatureStdExtSvpbmt
: SubtargetFeature<"svpbmt", "HasStdExtSvpbmt", "true",
"'Svpbmt' (Page-Based Memory Types)">;
def FeatureStdExtSvinval def FeatureStdExtSvinval
: SubtargetFeature<"svinval", "HasStdExtSvinval", "true", : SubtargetFeature<"svinval", "HasStdExtSvinval", "true",
"'Svinval' (Fine-Grained Address-Translation Cache Invalidation)">; "'Svinval' (Fine-Grained Address-Translation Cache Invalidation)">;
def HasStdExtSvinval : Predicate<"Subtarget->hasStdExtSvinval()">, def HasStdExtSvinval : Predicate<"Subtarget->hasStdExtSvinval()">,
AssemblerPredicate<(all_of FeatureStdExtSvinval), AssemblerPredicate<(all_of FeatureStdExtSvinval),
"'Svinval' (Fine-Grained Address-Translation Cache Invalidation)">; "'Svinval' (Fine-Grained Address-Translation Cache Invalidation)">;
def FeatureStdExtZtso def FeatureStdExtZtso
▲ Show 20 Lines • Show All 257 Lines • Show Last 20 Lines

llvm/lib/TargetParser/RISCVISAInfo.cpp

Show First 20 Lines • Show All 97 Lines • ▼ Show 20 Linesstatic const RISCVSupportedExtension SupportedExtensions[] = {
{"zve64f", RISCVExtensionVersion{1, 0}}, {"zve64f", RISCVExtensionVersion{1, 0}},
{"zve64d", RISCVExtensionVersion{1, 0}}, {"zve64d", RISCVExtensionVersion{1, 0}},
{"zicbom", RISCVExtensionVersion{1, 0}}, {"zicbom", RISCVExtensionVersion{1, 0}},
{"zicboz", RISCVExtensionVersion{1, 0}}, {"zicboz", RISCVExtensionVersion{1, 0}},
{"zicbop", RISCVExtensionVersion{1, 0}}, {"zicbop", RISCVExtensionVersion{1, 0}},
{"svnapot", RISCVExtensionVersion{1, 0}}, {"svnapot", RISCVExtensionVersion{1, 0}},
{"svpbmt", RISCVExtensionVersion{1, 0}},
{"svinval", RISCVExtensionVersion{1, 0}}, {"svinval", RISCVExtensionVersion{1, 0}},
{"xventanacondops", RISCVExtensionVersion{1, 0}}, {"xventanacondops", RISCVExtensionVersion{1, 0}},
{"xtheadvdot", RISCVExtensionVersion{1, 0}}, {"xtheadvdot", RISCVExtensionVersion{1, 0}},
}; };
static const RISCVSupportedExtension SupportedExperimentalExtensions[] = { static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
{"zihintntl", RISCVExtensionVersion{0, 2}}, {"zihintntl", RISCVExtensionVersion{0, 2}},
▲ Show 20 Lines • Show All 883 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/attributes.ll

Show All 31 Lines
; RUN: llc -mtriple=riscv32 -mattr=+zk %s -o - | FileCheck --check-prefix=RV32ZK %s ; RUN: llc -mtriple=riscv32 -mattr=+zk %s -o - | FileCheck --check-prefix=RV32ZK %s
; RUN: llc -mtriple=riscv32 -mattr=+zkn,+zkr,+zkt %s -o - | FileCheck --check-prefix=RV32COMBINEINTOZK %s ; RUN: llc -mtriple=riscv32 -mattr=+zkn,+zkr,+zkt %s -o - | FileCheck --check-prefix=RV32COMBINEINTOZK %s
; RUN: llc -mtriple=riscv32 -mattr=+zbkb,+zbkc,+zbkx,+zkne,+zknd,+zknh %s -o - | FileCheck --check-prefix=RV32COMBINEINTOZKN %s ; RUN: llc -mtriple=riscv32 -mattr=+zbkb,+zbkc,+zbkx,+zkne,+zknd,+zknh %s -o - | FileCheck --check-prefix=RV32COMBINEINTOZKN %s
; RUN: llc -mtriple=riscv32 -mattr=+zbkb,+zbkc,+zbkx,+zksed,+zksh %s -o - | FileCheck --check-prefix=RV32COMBINEINTOZKS %s ; RUN: llc -mtriple=riscv32 -mattr=+zbkb,+zbkc,+zbkx,+zksed,+zksh %s -o - | FileCheck --check-prefix=RV32COMBINEINTOZKS %s
; RUN: llc -mtriple=riscv32 -mattr=+zicbom %s -o - | FileCheck --check-prefix=RV32ZICBOM %s ; RUN: llc -mtriple=riscv32 -mattr=+zicbom %s -o - | FileCheck --check-prefix=RV32ZICBOM %s
; RUN: llc -mtriple=riscv32 -mattr=+zicboz %s -o - | FileCheck --check-prefix=RV32ZICBOZ %s ; RUN: llc -mtriple=riscv32 -mattr=+zicboz %s -o - | FileCheck --check-prefix=RV32ZICBOZ %s
; RUN: llc -mtriple=riscv32 -mattr=+zicbop %s -o - | FileCheck --check-prefix=RV32ZICBOP %s ; RUN: llc -mtriple=riscv32 -mattr=+zicbop %s -o - | FileCheck --check-prefix=RV32ZICBOP %s
; RUN: llc -mtriple=riscv32 -mattr=+svnapot %s -o - | FileCheck --check-prefix=RV32SVNAPOT %s ; RUN: llc -mtriple=riscv32 -mattr=+svnapot %s -o - | FileCheck --check-prefix=RV32SVNAPOT %s
; RUN: llc -mtriple=riscv32 -mattr=+svpbmt %s -o - | FileCheck --check-prefix=RV32SVPBMT %s
; RUN: llc -mtriple=riscv32 -mattr=+svinval %s -o - | FileCheck --check-prefix=RV32SVINVAL %s ; RUN: llc -mtriple=riscv32 -mattr=+svinval %s -o - | FileCheck --check-prefix=RV32SVINVAL %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zca %s -o - | FileCheck --check-prefix=RV32ZCA %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zca %s -o - | FileCheck --check-prefix=RV32ZCA %s
; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s
; RUN: llc -mtriple=riscv64 -mattr=+zmmul %s -o - | FileCheck --check-prefix=RV64ZMMUL %s ; RUN: llc -mtriple=riscv64 -mattr=+zmmul %s -o - | FileCheck --check-prefix=RV64ZMMUL %s
; RUN: llc -mtriple=riscv64 -mattr=+m,+zmmul %s -o - | FileCheck --check-prefix=RV64MZMMUL %s ; RUN: llc -mtriple=riscv64 -mattr=+m,+zmmul %s -o - | FileCheck --check-prefix=RV64MZMMUL %s
; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefix=RV64A %s ; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefix=RV64A %s
; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --check-prefix=RV64F %s ; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --check-prefix=RV64F %s
Show All 24 Lines
; RUN: llc -mtriple=riscv64 -mattr=+zk %s -o - | FileCheck --check-prefix=RV64ZK %s ; RUN: llc -mtriple=riscv64 -mattr=+zk %s -o - | FileCheck --check-prefix=RV64ZK %s
; RUN: llc -mtriple=riscv64 -mattr=+zkn,+zkr,+zkt %s -o - | FileCheck --check-prefix=RV64COMBINEINTOZK %s ; RUN: llc -mtriple=riscv64 -mattr=+zkn,+zkr,+zkt %s -o - | FileCheck --check-prefix=RV64COMBINEINTOZK %s
; RUN: llc -mtriple=riscv64 -mattr=+zbkb,+zbkc,+zbkx,+zkne,+zknd,+zknh %s -o - | FileCheck --check-prefix=RV64COMBINEINTOZKN %s ; RUN: llc -mtriple=riscv64 -mattr=+zbkb,+zbkc,+zbkx,+zkne,+zknd,+zknh %s -o - | FileCheck --check-prefix=RV64COMBINEINTOZKN %s
; RUN: llc -mtriple=riscv64 -mattr=+zbkb,+zbkc,+zbkx,+zksed,+zksh %s -o - | FileCheck --check-prefix=RV64COMBINEINTOZKS %s ; RUN: llc -mtriple=riscv64 -mattr=+zbkb,+zbkc,+zbkx,+zksed,+zksh %s -o - | FileCheck --check-prefix=RV64COMBINEINTOZKS %s
; RUN: llc -mtriple=riscv64 -mattr=+zicbom %s -o - | FileCheck --check-prefix=RV64ZICBOM %s ; RUN: llc -mtriple=riscv64 -mattr=+zicbom %s -o - | FileCheck --check-prefix=RV64ZICBOM %s
; RUN: llc -mtriple=riscv64 -mattr=+zicboz %s -o - | FileCheck --check-prefix=RV64ZICBOZ %s ; RUN: llc -mtriple=riscv64 -mattr=+zicboz %s -o - | FileCheck --check-prefix=RV64ZICBOZ %s
; RUN: llc -mtriple=riscv64 -mattr=+zicbop %s -o - | FileCheck --check-prefix=RV64ZICBOP %s ; RUN: llc -mtriple=riscv64 -mattr=+zicbop %s -o - | FileCheck --check-prefix=RV64ZICBOP %s
; RUN: llc -mtriple=riscv64 -mattr=+svnapot %s -o - | FileCheck --check-prefix=RV64SVNAPOT %s ; RUN: llc -mtriple=riscv64 -mattr=+svnapot %s -o - | FileCheck --check-prefix=RV64SVNAPOT %s
; RUN: llc -mtriple=riscv64 -mattr=+svpbmt %s -o - | FileCheck --check-prefix=RV64SVPBMT %s
; RUN: llc -mtriple=riscv64 -mattr=+svinval %s -o - | FileCheck --check-prefix=RV64SVINVAL %s ; RUN: llc -mtriple=riscv64 -mattr=+svinval %s -o - | FileCheck --check-prefix=RV64SVINVAL %s
; RUN: llc -mtriple=riscv64 -mattr=+xventanacondops %s -o - | FileCheck --check-prefix=RV64XVENTANACONDOPS %s ; RUN: llc -mtriple=riscv64 -mattr=+xventanacondops %s -o - | FileCheck --check-prefix=RV64XVENTANACONDOPS %s
; RUN: llc -mtriple=riscv64 -mattr=+xtheadvdot %s -o - | FileCheck --check-prefix=RV64XTHEADVDOT %s ; RUN: llc -mtriple=riscv64 -mattr=+xtheadvdot %s -o - | FileCheck --check-prefix=RV64XTHEADVDOT %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zawrs %s -o - | FileCheck --check-prefix=RV64ZAWRS %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zawrs %s -o - | FileCheck --check-prefix=RV64ZAWRS %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-ztso %s -o - | FileCheck --check-prefix=RV64ZTSO %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-ztso %s -o - | FileCheck --check-prefix=RV64ZTSO %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zca %s -o - | FileCheck --check-prefix=RV64ZCA %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zca %s -o - | FileCheck --check-prefix=RV64ZCA %s
; RV32M: .attribute 5, "rv32i2p0_m2p0" ; RV32M: .attribute 5, "rv32i2p0_m2p0"
Show All 28 Lines
; RV32ZK: .attribute 5, "rv32i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0" ; RV32ZK: .attribute 5, "rv32i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0"
; RV32COMBINEINTOZK: .attribute 5, "rv32i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0" ; RV32COMBINEINTOZK: .attribute 5, "rv32i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0"
; RV32COMBINEINTOZKN: .attribute 5, "rv32i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0" ; RV32COMBINEINTOZKN: .attribute 5, "rv32i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0"
; RV32COMBINEINTOZKS: .attribute 5, "rv32i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zks1p0_zksed1p0_zksh1p0" ; RV32COMBINEINTOZKS: .attribute 5, "rv32i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zks1p0_zksed1p0_zksh1p0"
; RV32ZICBOM: .attribute 5, "rv32i2p0_zicbom1p0" ; RV32ZICBOM: .attribute 5, "rv32i2p0_zicbom1p0"
; RV32ZICBOZ: .attribute 5, "rv32i2p0_zicboz1p0" ; RV32ZICBOZ: .attribute 5, "rv32i2p0_zicboz1p0"
; RV32ZICBOP: .attribute 5, "rv32i2p0_zicbop1p0" ; RV32ZICBOP: .attribute 5, "rv32i2p0_zicbop1p0"
; RV32SVNAPOT: .attribute 5, "rv32i2p0_svnapot1p0" ; RV32SVNAPOT: .attribute 5, "rv32i2p0_svnapot1p0"
; RV32SVPBMT: .attribute 5, "rv32i2p0_svpbmt1p0"
; RV32SVINVAL: .attribute 5, "rv32i2p0_svinval1p0" ; RV32SVINVAL: .attribute 5, "rv32i2p0_svinval1p0"
; RV32ZCA: .attribute 5, "rv32i2p0_zca0p70" ; RV32ZCA: .attribute 5, "rv32i2p0_zca0p70"
; RV64M: .attribute 5, "rv64i2p0_m2p0" ; RV64M: .attribute 5, "rv64i2p0_m2p0"
; RV64ZMMUL: .attribute 5, "rv64i2p0_zmmul1p0" ; RV64ZMMUL: .attribute 5, "rv64i2p0_zmmul1p0"
; RV64MZMMUL: .attribute 5, "rv64i2p0_m2p0_zmmul1p0" ; RV64MZMMUL: .attribute 5, "rv64i2p0_m2p0_zmmul1p0"
; RV64A: .attribute 5, "rv64i2p0_a2p0" ; RV64A: .attribute 5, "rv64i2p0_a2p0"
; RV64F: .attribute 5, "rv64i2p0_f2p0" ; RV64F: .attribute 5, "rv64i2p0_f2p0"
Show All 25 Lines
; RV64COMBINEINTOZK: .attribute 5, "rv64i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0" ; RV64COMBINEINTOZK: .attribute 5, "rv64i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0"
; RV64COMBINEINTOZKN: .attribute 5, "rv64i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0" ; RV64COMBINEINTOZKN: .attribute 5, "rv64i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0"
; RV64COMBINEINTOZKS: .attribute 5, "rv64i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zks1p0_zksed1p0_zksh1p0" ; RV64COMBINEINTOZKS: .attribute 5, "rv64i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zks1p0_zksed1p0_zksh1p0"
; RV64ZICBOM: .attribute 5, "rv64i2p0_zicbom1p0" ; RV64ZICBOM: .attribute 5, "rv64i2p0_zicbom1p0"
; RV64ZICBOZ: .attribute 5, "rv64i2p0_zicboz1p0" ; RV64ZICBOZ: .attribute 5, "rv64i2p0_zicboz1p0"
; RV64ZAWRS: .attribute 5, "rv64i2p0_zawrs1p0" ; RV64ZAWRS: .attribute 5, "rv64i2p0_zawrs1p0"
; RV64ZICBOP: .attribute 5, "rv64i2p0_zicbop1p0" ; RV64ZICBOP: .attribute 5, "rv64i2p0_zicbop1p0"
; RV64SVNAPOT: .attribute 5, "rv64i2p0_svnapot1p0" ; RV64SVNAPOT: .attribute 5, "rv64i2p0_svnapot1p0"
; RV64SVPBMT: .attribute 5, "rv64i2p0_svpbmt1p0"
; RV64SVINVAL: .attribute 5, "rv64i2p0_svinval1p0" ; RV64SVINVAL: .attribute 5, "rv64i2p0_svinval1p0"
; RV64XVENTANACONDOPS: .attribute 5, "rv64i2p0_xventanacondops1p0" ; RV64XVENTANACONDOPS: .attribute 5, "rv64i2p0_xventanacondops1p0"
; RV64XTHEADVDOT: .attribute 5, "rv64i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xtheadvdot1p0" ; RV64XTHEADVDOT: .attribute 5, "rv64i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xtheadvdot1p0"
; RV64ZTSO: .attribute 5, "rv64i2p0_ztso0p1" ; RV64ZTSO: .attribute 5, "rv64i2p0_ztso0p1"
; RV64ZCA: .attribute 5, "rv64i2p0_zca0p70" ; RV64ZCA: .attribute 5, "rv64i2p0_zca0p70"
define i32 @addi(i32 %a) { define i32 @addi(i32 %a) {
%1 = add i32 %a, 1 %1 = add i32 %a, 1
ret i32 %1 ret i32 %1
} }