[RISCV] Disable callee-saved register when the register is written by llvm.write_register intrinsic

[zixuan-wu]

Summary

Store of global named registers are always calls to llvm.write_register intrinsic. Normally, it is like in following C code.

register struct global_data *gd asm ("gp");

void arch_setup_gd(struct global_data *gd_ptr)
{
        gd = gd_ptr;

}

This patch is to avoid to save/restore those global named registers which are callee-saved registers.

[jrtc27]

AArch64 forbids it unless the register is marked reserved, which makes sense to me. I don't think this change is right.

[jrtc27]

(If the register is marked reserved with -ffixed-xN then you won't get the save/restore code here)

[arsenm]

If you're touching registers this way they should be reserved

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

1859

This is also one of those not-actually serialized in MIR fields

[zixuan-wu]

In D139996#4000175, @jrtc27 wrote:

(If the register is marked reserved with -ffixed-xN then you won't get the save/restore code here)

Nope, it's not enough. Before this patch, for example

struct global_data {};
register struct global_data *x9 asm ("x9");

void arch_setup_gd(struct global_data *gd_ptr)
{
        x9 = gd_ptr;

}

clang register.c -O2 -ffixed-x9 -S -o -

arch_setup_gd:                          # @arch_setup_gd
# %bb.0:                                # %entry
	addi	sp, sp, -16
	sd	s1, 8(sp)                       # 8-byte Folded Spill
	mv	s1, a0
	ld	s1, 8(sp)                       # 8-byte Folded Reload
	addi	sp, sp, 16
	ret

[zixuan-wu]

Gentle pin..

[luismarques]

In D139996#4000438, @zixuan-wu wrote:

Nope, it's not enough. Before this patch, for example

Handling this at the level of llvm.write_register seems like attacking the symptom rather than the root cause issue.
Aren't we just missing the logic to not spill the reserved register?

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

SDNode *BinOp =
                              CurDAG->getTargetConstant(ShiftedVal, DL, VT));
   SDNode *SLLI =
       CurDAG->getMachineNode(ShOpc, DL, VT, SDValue(BinOp, 0),
                              CurDAG->getTargetConstant(ShAmt, DL, VT));
   ReplaceNode(Node, SLLI);
   return true;
 }
 
+#define GET_REGISTER_MATCHER
+#include "RISCVGenAsmMatcher.inc"
+
 void RISCVDAGToDAGISel::Select(SDNode *Node) {
   // If we have a custom node, we have already selected.
   if (Node->isMachineOpcode()) {
     LLVM_DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << "\n");
     Node->setNodeId(-1);
     return;
   }
 
case RISCVISD::VFMV_V_F_VL: {
     // Update the chain.
     ReplaceUses(Src.getValue(1), SDValue(Load, 1));
     // Record the mem-refs
     CurDAG->setNodeMemRefs(Load, {Ld->getMemOperand()});
     // Replace the splat with the vlse.
     ReplaceNode(Node, Load);
     return;
   }
+  case ISD::WRITE_REGISTER: {
+    const auto *MD = cast<MDNodeSDNode>(Node->getOperand(1));
+    const auto *RegString = cast<MDString>(MD->getMD()->getOperand(0));
+
+    Register Reg = MatchRegisterAltName(RegString->getString());
+    if (Reg == RISCV::NoRegister)
+      Reg = MatchRegisterName(RegString->getString());
+    assert (Reg != RISCV::NoRegister && "Invalid register name at WRITE_REGISTER");
+
+    MachineRegisterInfo &MRI = MF->getRegInfo();
+    MRI.disableCalleeSavedRegister(Reg);
+    break;
+  }
   }
 
   // Select the default instruction.
   SelectCode(Node);
 }
 
 bool RISCVDAGToDAGISel::SelectInlineAsmMemoryOperand(
     const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) {

llvm/test/CodeGen/RISCV/get-register-noreserve.ll

 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mv sp, a0
 ; CHECK-NEXT:    ret
 entry:
   call void @llvm.write_register.i32(metadata !0, i32 %val)
   ret void
 }
 
+define i32 @get_gp() nounwind {
+; CHECK-LABEL: get_gp:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mv a0, gp
+; CHECK-NEXT:    ret
+entry:
+  %sp = call i32 @llvm.read_register.i32(metadata !3)
+  ret i32 %sp
+}
+
+define void @set_gp(i32 %val) nounwind {
+; CHECK-LABEL: set_gp:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mv gp, a0
+; CHECK-NEXT:    ret
+entry:
+  call void @llvm.write_register.i32(metadata !3, i32 %val)
+  ret void
+}
+
 define i32 @get_tp_arch_name() nounwind {
 ; CHECK-LABEL: get_tp_arch_name:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mv a0, tp
 ; CHECK-NEXT:    ret
 entry:
   %sp = call i32 @llvm.read_register.i32(metadata !1)
   ret i32 %sp
 }
 
 define i32 @get_csr_vlenb() nounwind {
 ; CHECK-LABEL: get_csr_vlenb:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    csrr a0, vlenb
 ; CHECK-NEXT:    ret
 entry:
   %sp = call i32 @llvm.read_register.i32(metadata !2)
   ret i32 %sp
 }
 
 
 declare i32 @llvm.read_register.i32(metadata) nounwind
 declare void @llvm.write_register.i32(metadata, i32) nounwind
 
-!0 = !{!"sp\00"}
-!1 = !{!"x4\00"}
+!0 = !{!"sp"}
+!1 = !{!"x4"}
 !2 = !{!"vlenb"}
+!3 = !{!"gp"}