[LoopVectorize] Clear cache of `LoopAccessInfoManager`

[Saldivarcher]

Summary

LAI is cached during the LoopDistribute pass, and is later re-used during LoopVectorize. The problem is that LoopVectorize changes SCEV, and the cached LAI does not get updated. Hence, when re-using the cached LAI, it references an invalid SCEV.

Fixes #59319

[fhahn]

Thanks for the patch! Some comments inline.

Could you add Fixes #59319 to the description, to make sure the issue is closed once this lands?

llvm/lib/Transforms/Scalar/LoopDistribute.cpp

995 ↗

(On Diff #481142)

We only need to clear if changes were made AFAICT

llvm/test/Transforms/LoopDistribute/pr59319.ll

3 ↗

(On Diff #481142)

nit: remove

5 ↗

(On Diff #481142)

Is this needed? If so, the test requires something like ; REQUIRES: x86-registered-target to make sure it is only run when the X86 backend is built.

13 ↗

(On Diff #481142)

nit: strip the indvars. prefix, it doesn't add anything and makes the names unnecessarily long.

24 ↗

(On Diff #481142)

Could you improve the naming of the blocks, e.g. loop.1, loop.2, something like that to make things easier to parse.

[Saldivarcher]

@fhahn thanks for taking a look! I made all the changes/improvements you suggested, looks a lot better.

Yeah, the assertion is only hit when a target is present, so that's why the target was there.

[Saldivarcher]

llvm/lib/Transforms/Scalar/LoopDistribute.cpp

995 ↗

(On Diff #481142)

The assertion is still hit if we only clear when changes are made, I think it's because we insert the loop here, then fail right after. So, there's still cached data when there are no changes made. Keep in mind that the LoopDistribute pass fails with all the loops, and all fail here.

[Saldivarcher]

@fhahn did you have any other comments/concerns?

[fhahn]

llvm/lib/Transforms/Scalar/LoopDistribute.cpp

995 ↗

(On Diff #481142)

Right, this indicates that LoopDistribute isn't the right place to fix it. We should only need invalidation *after* the IR changes. If the IR stays the same, there should be no issue with the cached loop-info objects.

I think the right place to invalidate here is in LoopVectorize's runImpl.

llvm/test/Transforms/LoopDistribute/pr59319.ll

2 ↗

(On Diff #481321)

no need to use <

5 ↗

(On Diff #481321)

nit: usually there's a space after ; both here and below.

8 ↗

(On Diff #481321)

check the full IR?

[fhahn]

llvm/test/Transforms/LoopDistribute/pr59319.ll

39 ↗

(On Diff #481321)

move the end of function

[Saldivarcher]

llvm/lib/Transforms/Scalar/LoopDistribute.cpp

995 ↗

(On Diff #481142)

When you mean invalidate, do you mean to clear the cache within LoopAccessInfoMap?

[Saldivarcher]

llvm/lib/Transforms/Scalar/LoopDistribute.cpp

995 ↗

(On Diff #481142)

When you mean invalidate, do you mean to clear the cache within LoopAccessInfoMap?

When you say*

[fhahn]

llvm/lib/Transforms/Scalar/LoopDistribute.cpp

995 ↗

(On Diff #481142)

When you mean invalidate, do you mean to clear the cache within LoopAccessInfoMap?

Yes

[Saldivarcher]

llvm/test/Transforms/LoopVectorize/pr59319.ll

9 ↗

(On Diff #486153)

check the full IR?

The resulting IR is pretty long, around ~150 lines. I think it might be a bit exhaustive to check the full resulting IR, is there something else I should check?

[Saldivarcher]

llvm/lib/Transforms/Vectorize/LoopVectorize.cpp

10609

@fhahn I wasn't sure where the best place to invalidate cache, if you think I should do it elsewhere I can do that.

[Saldivarcher]

llvm/test/Transforms/LoopVectorize/pr59319.ll

1 ↗

(On Diff #486153)

@fhahn I moved the test over to the LoopVectorize directory, hope that's alright! :)

[fhahn]

llvm/lib/Transforms/Vectorize/LoopVectorize.cpp

10609

It *should* be sufficient to do it if processLoop at line 10632 made modifications I think

llvm/test/Transforms/LoopVectorize/pr59319.ll

5 ↗

(On Diff #486153)

If it requires X86, please move it to the X86 subdirectory.

[Saldivarcher]

llvm/lib/Transforms/Vectorize/LoopVectorize.cpp

10609

That makes more sense, I only invalidate if something changed.

llvm/test/Transforms/LoopVectorize/X86/pr59319.ll

1 ↗

(On Diff #486310)

Ok, moved to the x86 directory, thanks for pointing that out.

[fhahn]

LGTM, with the comments addressed.

llvm/test/Transforms/LoopVectorize/X86/pr59319.ll

1 ↗

(On Diff #486310)

is it possible to specify a fixed VF/UF using -force-vector-width=X -force-vector-interleave=Y?

5 ↗

(On Diff #486310)

not needed now

8 ↗

(On Diff #486310)

It still would be good to make sure the IR we generate makes sense. You can use llvm/utils/update_test_checks.py to generate checks.

[fhahn]

As #59319 describes, enabling LoopDistribute along with LoopVectorize causes an assertion to be hit. The reason seems to be because the LoopDistribute pass doesn't clear out the cache of the LoopAccessInfoManager.

This needs updating, the reason is that we cache LAI during LoopDistribute, LoopVectorize makes changes that invalidate SCEV and then we re-use the cache LAI which references invalid SCEV expressions.

[Saldivarcher]

In D139601#4029994, @fhahn wrote:

As #59319 describes, enabling LoopDistribute along with LoopVectorize causes an assertion to be hit. The reason seems to be because the LoopDistribute pass doesn't clear out the cache of the LoopAccessInfoManager.

This needs updating, the reason is that we cache LAI during LoopDistribute, LoopVectorize makes changes that invalidate SCEV and then we re-use the cache LAI which references invalid SCEV expressions.

Updated!

llvm/test/Transforms/LoopVectorize/X86/pr59319.ll

8 ↗

(On Diff #486310)

Addressed all the comments. TIL about update_test_checks.py, thank you!

[fhahn]

LGTM, thanks! Just a few additional small comments for the test .

llvm/test/Transforms/LoopVectorize/X86/pr59319.ll

5 ↗

(On Diff #486724)

I *think* with the vectorization factor forced, the test doesn't need to be X86 specific. I think the triple now could be removed and the test moved out of the X86 directory.

might also be good to include a quick comment in the test that this tests LoopAccessInfo invalidation after LV modifying the IR. Might also be good to include something like loop-access-info-invalidation in the test name (in addition to prXXXX)

[Saldivarcher]

In D139601#4030711, @fhahn wrote:

LGTM, thanks! Just a few additional small comments for the test .

Thanks for taking the time to review this stuff, I appreciate it!

All comments should be addressed now. :)

[Saldivarcher]

@fhahn also, would you be able to commit this for me? I don't have commit access.

llvm/lib/Transforms/Vectorize/LoopVectorize.cpp

LoopVectorizeResult LoopVectorizePass::runImpl(
   // interleaving.
   if (!TTI->getNumberOfRegisters(TTI->getRegisterClassForType(true)) &&
       TTI->getMaxInterleaveFactor(1) < 2)
     return LoopVectorizeResult(false, false);
 
   bool Changed = false, CFGChanged = false;
 
   // The vectorizer requires loops to be in simplified form.
   // Since simplification may add new inner loops, it has to run before the
   // legality and profitability checks. This means running the loop vectorizer
   // will simplify all loops, regardless of whether anything end up being
   // vectorized.
   for (const auto &L : *LI)
     Changed |= CFGChanged |=
         simplifyLoop(L, DT, LI, SE, AC, nullptr, false /* PreserveLCSSA */);
 
   // Build up a worklist of inner-loops to vectorize. This is necessary as
LoopVectorizeResult LoopVectorizePass::runImpl(
   while (!Worklist.empty()) {
     Loop *L = Worklist.pop_back_val();
 
     // For the inner loops we actually process, form LCSSA to simplify the
     // transform.
     Changed |= formLCSSARecursively(*L, *DT, LI, SE);
 
     Changed |= CFGChanged |= processLoop(L);
+
+    if (Changed)
+      LAIs->clear();
   }
 
   // Process each loop nest in the function.
   return LoopVectorizeResult(Changed, CFGChanged);
 }
 
 PreservedAnalyses LoopVectorizePass::run(Function &F,
                                          FunctionAnalysisManager &AM) {

llvm/test/Transforms/LoopVectorize/pr59319-loop-access-info-invalidation.ll

+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -passes=loop-distribute,loop-vectorize -enable-loop-distribute -force-vector-width=4 -force-vector-interleave=1 -S \
+; RUN: %s | FileCheck %s
+
+; This test is to assure LoopAccessInfo invalidation after LoopVectorize
+; modifies the IR.
+define void @reduced(i32* %0, i32* %1, i64 %iv, i32* %2, i64 %iv76, i64 %iv93) {
+; CHECK-LABEL: @reduced(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP3:%.*]] = bitcast i32* [[TMP1:%.*]] to i8*
+; CHECK-NEXT:    [[TMP4:%.*]] = add i64 [[IV:%.*]], 1
+; CHECK-NEXT:    [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP4]], 4
+; CHECK-NEXT:    br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
+; CHECK:       vector.ph:
+; CHECK-NEXT:    [[N_MOD_VF:%.*]] = urem i64 [[TMP4]], 4
+; CHECK-NEXT:    [[IND_END:%.*]] = sub i64 [[TMP4]], [[N_MOD_VF]]
+; CHECK-NEXT:    br label [[VECTOR_BODY:%.*]]
+; CHECK:       vector.body:
+; CHECK-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
+; CHECK-NEXT:    [[TMP5:%.*]] = add i64 [[INDEX]], 0
+; CHECK-NEXT:    [[TMP6:%.*]] = add i64 [[INDEX]], 1
+; CHECK-NEXT:    [[TMP7:%.*]] = add i64 [[INDEX]], 2
+; CHECK-NEXT:    [[TMP8:%.*]] = add i64 [[INDEX]], 3
+; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
+; CHECK-NEXT:    [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[IND_END]]
+; CHECK-NEXT:    br i1 [[TMP9]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; CHECK:       middle.block:
+; CHECK-NEXT:    [[CMP_N:%.*]] = icmp eq i64 [[TMP4]], [[IND_END]]
+; CHECK-NEXT:    [[IND_ESCAPE:%.*]] = sub i64 [[IND_END]], 1
+; CHECK-NEXT:    br i1 [[CMP_N]], label [[LOOP_2_PREHEADER:%.*]], label [[SCALAR_PH]]
+; CHECK:       scalar.ph:
+; CHECK-NEXT:    [[BC_RESUME_VAL:%.*]] = phi i64 [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ]
+; CHECK-NEXT:    [[BC_RESUME_VAL1:%.*]] = phi i64 [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ]
+; CHECK-NEXT:    br label [[LOOP_1:%.*]]
+; CHECK:       loop.1:
+; CHECK-NEXT:    [[IV761:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT77:%.*]], [[LOOP_1]] ]
+; CHECK-NEXT:    [[IV4:%.*]] = phi i64 [ [[BC_RESUME_VAL1]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP_1]] ]
+; CHECK-NEXT:    [[IV_NEXT77]] = add i64 [[IV761]], 1
+; CHECK-NEXT:    [[ARRAYIDX_I_I50:%.*]] = getelementptr i32, i32* [[TMP0:%.*]], i64 [[IV76:%.*]]
+; CHECK-NEXT:    [[IV_NEXT]] = add i64 [[IV4]], 1
+; CHECK-NEXT:    [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV4]], [[IV]]
+; CHECK-NEXT:    br i1 [[EXITCOND_NOT]], label [[LOOP_2_PREHEADER]], label [[LOOP_1]], !llvm.loop [[LOOP2:![0-9]+]]
+; CHECK:       loop.2.preheader:
+; CHECK-NEXT:    [[IV761_LCSSA:%.*]] = phi i64 [ [[IV761]], [[LOOP_1]] ], [ [[IND_ESCAPE]], [[MIDDLE_BLOCK]] ]
+; CHECK-NEXT:    [[MIN_ITERS_CHECK9:%.*]] = icmp ult i64 [[TMP4]], 4
+; CHECK-NEXT:    br i1 [[MIN_ITERS_CHECK9]], label [[SCALAR_PH8:%.*]], label [[VECTOR_MEMCHECK:%.*]]
+; CHECK:       vector.memcheck:
+; CHECK-NEXT:    [[SCEVGEP:%.*]] = getelementptr i32, i32* [[TMP1]], i64 1
+; CHECK-NEXT:    [[SCEVGEP2:%.*]] = bitcast i32* [[SCEVGEP]] to i8*
+; CHECK-NEXT:    [[SCEVGEP3:%.*]] = getelementptr i32, i32* [[TMP0]], i64 [[IV761_LCSSA]]
+; CHECK-NEXT:    [[SCEVGEP34:%.*]] = bitcast i32* [[SCEVGEP3]] to i8*
+; CHECK-NEXT:    [[TMP10:%.*]] = add i64 [[IV761_LCSSA]], 1
+; CHECK-NEXT:    [[SCEVGEP5:%.*]] = getelementptr i32, i32* [[TMP0]], i64 [[TMP10]]
+; CHECK-NEXT:    [[SCEVGEP56:%.*]] = bitcast i32* [[SCEVGEP5]] to i8*
+; CHECK-NEXT:    [[BOUND0:%.*]] = icmp ult i8* [[TMP3]], [[SCEVGEP56]]
+; CHECK-NEXT:    [[BOUND1:%.*]] = icmp ult i8* [[SCEVGEP34]], [[SCEVGEP2]]
+; CHECK-NEXT:    [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]]
+; CHECK-NEXT:    br i1 [[FOUND_CONFLICT]], label [[SCALAR_PH8]], label [[VECTOR_PH10:%.*]]
+; CHECK:       vector.ph10:
+; CHECK-NEXT:    [[N_MOD_VF11:%.*]] = urem i64 [[TMP4]], 4
+; CHECK-NEXT:    [[N_VEC:%.*]] = sub i64 [[TMP4]], [[N_MOD_VF11]]
+; CHECK-NEXT:    br label [[VECTOR_BODY14:%.*]]
+; CHECK:       vector.body14:
+; CHECK-NEXT:    [[INDEX15:%.*]] = phi i64 [ 0, [[VECTOR_PH10]] ], [ [[INDEX_NEXT16:%.*]], [[VECTOR_BODY14]] ]
+; CHECK-NEXT:    store i32 0, i32* [[TMP1]], align 4, !alias.scope !4, !noalias !7
+; CHECK-NEXT:    [[INDEX_NEXT16]] = add nuw i64 [[INDEX15]], 4
+; CHECK-NEXT:    [[TMP11:%.*]] = icmp eq i64 [[INDEX_NEXT16]], [[N_VEC]]
+; CHECK-NEXT:    br i1 [[TMP11]], label [[MIDDLE_BLOCK7:%.*]], label [[VECTOR_BODY14]], !llvm.loop [[LOOP9:![0-9]+]]
+; CHECK:       middle.block7:
+; CHECK-NEXT:    [[CMP_N13:%.*]] = icmp eq i64 [[TMP4]], [[N_VEC]]
+; CHECK-NEXT:    br i1 [[CMP_N13]], label [[LOOP_3_LR_PH:%.*]], label [[SCALAR_PH8]]
+; CHECK:       scalar.ph8:
+; CHECK-NEXT:    [[BC_RESUME_VAL12:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK7]] ], [ 0, [[LOOP_2_PREHEADER]] ], [ 0, [[VECTOR_MEMCHECK]] ]
+; CHECK-NEXT:    br label [[LOOP_2:%.*]]
+; CHECK:       loop.3.lr.ph:
+; CHECK-NEXT:    [[IDXPROM_I_I61:%.*]] = and i64 [[IV761_LCSSA]], 1
+; CHECK-NEXT:    [[ARRAYIDX_I_I62:%.*]] = getelementptr i32, i32* [[TMP0]], i64 [[IDXPROM_I_I61]]
+; CHECK-NEXT:    [[ARRAYIDX_I_I6220:%.*]] = bitcast i32* [[ARRAYIDX_I_I62]] to i8*
+; CHECK-NEXT:    [[MIN_ITERS_CHECK28:%.*]] = icmp ult i64 [[TMP4]], 4
+; CHECK-NEXT:    br i1 [[MIN_ITERS_CHECK28]], label [[SCALAR_PH27:%.*]], label [[VECTOR_MEMCHECK17:%.*]]
+; CHECK:       vector.memcheck17:
+; CHECK-NEXT:    [[SCEVGEP18:%.*]] = getelementptr i32, i32* [[TMP1]], i64 1
+; CHECK-NEXT:    [[SCEVGEP1819:%.*]] = bitcast i32* [[SCEVGEP18]] to i8*
+; CHECK-NEXT:    [[TMP12:%.*]] = add nuw nsw i64 [[IDXPROM_I_I61]], 1
+; CHECK-NEXT:    [[SCEVGEP21:%.*]] = getelementptr i32, i32* [[TMP0]], i64 [[TMP12]]
+; CHECK-NEXT:    [[SCEVGEP2122:%.*]] = bitcast i32* [[SCEVGEP21]] to i8*
+; CHECK-NEXT:    [[BOUND023:%.*]] = icmp ult i8* [[TMP3]], [[SCEVGEP2122]]
+; CHECK-NEXT:    [[BOUND124:%.*]] = icmp ult i8* [[ARRAYIDX_I_I6220]], [[SCEVGEP1819]]
+; CHECK-NEXT:    [[FOUND_CONFLICT25:%.*]] = and i1 [[BOUND023]], [[BOUND124]]
+; CHECK-NEXT:    br i1 [[FOUND_CONFLICT25]], label [[SCALAR_PH27]], label [[VECTOR_PH29:%.*]]
+; CHECK:       vector.ph29:
+; CHECK-NEXT:    [[N_MOD_VF30:%.*]] = urem i64 [[TMP4]], 4
+; CHECK-NEXT:    [[N_VEC31:%.*]] = sub i64 [[TMP4]], [[N_MOD_VF30]]
+; CHECK-NEXT:    br label [[VECTOR_BODY34:%.*]]
+; CHECK:       vector.body34:
+; CHECK-NEXT:    [[INDEX35:%.*]] = phi i64 [ 0, [[VECTOR_PH29]] ], [ [[INDEX_NEXT36:%.*]], [[VECTOR_BODY34]] ]
+; CHECK-NEXT:    store i32 0, i32* [[TMP1]], align 4, !alias.scope !10, !noalias !13
+; CHECK-NEXT:    [[INDEX_NEXT36]] = add nuw i64 [[INDEX35]], 4
+; CHECK-NEXT:    [[TMP13:%.*]] = icmp eq i64 [[INDEX_NEXT36]], [[N_VEC31]]
+; CHECK-NEXT:    br i1 [[TMP13]], label [[MIDDLE_BLOCK26:%.*]], label [[VECTOR_BODY34]], !llvm.loop [[LOOP15:![0-9]+]]
+; CHECK:       middle.block26:
+; CHECK-NEXT:    [[CMP_N33:%.*]] = icmp eq i64 [[TMP4]], [[N_VEC31]]
+; CHECK-NEXT:    br i1 [[CMP_N33]], label [[LOOP_CLEANUP:%.*]], label [[SCALAR_PH27]]
+; CHECK:       scalar.ph27:
+; CHECK-NEXT:    [[BC_RESUME_VAL32:%.*]] = phi i64 [ [[N_VEC31]], [[MIDDLE_BLOCK26]] ], [ 0, [[LOOP_3_LR_PH]] ], [ 0, [[VECTOR_MEMCHECK17]] ]
+; CHECK-NEXT:    br label [[LOOP_3:%.*]]
+; CHECK:       loop.2:
+; CHECK-NEXT:    [[IV846:%.*]] = phi i64 [ [[IV_NEXT85:%.*]], [[LOOP_2]] ], [ [[BC_RESUME_VAL12]], [[SCALAR_PH8]] ]
+; CHECK-NEXT:    [[IV_NEXT87:%.*]] = add i64 0, 0
+; CHECK-NEXT:    [[ARRAYIDX_I_I56:%.*]] = getelementptr i32, i32* [[TMP0]], i64 [[IV761_LCSSA]]
+; CHECK-NEXT:    [[TMP14:%.*]] = load i32, i32* [[ARRAYIDX_I_I56]], align 4
+; CHECK-NEXT:    store i32 0, i32* [[TMP1]], align 4
+; CHECK-NEXT:    [[IV_NEXT85]] = add i64 [[IV846]], 1
+; CHECK-NEXT:    [[EXITCOND92_NOT:%.*]] = icmp eq i64 [[IV846]], [[IV]]
+; CHECK-NEXT:    br i1 [[EXITCOND92_NOT]], label [[LOOP_3_LR_PH]], label [[LOOP_2]], !llvm.loop [[LOOP16:![0-9]+]]
+; CHECK:       loop.3:
+; CHECK-NEXT:    [[IV932:%.*]] = phi i64 [ [[BC_RESUME_VAL32]], [[SCALAR_PH27]] ], [ [[IV_NEXT94:%.*]], [[LOOP_3]] ]
+; CHECK-NEXT:    [[TMP15:%.*]] = load i32, i32* [[ARRAYIDX_I_I62]], align 4
+; CHECK-NEXT:    [[ARRAYIDX_I_I653:%.*]] = getelementptr i32, i32* [[TMP2:%.*]], i64 [[IV93:%.*]]
+; CHECK-NEXT:    store i32 0, i32* [[TMP1]], align 4
+; CHECK-NEXT:    [[IV_NEXT94]] = add i64 [[IV932]], 1
+; CHECK-NEXT:    [[EXITCOND97_NOT:%.*]] = icmp eq i64 [[IV932]], [[IV]]
+; CHECK-NEXT:    br i1 [[EXITCOND97_NOT]], label [[LOOP_CLEANUP]], label [[LOOP_3]], !llvm.loop [[LOOP17:![0-9]+]]
+; CHECK:       loop.cleanup:
+; CHECK-NEXT:    ret void
+;
+entry:
+  br label %loop.1
+
+loop.1:                                         ; preds = %loop.1, %entry
+  %iv761 = phi i64 [ 0, %entry ], [ %iv.next77, %loop.1 ]
+  %iv4 = phi i64 [ 0, %entry ], [ %iv.next, %loop.1 ]
+  %iv.next77 = add i64 %iv761, 1
+  %arrayidx.i.i50 = getelementptr i32, i32* %0, i64 %iv76
+  %iv.next = add i64 %iv4, 1
+  %exitcond.not = icmp eq i64 %iv4, %iv
+  br i1 %exitcond.not, label %loop.2.preheader, label %loop.1
+
+loop.2.preheader:                             ; preds = %loop.1
+  br label %loop.2
+
+loop.3.lr.ph:                                 ; preds = %loop.2
+  %idxprom.i.i61 = and i64 %iv761, 1
+  %arrayidx.i.i62 = getelementptr i32, i32* %0, i64 %idxprom.i.i61
+  br label %loop.3
+
+loop.2:                                       ; preds = %loop.2, %loop.2.preheader
+  %iv846 = phi i64 [ %iv.next85, %loop.2 ], [ 0, %loop.2.preheader ]
+  %iv.next87 = add i64 0, 0
+  %arrayidx.i.i56 = getelementptr i32, i32* %0, i64 %iv761
+  %3 = load i32, i32* %arrayidx.i.i56, align 4
+  store i32 0, i32* %1, align 4
+  %iv.next85 = add i64 %iv846, 1
+  %exitcond92.not = icmp eq i64 %iv846, %iv
+  br i1 %exitcond92.not, label %loop.3.lr.ph, label %loop.2
+
+loop.3:                                       ; preds = %loop.3, %loop.3.lr.ph
+  %iv932 = phi i64 [ 0, %loop.3.lr.ph ], [ %iv.next94, %loop.3 ]
+  %4 = load i32, i32* %arrayidx.i.i62, align 4
+  %arrayidx.i.i653 = getelementptr i32, i32* %2, i64 %iv93
+  store i32 0, i32* %1, align 4
+  %iv.next94 = add i64 %iv932, 1
+  %exitcond97.not = icmp eq i64 %iv932, %iv
+  br i1 %exitcond97.not, label %loop.cleanup, label %loop.3
+
+loop.cleanup:                               ; preds = %loop.3
+  ret void
+}