[RISCV] Replace uses of hasStdExtC with COrZca.

[craig.topper]

Summary

Except MakeCompressible which will need more work.

[craig.topper]

Remove a piece of testing code

[reames]

LGTM

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp

if (Res.size() > 2 && ActiveFeatures[RISCV::FeatureStdExtZbb]) {
     }
   }
   return Res;
 }
 
 int getIntMatCost(const APInt &Val, unsigned Size,
                   const FeatureBitset &ActiveFeatures, bool CompressionCost) {
   bool IsRV64 = ActiveFeatures[RISCV::Feature64Bit];
-  bool HasRVC = CompressionCost && ActiveFeatures[RISCV::FeatureStdExtC];
+  bool HasRVC = CompressionCost && (ActiveFeatures[RISCV::FeatureStdExtC] ||
+                                    ActiveFeatures[RISCV::FeatureExtZca]);
   int PlatRegSize = IsRV64 ? 64 : 32;
 
   // Split the constant into platform register sized chunks, and calculate cost
   // of each chunk.
   int Cost = 0;
   for (unsigned ShiftVal = 0; ShiftVal < Size; ShiftVal += PlatRegSize) {
     APInt Chunk = Val.ashr(ShiftVal).sextOrTrunc(PlatRegSize);
     InstSeq MatSeq = generateInstSeq(Chunk.getSExtValue(), ActiveFeatures);

llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp

bool RISCVMakeCompressibleOpt::runOnMachineFunction(MachineFunction &Fn) {
   // This is a size optimization.
   if (skipFunction(Fn.getFunction()) || !Fn.getFunction().hasMinSize())
     return false;
 
   const RISCVSubtarget &STI = Fn.getSubtarget<RISCVSubtarget>();
   const RISCVInstrInfo &TII = *STI.getInstrInfo();
 
   // This optimization only makes sense if compressed instructions are emitted.
+  // FIXME: Support Zca, Zcf, Zcd granularity.
   if (!STI.hasStdExtC())
     return false;
 
   for (MachineBasicBlock &MBB : Fn) {
     LLVM_DEBUG(dbgs() << "MBB: " << MBB.getName() << "\n");
     for (MachineInstr &MI : MBB) {
       // Determine if this instruction would otherwise be compressed if not for
       // an uncompressible register or offset.

llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp

if (VLENBSized > 0) {
     Ops.append({dwarf::DW_OP_bregx, VLENB, 0ULL});
     Ops.push_back(dwarf::DW_OP_mul);
     Ops.push_back(dwarf::DW_OP_minus);
   }
 }
 
 unsigned
 RISCVRegisterInfo::getRegisterCostTableIndex(const MachineFunction &MF) const {
-  return MF.getSubtarget<RISCVSubtarget>().hasStdExtC() ? 1 : 0;
+  return MF.getSubtarget<RISCVSubtarget>().hasStdExtCOrZca() ? 1 : 0;
 }
 
 // Add two address hints to improve chances of being able to use a compressed
 // instruction.
 bool RISCVRegisterInfo::getRegAllocationHints(
     Register VirtReg, ArrayRef<MCPhysReg> Order,
     SmallVectorImpl<MCPhysReg> &Hints, const MachineFunction &MF,
     const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const {

llvm/test/CodeGen/RISCV/add-before-shl.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs --riscv-no-aliases < %s \
 ; RUN:   | FileCheck -check-prefixes=RV32I %s
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs --riscv-no-aliases < %s \
 ; RUN:   | FileCheck -check-prefixes=RV64I %s
 ; RUN: llc -mtriple=riscv32 -mattr=+c -verify-machineinstrs --riscv-no-aliases \
 ; RUN:   < %s | FileCheck -check-prefixes=RV32C %s
 ; RUN: llc -mtriple=riscv64 -mattr=+c -verify-machineinstrs --riscv-no-aliases \
 ; RUN:   < %s | FileCheck -check-prefixes=RV64C %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zca -verify-machineinstrs --riscv-no-aliases \
+; RUN:   < %s | FileCheck -check-prefixes=RV32C %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zca -verify-machineinstrs --riscv-no-aliases \
+; RUN:   < %s | FileCheck -check-prefixes=RV64C %s
 
 ; These test that constant adds are not moved after shifts by DAGCombine,
 ; if the constant is cheaper to materialise before it has been shifted.
 
 define signext i32 @add_small_const(i32 signext %a) nounwind {
 ; RV32I-LABEL: add_small_const:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a0, a0, 1