[mlir][NFC] Remove trailing whitespaces from `*.td` and `*.mlir` files.

[hanchung]

Summary

This is generated by running

sed --in-place 's/[[:space:]]\+$//' mlir/**/*.td
sed --in-place 's/[[:space:]]\+$//' mlir/**/*.mlir

[dcaballe]

Thanks!

mlir/include/mlir/Dialect/Async/IR/AsyncOps.td

 
 def Async_FuncOp : Async_Op<"func",
     [CallableOpInterface, FunctionOpInterface,
      IsolatedFromAbove, OpAsmOpInterface, Symbol]> {
   let summary = "async function operation";
   let description = [{
     An async function is like a normal function, but supports non-blocking
     await. Internally, async function is lowered to the LLVM coroutinue with
-    async runtime intrinsic. It can return an async token and/or async values. 
-    The token represents the execution state of async function and can be used 
+    async runtime intrinsic. It can return an async token and/or async values.
+    The token represents the execution state of async function and can be used
     when users want to express dependencies on some side effects, e.g.,
     the token becomes available once every thing in the func body is executed.
 
     Example:
 
     ```mlir
     // Async function can't return void, it always must be some async thing.
     async.func @async.0() -> !async.token {

mlir/include/mlir/Dialect/Bufferization/IR/BufferizationEnums.td

 //
 //===----------------------------------------------------------------------===//
 
 #ifndef BUFFERIZATION_ENUMS
 #define BUFFERIZATION_ENUMS
 
 include "mlir/IR/EnumAttr.td"
 
-def LayoutMapOption : I32EnumAttr<"LayoutMapOption", 
+def LayoutMapOption : I32EnumAttr<"LayoutMapOption",
                                   "option for map layout", [
   I32EnumAttrCase<"InferLayoutMap", 0>,
   I32EnumAttrCase<"IdentityLayoutMap", 1>,
   I32EnumAttrCase<"FullyDynamicLayoutMap", 2>
 ]> {
   let cppNamespace = "::mlir::bufferization";
 }
 
 #endif // BUFFERIZATION_ENUMS

mlir/include/mlir/Dialect/Complex/IR/ComplexOps.td

def ConstantOp : Complex_Op<"constant", [
   }];
 
   let arguments = (ins ArrayAttr:$value);
   let results = (outs Complex<AnyFloat>:$complex);
 
   let assemblyFormat = "$value attr-dict `:` type($complex)";
   let hasFolder = 1;
   let hasVerifier = 1;
-  
   let extraClassDeclaration = [{
     /// Returns true if a constant operation can be built with the given value
     /// and result type.
     static bool isBuildableWith(Attribute value, Type type);
   }];
 }
 
 //===----------------------------------------------------------------------===//

mlir/include/mlir/Dialect/GPU/IR/ParallelLoopMapperAttr.td

 
 // Attribute that drives conversion of a scf.parallel to gpu.launch
 // operation.
 // processor: the hardware id to map to.
 // map : An affine map that is used to pre-process hardware ids before
 //       substitution.
 // bound : An affine map that is used to compute the bound of the hardware
 //         id based on an upper bound of the number of iterations.
-def ParallelLoopDimMappingAttr 
+def ParallelLoopDimMappingAttr
     : GPU_Attr<"ParallelLoopDimMapping", "loop_dim_map"> {
   let parameters = (ins
     EnumParameter<ProcessorEnum>:$processor,
     "AffineMap":$map,
     "AffineMap":$bound
   );
   let assemblyFormat = "`<` struct(params) `>`";
 }
 
 def ParallelLoopMappingAttr :
     TypedArrayAttrBase<ParallelLoopDimMappingAttr,
                        "parallel loop to processor mapping attribute">;
 
 #endif // PARALLEL_LOOP_MAPPER_ATTR

mlir/include/mlir/Dialect/GPU/TransformOps/GPUDeviceMappingAttr.td

 //===-- GPUDeviceMappingAttr.td - Attribute definition -----*- tablegen -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
-// Defines the attribute used to map loops to gpu. 
+// Defines the attribute used to map loops to gpu.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef GPU_DEVICE_MAPPING_ATTR
 #define GPU_DEVICE_MAPPING_ATTR
 
 include "mlir/Dialect/GPU/IR/GPUBase.td"
 include "mlir/IR/EnumAttr.td"
 include "mlir/Dialect/SCF/IR/DeviceMappingInterface.td"
 
 def DimX : I64EnumAttrCase<"DimX", 0, "x">;
 def DimY : I64EnumAttrCase<"DimY", 1, "y">;
 def DimZ : I64EnumAttrCase<"DimZ", 2, "z">;
 
 def ThreadsEnum : I64EnumAttr<"Threads", "threads for loop mapping", [
     DimX, DimY, DimZ]> {
   let cppNamespace = "::mlir::gpu";
 }
 
-def GPUThreadMappingAttr 
-    : GPU_Attr<"GPUThreadMapping", "thread", [ 
+def GPUThreadMappingAttr
+    : GPU_Attr<"GPUThreadMapping", "thread", [
       DeclareAttrInterfaceMethods<DeviceMappingAttrInterface> ]> {
   let parameters = (ins
     EnumParameter<ThreadsEnum>:$thread
   );
   let assemblyFormat = "`<` params `>`";
   let description = [{
     An attribute that allows defining thread parallelism for GPU devices.
 
-    Thread (aka work item) are grouped into a thread blocks where block may be 
-    described by a 1-, 2-, or 3-dimensional rectangle. This attribute indicates 
-    that thread parallelism is desired. It can be consumed by lowering to 
+    Thread (aka work item) are grouped into a thread blocks where block may be
+    described by a 1-, 2-, or 3-dimensional rectangle. This attribute indicates
+    that thread parallelism is desired. It can be consumed by lowering to
     generate GPU.
   }];
 }
 
 def BlocksEnum : I64EnumAttr<"Blocks", "threads for loop mapping", [
     DimX, DimY, DimZ]> {
   let cppNamespace = "::mlir::gpu";
 }
 
-def GPUBlockMappingAttr : GPU_Attr<"GPUBlockMapping", "block", [ 
+def GPUBlockMappingAttr : GPU_Attr<"GPUBlockMapping", "block", [
   DeclareAttrInterfaceMethods<DeviceMappingAttrInterface> ] >  {
   let parameters = (ins
     EnumParameter<BlocksEnum>:$block
   );
   let assemblyFormat = "`<` params `>`";
   let description = [{
     An attribute that allows defining thread block parallelism for GPU devices.
 
-    Thread blocks (aka work-group) are grouped into a grid where grid may be 
-    described by a 1-, 2-, or 3-dimensional rectangle. This attribute indicates 
+    Thread blocks (aka work-group) are grouped into a grid where grid may be
+    described by a 1-, 2-, or 3-dimensional rectangle. This attribute indicates
     that thread block parallelism is desired. It can be consumed by lowering to
     generate GPU code.
   }];
 }
 
 #endif // GPU_DEVICE_MAPPING_ATTR

mlir/include/mlir/Dialect/GPU/TransformOps/GPUTransformOps.td

 
 include "mlir/Dialect/Transform/IR/TransformDialect.td"
 include "mlir/Dialect/Transform/IR/TransformEffects.td"
 include "mlir/Dialect/Transform/IR/TransformInterfaces.td"
 include "mlir/Dialect/PDL/IR/PDLTypes.td"
 include "mlir/Interfaces/SideEffectInterfaces.td"
 include "mlir/IR/OpBase.td"
 
-def MapNestedForeachToThreads : 
+def MapNestedForeachToThreads :
   Op<Transform_Dialect, "gpu.map_nested_foreach_to_threads",
-    [FunctionalStyleTransformOpTrait, 
+    [FunctionalStyleTransformOpTrait,
      MemoryEffectsOpInterface,
      TransformEachOpTrait,
      TransformOpInterface]> {
   let description = [{
       Target the `gpu.launch op` and rewrite all `scf.foreach_thread`
       nested in it to distributed `gpu.thread_id` attribute.
 
-      The operation searches for `scf.foreach_thread` ops nested under `target` 
-      and maps each such op to GPU threads. Mapping is one-to-one and the 
-      induction variables of `scf.foreach_thread` are rewritten to 
-      `gpu.thread_id` according to the `mapping` attribute. 
-      
-      Sibling `scf.foreach_thread` are supported in which case, the union of 
+      The operation searches for `scf.foreach_thread` ops nested under `target`
+      and maps each such op to GPU threads. Mapping is one-to-one and the
+      induction variables of `scf.foreach_thread` are rewritten to
+      `gpu.thread_id` according to the `mapping` attribute.
+      Sibling `scf.foreach_thread` are supported in which case, the union of
       the number of threads is computed and may result in predication.
 
-      Multiple scf.foreach_thread are supported per `gpu.launch` in which case, 
-      the max of all the threads is computed and taken for the global 
-      `gpu.thread_id`. If necessary, `scf.foreach_thread` that do not use the 
+      Multiple scf.foreach_thread are supported per `gpu.launch` in which case,
+      the max of all the threads is computed and taken for the global
+      `gpu.thread_id`. If necessary, `scf.foreach_thread` that do not use the
       whole thread range result in predicated computations.
 
-      Dynamic `scf.foreach_thread` trip counts are currently not supported. 
+      Dynamic `scf.foreach_thread` trip counts are currently not supported.
       Dynamic block dim sizes are currently not supported.
 
       Only **bufferized** `scf.foreach_thread` are currently supported.
-      Only `scf.foreach_thread` distributed to **at most 3 dimensions** are 
+      Only `scf.foreach_thread` distributed to **at most 3 dimensions** are
       currently supported.
-    
       Barriers are inserted after each scf.foreach_thread op for now.
 
-      The operation alters the block size of the given gpu_launch using 
+      The operation alters the block size of the given gpu_launch using
       blockDim argument.
 
       #### Return modes:
-      
       This operation ignores non-gpu_launch ops and drops them in the return.
 
-      If any scf.foreach_thread with tensors is found, the transform definitely 
-      fails.    
+      If any scf.foreach_thread with tensors is found, the transform definitely
+      fails.
 
-      If all the scf.foreach_thread operations contained within the LaunchOp 
-      referred to by the `target` PDLOperation lower to GPU properly, the 
+      If all the scf.foreach_thread operations contained within the LaunchOp
+      referred to by the `target` PDLOperation lower to GPU properly, the
       transform succeeds. Otherwise the transform definitely fails.
-      
       The returned handle points to the same LaunchOp operand, consuming it and
-      producing a new SSA value to satisfy chaining and linearity of the IR 
+      producing a new SSA value to satisfy chaining and linearity of the IR
       properties.
 
       #### Example:
 
       ```
       gpu.launch blocks(%bx, %by, %bz) in (%x = %0, %y = %1, %z = %2)
                  threads(%tx, %ty, %tz) in (%tx = %3, %ty = %4, %tz = %5) {
         scf.foreach_thread (%i, %j) in (7, 9) {
let description = [{
           ... // body 1
         }
         gpu.barrier
         if (threadIdx.y < 1) {
           ... // body 2
         }
         gpu.barrier
         gpu.terminator
-      }      
+      }
       ```
     }];
 
   let arguments = (ins PDL_Operation:$target,
                    DefaultValuedAttr<I64ArrayAttr, "{}">:$blockDim,
                    DefaultValuedAttr<BoolAttr, "true">:$syncAfterDistribute);
   let results = (outs PDL_Operation:$result);
 
   let assemblyFormat = "$target attr-dict";
-  let extraClassDeclaration = [{    
+  let extraClassDeclaration = [{
     ::mlir::DiagnosedSilenceableFailure applyToOne(
-        ::mlir::Operation *target, 
-        ::llvm::SmallVectorImpl<::mlir::Operation *> &results, 
+        ::mlir::Operation *target,
+        ::llvm::SmallVectorImpl<::mlir::Operation *> &results,
         ::mlir::transform::TransformState &state);
   }];
 }
 
 
-def MapForeachToBlocks : 
+def MapForeachToBlocks :
   Op<Transform_Dialect, "gpu.map_foreach_to_blocks",
     [FunctionalStyleTransformOpTrait,
      MemoryEffectsOpInterface,
      TransformOpInterface,
      TransformEachOpTrait]> {
   let description = [{
     Target the gpu_launch op and rewrite the top level `scf.foreach_thread`
-    to distributed gpu.block_id attribute. If `generate_gpu_launch` attribute 
-    is set, then first generates `gpu_launch` and moves the top level 
+    to distributed gpu.block_id attribute. If `generate_gpu_launch` attribute
+    is set, then first generates `gpu_launch` and moves the top level
     `scf.foreach_thread` inside.
 
-    The operation searches top level `scf.foreach_thread` ops under 
-    `gpu_launch` and maps each such op to GPU blocks. Mapping is 
-    one-to-one and the induction variables of `scf.foreach_thread` are 
+    The operation searches top level `scf.foreach_thread` ops under
+    `gpu_launch` and maps each such op to GPU blocks. Mapping is
+    one-to-one and the induction variables of `scf.foreach_thread` are
     rewritten to gpu.block_id according to the `thread_dim_apping` attribute.
 
-    Dynamic, `scf.foreach_thread` trip counts are currently not supported. 
+    Dynamic, `scf.foreach_thread` trip counts are currently not supported.
     Dynamic block dim sizes are currently not supported.
 
     Only **bufferized** scf.foreach_thread are currently supported.
-    Only scf.foreach_thread distributed to **at most 3 dimensions** are 
+    Only scf.foreach_thread distributed to **at most 3 dimensions** are
     currently supported.
 
-    The operation alters the block size of the given gpu_launch using 
+    The operation alters the block size of the given gpu_launch using
     gridDim argument.
 
     #### Return modes:
-    
     This operation ignores non-gpu_launch ops and drops them in the return.
 
-    If any scf.foreach_thread with tensors is found, the transform definitely 
-    fails.    
+    If any scf.foreach_thread with tensors is found, the transform definitely
+    fails.
 
-    If all the scf.foreach_thread operations contained within the LaunchOp 
-    referred to by the `target` PDLOperation lower to GPU properly, the 
+    If all the scf.foreach_thread operations contained within the LaunchOp
+    referred to by the `target` PDLOperation lower to GPU properly, the
     transform succeeds. Otherwise the transform definitely fails.
 
     The returned handle points to the same LaunchOp operand, consuming it and
-    producing a new SSA value to satisfy chaining and linearity of the IR 
+    producing a new SSA value to satisfy chaining and linearity of the IR
     properties.
   }];
 
   let arguments = (ins PDL_Operation:$target,
                    DefaultValuedAttr<I64ArrayAttr, "{}">:$gridDim,
                    UnitAttr:$generate_gpu_launch);
   let results = (outs PDL_Operation:$result);
 
   let assemblyFormat = "$target attr-dict";
   let extraClassDeclaration = [{
     ::mlir::DiagnosedSilenceableFailure applyToOne(
-        ::mlir::Operation *target, 
-        ::llvm::SmallVectorImpl<::mlir::Operation *> &results, 
+        ::mlir::Operation *target,
+        ::llvm::SmallVectorImpl<::mlir::Operation *> &results,
         ::mlir::transform::TransformState &state);
   }];
 }
 
 #endif // GPU_TRANSFORM_OPS

mlir/include/mlir/Dialect/LLVMIR/LLVMEnums.td

 def DISubprogramFlags : I32BitEnumAttr<
     "DISubprogramFlags",
     "LLVM DISubprogram flags", [
       LLVM_DISPVirtual,
       LLVM_DISPPureVirtual,
       LLVM_DISPLocalToUnit,
       LLVM_DISPDefinition,
       LLVM_DISPOptimized,
-      LLVM_DISPPure, 
+      LLVM_DISPPure,
       LLVM_DISPElemental,
       LLVM_DISPRecursive,
       LLVM_DISPMainSubprogram,
       LLVM_DISPDeleted,
       LLVM_DISPObjCDirect
     ]> {
   let cppNamespace = "::mlir::LLVM";
   let printBitEnumPrimaryGroups = 1;

mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td

let extraClassDeclaration = [{
     static StringRef getReqntidXName() { return "reqntidx"; }
     static StringRef getReqntidYName() { return "reqntidy"; }
     static StringRef getReqntidZName() { return "reqntidz"; }
 
     /// Get the name of the attribute used to annotate min CTA required
     /// per SM for kernel functions.
     static StringRef getMinctasmAttrName() { return "nvvm.minctasm"; }
 
-    /// Get the name of the attribute used to annotate max number of 
+    /// Get the name of the attribute used to annotate max number of
     /// registers that can be allocated per thread.
     static StringRef getMaxnregAttrName() { return "nvvm.maxnreg"; }
   }];
 
   let useDefaultAttributePrinterParser = 1;
 }
 
 //===----------------------------------------------------------------------===//

mlir/include/mlir/Dialect/Linalg/TransformOps/LinalgTransformOps.td

def DecomposeOp : Op<Transform_Dialect, "structured.decompose",
     [FunctionalStyleTransformOpTrait, MemoryEffectsOpInterface,
      TransformOpInterface, TransformEachOpTrait]> {
   let description = [{
     Decomposes named complex operations, such as higher-dimensional
     (depthwise) convolutions, into combinations of lower-dimensional equivalents
     when possible.
 
     #### Return modes
-    
     This operation ignores non-Linalg ops and drops them in the return.
     If all the operations referred to by the `target` PDLOperation decompose
     properly, the transform succeeds. Otherwise the transform silently fails.
-    The return handle points to only the subset of successfully produced 
+    The return handle points to only the subset of successfully produced
     computational operations, which can be empty.
   }];
 
   let arguments = (ins PDL_Operation:$target);
   let results = (outs PDL_Operation:$transformed);
   let assemblyFormat = "$target attr-dict";
 
   let extraClassDeclaration = [{
     ::mlir::DiagnosedSilenceableFailure applyToOne(
-        ::mlir::linalg::LinalgOp target, 
-        ::llvm::SmallVectorImpl<::mlir::Operation *> &results, 
+        ::mlir::linalg::LinalgOp target,
+        ::llvm::SmallVectorImpl<::mlir::Operation *> &results,
         ::mlir::transform::TransformState &state);
   }];
 }
 
 def FuseOp : Op<Transform_Dialect, "structured.fuse",
     [FunctionalStyleTransformOpTrait, MemoryEffectsOpInterface,
      DeclareOpInterfaceMethods<TransformOpInterface>]> {
   let description = [{
let description = [{
     The producer is typically a slice of a tileable op (i.e., implements
     TilingInterface). In that case, this transform computes the accessed
     producer slice inside of the containing op ("tile and fuse"). Otherwise,
     the entire producer is cloned inside the containing op ("clone and fuse").
 
     The containing op handle must be associated with exactly one payload op. The
     producer op handle may be associated with multiple payload ops. This
     transform fuses producers one-by-one, always picking an unspecified producer
-    that has at least one use inside the containing op among the 
+    that has at least one use inside the containing op among the
     producers.
 
     Note: If a producer has multiple uses inside the containing op, it is
     currently tiled and/or cloned multiple times into the containing op.
     TODO: Reuse already fused OpResults instead of tiling/cloning a second time
     when possible. Fuse producers according to a topological sorting to achieve
     the largest amount of reuse.
 
def FuseIntoContainingOp :
   ];
 }
 
 def GeneralizeOp : Op<Transform_Dialect, "structured.generalize",
     [FunctionalStyleTransformOpTrait, MemoryEffectsOpInterface,
      TransformOpInterface, TransformEachOpTrait]> {
   let description = [{
     Transforms a named structured operation into the generic form with the
-    explicit attached region. 
-    
+    explicit attached region.
     #### Return modes
-    
     This operation ignores non-Linalg ops and drops them in the return.
     If all the operations referred to by the `target` PDLOperation generalize
     properly, the transform succeeds. Otherwise the transform silently fails.
-    The return handle points to only the subset of successfully produced 
+    The return handle points to only the subset of successfully produced
     equivalent generic operations, which can be empty or contain the original
     ops if they were already in generic form.
   }];
 
   let arguments = (ins PDL_Operation:$target);
   let results = (outs PDL_Operation:$transformed);
   let assemblyFormat = "$target attr-dict";
 
   let extraClassDeclaration = [{
     ::mlir::DiagnosedSilenceableFailure applyToOne(
-        ::mlir::linalg::LinalgOp target, 
-        ::llvm::SmallVectorImpl<::mlir::Operation *> &results, 
+        ::mlir::linalg::LinalgOp target,
+        ::llvm::SmallVectorImpl<::mlir::Operation *> &results,
         ::mlir::transform::TransformState &state);
   }];
 }
 
 def InterchangeOp : Op<Transform_Dialect, "structured.interchange",
     [FunctionalStyleTransformOpTrait, MemoryEffectsOpInterface,
     TransformOpInterface, TransformEachOpTrait]> {
   let description = [{
     Interchanges the iterators of the operations pointed to by the target handle
     using the iterator interchange attribute.
 
     #### Return modes
-    
     This operation ignores non-linalg::Generic ops and drops them in the return.
     This operation fails if the interchange attribute is invalid.
     If all the operations referred to by the `target` PDLOperation interchange
-    properly, the transform succeeds. 
+    properly, the transform succeeds.
     If any interchange fails, the transform definitely fails.
-    The return handle points to only the subset of successfully produced 
+    The return handle points to only the subset of successfully produced
     interchanged operations, which can be empty.
   }];
 
   let arguments =
     (ins PDL_Operation:$target,
          DefaultValuedAttr<I64ArrayAttr, "{}">:$iterator_interchange);
   let results = (outs PDL_Operation:$transformed);
 
   let assemblyFormat = "$target attr-dict";
   let hasVerifier = 1;
 
   let extraClassDeclaration = [{
     ::mlir::DiagnosedSilenceableFailure applyToOne(
-        ::mlir::linalg::GenericOp target, 
-        ::llvm::SmallVectorImpl<::mlir::Operation *> &results, 
+        ::mlir::linalg::GenericOp target,
+        ::llvm::SmallVectorImpl<::mlir::Operation *> &results,
         ::mlir::transform::TransformState &state);
   }];
 }
 
 def MatchInterfaceEnum : I32EnumAttr<"MatchInterfaceEnum", "An interface to match",
     [
       I32EnumAttrCase<"LinalgOp", 0>,
       I32EnumAttrCase<"TilingInterface", 1>
The following constraints are supported:
       - interface: an optional MatchInterfaceEnum specifying an enum
         representation for an interface to target.
       - ops: an optional StrArrayAttr specifying the concrete name of an op.
         Multiple names can be specified. Matched ops must have one of specified
         names.
       - attribute: the matched op must have all specified attributes (with their
         specified values).
       - filter_result_type: the matched op must return exactly this one type.
-      
     Note: Only ops that satisfy all specified constraints are matched.
 
     TODO: Extend with regions to allow a limited form of constraints.
 
     #### Return modes
 
     This op traverses the ops nested under `target` and returns the handles to
     all the operations that match the requirements.
 
-    This op fails if the target is not a handle to exactly one operation. 
+    This op fails if the target is not a handle to exactly one operation.
     Otherwise it succeeds.
 
     This operation does not consume the target handle and produces new handles:
     it is a navigation op.
   }];
 
   let arguments = (ins PDL_Operation:$target,
                        OptionalAttr<StrArrayAttr>:$ops,
let arguments = (ins PDL_Operation:$target,
                        DefaultValuedAttr<I64Attr, "1">:$divisor);
   let results = (outs PDL_Operation:$low_size,
                       PDL_Operation:$high_size,
                       PDL_Operation:$split_point);
   let assemblyFormat = "$target attr-dict";
 
   let extraClassDeclaration = [{
     ::mlir::DiagnosedSilenceableFailure applyToOne(
-        ::mlir::linalg::LinalgOp target, 
+        ::mlir::linalg::LinalgOp target,
         ::llvm::SmallVector<::mlir::Operation *> &results,
         TransformState &state);
   }];
 }
 
 def PadOp : Op<Transform_Dialect, "structured.pad",
     [FunctionalStyleTransformOpTrait, MemoryEffectsOpInterface,
      TransformOpInterface, TransformEachOpTrait]> {
   let description = [{
     Pads the operations pointed to by the target handle using the options
     provides as operation attributes.
 
     #### Return modes
-    
     This operation ignores non-Linalg ops and drops them in the return.
     This operation may produce a definiteFailure if the padding fails for any
     reason.
     If all the operations referred to by the `target` PDLOperation pad
     properly, the transform succeeds. Otherwise the transform silently fails.
-    The return handle points to only the subset of successfully produced 
+    The return handle points to only the subset of successfully produced
     padded operations, which can be empty.
   }];
 
   let arguments =
     (ins PDL_Operation:$target,
          DefaultValuedAttr<ArrayAttr, "{}">:$padding_values,
          DefaultValuedAttr<I64ArrayAttr, "{}">:$padding_dimensions,
          DefaultValuedAttr<I64ArrayAttr, "{}">:$pack_paddings,
          DefaultValuedAttr<I64ArrayAttr, "{}">:$hoist_paddings,
          DefaultValuedAttr<
           TypedArrayAttrBase<I64ArrayAttr, "array of arrays of i64">,
           "{}">:$transpose_paddings);
   let results = (outs PDL_Operation:$transformed);
 
   let assemblyFormat = "$target attr-dict";
   let hasVerifier = 1;
 
   let extraClassDeclaration = [{
     ::mlir::DiagnosedSilenceableFailure applyToOne(
-        ::mlir::linalg::LinalgOp target, 
-        ::llvm::SmallVectorImpl<::mlir::Operation *> &results, 
+        ::mlir::linalg::LinalgOp target,
+        ::llvm::SmallVectorImpl<::mlir::Operation *> &results,
         ::mlir::transform::TransformState &state);
   }];
 }
 
 def PromoteOp : Op<Transform_Dialect, "structured.promote",
     [FunctionalStyleTransformOpTrait, MemoryEffectsOpInterface,
     TransformOpInterface, TransformEachOpTrait]> {
   let description = [{
     Promotes the specified operands of the target into a separate memory buffer.
 
-    At this point, this transform does not allow customizing alloc/dealloc 
+    At this point, this transform does not allow customizing alloc/dealloc
     functions nor the behavior on copy in/out operations.
 
     #### Return modes
-    
-    This operation applies to a single Linalg op that satisfies the 
+    This operation applies to a single Linalg op that satisfies the
     `promoteSubviewsPrecondition`, otherwise it fails.
-    
     If the operations referred to by the `target` PDLOperation promote
-    properly, the transform succeeds. 
+    properly, the transform succeeds.
 
-    When successful, the return handle points to the $target operation that 
+    When successful, the return handle points to the $target operation that
     was modified inplace.
   }];
 
   let arguments = (ins PDL_Operation:$target,
                        DefaultValuedAttr<I64ArrayAttr, "{}">:$operands_to_promote,
                        DefaultValuedAttr<BoolArrayAttr, "{}">:$use_full_tile_buffers,
                        UnitAttr:$use_full_tiles_by_default,
                        UnitAttr:$use_alloca,
                        OptionalAttr<I64Attr>:$alignment);
   let results = (outs PDL_Operation:$transformed);
 
   let assemblyFormat = "$target attr-dict";
 
   let extraClassDeclaration = [{
     ::mlir::DiagnosedSilenceableFailure applyToOne(
-        ::mlir::linalg::LinalgOp target, 
-        ::llvm::SmallVectorImpl<::mlir::Operation *> &results, 
+        ::mlir::linalg::LinalgOp target,
+        ::llvm::SmallVectorImpl<::mlir::Operation *> &results,
         ::mlir::transform::TransformState &state);
   }];
 }
 
 def ScalarizeOp : Op<Transform_Dialect, "structured.scalarize",
     [FunctionalStyleTransformOpTrait, MemoryEffectsOpInterface,
      TransformOpInterface, TransformEachOpTrait]> {
   let description = [{
     Indicates that ops of a specific kind in the given function should be
     scalarized (i.e. their dynamic dimensions tiled by 1).
 
     #### Return modes:
-    
     This operation ignores non-Linalg ops and drops them in the return.
     This operation produces `definiteFailure` if the scalarization fails for any
     reason.
     If all the operations referred to by the `target` PDLOperation scalarize
     properly, the transform succeeds. Otherwise the transform silently fails.
 
-    The return handle points to only the subset of successfully produced 
+    The return handle points to only the subset of successfully produced
     tiled-by-1 operations, which can be empty.
 
     This operation does not return handles to the tiled loop.
     We make this design choice because it is hard to know ahead of time the
     number of loops that will be produced (it depends on the number of dynamic
     dimensions after multiple transformations have been applied).
     Loops can always be recovered by navigating from the tiled operations if
     needed.
   }];
 
   let arguments = (ins PDL_Operation:$target);
   let results = (outs PDL_Operation:$result);
 
   let assemblyFormat = "$target attr-dict";
 
   let extraClassDeclaration = [{
     ::mlir::DiagnosedSilenceableFailure applyToOne(
-        ::mlir::linalg::LinalgOp target, 
-        ::llvm::SmallVectorImpl<::mlir::Operation *> &results, 
+        ::mlir::linalg::LinalgOp target,
+        ::llvm::SmallVectorImpl<::mlir::Operation *> &results,
         ::mlir::transform::TransformState &state);
   }];
 }
 
 def SplitOp : Op<Transform_Dialect, "structured.split",
     [DeclareOpInterfaceMethods<MemoryEffectsOpInterface>,
      DeclareOpInterfaceMethods<TransformOpInterface>]> {
   let description = [{
def SplitOp : Op<Transform_Dialect, "structured.split",
   let hasVerifier = 1;
   let hasCustomAssemblyFormat = 1;
 }
 
 def SplitReductionOp : Op<Transform_Dialect, "structured.split_reduction",
        [FunctionalStyleTransformOpTrait, MemoryEffectsOpInterface,
         TransformEachOpTrait, TransformOpInterface]> {
   let description = [{
-    Indicates that the given `target` op should be transformed with the 
+    Indicates that the given `target` op should be transformed with the
     `splitReduction` transformation and split factor provided as attribute.
 
-    The `splitReduction` transformation splits the first single linalg op 
-    reduction into a parallel and reduction dimension. 
-    A new `linalg.generic` op is created to perform the rest of the reduction. 
-    
+    The `splitReduction` transformation splits the first single linalg op
+    reduction into a parallel and reduction dimension.
+    A new `linalg.generic` op is created to perform the rest of the reduction.
     The transformation supports different configurations attributes:
-      - split_factor: the factor by which to split (i.e. the size of the 
+      - split_factor: the factor by which to split (i.e. the size of the
         remaining reduction after splitting).
-      - insert_split_dimension: the dimension in the temporary tensor into 
+      - insert_split_dimension: the dimension in the temporary tensor into
         which the new parallel dimension is inserted.
       - inner_parallel: specifies whether the parallel dimension is before or
         after the reduction dimension in the splitting op.
-      - use_scaling_algorithm: whether to use a scaling based formulation that 
+      - use_scaling_algorithm: whether to use a scaling based formulation that
         does not create an ExpandShapeOp (default: do not use scaling)
-      - use_alloc: whether to use an alloc op to allocate the temporary 
+      - use_alloc: whether to use an alloc op to allocate the temporary
         tensor (default: do not use alloc op)
 
     #### Return modes
-    
     This operation ignores non-Linalg ops and drops them in the return.
     This operation produces `definiteFailure` if the splitting fails for any
     reason.
 
     If all the operations referred to by the `target` PDLOperation split
     properly, the transform succeeds. Otherwise the transform silently fails.
-    The 4 returned handles points to only the subset of successfully produced 
+    The 4 returned handles points to only the subset of successfully produced
     computational operations, which can all be empty.
     This 4 returned handles point to:
-      - the init op (or tensor_alloc op if use_alloc = true), 
-      - the fill op used to initialize the neutral element, 
-      - the split op and 
+      - the init op (or tensor_alloc op if use_alloc = true),
+      - the fill op used to initialize the neutral element,
+      - the split op and
       - the result-combining op.
 
     #### Example (default: `use_scaling_algorithm = false, use_alloc = false`):
-    
     ```
       %r = linalg.generic {indexing_maps = [affine_map<(d0) -> (d0)>,
                                             affine_map<(d0) -> ()>],
             iterator_types = ["reduction"]}
       ins(%in : tensor<32xf32>)
       outs(%out : tensor<f32>) {
       ^bb0(%arg1: f32, %arg2: f32):
         %y = arith.addf %arg1, %arg2 : f32
         linalg.yield %y : f32
       } -> tensor<f32>
     ```
-    
     is split into:
-    
     ```
       %cst = arith.constant 0.000000e+00 : f32
       %0 = tensor.expand_shape %in [[0, 1]] : tensor<32xf32> into tensor<4x8xf32>
       %1 = tensor.empty() : tensor<4xf32>
       %2 = linalg.fill ins(%cst : f32) outs(%1 : tensor<4xf32>) -> tensor<4xf32>
       %3 = linalg.generic {indexing_maps = [affine_map<(d0, d1) -> (d0, d1)>,
                                             affine_map<(d0, d1) -> (d0)>],
         iterator_types = ["parallel", "reduction"]}
         ins(%0 : tensor<4x8xf32>) outs(%2 : tensor<4xf32>) {
         ^bb0(%arg3: f32, %arg5: f32):
         %5 = arith.addf %arg3, %arg4 : f32
         linalg.yield %5 : f32
       } -> tensor<4xf32>
       %r = linalg.generic {indexing_maps = [affine_map<(d0) -> (d0)>,
                                             affine_map<(d0) -> ()>],
         iterator_types = ["reduction"]}
         ins(%3 : tensor<4xf32>) outs(%out : tensor<f32>) {
         ^bb0(%arg3: f32, %arg4: f32):
         %5 = arith.addf %arg3, %arg4 : f32
         linalg.yield %5 : f32
       } -> tensor<f32>
     ```
 
     #### Example (`use_scaling_algorithm = true, use_alloc = true`):
-    
-    Instead of introducing an ExpandShapeOp, this scaling-based implementation 
+    Instead of introducing an ExpandShapeOp, this scaling-based implementation
     rewrites a reduction dimension `k` into `k * split_factor + kk`.
-    The dimension `kk` is added as an extra parallel dimension to the 
+    The dimension `kk` is added as an extra parallel dimension to the
     intermediate output tensor at position `insert_split_dimension`.
 
-    Consider a minimal example where `k` is reduced: 
+    Consider a minimal example where `k` is reduced:
         O(i, j) += I(i, j, k)
     Assume i=3, j=5, k=128, split_factor=16 and insert_split_dimension=0.
-    The compute is rewritten as: 
+    The compute is rewritten as:
       a. O_i(kk, i, j) += I(i, j, 16 * k + kk)
       b. O(i, j) += O_i(kk, i, j)
     The intermediate tensor O_i is of shape (128/16)x3x5 == 8x3x5.
 
     #### Example:
 
     ```
      %0 = linalg.matmul ins(%A, %B: tensor<16x256xf32>, tensor<256x32xf32>)
OpBuilder<(ins "Value":$target,
                    "int64_t":$insertSplitDimension,
                    CArg<"bool", "false">:$innerParallel,
                    CArg<"bool", "false">:$useScalingAlgorithm,
                    CArg<"bool", "false">:$useAlloc)>
   ];
 
   let extraClassDeclaration = [{
     ::mlir::DiagnosedSilenceableFailure applyToOne(
-        ::mlir::linalg::LinalgOp target, 
-        ::llvm::SmallVectorImpl<::mlir::Operation *> &results, 
+        ::mlir::linalg::LinalgOp target,
+        ::llvm::SmallVectorImpl<::mlir::Operation *> &results,
         ::mlir::transform::TransformState &state);
   }];
 }
 
 def TileReductionUsingScfOp : Op<Transform_Dialect, "structured.tile_reduction_using_scf",
        [FunctionalStyleTransformOpTrait, MemoryEffectsOpInterface,
         TransformEachOpTrait, TransformOpInterface]> {
   let description = [{
-    Indicates that the given `target` op should be transformed with the 
+    Indicates that the given `target` op should be transformed with the
     `tileReduction` transformation with the tile size provided as attribute.
-    
     This transformation tiles the `target` along the reduction dimensions. It
     creates a tensor initialized with the identity value. Then it creates nested
     loops with a parallel version of `target` op inside. The parallel op
     dimensions are less or equal to the tile size passed by user.
     After the loop a merge operation is created to do a final reduction with the
     partial reductions.
     The initial tensor always uses the tile size dimension. This may overallocate
     if the tile size is greater than the reduction dimension.
 
     #### Return modes
 
     This 3 returned handles point to:
-      - the fill op used to initialize the neutral element, 
-      - the parallel tiled op and 
+      - the fill op used to initialize the neutral element,
+      - the parallel tiled op and
       - the result-combining op.
 
     #### Example:
-    
     ```
       %red = linalg.generic {indexing_maps = [affine_map<(d0, d1) -> (d0, d1)>,
                                               affine_map<(d0, d1) -> (d0)>],
       iterator_types = ["parallel", "reduction"]}
       ins(%arg0 : tensor<?x?xf32>)
       outs(%out : tensor<?xf32>) {
         ^bb0(%arg7: f32, %arg9: f32):
         %1 = arith.addf %arg7, %arg9 : f32
         linalg.yield %1 : f32
       } -> tensor<?xf32>
       return %red : tensor<?xf32>
     ```
-  
     is transformed into:
-    
     ```
       %0 = tensor.empty(%dim_1) : tensor<?x5xf32>
       %1 = linalg.fill ins(%cst : f32) outs(%0 : tensor<?x5xf32>) -> tensor<?x5xf32>
       %2 = scf.for %arg2 = %c0 to %dim_0 step %c5 iter_args(%arg3 = %1) -> (tensor<?x5xf32>) {
         %extracted_slice = tensor.extract_slice %1[0, 0] [%dim, 5] [1, 1] : tensor<?x5xf32> to tensor<?x5xf32>
         %extracted_slice_2 = tensor.extract_slice %arg0[0, %arg2] [%dim, 5] [1, 1] : tensor<?x?xf32> to tensor<?x5xf32>
-        %4 = linalg.generic {indexing_maps = [affine_map<(d0, d1) -> (d0, d1)>, 
+        %4 = linalg.generic {indexing_maps = [affine_map<(d0, d1) -> (d0, d1)>,
                                               affine_map<(d0, d1) -> (d0, d1)>],
         iterator_types = ["parallel", "parallel"]}
         ins(%extracted_slice_2 : tensor<?x5xf32>)
         outs(%extracted_slice : tensor<?x5xf32>) {
         ^bb0(%in: f32, %out: f32):
           %5 = arith.addf %in, %out : f32
           linalg.yield %5 : f32
         } -> tensor<?x5xf32>
def TileReductionUsingScfOp : Op<Transform_Dialect, "structured.tile_reduction_using_scf",
   let results = (outs PDL_Operation:$fill_op,
                       PDL_Operation:$split_linalg_op,
                       PDL_Operation:$combining_linalg_op);
 
   let assemblyFormat = "$target attr-dict";
 
   let extraClassDeclaration = [{
     ::mlir::DiagnosedSilenceableFailure applyToOne(
-        ::mlir::linalg::LinalgOp target, 
-        ::llvm::SmallVectorImpl<::mlir::Operation *> &results, 
+        ::mlir::linalg::LinalgOp target,
+        ::llvm::SmallVectorImpl<::mlir::Operation *> &results,
         ::mlir::transform::TransformState &state);
   }];
 }
 
-def TileReductionUsingForeachThreadOp : 
+def TileReductionUsingForeachThreadOp :
   Op<Transform_Dialect, "structured.tile_reduction_using_foreach_thread",
        [FunctionalStyleTransformOpTrait, MemoryEffectsOpInterface,
         TransformEachOpTrait, TransformOpInterface]> {
   let description = [{
     Tile a PartialReductionOpInterface op to a tiled `scf.foreach_thread` doing
     partial reduction.
 
     This transformation tiles the `target` along the reduction dimensions. It
     creates a tensor initialized with the identity value. Then it creates a
     `scf.foreach_thread` loops with the number threads given by `num_threads`.
     The op is tiled op with a size equal to `floordiv(size, num_threads)`.
     All the partial reduction value is are parallel inserted to create a new
     tensor. After the loop a merge operation is created to do a final reduction
     with the partial reductions tensor.
-    
     #### Return modes
 
     This 3 returned handles point to:
-      - the fill op used to initialize the neutral element, 
-      - the parallel tiled op and 
+      - the fill op used to initialize the neutral element,
+      - the parallel tiled op and
       - the result-combining op.
 
     #### Example:
-    
     ```
       %red = linalg.generic {indexing_maps = [affine_map<(d0, d1) -> (d0, d1)>,
                                               affine_map<(d0, d1) -> (d0)>],
       iterator_types = ["parallel", "reduction"]}
       ins(%arg0 : tensor<?x?xf32>)
       outs(%out : tensor<?xf32>) {
         ^bb0(%arg7: f32, %arg9: f32):
         %1 = arith.addf %arg7, %arg9 : f32
         linalg.yield %1 : f32
       } -> tensor<?xf32>
       return %red : tensor<?xf32>
     ```
-  
     is transformed into:
-    
     ```
       %0 = tensor.empty(%dim_1) : tensor<?x5xf32>
       %1 = linalg.fill ins(%cst : f32) outs(%0 : tensor<?x5xf32>) -> tensor<?x5xf32>
       %2 = scf.foreach_thread (%arg2) in (%c5) shared_outs(%arg3 = %1) -> (tensor<?x5xf32>) {
         %4 = affine.min #map(%arg2)[%dim_0]
         %5 = affine.max #map1(%4)
         %extracted_slice = tensor.extract_slice %arg3[0, %arg2] [%dim, 1] [1, 1] : tensor<?x5xf32> to tensor<?xf32>
         %6 = affine.apply #map2(%arg2)[%dim_0]
def TileReductionUsingForeachThreadOp :
   let results = (outs PDL_Operation:$fill_op,
                       PDL_Operation:$split_linalg_op,
                       PDL_Operation:$combining_linalg_op);
 
   let assemblyFormat = "$target attr-dict";
 
   let extraClassDeclaration = [{
     ::mlir::DiagnosedSilenceableFailure applyToOne(
-        ::mlir::linalg::LinalgOp target, 
-        ::llvm::SmallVectorImpl<::mlir::Operation *> &results, 
+        ::mlir::linalg::LinalgOp target,
+        ::llvm::SmallVectorImpl<::mlir::Operation *> &results,
         ::mlir::transform::TransformState &state);
   }];
 }
 
 def TileOp : Op<Transform_Dialect, "structured.tile",
        [DeclareOpInterfaceMethods<TransformOpInterface>,
         DeclareOpInterfaceMethods<MemoryEffectsOpInterface>]> {
   let description = [{
let description = [{
     `num_threads` and `tile_size` can be either static index attributes or SSA
     values of PDL operation handle type (or a mix thereof). Operation handles
     must be mapped to exactly one op that has exactly one result of index type.
 
     Static zero tile sizes indicate that the dimension is not tiled and can be
     thought of as tiling by the full size of data.
 
     It is the user's responsibility to ensure that `num_threads/tile_sizes` is
-    a valid tiling specification (i.e. that only tiles parallel dimensions, 
+    a valid tiling specification (i.e. that only tiles parallel dimensions,
     e.g. in the Linalg case).
 
     If non-empty, the `mapping` is added as an attribute to the
     resulting `scf.foreach_thread`.
 
     Note: `tile_sizes` and `num_threads` are variadic. Each tile size/number of
     threads can be an index attribute or a transform handle that is mapped to
     exactly one payload op with exactly one index result.
 
     #### Return modes
 
     This operation ignores ops that do not implement the TilingInterface and
     drops them in the return.
 
     If all the operations referred to by the `target` PDLOperation tile
     successfully, the transform succeeds.
     Otherwise the transform silently fails.
-    
     The two returned handles point to only the subset of successfully produced
     tiled operations, which can all be empty.
-    
     These two returned handles point to:
       - the new scf.foreach_thread op,
       - the tiled op that implements TilingInterface.
 
     #### Example using `num_threads`
 
     ```
     %0 = pdl_match @match_matmul in %arg1
let arguments = (ins PDL_Operation:$target,
                    DefaultValuedOptionalAttr<DenseI64ArrayAttr, "{}">:$static_tile_sizes,
                    OptionalAttr<DeviceMappingArrayAttr>:$mapping);
   let results = (outs PDL_Operation:$foreach_thread_op,
                       PDL_Operation:$tiled_op);
 
   let builders = [
     OpBuilder<(ins "Value":$target,
                    "ArrayRef<int64_t>":$staticTileSizes,
-                   CArg<"::mlir::transform::TileSizesSpec", 
+                   CArg<"::mlir::transform::TileSizesSpec",
                         "::mlir::transform::TileSizesSpec()">,
                    CArg<"ArrayAttr", "{}">:$mapping)>,
     OpBuilder<(ins "Value":$target,
                    "ArrayRef<OpFoldResult>":$mixedTileSizes,
-                   CArg<"::mlir::transform::TileSizesSpec", 
+                   CArg<"::mlir::transform::TileSizesSpec",
                         "::mlir::transform::TileSizesSpec()">,
                    CArg<"ArrayAttr", "{}">:$mapping)>,
     OpBuilder<(ins "Value":$target,
                    "ArrayRef<int64_t>":$staticNumThreads,
-                   CArg<"::mlir::transform::NumThreadsSpec", 
+                   CArg<"::mlir::transform::NumThreadsSpec",
                         "::mlir::transform::NumThreadsSpec()">,
                    CArg<"ArrayAttr", "{}">:$mapping)>,
     OpBuilder<(ins "Value":$target,
                    "ArrayRef<OpFoldResult>":$mixedNumThreads,
-                   CArg<"::mlir::transform::NumThreadsSpec", 
+                   CArg<"::mlir::transform::NumThreadsSpec",
                         "::mlir::transform::NumThreadsSpec()">,
                    CArg<"ArrayAttr", "{}">:$mapping)>
   ];
 
   let assemblyFormat = [{
     $target oilist(
         `num_threads` custom<DynamicIndexList>($num_threads,
                                                $static_num_threads) |
let description = [{
     function, performing the transformation, and inlining it back. This
     transformation only fails if the entire pattern rewriting failed, i.e., it
     does **not** fail when no ops were vectorized.
 
     Note that this transformation is invalidating the handles to any payload IR
     operation that is contained inside the vectorization target.
 
     This transformation supports the following attributes:
-      - `vectorize_padding`: a UnitAttr to activate the vectorization of 
-      `tensor.pad` ops. Different pipelines may prefer to lower such ops to 
+      - `vectorize_padding`: a UnitAttr to activate the vectorization of
+      `tensor.pad` ops. Different pipelines may prefer to lower such ops to
       loops.
       - `disable_multi_reduction_to_contract_patterns`: a UnitAttr to deactivate
-      the rewrite of `vector.multi_reduction` to `vector.contract`. This is 
+      the rewrite of `vector.multi_reduction` to `vector.contract`. This is
       intended to be used in tests only.
       - `disable_transfer_permutation_map_lowering_patterns`: a UnitAttr to
       deactivate the rewrite of `vector.transfer` with permutation maps into
       explicit `vector.transpose` operations. This is intended to be used in
       tests only but may be promotoed to a first class attribute in the future.
 
     #### Return modes:
-    
     This operation produces `definiteFailure` if vectorization fails for any
     reason.
-    The operation always returns the handle to the target op that is expected 
+    The operation always returns the handle to the target op that is expected
     to be isolated from above.
   }];
 
   let arguments = (ins PDL_Operation:$target,
-                   UnitAttr:$vectorize_padding,                   
-                   UnitAttr:$disable_multi_reduction_to_contract_patterns,                   
+                   UnitAttr:$vectorize_padding,
+                   UnitAttr:$disable_multi_reduction_to_contract_patterns,
                    UnitAttr:$disable_transfer_permutation_map_lowering_patterns);
   let results = (outs PDL_Operation:$transformed);
 
   let assemblyFormat = "$target attr-dict";
 
   let builders = [
     OpBuilder<(ins "Value":$target, CArg<"bool", "false">:$vectorizePadding)>
   ];
   let extraClassDeclaration = [{
     ::mlir::DiagnosedSilenceableFailure applyToOne(
-        ::mlir::Operation *target, 
-        ::llvm::SmallVectorImpl<::mlir::Operation *> &results, 
+        ::mlir::Operation *target,
+        ::llvm::SmallVectorImpl<::mlir::Operation *> &results,
         ::mlir::transform::TransformState &state);
   }];
 }
 
 #endif // LINALG_TRANSFORM_OPS

mlir/include/mlir/Dialect/NVGPU/IR/NVGPU.td

 include "mlir/Interfaces/SideEffectInterfaces.td"
 include "mlir/IR/AttrTypeBase.td"
 include "mlir/IR/OpBase.td"
 
 def NVGPU_Dialect : Dialect {
   let name = "nvgpu";
   let cppNamespace = "::mlir::nvgpu";
   let description = [{
-    The `NVGPU` dialect provides a bridge between higher-level target-agnostic 
-    dialects (GPU and Vector) and the lower-level target-specific dialect 
-    (LLVM IR based NVVM dialect) for NVIDIA GPUs. This allow representing PTX 
-    specific operations while using MLIR high level dialects such as Memref 
+    The `NVGPU` dialect provides a bridge between higher-level target-agnostic
+    dialects (GPU and Vector) and the lower-level target-specific dialect
+    (LLVM IR based NVVM dialect) for NVIDIA GPUs. This allow representing PTX
+    specific operations while using MLIR high level dialects such as Memref
     and Vector for memory and target-specific register operands, respectively.
   }];
 
   let useDefaultTypePrinterParser = 1;
 }
 
 //===----------------------------------------------------------------------===//
 // NVGPU Type Definitions
 //===----------------------------------------------------------------------===//
 
 class NVGPU_Type<string name, string typeMnemonic,
         list<Trait> traits = []> : TypeDef<NVGPU_Dialect, name, traits> {
   let mnemonic = typeMnemonic;
 }
 
-def NVGPU_DeviceAsyncToken : NVGPU_Type<"DeviceAsyncToken",  
+def NVGPU_DeviceAsyncToken : NVGPU_Type<"DeviceAsyncToken",
                                         "device.async.token", []> {
   let summary = "device async token type";
   let description = [{
     `nvgpu.device.async.token` is a type returned by an asynchronous operation
     that runs on the GPU (device). It is used to establish an SSA-based link
     between the async operation (e.g. DeviceAsyncCopy) and operations that
     group or synchronize the async operations (e.g. DeviceAsyncCreateGroupOp,
     DeviceAsyncWaitOp).
   }];
 }
 
 //===----------------------------------------------------------------------===//
 // NVGPU Op Definitions
 //===----------------------------------------------------------------------===//
 
 class NVGPU_Op<string mnemonic, list<Trait> traits = []> :
   Op<NVGPU_Dialect, mnemonic, traits> {}
 
 def NVGPU_LdMatrixOp : NVGPU_Op<"ldmatrix", [
                                 MemoryEffects<[MemRead]>,
-                                PredOpTrait<"srcMemref and res have same element type", 
+                                PredOpTrait<"srcMemref and res have same element type",
                                             TCresVTEtIsSameAsOp<0, 0>>]> {
   let description = [{
     The `nvgpu.ldmatrix` op represents loading a matrix fragment from
-    memory to registers. The source and result type must be compatible 
+    memory to registers. The source and result type must be compatible
     with lowering to the `nvvm.ldmatrix` instruction. This op represents
     the distributed version of a `vector.transfer_read` as an intermediate
     step between lowering from `vector.transfer_read` to `nvvm.ldmatrix`.
 
     This operation is meant to follow the semantic of described here:
     https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#warp-level-matrix-instructions-ldmatrix
 
     Example:
let assemblyFormat = [{
     $srcMemref`[` $indices `]` attr-dict `:` type($srcMemref) `->` type($res)
   }];
 
   let hasVerifier = 1;
 }
 
 class NVGPU_MmaSyncOp<string mnemonic> :
         NVGPU_Op<mnemonic,  [Pure,
-                             PredOpTrait<"matrixA and matrixB have same element type", 
+                             PredOpTrait<"matrixA and matrixB have same element type",
                                          TCopVTEtIsSameAs<0, 1>>]> {
   code extraBaseClassDeclaration = [{
-    std::array<int64_t, 3> getMmaShapeAsArray() {      
+    std::array<int64_t, 3> getMmaShapeAsArray() {
       ArrayAttr mmaShape = this->getMmaShape();
       assert(mmaShape.size() == 3 && "mmaShape should be three integers");
       return {mmaShape[0].cast<IntegerAttr>().getInt(),
               mmaShape[1].cast<IntegerAttr>().getInt(),
               mmaShape[2].cast<IntegerAttr>().getInt()};
     }
   }];
 
   let hasVerifier = 1;
 }
 
 def NVGPU_MmaSyncOp : NVGPU_MmaSyncOp<"mma.sync"> {
   let description = [{
     The `nvgpu.mma.sync` op represents the warp-level matrix-multiply-and-
-    accumulate (mma) operation that is compatible with `nvvm.mma.sync`. 
-    The operands and results vector sizes are thread-level onwership to 
-    the warp-level mma operation shape. `mmaShape` attribute holds the 
+    accumulate (mma) operation that is compatible with `nvvm.mma.sync`.
+    The operands and results vector sizes are thread-level onwership to
+    the warp-level mma operation shape. `mmaShape` attribute holds the
     warp-level matrix-multiply shape.
-    
-    The `nvgpu.mma.sync` op serves as an intermediate point between lowering from 
+    The `nvgpu.mma.sync` op serves as an intermediate point between lowering from
     `vector.contract` to `nvvm.mma.sync`.
 
     This operation is meant to follow the semantic of described here:
       https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#warp-level-matrix-instructions-mma
 
     Example:
 
     ```mlir
-    %res = nvgpu.mma.sync (%matrixA, %matrixB, %matrixC) {mmaShape = [16, 8, 16]} : 
+    %res = nvgpu.mma.sync (%matrixA, %matrixB, %matrixC) {mmaShape = [16, 8, 16]} :
         (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf32>) -> vector<2x2xf32>
     ```
   }];
-  let arguments = (ins AnyVector:$matrixA, 
+  let arguments = (ins AnyVector:$matrixA,
                        AnyVector:$matrixB,
-                       AnyVector:$matrixC, 
+                       AnyVector:$matrixC,
                        I64ArrayAttr:$mmaShape,
                        OptionalAttr<UnitAttr>:$tf32Enabled
                        );
 
   let results = (outs AnyVector:$res);
 
   let builders = [
-    OpBuilder<(ins "Value":$matrixA, 
-                   "Value":$matrixB, 
-                   "Value":$matrixC, 
+    OpBuilder<(ins "Value":$matrixA,
+                   "Value":$matrixB,
+                   "Value":$matrixC,
                    "ArrayAttr":$mmaShape)>
   ];
 
   let assemblyFormat = [{
     `(` $matrixA`,` $matrixB`,` $matrixC `)` attr-dict
     `:` `(` type($matrixA) `,` type($matrixB) `,` type($matrixC) `)` `->` type($res)
   }];
 
def NVGPU_MmaSparseSyncOp : NVGPU_MmaSyncOp<"mma.sp.sync"> {
   https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#warp-level-matrix-instructions-for-sparse-mma
 
   The way the indices are distributed among the threads in a warp is controlled
   by the optional `sparsity_selector` operand, which is `0` by default. For
   more information, please consult the PTX documentation linked above.
 
   Example (targetingthe f16 16x8x32 `mma.sp` PTX instruction):
 
-  ```mlir  
+  ```mlir
   nvgpu.mma.sp.sync (%a, %b, %c) metadata (%meta) {mmaShape = [16, 8, 32]} :
-    (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>    
-  ```  
+    (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+  ```
   }];
 
-  let arguments = (ins AnyVector:$matrixA,                       
+  let arguments = (ins AnyVector:$matrixA,
                        AnyVector:$matrixB,
                        AnyVector:$matrixC,
                        NVGPU_MmaSparseSyncMetadataType:$sparseMetadata,
                        I64ArrayAttr:$mmaShape,
                        DefaultValuedAttr<I32Attr, "0">:$sparsitySelector,
                        OptionalAttr<UnitAttr>:$tf32Enabled
                        );
 
def NVGPU_MmaSparseSyncOp : NVGPU_MmaSyncOp<"mma.sp.sync"> {
   let extraClassDeclaration = extraBaseClassDeclaration;
 }
 
 def NVGPU_DeviceAsyncCopyOp : NVGPU_Op<"device_async_copy", [
                                        AttrSizedOperandSegments]> {
   let summary = "device-side asynchronous copy";
   let description = [{
     The `nvgpu.device_async_copy` op initiates an asynchronous copy operation of
-    elements from source (global memory) to the destination (shared memory) 
+    elements from source (global memory) to the destination (shared memory)
     without blocking the thread. The async copy is added to a group.
 
     This op is meant to be used with `nvgpu.device_async_create_group` and
     `nvgpu.device_async_wait` to synchronize copies as explained in those ops
-    descriptions. 
-    
-    `bypassL1` attribute is hint to the hardware to bypass the L1 cache during 
-    async copy, this hint may be ignored by the hardware. 
-    
-    `dstElements` attribute is the total number of elements written to 
+    descriptions.
+    `bypassL1` attribute is hint to the hardware to bypass the L1 cache during
+    async copy, this hint may be ignored by the hardware.
+    `dstElements` attribute is the total number of elements written to
     destination (shared memory).
 
-    `srcElements` argument is the total number of elements read from 
+    `srcElements` argument is the total number of elements read from
     source (global memory).
-    
-    `srcElements` is an optional argument and when present the op only reads 
-    `srcElements` number of elements from the source (global memory) and zero fills 
+    `srcElements` is an optional argument and when present the op only reads
+    `srcElements` number of elements from the source (global memory) and zero fills
     the rest of the elements in the destination (shared memory).
 
     In order to do a copy and wait for the result we need the following
     combination:
     ```
     // copy 1.
     %cp1 = nvgpu.device_async_copy %A[%c0], %B[%c0], 4 :memref<16xf32> to memref<16xf32, 3>
     // copy 2.

mlir/include/mlir/Dialect/PDL/IR/PDLOps.td

let description = [{
     Example:
 
     ```mlir
     // Construct a range of values.
     %valueRange = pdl.range %inputValue, %inputRange : !pdl.value, !pdl.range<value>
 
     // Construct a range of types.
     %typeRange = pdl.range %inputType, %inputRange : !pdl.type, !pdl.range<type>
-    
     // Construct an empty range of types.
     %valueRange = pdl.range : !pdl.range<type>
     ```
 
     TODO: Range construction is currently limited to rewrites, but it could
     be extended to constraints under certain circustances; i.e., if we can
     determine how to extract the underlying elements. If we can't, e.g. if
     there are multiple sub ranges used for construction, we won't be able

mlir/include/mlir/Dialect/PDLInterp/IR/PDLInterpOps.td

let description = [{
     Example:
 
     ```mlir
     // Construct a range of values.
     %valueRange = pdl_interp.create_range %inputValue, %inputRange : !pdl.value, !pdl.range<value>
 
     // Construct a range of types.
     %typeRange = pdl_interp.create_range %inputType, %inputRange : !pdl.type, !pdl.range<type>
-    
     // Construct an empty range of types.
     %valueRange = pdl_interp.create_range : !pdl.range<type>
     ```
   }];
 
   let arguments = (ins Variadic<PDL_AnyType>:$arguments);
   let results = (outs PDL_RangeOf<AnyTypeOf<[PDL_Type, PDL_Value]>>:$result);
   let assemblyFormat = [{

mlir/include/mlir/Dialect/SCF/IR/DeviceMappingInterface.td

 //===----------------------------------------------------------------------===//
 // Attribute interfaces
 //===----------------------------------------------------------------------===//
 
 def DeviceMappingAttrInterface : AttrInterface<"DeviceMappingAttrInterface"> {
   let cppNamespace = "::mlir";
   let description = [{
     Attribute interface describing how to map a region to a processing unit.
-    
-    It is intended to be a generic mechanism for binding regions to execution 
-    units of an actual or virtual device. Each device first expresses its own 
-    mappings, and those mappings must implement this interface. These mappings 
-    can be used by the device-specific code generators and the desired regions 
+    It is intended to be a generic mechanism for binding regions to execution
+    units of an actual or virtual device. Each device first expresses its own
+    mappings, and those mappings must implement this interface. These mappings
+    can be used by the device-specific code generators and the desired regions
     can be connected to the given processing unit.
-    
-    Currently, `scf.foreach_thread` uses this interface to express the mapping 
-    of the loops it contains to the GPU's parallelism units such as threads and 
+    Currently, `scf.foreach_thread` uses this interface to express the mapping
+    of the loops it contains to the GPU's parallelism units such as threads and
     thread blocks.
   }];
 
  let methods = [
     InterfaceMethod<[{
         Returns mapping as an integer from the attribute.
       }],
       "int64_t", "getMappingId", (ins)
     >
   ];
 }
 
-def DeviceMappingArrayAttr : 
-  TypedArrayAttrBase<DeviceMappingAttrInterface, 
+def DeviceMappingArrayAttr :
+  TypedArrayAttrBase<DeviceMappingAttrInterface,
   "Device Mapping array attribute"> { }
 
 #endif // MLIR_DEVICEMAPPINGINTERFACE

mlir/include/mlir/Dialect/SCF/IR/SCFOps.td

let description = [{
     The name "thread" conveys the fact that the parallel execution is mapped
     (i.e. distributed) to a set of virtual threads of execution, one function
     application per thread. Further lowerings are responsible for specifying
     how this is materialized on concrete hardware resources.
 
     An optional `mapping` is an attribute array that specifies processing units
     with their dimension, how it remaps 1-1 to a set of concrete processing
     element resources (e.g. a CUDA grid dimension or a level of concrete nested
-    async parallelism). It is expressed via any attribute that implements the 
-    device mapping interface. It is the reponsibility of the lowering mechanism 
-    to interpret the `mapping` attributes in the context of the concrete target 
-    the op is lowered to, or to ignore it when the specification is ill-formed 
+    async parallelism). It is expressed via any attribute that implements the
+    device mapping interface. It is the reponsibility of the lowering mechanism
+    to interpret the `mapping` attributes in the context of the concrete target
+    the op is lowered to, or to ignore it when the specification is ill-formed
     or unsupported for a particular target.
 
     The only allowed terminator is `scf.foreach_thread.perform_concurrently`.
     `scf.foreach_thread` returns one value per `shared_out` operand. The
     actions of the `perform_concurrently` terminators specify how to combine the
     partial results of all parallel invocations into a full value, in some
     unspecified order. The "destination" of each such op must be a `shared_out`
     block argument of the `scf.foreach_thread` op.
let description = [{
     // Sequential context.
     //
     ```
 
     Example with mapping attribute:
 
     ```mlir
     //
-    // Sequential context. Here `mapping` is expressed as GPU thread mapping 
+    // Sequential context. Here `mapping` is expressed as GPU thread mapping
     // attributes
     //
     %matmul_and_pointwise:2 = scf.foreach_thread (%thread_id_1, %thread_id_2) in
         (%num_threads_1, %numthread_id_2) shared_outs(...)
       -> (tensor<?x?xT>, tensor<?xT>) {
       //
       // Parallel context, each thread with id = **(%thread_id_2, %thread_id_1)**
       // runs its version of the code.

mlir/include/mlir/Dialect/Tensor/IR/TensorOps.td

class Tensor_OpWithOffsetSizesAndStrides<string mnemonic,
   }];
 }
 
 //===----------------------------------------------------------------------===//
 // CastOp
 //===----------------------------------------------------------------------===//
 
 def Tensor_CastOp : Tensor_Op<"cast", [
-    DeclareOpInterfaceMethods<CastOpInterface>, 
+    DeclareOpInterfaceMethods<CastOpInterface>,
     DeclareOpInterfaceMethods<OpAsmOpInterface, ["getAsmResultNames"]>,
     Pure
   ]> {
   let summary = "tensor cast operation";
   let description = [{
     Convert a tensor from one type to an equivalent type without changing any
     data elements. The source and destination types must both be tensor types
     with the same element type. If both are ranked, then the rank should be the

 //===----------------------------------------------------------------------===//
 // ExtractSliceOp
 //===----------------------------------------------------------------------===//
 
 def Tensor_ExtractSliceOp : Tensor_OpWithOffsetSizesAndStrides<"extract_slice", [
     DeclareOpInterfaceMethods<OpAsmOpInterface, ["getAsmResultNames"]>,
     DeclareOpInterfaceMethods<ReifyRankedShapedTypeOpInterface>,
     AttrSizedOperandSegments,
-    Pure, 
+    Pure,
     OffsetSizeAndStrideOpInterface
   ]> {
   let summary = "extract slice operation";
   let description = [{
     The "extract_slice" operation extract a tensor from another tensor as
     specified by the operation's offsets, sizes and strides arguments.
 
     The extract_slice operation supports the following arguments:
OpBuilder<(ins "Value":$source, "ValueRange":$offsets,
       CArg<"ArrayRef<NamedAttribute>", "{}">:$attrs)>,
     // Build an ExtractSliceOp with dynamic entries and inferred result type.
     OpBuilder<(ins "RankedTensorType":$resultType, "Value":$source,
       "ValueRange":$offsets, "ValueRange":$sizes, "ValueRange":$strides,
       CArg<"ArrayRef<NamedAttribute>", "{}">:$attrs)>,
     // Build an ExtractSliceOp with mixed static and dynamic entries packed in
     // a Range vector.
     OpBuilder<(ins "Value":$source, "ArrayRef<Range>":$ranges,
-      CArg<"ArrayRef<NamedAttribute>", "{}">:$attrs)>,    
+      CArg<"ArrayRef<NamedAttribute>", "{}">:$attrs)>,
   ];
 
   let extraClassDeclaration = extraBaseClassDeclaration # [{
     /// Returns the type of the base tensor operand.
     RankedTensorType getSourceType() {
       return getSource().getType().cast<RankedTensorType>();
     }
 
def Tensor_GatherOp : Tensor_Op<"gather", [
     Pure
   ]> {
   let summary = "gather a subset of a tensor at specified indices";
   let description = [{
     The `gather` operation extracts a subset of the elements from a `source`
     tensor at the given indices.
 
     In its most general form, the tensor of indices specifies all the coordinates
-    of every element to extract (i.e. COO format, without the payload). 
+    of every element to extract (i.e. COO format, without the payload).
     The indices are expected to be confined to coordinate values that fit the
     range of the `source` tensor, otherwise the behavior is undefined.
 
     The leading dimensions of the index tensor give the result tensor its leading
-    dimensions. The trailing dimensions of the result tensor are obtained from 
-    the source tensor by omitting the dimensions specified in `gather_dims` 
+    dimensions. The trailing dimensions of the result tensor are obtained from
+    the source tensor by omitting the dimensions specified in `gather_dims`
     (rank-reducing semantics) or setting them to `1` (rank-preserving semantics)
     (see examples).
     The trailing dimension of the index tensor contains the coordinates and is
     expected to have its size equal to the number of dimensions being gathered.
     This convention allows an idiomatic specification and lowering of "gathering
-    multiple N-D slices from the source tensor". 
+    multiple N-D slices from the source tensor".
 
     Note: in the examples below, we separate out the indexing part of the tensor
     type by a whitespace for readability purposes.
 
     Example:
 
     ```mlir
-        // For each 1x2 triple of coordinates in %indices, extract the 
+        // For each 1x2 triple of coordinates in %indices, extract the
         // element (i.e. 0-D subset) at the coordinates triple in %source.
         //
         %out = tensor.gather %source[%indices] gather_dims([0, 1, 2]) :
           (tensor<4x4x4xf32>, tensor<1x2x 3xindex>) -> tensor<1x2x 1x1x1xf32>
 
         // Note: result type may be further rank-reduced to tensor<1x2x f32>.
     ```
 
     A slice variant is provided to allow specifying whole slices of the source
     tensor.
 
     Example:
 
     ```mlir
         // For each 5x6 singleton of coordinates in %indices, extract the 2-D
         // slice %source[*, %indices[...]:%indices[...] + 1, *] with the indices
         // corresponding to the `gather_dims` attribute specified by %indices.
         //
-        %out = tensor.gather %source[%indices] gather_dims([1]) : 
+        %out = tensor.gather %source[%indices] gather_dims([1]) :
           (tensor<3x4x5xf32>, tensor<6x7x 1xindex>) -> tensor<6x7x 3x1x5xf32>
 
         // Note: result type may be further rank-reduced to tensor<6x7x 3x5xf32>.
     ```
 
     The dimensions specified in the gather_dims attribute are ones for which the
-    result tensor has size `1`. 
+    result tensor has size `1`.
     I.e. if the source type is `axbxcxd` and the coordinates are [1, 3], then
     the shape suffix is `ax1xcx1`.
     Gather also allows rank-reducing semantics where the shape `ax1xcx1` can be
     further simplified to `axc`.
 
-    The elemental type of the indices tensor can be any integer type. 
+    The elemental type of the indices tensor can be any integer type.
     In the absence of target-specific or problem specific information the default
     type one should use is `index`.
 
     This operation does not support unranked tensors.
 
     An optional `unique` unit attribute may be specified to indicate that the
     coordinates in `indices` are statically guaranteed to be unique at runtime.
     Incorrectly setting the `unique` attribute when the coordinates are not truly
     unique is undefined behavior.
 
-    Only full slices are meant to be supported by this op, if one desires 
+    Only full slices are meant to be supported by this op, if one desires
     partial slices (e.g. strided windows) one should compose this op with other
     tensor ops (e.g. tensor.extract_slice). This is to avoid a slippery slope of
     complexity that would make the op unusable in practice.
 
-    At the tensor-level, the index tensor is specified in an AoS form (i.e. 
-    coordinate tuple is the most minor). It is the responsibility of further 
+    At the tensor-level, the index tensor is specified in an AoS form (i.e.
+    coordinate tuple is the most minor). It is the responsibility of further
     lowerings and bufferiation to implement various concrete layouts.
 
     Note: As currently specified, the operation must lower to an abstraction that
     performs copies to the output tensor. This is because the buffer type system
-    is currently not rich enough to allow multiple non-contiguous views in the 
+    is currently not rich enough to allow multiple non-contiguous views in the
     same type. This is visible more clearly in a notional buffer version of the
     op:
 
     ```mlir
         // memref<?x4x1xf32> is a contiguous buffer of ?x4x1 elements.
         // gather from random source slices must copy to the contiguous output.
-        %out = memref.gather %source[%indices] gather_dims([1]) : 
+        %out = memref.gather %source[%indices] gather_dims([1]) :
           (memref<4x4xf32>, memref<?x 1xindex>) -> memref<?x 4x1xf32>
 
-        // Nested buffer support would allow gather to directly index into the 
+        // Nested buffer support would allow gather to directly index into the
         // source buffer (i.e. represent a jagged view into the source).
-        %out = memref.gather %source[%indices] gather_dims([1]) : 
+        %out = memref.gather %source[%indices] gather_dims([1]) :
           (memref<4x4xf32>, memref<?x 1xindex>) -> memref<? x memref<4x1xf32>>
     ```
   }];
 
-  let arguments = (ins AnyRankedTensor:$source, 
+  let arguments = (ins AnyRankedTensor:$source,
                        RankedTensorOf<[AnySignlessIntegerOrIndex]>:$indices,
                        DenseI64ArrayAttr:$gather_dims,
                        UnitAttr:$unique);
   let results = (outs AnyRankedTensor:$result);
 
   let assemblyFormat = [{
-    $source `[` $indices `]` 
+    $source `[` $indices `]`
       `gather_dims` `(` $gather_dims `)`
-      (`unique` $unique^)?  
+      (`unique` $unique^)?
       attr-dict
     `:` functional-type(operands, results)
   }];
 
   let extraClassDeclaration = [{
-    // TODO: InferTypeOpInterface once enough confidence is built with 
+    // TODO: InferTypeOpInterface once enough confidence is built with
     // tensor<tensor> and its lwoering to memref<memref>.
     static RankedTensorType inferResultType(RankedTensorType sourceType,
                                             RankedTensorType indicesType,
                                             ArrayRef<int64_t> gatherDims,
                                             bool rankReduced);
     RankedTensorType getIndicesType() {
       return getIndices().getType().cast<RankedTensorType>();
     }

 
 //===----------------------------------------------------------------------===//
 // InsertSliceOp
 //===----------------------------------------------------------------------===//
 
 def Tensor_InsertSliceOp : Tensor_OpWithOffsetSizesAndStrides<"insert_slice", [
     DeclareOpInterfaceMethods<OpAsmOpInterface, ["getAsmResultNames"]>,
     DeclareOpInterfaceMethods<ReifyRankedShapedTypeOpInterface>,
-    AttrSizedOperandSegments, 
+    AttrSizedOperandSegments,
     DestinationStyleOpInterface,
-    Pure, 
+    Pure,
     OffsetSizeAndStrideOpInterface,
     TypesMatchWith<"expected result type to match dest type",
                    "dest", "result", "$_self">
   ]> {
   let summary = "insert_slice operation";
   let description = [{
     The "insert_slice" operation insert a tensor `source` into another
     tensor `dest` as specified by the operation's offsets, sizes and strides

 }
 
 //===----------------------------------------------------------------------===//
 // PadOp
 //===----------------------------------------------------------------------===//
 
 def Tensor_PadOp : Tensor_Op<"pad", [
     DeclareOpInterfaceMethods<OpAsmOpInterface, ["getAsmResultNames"]>,
-    AttrSizedOperandSegments, 
+    AttrSizedOperandSegments,
     Pure,
     SingleBlockImplicitTerminator<"mlir::tensor::YieldOp">]> {
   let summary = "tensor pad operation";
   let description = [{
     `tensor.pad` is an operation that pads the `source` tensor
     with given `low` and `high` padding config.
 
     The PadOp operation supports the following arguments:

 //===----------------------------------------------------------------------===//
 // ScatterOp
 //===----------------------------------------------------------------------===//
 
 def Tensor_ScatterOp : Tensor_Op<"scatter", [
     DeclareOpInterfaceMethods<OpAsmOpInterface, ["getAsmResultNames"]>,
     Pure
   ]> {
-  let summary = 
+  let summary =
     "scatter a tensor into a destination tensor at specified indices";
   let description = [{
     The `scatter` operation inserts a `source` tensor into a `dest` tensor at
     the given indices.
 
     In its most general form, the tensor of indices specifies all the coordinates
     of every element to insert (i.e. COO format, without the payload).
     The indices are expected to be confined to coordinate values that fit the
     range of the `dest` tensor, otherwise the behavior is undefined.
 
-    The leading dimensions of the index tensor must match that of the dest 
+    The leading dimensions of the index tensor must match that of the dest
     tensor. The trailing dimensions of the dest tensor must match those of the
-    source tensor by omitting the dimensions specified in scatter_dims 
+    source tensor by omitting the dimensions specified in scatter_dims
     (rank-reducing semantics) or setting them to `1` (rank-preserving semantics)
-    (see examples). 
-    This convention allows an idiomatic specification and lowering of 
-    "scattering multiple N-D slices into the dest tensor". 
+    (see examples).
+    This convention allows an idiomatic specification and lowering of
+    "scattering multiple N-D slices into the dest tensor".
     The result type must match the type of the dest tensor.
 
     Note: in the examples below, we separate out the indexing part of the tensor
     type by a whitespace for readability purposes.
 
     Example:
 
     ```mlir
-        // For each 1x2 triple of coordinates in %indices, insert the 
+        // For each 1x2 triple of coordinates in %indices, insert the
         // element (i.e. 0-D subset) at the coordinates triple in %dest.
         //
         %out = tensor.scatter %source into %dest[%indices]
             scatter_dims([0, 1, 2]) unique :
           (tensor<1x2x 1x1x1xf32>, tensor<4x4x4xf32>, tensor<1x2x 3xindex>)
             -> tensor<4x4x4xf32>
 
         // Note: source type may be further rank-reduced to tensor<1x2x f32>.
     ```
 
     A slice variant is provided to allow specifying insertion of whole tensor
     slices into the `dest` tensor.
 
     Example:
 
     ```mlir
         // For each 3 singleton of coordinates in %indices, insert the 2-D
         // slice into %dest[*, %indices[...]:%indices[...] + 1, *] with the
         // indices corresponding to the scatter_dims attribute specified by
         // %indices.
         //
-        %out = tensor.scatter %source into %dest[%indices] scatter_dims([1]) unique : 
+        %out = tensor.scatter %source into %dest[%indices] scatter_dims([1]) unique :
           (tensor<3x 4x1x6xf32>, tensor<4x5x6xf32>, tensor<3x 1xindex>)
             -> tensor<4x5x6xf32>
     ```
 
     The dimensions specified in the scatter_dims attribute are ones for which the
-    source tensor has size `1`. 
+    source tensor has size `1`.
     I.e. if the dest type is `axbxcxd` and the coordinates are [1, 3], then
     the source type suffix is `ax1xcx1`.
     Sactter also allows rank-reducing semantics where the shape `ax1xcx1` can be
     further simplified to `axc`.
 
-    The elemental type of the indices tensor can be any integer type. 
+    The elemental type of the indices tensor can be any integer type.
     In the absence of target-specific or problem specific information the default
     type one should use is `index`.
 
     This operation does not support unranked tensors.
 
     A `unique` unit attribute must be be specified to indicate that the
     coordinates are statically guaranteed to be unique at runtime. If coordinates
     are not truly unique at runtime, the behavior is undefined.
 
-    Only full slices are meant to be supported by this op, if one desires 
+    Only full slices are meant to be supported by this op, if one desires
     partial slices (e.g. strided windows) one should compose this op with other
     tensor ops (e.g. tensor.insert_slice). This is to avoid a slippery slope of
     complexity that would make the op unusable in practice.
 
-    At the tensor-level, the index tensor is specified in an AoS form (i.e. 
-    coordinate tuple is the most minor). It is the responsibility of further 
+    At the tensor-level, the index tensor is specified in an AoS form (i.e.
+    coordinate tuple is the most minor). It is the responsibility of further
     lowerings and bufferiation to implement various concrete layouts.
 
     Note: As currently specified, the operation must lower to an abstraction that
     performs copies to the output tensor. This is because the buffer type system
-    is currently not rich enough to allow multiple non-contiguous views in the 
+    is currently not rich enough to allow multiple non-contiguous views in the
     same type. This is visible more clearly in a notional buffer version of the
     op:
 
     ```mlir
         // memref<?x 4xf32> is a contiguous buffer of ?x4 elements, scatter into
         // random dest slices must copy to the contiguous dest.
         //
         some_side_effecting_op_writing_into %source, ...: memref<3x 4xf32>
-        memref.scatter %source into %dest[%indices] scatter_dims([1]) unique : 
+        memref.scatter %source into %dest[%indices] scatter_dims([1]) unique :
           (memref<3x 4xf32>, memref<?x 4xf32>, memref<?x 1xindex>)
 
         // Nested buffer support in the producing op would allow writing directly
         // into the dest buffer.
-        %v = some_nested_buffer_view_op %dest[%indices] scatter_dims([1]) unique : 
+        %v = some_nested_buffer_view_op %dest[%indices] scatter_dims([1]) unique :
           memref<? x memref<4xf32>>
         some_side_effecting_op_writing_into %v, ...: memref<? x memref<4xf32>>
     ```
   }];
 
-  let arguments = (ins AnyRankedTensor:$source, 
-                       AnyRankedTensor:$dest, 
+  let arguments = (ins AnyRankedTensor:$source,
+                       AnyRankedTensor:$dest,
                        RankedTensorOf<[AnySignlessIntegerOrIndex]>:$indices,
                        DenseI64ArrayAttr:$scatter_dims,
                        UnitAttr:$unique);
   let results = (outs AnyRankedTensor:$result);
 
   let assemblyFormat = [{
-    $source `into` $dest `[` $indices `]` 
+    $source `into` $dest `[` $indices `]`
       `scatter_dims` `(` $scatter_dims `)`
       (`unique` $unique^)?
       attr-dict
     `:` functional-type(operands, results)
   }];
 
   let extraClassDeclaration = [{
     RankedTensorType getDestType() {
class Tensor_RelayoutOp<string mnemonic, list<Trait> traits = []> :
         DeclareOpInterfaceMethods<ReifyRankedShapedTypeOpInterface>,
         TypesMatchWith<"result type matches type of dest",
                    "dest", "result",
                    "$_self">])> {
 
   code commonExtraClassDeclaration = [{
     int64_t getSourceRank() { return getSource().getType().getRank(); };
     int64_t getDestRank() { return getDest().getType().getRank(); };
-    RankedTensorType getSourceType() { 
+    RankedTensorType getSourceType() {
       return getSource().getType().cast<RankedTensorType>(); };
     RankedTensorType getDestType() {
       return getDest().getType().cast<RankedTensorType>(); };
 
-    /// Return position for init operand. Init operand is `dest`. 
+    /// Return position for init operand. Init operand is `dest`.
     std::pair<int64_t, int64_t> getDpsInitsPositionRange() {
       return {1, 2}; // `dest` operand
     }
 
     /// Interface method for ConditionallySpeculatable.
-    Speculation::Speculatability getSpeculatability();   
- 
-    /// Return a mapping from positions `inner_dims_pos` to their 
+    Speculation::Speculatability getSpeculatability();
+    /// Return a mapping from positions `inner_dims_pos` to their
     /// tile factors.
     DenseMap<int64_t, OpFoldResult> getDimAndTileMapping();
-    
     /// Return the tile sizes as OpFoldResult.
     SmallVector<OpFoldResult> getMixedTiles();
-    
-    /// Return the tile sizes as `int64_t`. If a tile size is dynamic 
-    /// a sentinel `kDynamic` is introduced at that position in 
+    /// Return the tile sizes as `int64_t`. If a tile size is dynamic
+    /// a sentinel `kDynamic` is introduced at that position in
     /// the returned vector.
     SmallVector<int64_t> getStaticTiles();
   }];
-  
   let hasVerifier = 1;
 }
 
 def Tensor_PackOp : Tensor_RelayoutOp<"pack", [
     AttrSizedOperandSegments]> {
   let summary = "tensor pack operation";
-  let description = [{ 
+  let description = [{
     The pack operation converts an input tensor to a higher-dimensional tensor
     with a tiled and packed layout. The mandatory `inner_dims_pos` attribute
     specifies a permutation for the original dimensions, while `inner_tiles` is the
     tiling factor for each dimension. The optional attribute `outer_dims_perm`
     specifies the order for the tiled data dimension, while the attribute
     `padding_value` specifies a padding value at the boundary on non-perfectly
-    divisible dimensions. Padding is optional: 
-    - If absent, it is UB if the tile does not perfectly divide the dimension.  
-    - If present, it will pad along high dimensions (high-padding) to make the 
-      tile complete. 
+    divisible dimensions. Padding is optional:
+    - If absent, it is UB if the tile does not perfectly divide the dimension.
+    - If present, it will pad along high dimensions (high-padding) to make the
+      tile complete.
 
     Example NC_to_NCnc:
 
     ```mlir
     tensor.pack %source inner_dims_pos = [0, 1]
       inner_tiles = [8, 32] into %dest : tensor<128x256xf32> -> tensor<16x8x8x32xf32>
     ```
     Example CK to KCck
let arguments = (ins AnyRankedTensor:$source,
                        AnyRankedTensor:$dest,
                        Optional<AnyType>:$padding_value,
                        DefaultValuedOptionalAttr<DenseI64ArrayAttr, "{}">:$outer_dims_perm,
                        DenseI64ArrayAttr:$inner_dims_pos,
                        Variadic<Index>:$inner_tiles,
                        DenseI64ArrayAttr:$static_inner_tiles);
   let results = (outs AnyRankedTensor:$result);
   let assemblyFormat = [{
-    $source 
+    $source
     (`padding_value` `(` $padding_value^ `:` type($padding_value) `)`)?
-    (`outer_dims_perm` `=` $outer_dims_perm^)?  
+    (`outer_dims_perm` `=` $outer_dims_perm^)?
     `inner_dims_pos` `=` $inner_dims_pos
     `inner_tiles` `=`
     custom<DynamicIndexList>($inner_tiles, $static_inner_tiles)
     `into` $dest attr-dict `:` type($source) `->` type($dest)
   }];
 
   let builders = [
     OpBuilder<(ins "Value":$source, "Value":$dest,
       "ArrayRef<int64_t>":$innerDimsPos,
       "ArrayRef<OpFoldResult>":$innerTiles,
       CArg<"Optional<Value>", "llvm::None">:$paddingValue,
       CArg<"ArrayRef<int64_t>", "{}">:$outerDimsPerm)>
   ];
 
   let extraClassDeclaration = commonExtraClassDeclaration # [{
     // Method to get the `ShapedType` of the result based on the inner tiles,
-    // position of the inner tiles (innerDimsPos)  and interchange vector of  
+    // position of the inner tiles (innerDimsPos)  and interchange vector of
     // outer loops (outerDimsPerm).
     static ShapedType inferPackedType(ShapedType sourceType,
         ArrayRef<int64_t> innerTileSizes, ArrayRef<int64_t> innerDimsPos,
         ArrayRef<int64_t> outerDimsPerm = {});
-  }]; 
+  }];
 }
 
 //===----------------------------------------------------------------------===//
 // UnPackOp
 //===----------------------------------------------------------------------===//
 
 def Tensor_UnPackOp : Tensor_RelayoutOp<"unpack"> {
   let summary = "tensor unpack operation";
let description = [{
     ```mlir
     tensor.unpack %source inner_dims_pos = [0, 1]
       inner_tiles = [8, 32] into %dest : tensor<16x8x8x32xf32> -> tensor<128x256xf32>
     ```
 
     Example CK to KCck:
 
     ```mlir
-    tensor.unapck %source outer_dims_perm = [1, 0] inner_dims_pos = [0, 1] 
+    tensor.unapck %source outer_dims_perm = [1, 0] inner_dims_pos = [0, 1]
       inner_tiles = [8, 32] into %dest : tensor<8x16x8x32xf32> -> tensor<128x256xf32>
     ```
   }];
   let arguments = (ins AnyRankedTensor:$source,
                        AnyRankedTensor:$dest,
                        DefaultValuedOptionalAttr<DenseI64ArrayAttr, "{}">:$outer_dims_perm,
                        DenseI64ArrayAttr:$inner_dims_pos,
                        Variadic<Index>:$inner_tiles,

mlir/include/mlir/Dialect/Tosa/IR/TosaOpBase.td

 // quantization support: https://mlir.llvm.org/docs/Quantization/, and supports
 // uniform quantization. Depending on datatype, asymmetric and symmetric
 // quantization are supported. The types themselves are described in
 // TosaTypesBase.td .
 
 // This quantization attribute expresses numerical behavior of operators where
 // the operator has a numerical relationship between a single input and output.
 // For example: tosa.negate.
-def Tosa_UnaryOpQuantizationAttr 
+def Tosa_UnaryOpQuantizationAttr
     : Tosa_Attr<"UnaryOpQuantization", "unary_quant"> {
   let summary = "Attribute for UnaryOp quantization information.";
   let parameters = (ins "int64_t":$input_zp, "int64_t":$output_zp);
   let assemblyFormat = "`<` struct(params) `>`";
 }
 
 // There is no explicit BinaryOpQuantizationAttr for 2-input/1-output ops. In
 // this case, a tosa.rescale is used to express the inputs to the same scale.
 // TODO: Upload WIP legalization document describing this construction by
 // example.
 
 // This quantization attribute holds input and weight zero point. Both the
 // ConvOp and MatMulOp QuantizationAttrs follow a common design semantic where
 // their ownquantization attribute only expresses the numerical behavior at
 // the inputs.
 // The scaling of their accumulator output is done using an explicit
 // tosa.rescale operator that scales the accumulator result to output scale.
-def Tosa_ConvOpQuantizationAttr 
-    : Tosa_Attr<"ConvOpQuantization", "conv_quant"> { 
+def Tosa_ConvOpQuantizationAttr
+    : Tosa_Attr<"ConvOpQuantization", "conv_quant"> {
   let summary = "Attribute for Conv type op quantization information.";
   let parameters = (ins "int64_t":$input_zp, "int64_t":$weight_zp);
   let assemblyFormat = "`<` struct(params) `>`";
 }
 
-def Tosa_MatMulOpQuantizationAttr 
+def Tosa_MatMulOpQuantizationAttr
     : Tosa_Attr< "MatMulOpQuantization", "matmul_quant"> {
   let summary = "Attribute for MatMulOp quantization information.";
   let parameters = (ins "int64_t":$a_zp, "int64_t":$b_zp);
   let assemblyFormat = "`<` struct(params) `>`";
 }
 
 // This attribute holds input zero point correction applied to the padding
 // zeros to ensure numerical accuracy in the subsequent TOSA operations.

mlir/include/mlir/Dialect/Tosa/IR/TosaUtilOps.td

 //===-- TosaUtilOps.td - TOSA dialect utility operations ---*- tablegen -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
-// This file defines codegen utility operators for the TOSA dialect. 
-// These operators are not part of the formal TOSA specification and 
-// are intended to aid code generation from TOSA. 
+// This file defines codegen utility operators for the TOSA dialect.
+// These operators are not part of the formal TOSA specification and
+// are intended to aid code generation from TOSA.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef TOSA_UTIL_OPS
 #define TOSA_UTIL_OPS
 
 include "mlir/IR/OpBase.td"
 

mlir/include/mlir/Dialect/Tosa/Transforms/Passes.td

def TosaMakeBroadcastable : Pass<"tosa-make-broadcastable", "func::FuncOp"> {
 
   let constructor = "createTosaMakeBroadcastablePass()";
 }
 
 def TosaOptionalDecompositions
   : Pass<"tosa-optional-decompositions", "func::FuncOp"> {
   let summary = "Applies Tosa operations optional decompositions";
   let description = [{
-    Pass to apply the Tosa operations decompositions 
+    Pass to apply the Tosa operations decompositions
     exposed as populate functions in include/mlir/Dialect/Tosa/Transforms/Passes.h
   }];
 
   let constructor = "tosa::createTosaOptionalDecompositions()";
 }
 
 def TosaProfileType : I32EnumAttr<"TosaProfileEnum", "Tosa profile",
     [

mlir/include/mlir/Dialect/Transform/IR/TransformOps.td

let description = [{
     transformations. The scope operation must be isolated from above. There is
     no check that the transforms are indeed scoped as their "apply" methods can
     be arbitrarily complex. Therefore it is the responsibility of the user to
     ensure that the transforms are scoped correctly, or to produce an
     irrecoverable error and thus abort the execution without attempting the
     remaining alternatives. Note that the payload IR outside of the given scope
     is not necessarily in the valid state, or even accessible to the
     transformation.
-    
     The changes to the IR within the scope performed by transforms in the failed
     alternative region are reverted before attempting the next region.
     Practically, this is achieved by cloning the scope. Therefore it is advised
     to limit the scope as much as possible and place the most likely
     alternatives early in the region list. The operation is also isolated from
     above and requires rediscovering the operations within the given scope to
     avoid additional handle invalidation. The latter restriction may be lifted
     in the future.
let description = [{
     This op generates as many handles as the terminating YieldOp has operands.
     For each result, the payload ops of the corresponding YieldOp operand are
     merged and mapped to the same resulting handle.
   }];
 
   let arguments = (ins TransformTypeInterface:$target);
   let results = (outs Variadic<TransformTypeInterface>:$results);
   let regions = (region SizedRegion<1>:$body);
-  let assemblyFormat = 
+  let assemblyFormat =
     "$target `:` type($target) (`->` type($results)^)? $body attr-dict";
   let hasVerifier = 1;
 
   let extraClassDeclaration = [{
     /// Allow the dialect prefix to be omitted.
     static StringRef getDefaultDialect() { return "transform"; }
 
     BlockArgument getIterationVariable() {

 }
 
 def SplitHandlesOp : TransformDialectOp<"split_handles",
     [FunctionalStyleTransformOpTrait,
      DeclareOpInterfaceMethods<TransformOpInterface>,
      DeclareOpInterfaceMethods<MemoryEffectsOpInterface>]> {
   let summary = "Splits handles from a union of payload ops to a list";
   let description = [{
-    Creates `num_result_handles` transform IR handles extracted from the 
+    Creates `num_result_handles` transform IR handles extracted from the
     `handle` operand. The resulting Payload IR operation handles are listed
     in the same order as the operations appear in the source `handle`.
     This is useful for ensuring a statically known number of operations are
     tracked by the source `handle` and to extract them into individual handles
     that can be further manipulated in isolation.
 
     This operation succeeds and returns `num_result_handles` if the statically
-    specified `num_result_handles` corresponds to the dynamic number of 
+    specified `num_result_handles` corresponds to the dynamic number of
     operations contained in the source `handle`. Otherwise it silently fails.
   }];
 
   let arguments = (ins TransformTypeInterface:$handle,
                        I64Attr:$num_result_handles);
   let results = (outs Variadic<TransformTypeInterface>:$results);
 
   let builders = [
     OpBuilder<(ins "Value":$handle, "int64_t":$numResultHandles)>
   ];
 
   let assemblyFormat = [{
-    $handle `in` `[` $num_result_handles `]` 
+    $handle `in` `[` $num_result_handles `]`
     attr-dict `:` functional-type(operands, results)
   }];
 }
 
 def PDLMatchOp : TransformDialectOp<"pdl_match",
     [DeclareOpInterfaceMethods<TransformOpInterface>,
      DeclareOpInterfaceMethods<MemoryEffectsOpInterface>]> {
   let summary = "Finds ops that match the named PDL pattern";
let description = [{
     of the matched ops.
 
     The transformation is considered successful regardless of whether some
     Payload IR ops actually matched the pattern and only fails if the pattern
     could not be looked up or compiled.
   }];
 
   let arguments = (ins
-    Arg<TransformTypeInterface, "Payload IR scope to match within">:$root, 
+    Arg<TransformTypeInterface, "Payload IR scope to match within">:$root,
     SymbolRefAttr:$pattern_name);
   let results = (outs
     Res<TransformTypeInterface, "Handle to the matched Payload IR ops">:$matched);
 
   let assemblyFormat = "$pattern_name `in` $root attr-dict `:` "
                        "functional-type(operands, results)";
 }
 
let description = [{
     computed by repeating the list of payload IR ops associated with the
     operand handle as many times as the "pattern" handle has associated
     operations. For example, if pattern is associated with [op1, op2] and the
     operand handle is associated with [op3, op4, op5], the resulting handle
     will be associated with [op3, op4, op5, op3, op4, op5].
 
     This transformation is useful to "align" the sizes of payload IR lists
     before a transformation that expects, e.g., identically-sized lists. For
-    example, a transformation may be parameterized by same notional per-target 
+    example, a transformation may be parameterized by same notional per-target
     size computed at runtime and supplied as another handle, the replication
     allows this size to be computed only once and used for every target instead
     of replicating the computation itself.
 
     Note that it is undesirable to pass a handle with duplicate operations to
     an operation that consumes the handle. Handle consumption often indicates
     that the associated payload IR ops are destroyed, so having the same op
     listed more than once will lead to double-free. Single-operand

 def YieldOp : TransformDialectOp<"yield", [Terminator]> {
   let summary = "Yields operation handles from a transform IR region";
   let description = [{
     This terminator operation yields operation handles from regions of the
     transform IR ops back to the containing op. It is not itself associated with
     any transformation on the payload IR and is used for flow purposes only.
   }];
 
-  let arguments = (ins 
+  let arguments = (ins
     Arg<Variadic<TransformTypeInterface>, "Operation handles yielded back to the parent",
         [TransformMappingRead]>:$operands);
   let assemblyFormat = "operands attr-dict (`:` type($operands)^)?";
 
   let builders = [
     OpBuilder<(ins), [{
       return build($_builder, $_state, ::mlir::ValueRange());
     }]>
   ];
 }
 
 #endif // MLIR_DIALECT_TRANSFORM_IR_TRANSFORMOPS

mlir/include/mlir/IR/BuiltinTypes.td

let description = [{
     Both offsets and strides may be _dynamic_, that is, unknown at compile time.
     This is represented by using a question mark (`?`) instead of the value in
     the textual form of the IR.
 
     The strided layout converts into the following canonical one-dimensional
     affine form through explicit linearization:
 
     ```mlir
-    affine_map<(d0, ... dN)[offset, stride0, ... strideN] -> 
+    affine_map<(d0, ... dN)[offset, stride0, ... strideN] ->
                 (offset + d0 * stride0 + ... dN * strideN)>
     ```
 
     Therefore, it is never subject to the implicit row-major layout
     interpretation.
 
     ##### Codegen of Unranked Memref
 

mlir/include/mlir/IR/OpAsmInterface.td

 
 //===----------------------------------------------------------------------===//
 // ResourceHandleParameter
 //===----------------------------------------------------------------------===//
 
 /// This parameter represents a handle to a resource that is encoded into the
 /// "dialect_resources" section of the assembly format. This parameter expects a
 /// C++ `handleType` that derives from `AsmDialectResourceHandleBase` and
-/// implements a derived handle to the desired resource type. 
+/// implements a derived handle to the desired resource type.
 class ResourceHandleParameter<string handleType, string desc = "">
     : AttrOrTypeParameter<handleType, desc> {
   let parser = "$_parser.parseResourceHandle<" # handleType # ">()";
   let printer = "$_printer.printResourceHandle($_self)";
 }
 
 #endif // MLIR_IR_OPASMINTERFACE_TD

mlir/include/mlir/IR/SubElementInterfaces.td

 
 def SubElementAttrInterface
     : AttrInterface<"SubElementAttrInterface">,
       SubElementInterfaceBase<"SubElementAttrInterface", "::mlir::Attribute",
                               "$_attr"> {
   let description = [{
     An interface used to query and manipulate sub-elements, such as sub-types
     and sub-attributes of a composite attribute.
-    
     To support the introspection of custom parameters that hold sub-elements,
     a specialization of the `AttrTypeSubElementHandler` class must be provided.
   }];
 }
 
 //===----------------------------------------------------------------------===//
 // SubElementTypeInterface
 //===----------------------------------------------------------------------===//
 
 def SubElementTypeInterface
     : TypeInterface<"SubElementTypeInterface">,
       SubElementInterfaceBase<"SubElementTypeInterface", "::mlir::Type",
                               "$_type"> {
   let description = [{
     An interface used to query and manipulate sub-elements, such as sub-types
     and sub-attributes of a composite type.
-    
     To support the introspection of custom parameters that hold sub-elements,
     a specialization of the `AttrTypeSubElementHandler` class must be provided.
   }];
 }
 
 #endif // MLIR_IR_SUBELEMENTINTERFACES_TD_

mlir/include/mlir/Interfaces/ControlFlowInterfaces.td

InterfaceMethod<[{
         Returns the operands of this operation used as the entry arguments when
         entering the region at `index`, which was specified as a successor of
         this operation by `getSuccessorRegions`, or the operands forwarded to
         the operation's results when it branches back to itself. These operands
         should correspond 1-1 with the successor inputs specified in
         `getSuccessorRegions`.
       }],
       "::mlir::OperandRange", "getSuccessorEntryOperands",
-      (ins "::llvm::Optional<unsigned>":$index), [{}], 
+      (ins "::llvm::Optional<unsigned>":$index), [{}],
       /*defaultImplementation=*/[{
         auto operandEnd = this->getOperation()->operand_end();
         return ::mlir::OperandRange(operandEnd, operandEnd);
       }]
     >,
     InterfaceMethod<[{
         Returns the viable successors of a region at `index`, or the possible
         successors when branching from the parent op if `index` is None. These

mlir/include/mlir/Interfaces/ParallelCombiningOpInterface.td

 #define MLIR_INTERFACES_PARALLELCOMBININGOPINTERFACE
 
 include "mlir/IR/OpBase.td"
 
 def ParallelCombiningOpInterface : OpInterface<"ParallelCombiningOpInterface"> {
   let description = [{
     A parallel combining op is an op with a region.
 
-    This is useful as a terminator to parallel operations that iterate over 
-    some set and return tensors while avoiding tight coupling between the 
+    This is useful as a terminator to parallel operations that iterate over
+    some set and return tensors while avoiding tight coupling between the
     iterating op, the combining op and the individual subtensor producing ops.
   }];
   let cppNamespace = "::mlir";
 
   let methods = [
     InterfaceMethod<
       /*desc=*/[{
         Return `idx`^th result of the parent operation.

mlir/include/mlir/Interfaces/TilingInterface.td

let methods = [
           the output required. This is different from
           `getTiledImplementation` which generates the tiled
           implementation of the operation given a tile of the
           iteration space. This method generates a tiled
           implementation of the operation based on the tile of the
           result required. This method enables fusion by using tile
           and fuse. The method returns failure if the operation can't be
           tiled to generate the result tile. In practical terms this
-          implies it cannot be tiled and fused with its consumers.        
+          implies it cannot be tiled and fused with its consumers.
 
           - `offsets` provides the offset of the tile in the coordinate system
             of the original iteration space, i.e., if an iteration space
             dimension had non-zero offset, it must be included in the offset
             provided here (as opposed to zero-based offset "relative" to the
             iteration space).
           - `sizes` provides the size of the tile.
         }],
         /*retType=*/"FailureOr<Value>",
         /*methodName=*/"generateResultTileValue",
         /*args=*/(ins
           "OpBuilder &":$b,
           "unsigned":$resultNumber,
           "ArrayRef<OpFoldResult>":$offsets,
           "ArrayRef<OpFoldResult>":$sizes),
         /*methodBody=*/"",
         /*defaultImplementation=*/[{
           return failure();
         }]
       >,
       InterfaceMethod<
         /*desc=*/[{
-          Generates the scalar implementation of the operation. 
+          Generates the scalar implementation of the operation.
 
           Given the list `ivs` that represent points in the iteration space
           (as specified by `getIterationDomain()`) returns the scalar operations
           that represent the computation at that point in the iteration space.
           This method is typically used as the "exit path", i.e. once all
-          transformations are done, this method can be used to lower to scalar 
+          transformations are done, this method can be used to lower to scalar
           code that can then be lowered to LLVM or SPIR-V dialects.
         }],
         /*retType=*/"LogicalResult",
         /*methodName=*/"generateScalarImplementation",
         /*args=*/(ins
             "OpBuilder &":$b,
             "Location ":$loc,
             "ValueRange ":$ivs),
         /*methodBody=*/"",
         /*defaultImplementation=*/[{
           return failure();
         }]
       >
-  ];  
+  ];
 }
 
 def PartialReductionOpInterface : OpInterface<"PartialReductionOpInterface"> {
   let description = [{
     Interface for allowing operations to expose information needed to
     tile reductions using partial reduction followed by merge. This is
     complementary to TilingInterface to tile reductions.
   }];

mlir/test/Analysis/DataFlow/test-dead-code-analysis.mlir

 // RUN: mlir-opt -test-dead-code-analysis 2>&1 %s | FileCheck %s
 
 // CHECK: test_cfg:
 // CHECK:  region #0
 // CHECK:   ^bb0 = live
 // CHECK:   ^bb1 = live
 // CHECK:    from ^bb1 = live
 // CHECK:    from ^bb0 = live
 // CHECK:   ^bb2 = live
 // CHECK:    from ^bb1 = live
-func.func @test_cfg(%cond: i1) -> () 
+func.func @test_cfg(%cond: i1) -> ()
     attributes {tag = "test_cfg"} {
   cf.br ^bb1
 
 ^bb1:
   cf.cond_br %cond, ^bb1, ^bb2
 
 ^bb2:
   return
 }
 
 func.func @test_region_control_flow(%cond: i1, %arg0: i64, %arg1: i64) -> () {
   // CHECK: test_if:
   // CHECK:  region #0
   // CHECK: region_preds: (all) predecessors:
-  // CHECK:   scf.if 
+  // CHECK:   scf.if
   // CHECK:  region #1
   // CHECK: region_preds: (all) predecessors:
-  // CHECK:   scf.if 
+  // CHECK:   scf.if
   // CHECK: op_preds: (all) predecessors:
   // CHECK:   scf.yield {then}
   // CHECK:   scf.yield {else}
   scf.if %cond {
     scf.yield {then}
   } else {
     scf.yield {else}
-  } {tag = "test_if"} 
+  } {tag = "test_if"}
 
   // test_while:
   //  region #0
   // region_preds: (all) predecessors:
-  //   scf.while 
-  //   scf.yield 
+  //   scf.while
+  //   scf.yield
   //  region #1
   // region_preds: (all) predecessors:
   //   scf.condition
   // op_preds: (all) predecessors:
   //   scf.condition
   %c2_i64 = arith.constant 2 : i64
   %0:2 = scf.while (%arg2 = %arg0) : (i64) -> (i64, i64) {
     %1 = arith.cmpi slt, %arg2, %arg1 : i64
     scf.condition(%1) %arg2, %arg2 : i64, i64
   } do {
   ^bb0(%arg2: i64, %arg3: i64):
     %1 = arith.muli %arg3, %c2_i64 : i64
     scf.yield %1 : i64
   } attributes {tag = "test_while"}
 
   return
 }
 
 // CHECK: foo:
 // CHECK:  region #0
 // CHECK:   ^bb0 = live
 // CHECK: op_preds: (all) predecessors:
 // CHECK:   func.call @foo(%{{.*}}) {tag = "a"}
 // CHECK:   func.call @foo(%{{.*}}) {tag = "b"}
-func.func private @foo(%arg0: i32) -> i32 
+func.func private @foo(%arg0: i32) -> i32
     attributes {tag = "foo"} {
-  return {a} %arg0 : i32 
+  return {a} %arg0 : i32
 }
 
 // CHECK: bar:
 // CHECK:  region #0
 // CHECK:   ^bb0 = live
 // CHECK: op_preds: predecessors:
 // CHECK:   func.call @bar(%{{.*}}) {tag = "c"}
-func.func @bar(%cond: i1) -> i32 
+func.func @bar(%cond: i1) -> i32
     attributes {tag = "bar"} {
   cf.cond_br %cond, ^bb1, ^bb2
 
 ^bb1:
   %c0 = arith.constant 0 : i32
   return {b} %c0 : i32
 
 ^bb2:

 
 // CHECK: test_unknown_branch:
 // CHECK:  region #0
 // CHECK:   ^bb0 = live
 // CHECK:   ^bb1 = live
 // CHECK:    from ^bb0 = live
 // CHECK:   ^bb2 = live
 // CHECK:    from ^bb0 = live
-func.func @test_unknown_branch() -> () 
+func.func @test_unknown_branch() -> ()
     attributes {tag = "test_unknown_branch"} {
   "test.unknown_br"() [^bb1, ^bb2] : () -> ()
 
 ^bb1:
   return
 
 ^bb2:
   return
 }
 
 // CHECK: test_unknown_region:
 // CHECK:  region #0
 // CHECK:   ^bb0 = live
 // CHECK:  region #1
 // CHECK:   ^bb0 = live
 func.func @test_unknown_region() -> () {
   "test.unknown_region_br"() ({
   ^bb0:
     "test.unknown_region_end"() : () -> ()
-  }, {    
+  }, {
   ^bb0:
     "test.unknown_region_end"() : () -> ()
   }) {tag = "test_unknown_region"} : () -> ()
   return
 }
 
 // CHECK: test_known_dead_block:
 // CHECK:  region #0
 // CHECK:   ^bb0 = live
 // CHECK:   ^bb1 = live
 // CHECK:   ^bb2 = dead
-func.func @test_known_dead_block() -> () 
+func.func @test_known_dead_block() -> ()
     attributes {tag = "test_known_dead_block"} {
   %true = arith.constant true
   cf.cond_br %true, ^bb1, ^bb2
 
 ^bb1:
   return
 
 ^bb2:
   return
 }
 
 // CHECK: test_known_dead_edge:
 // CHECK:   ^bb2 = live
 // CHECK:    from ^bb1 = dead
 // CHECK:    from ^bb0 = live
 func.func @test_known_dead_edge(%arg0: i1) -> ()
     attributes {tag = "test_known_dead_edge"} {
   cf.cond_br %arg0, ^bb1, ^bb2
 
 ^bb1:
-  %true = arith.constant true 
+  %true = arith.constant true
   cf.cond_br %true, ^bb3, ^bb2
 
 ^bb2:
   return
 
 ^bb3:
   return
 }
 
 func.func @test_known_region_predecessors() -> () {
   %false = arith.constant false
   // CHECK: test_known_if:
   // CHECK:  region #0
   // CHECK:   ^bb0 = dead
   // CHECK:  region #1
   // CHECK:   ^bb0 = live
   // CHECK: region_preds: (all) predecessors:
-  // CHECK:   scf.if 
+  // CHECK:   scf.if
   // CHECK: op_preds: (all) predecessors:
   // CHECK:   scf.yield {else}
   scf.if %false {
     scf.yield {then}
   } else {
     scf.yield {else}
-  } {tag = "test_known_if"} 
+  } {tag = "test_known_if"}
   return
 }
 
 // CHECK: callable:
 // CHECK:  region #0
 // CHECK:   ^bb0 = live
 // CHECK: op_preds: predecessors:
 // CHECK:   func.call @callable() {then}
 func.func @callable() attributes {tag = "callable"} {
   return
 }
 
 func.func @test_dead_callsite() -> () {
   %true = arith.constant true
   scf.if %true {
     func.call @callable() {then} : () -> ()
-    scf.yield 
+    scf.yield
   } else {
     func.call @callable() {else} : () -> ()
-    scf.yield 
+    scf.yield
   }
   return
 }
 
 func.func private @test_dead_return(%arg0: i32) -> i32 {
   %true = arith.constant true
   cf.cond_br %true, ^bb1, ^bb1
 

mlir/test/Analysis/test-foo-analysis.mlir

 // RUN: mlir-opt -split-input-file -pass-pipeline='builtin.module(func.func(test-foo-analysis))' %s 2>&1 | FileCheck %s
 
 // CHECK-LABEL: function: @test_default_init
 func.func @test_default_init() -> () {
   // CHECK: a -> 0
   "test.foo"() {tag = "a"} : () -> ()
-  return 
+  return
 }
 
 // -----
 
 // CHECK-LABEL: function: @test_one_join
 func.func @test_one_join() -> () {
   // CHECK: a -> 0
   "test.foo"() {tag = "a"} : () -> ()
   // CHECK: b -> 1
   "test.foo"() {tag = "b", foo = 1 : ui64} : () -> ()
-  return 
+  return
 }
 
 // -----
 
 // CHECK-LABEL: function: @test_two_join
 func.func @test_two_join() -> () {
   // CHECK: a -> 0
   "test.foo"() {tag = "a"} : () -> ()
   // CHECK: b -> 1
   "test.foo"() {tag = "b", foo = 1 : ui64} : () -> ()
   // CHECK: c -> 0
   "test.foo"() {tag = "c", foo = 1 : ui64} : () -> ()
-  return 
+  return
 }
 
 // -----
 
 // CHECK-LABEL: function: @test_fork
 func.func @test_fork() -> () {
   // CHECK: init -> 1
   "test.branch"() [^bb0, ^bb1] {tag = "init", foo = 1 : ui64} : () -> ()

mlir/test/Conversion/ComplexToStandard/convert-to-standard.mlir

func.func @complex_log1p(%arg: complex<f32>) -> complex<f32> {
   return %log1p : complex<f32>
 }
 
 // CHECK: %[[REAL:.*]] = complex.re %[[ARG]] : complex<f32>
 // CHECK: %[[IMAG:.*]] = complex.im %[[ARG]] : complex<f32>
 // CHECK: %[[ONE_HALF:.*]] = arith.constant 5.000000e-01 : f32
 // CHECK: %[[ONE:.*]] = arith.constant 1.000000e+00 : f32
 // CHECK: %[[TWO:.*]] = arith.constant 2.000000e+00 : f32
-// CHECK: %[[SQ_SUM_0:.*]] = arith.mulf %[[REAL]], %[[REAL]] : f32 
+// CHECK: %[[SQ_SUM_0:.*]] = arith.mulf %[[REAL]], %[[REAL]] : f32
 // CHECK: %[[TWO_REAL:.*]] = arith.mulf %[[REAL]], %[[TWO]] : f32
-// CHECK: %[[SQ_SUM_1:.*]] = arith.addf %[[SQ_SUM_0]], %[[TWO_REAL]] : f32 
-// CHECK: %[[SQ_IMAG:.*]] = arith.mulf %[[IMAG]], %[[IMAG]] : f32 
-// CHECK: %[[SQ_SUM_2:.*]] = arith.addf %[[SQ_SUM_1]], %[[SQ_IMAG]] : f32 
-// CHECK: %[[LOG_SQ_SUM:.*]] = math.log1p %[[SQ_SUM_2]] : f32 
+// CHECK: %[[SQ_SUM_1:.*]] = arith.addf %[[SQ_SUM_0]], %[[TWO_REAL]] : f32
+// CHECK: %[[SQ_IMAG:.*]] = arith.mulf %[[IMAG]], %[[IMAG]] : f32
+// CHECK: %[[SQ_SUM_2:.*]] = arith.addf %[[SQ_SUM_1]], %[[SQ_IMAG]] : f32
+// CHECK: %[[LOG_SQ_SUM:.*]] = math.log1p %[[SQ_SUM_2]] : f32
 // CHECK: %[[RESULT_REAL:.*]] = arith.mulf %[[LOG_SQ_SUM]], %[[ONE_HALF]] : f32
 // CHECK: %[[REAL_PLUS_ONE:.*]] = arith.addf %[[REAL]], %[[ONE]] : f32
-// CHECK: %[[RESULT_IMAG:.*]] = math.atan2 %[[IMAG]], %[[REAL_PLUS_ONE]] : f32 
+// CHECK: %[[RESULT_IMAG:.*]] = math.atan2 %[[IMAG]], %[[REAL_PLUS_ONE]] : f32
 // CHECK: %[[RESULT:.*]] = complex.create %[[RESULT_REAL]], %[[RESULT_IMAG]] : complex<f32>
 // CHECK: return %[[RESULT]] : complex<f32>
 
 // -----
 
 // CHECK-LABEL: func @complex_mul
 // CHECK-SAME: (%[[LHS:.*]]: complex<f32>, %[[RHS:.*]]: complex<f32>)
 func.func @complex_mul(%lhs: complex<f32>, %rhs: complex<f32>) -> complex<f32> {

mlir/test/Conversion/FuncToLLVM/convert-types.mlir

 // RUN: mlir-opt -test-convert-call-op %s | FileCheck %s
 
 // CHECK-LABEL: @ptr
 // CHECK: !llvm.ptr<i42>
 func.func private @ptr() -> !llvm.ptr<!test.smpla>
 
 // CHECK-LABEL: @opaque_ptr
 // CHECK: !llvm.ptr
 // CHECK-NOT: <
 func.func private @opaque_ptr() -> !llvm.ptr
 
 // CHECK-LABEL: @ptr_ptr()
-// CHECK: !llvm.ptr<ptr<i42>> 
+// CHECK: !llvm.ptr<ptr<i42>>
 func.func private @ptr_ptr() -> !llvm.ptr<!llvm.ptr<!test.smpla>>
 
 // CHECK-LABEL: @struct_ptr()
-// CHECK: !llvm.struct<(ptr<i42>)> 
+// CHECK: !llvm.struct<(ptr<i42>)>
 func.func private @struct_ptr() -> !llvm.struct<(ptr<!test.smpla>)>
 
 // CHECK-LABEL: @named_struct_ptr()
 // CHECK: !llvm.struct<"_Converted_named", (ptr<i42>)>
 func.func private @named_struct_ptr() -> !llvm.struct<"named", (ptr<!test.smpla>)>
 
 // CHECK-LABEL: @named_no_convert
 // CHECK: !llvm.struct<"no_convert", (ptr<struct<"no_convert">>)>
 func.func private @named_no_convert() -> !llvm.struct<"no_convert", (ptr<struct<"no_convert">>)>
 
 // CHECK-LABEL: @array_ptr()
-// CHECK: !llvm.array<10 x ptr<i42>> 
+// CHECK: !llvm.array<10 x ptr<i42>>
 func.func private @array_ptr() -> !llvm.array<10 x ptr<!test.smpla>>
 
 // CHECK-LABEL: @func()
 // CHECK: !llvm.ptr<func<i42 (i42)>>
 func.func private @func() -> !llvm.ptr<!llvm.func<!test.smpla (!test.smpla)>>
 
 // TODO: support conversion of recursive types in the conversion infra.
 // CHECK-LABEL: @named_recursive()
 // CHECK: !llvm.struct<"_Converted_recursive", (ptr<i42>, ptr<struct<"_Converted_recursive">>)>
 func.func private @named_recursive() -> !llvm.struct<"recursive", (ptr<!test.smpla>, ptr<struct<"recursive">>)>
 

mlir/test/Conversion/FuncToLLVM/func-memref-return.mlir

func.func @check_memref_func_call(%in : memref<10xi8>) -> memref<20xi8> {
   // BAREPTR-NEXT:    %[[res:.*]] = llvm.extractvalue %[[outDesc]][1] : !llvm.struct<(ptr<i8>, ptr<i8>, i64, array<1 x i64>, array<1 x i64>)>
   // BAREPTR-NEXT:    llvm.return %[[res]] : !llvm.ptr<i8>
   return %res : memref<20xi8>
 }
 
 // -----
 
 // BAREPTR-LABEL: func @check_return(
-// BAREPTR-SAME: %{{.*}}: memref<?xi8>) -> memref<?xi8> 
+// BAREPTR-SAME: %{{.*}}: memref<?xi8>) -> memref<?xi8>
 func.func @check_return(%in : memref<?xi8>) -> memref<?xi8> {
   // BAREPTR: llvm.return {{.*}} : !llvm.struct<(ptr<i8>, ptr<i8>, i64, array<1 x i64>, array<1 x i64>)>
   return %in : memref<?xi8>
 }

mlir/test/Conversion/MemRefToLLVM/convert-alloca-scope.mlir

 // RUN: mlir-opt -convert-memref-to-llvm %s | FileCheck %s
 
 // CHECK-LABEL: @empty
 func.func @empty() {
-  // CHECK: llvm.intr.stacksave 
+  // CHECK: llvm.intr.stacksave
   // CHECK: llvm.br
   memref.alloca_scope {
     memref.alloca_scope.return
   }
-  // CHECK: llvm.intr.stackrestore 
+  // CHECK: llvm.intr.stackrestore
   // CHECK: llvm.br
   return
 }
 
 // CHECK-LABEL: @returns_nothing
 func.func @returns_nothing(%b: f32) {
   %a = arith.constant 10.0 : f32
-  // CHECK: llvm.intr.stacksave 
+  // CHECK: llvm.intr.stacksave
   memref.alloca_scope {
     %c = arith.addf %a, %b : f32
     memref.alloca_scope.return
   }
-  // CHECK: llvm.intr.stackrestore 
+  // CHECK: llvm.intr.stackrestore
   return
 }
 
 // CHECK-LABEL: @returns_one_value
 func.func @returns_one_value(%b: f32) -> f32 {
   %a = arith.constant 10.0 : f32
-  // CHECK: llvm.intr.stacksave 
+  // CHECK: llvm.intr.stacksave
   %result = memref.alloca_scope -> f32 {
     %c = arith.addf %a, %b : f32
     memref.alloca_scope.return %c: f32
   }
-  // CHECK: llvm.intr.stackrestore 
+  // CHECK: llvm.intr.stackrestore
   return %result : f32
 }
 
 // CHECK-LABEL: @returns_multiple_values
 func.func @returns_multiple_values(%b: f32) -> f32 {
   %a = arith.constant 10.0 : f32
-  // CHECK: llvm.intr.stacksave 
+  // CHECK: llvm.intr.stacksave
   %result1, %result2 = memref.alloca_scope -> (f32, f32) {
     %c = arith.addf %a, %b : f32
     %d = arith.subf %a, %b : f32
     memref.alloca_scope.return %c, %d: f32, f32
   }
-  // CHECK: llvm.intr.stackrestore 
+  // CHECK: llvm.intr.stackrestore
   %result = arith.addf %result1, %result2 : f32
   return %result : f32
 }

mlir/test/Conversion/NVGPUToNVVM/nvgpu-to-nvvm.mlir

 // RUN: mlir-opt --convert-nvgpu-to-nvvm --split-input-file %s | FileCheck %s
 
 // CHECK-LABEL: @m16n8k16_fp16
 func.func @m16n8k16_fp16(%arg0: vector<4x2xf16>, %arg1: vector<2x2xf16>, %arg2: vector<2x2xf16>) -> vector<2x2xf16> {
   // CHECK: llvm.extractvalue %{{.*}}[0] : !llvm.array<4 x vector<2xf16>>
   // CHECK: llvm.extractvalue %{{.*}}[1] : !llvm.array<4 x vector<2xf16>>
   // CHECK: llvm.extractvalue %{{.*}}[2] : !llvm.array<4 x vector<2xf16>>
   // CHECK: llvm.extractvalue %{{.*}}[3] : !llvm.array<4 x vector<2xf16>>
   // CHECK: llvm.extractvalue %{{.*}}[0] : !llvm.array<2 x vector<2xf16>>
   // CHECK: llvm.extractvalue %{{.*}}[1] : !llvm.array<2 x vector<2xf16>>
   // CHECK: llvm.extractvalue %{{.*}}[0] : !llvm.array<2 x vector<2xf16>>
   // CHECK: llvm.extractvalue %{{.*}}[1] : !llvm.array<2 x vector<2xf16>>
   // CHECK-NOT llvm.extractvalue
   // CHECK: [[d:%.+]] = nvvm.mma.sync
   // CHECK-SAME: shape = #nvvm.shape<m = 16, n = 8, k = 16>
-  %d = nvgpu.mma.sync (%arg0, %arg1, %arg2) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>    
-  // CHECK-DAG: llvm.extractvalue [[d]][0] : !llvm.struct<(vector<2xf16>, vector<2xf16>)>    
+  %d = nvgpu.mma.sync (%arg0, %arg1, %arg2) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+  // CHECK-DAG: llvm.extractvalue [[d]][0] : !llvm.struct<(vector<2xf16>, vector<2xf16>)>
   // CHECK-DAG: llvm.extractvalue [[d]][1] : !llvm.struct<(vector<2xf16>, vector<2xf16>)>
   // CHECK: llvm.mlir.undef : !llvm.array<2 x vector<2xf16>>
   // CHECK-DAG: llvm.insertvalue {{%.+}}, {{%.+}}[0] : !llvm.array<2 x vector<2xf16>>
-  // CHECK-DAG: llvm.insertvalue {{%.+}}, {{%.+}}[1] : !llvm.array<2 x vector<2xf16>>      
+  // CHECK-DAG: llvm.insertvalue {{%.+}}, {{%.+}}[1] : !llvm.array<2 x vector<2xf16>>
   return %d : vector<2x2xf16>
 }
 
 // -----
 
 // Same as above but with fp32 acumulation type.
 
 // CHECK-LABEL: @m16n8k16_fp16_fp32
 func.func @m16n8k16_fp16_fp32(%arg0: vector<4x2xf16>, %arg1: vector<2x2xf16>, %arg2: vector<2x2xf32>) -> vector<2x2xf32> {
   // We just need to check the mma instruction and the manipulatin of the result.
   // CHECK: [[d:%.+]] = nvvm.mma.sync
   // CHECK-SAME: shape = #nvvm.shape<m = 16, n = 8, k = 16>
   // CHECK-SAME: (vector<2xf16>, vector<2xf16>, f32) -> !llvm.struct<(f32, f32, f32, f32)>
-  %d = nvgpu.mma.sync (%arg0, %arg1, %arg2) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf32>) -> vector<2x2xf32>    
+  %d = nvgpu.mma.sync (%arg0, %arg1, %arg2) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf32>) -> vector<2x2xf32>
   // CHECK: [[undef:%.+]] = llvm.mlir.undef : vector<2xf32>
   // CHECK-DAG: llvm.extractvalue [[d]][0] : !llvm.struct<(f32, f32, f32, f32)>
   // CHECK-DAG: llvm.extractvalue [[d]][1] : !llvm.struct<(f32, f32, f32, f32)>
   // CHECK: [[d00:%.+]] = llvm.insertelement {{%.+}}, [[undef]][{{.*}}] : vector<2xf32>
   // CHECK: [[d01:%.+]] = llvm.insertelement {{%.+}}, [[d00]][{{.*}}] : vector<2xf32>
 
-  // CHECK: [[undef:%.+]] = llvm.mlir.undef : vector<2xf32>  
+  // CHECK: [[undef:%.+]] = llvm.mlir.undef : vector<2xf32>
   // CHECK-DAG: llvm.extractvalue [[d]][2] : !llvm.struct<(f32, f32, f32, f32)>
   // CHECK-DAG: llvm.extractvalue [[d]][3] : !llvm.struct<(f32, f32, f32, f32)>
   // CHECK: [[d10:%.+]] = llvm.insertelement {{%.+}}, [[undef]][{{.*}}] : vector<2xf32>
   // CHECK: [[d11:%.+]] = llvm.insertelement {{%.+}}, [[d10]][{{.*}}] : vector<2xf32>
-  
   // CHECK-DAG: llvm.insertvalue [[d01]], {{%.+}}[0] : !llvm.array<2 x vector<2xf32>>
-  // CHECK-DAG: llvm.insertvalue [[d11]], {{%.+}}[1] : !llvm.array<2 x vector<2xf32>>      
+  // CHECK-DAG: llvm.insertvalue [[d11]], {{%.+}}[1] : !llvm.array<2 x vector<2xf32>>
   return %d : vector<2x2xf32>
 }
 
 // -----
 
 // CHECK-LABEL: @m16n8k8_fp16
 func.func @m16n8k8_fp16(%arg0: vector<2x2xf16>, %arg1: vector<1x2xf16>, %arg2: vector<2x2xf16>) -> vector<2x2xf16> {
   // CHECK: llvm.extractvalue %{{.*}}[0] : !llvm.array<2 x vector<2xf16>>
   // CHECK: llvm.extractvalue %{{.*}}[1] : !llvm.array<2 x vector<2xf16>>
   // CHECK: llvm.extractvalue %{{.*}}[0] : !llvm.array<1 x vector<2xf16>>
   // CHECK: llvm.extractvalue %{{.*}}[0] : !llvm.array<2 x vector<2xf16>>
   // CHECK: llvm.extractvalue %{{.*}}[1] : !llvm.array<2 x vector<2xf16>>
   // CHECK-NOT llvm.extractvalue
   // CHECK: [[d:%.+]] = nvvm.mma.sync
   // CHECK-SAME: shape = #nvvm.shape<m = 16, n = 8, k = 8>
-  %d = nvgpu.mma.sync (%arg0, %arg1, %arg2) {mmaShape = [16, 8, 8]} : (vector<2x2xf16>, vector<1x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>    
-  // CHECK-DAG: llvm.extractvalue [[d]][0] : !llvm.struct<(vector<2xf16>, vector<2xf16>)>    
+  %d = nvgpu.mma.sync (%arg0, %arg1, %arg2) {mmaShape = [16, 8, 8]} : (vector<2x2xf16>, vector<1x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+  // CHECK-DAG: llvm.extractvalue [[d]][0] : !llvm.struct<(vector<2xf16>, vector<2xf16>)>
   // CHECK-DAG: llvm.extractvalue [[d]][1] : !llvm.struct<(vector<2xf16>, vector<2xf16>)>
   // CHECK: llvm.mlir.undef : !llvm.array<2 x vector<2xf16>>
   // CHECK-DAG: llvm.insertvalue {{%.+}}, {{%.+}}[0] : !llvm.array<2 x vector<2xf16>>
-  // CHECK-DAG: llvm.insertvalue {{%.+}}, {{%.+}}[1] : !llvm.array<2 x vector<2xf16>>      
+  // CHECK-DAG: llvm.insertvalue {{%.+}}, {{%.+}}[1] : !llvm.array<2 x vector<2xf16>>
   // CHECK: return
   return %d : vector<2x2xf16>
 }
 
 // -----
 
 
 // CHECK-LABEL: @m16n8k32_int8

 
 // -----
 
 // CHECK-LABEL: @m16n8k32_i4
 func.func @m16n8k32_i4(%arg0: vector<2x8xi4>, %arg1: vector<1x8xi4>, %arg2: vector<2x2xi32>) -> vector<2x2xi32> {
   // CHECK: [[el:%.+]] = llvm.extractvalue %{{.*}}[{{.*}}] : !llvm.array<2 x vector<8xi4>>
   // CHECK: llvm.bitcast [[el]] : vector<8xi4> to i32
   // CHECK: [[el:%.+]] = llvm.extractvalue %{{.*}}[{{.*}}] : !llvm.array<2 x vector<8xi4>>
-  // CHECK: llvm.bitcast [[el]] : vector<8xi4> to i32    
+  // CHECK: llvm.bitcast [[el]] : vector<8xi4> to i32
   // CHECK: [[el:%.+]] = llvm.extractvalue %{{.*}}[{{.*}}] : !llvm.array<1 x vector<8xi4>>
-  // CHECK: llvm.bitcast [[el]] : vector<8xi4> to i32  
+  // CHECK: llvm.bitcast [[el]] : vector<8xi4> to i32
   // CHECK: [[el:%.+]] = llvm.extractvalue %{{.*}}[{{.*}}] : !llvm.array<2 x vector<2xi32>>
   // CHECK: [[el:%.+]] = llvm.extractvalue %{{.*}}[{{.*}}] : !llvm.array<2 x vector<2xi32>>
   // CHECK: [[d:%.+]] = nvvm.mma.sync
   // CHECK-SAME: intOverflowBehavior = #nvvm.mma_int_overflow<satfinite>
   // CHECK-SAME: multiplicandAPtxType = #nvvm.mma_type<s4>
   // CHECK-SAME: multiplicandBPtxType = #nvvm.mma_type<s4>
   // CHECK-SAME: shape = #nvvm.shape<m = 16, n = 8, k = 32>
   %d = nvgpu.mma.sync (%arg0, %arg1, %arg2) {mmaShape = [16, 8, 32]} : (vector<2x8xi4>, vector<1x8xi4>, vector<2x2xi32>) -> vector<2x2xi32>

 func.func @m8n8k4_f64(%arg0: vector<1x1xf64>, %arg1: vector<1x1xf64>, %arg2: vector<1x2xf64>) -> vector<1x2xf64> {
   // CHECK: llvm.extractvalue
   // CHECK: llvm.extractvalue
   // CHECK: llvm.extractvalue
   // CHECK: [[d:%.+]] = nvvm.mma.sync A[{{%.+}}] B[{{%.+}}] C[{{%.+}}, {{%.+}}]
   // CHECK-SAME: shape = #nvvm.shape<m = 8, n = 8, k = 4>
   %d = nvgpu.mma.sync (%arg0, %arg1, %arg2) {mmaShape = [8, 8, 4]} : (vector<1x1xf64>, vector<1x1xf64>, vector<1x2xf64>) -> vector<1x2xf64>
   // CHECK: llvm.mlir.undef : vector<2xf64>
-  // CHECK-DAG: llvm.extractvalue [[d]][0] : !llvm.struct<(f64, f64)>    
+  // CHECK-DAG: llvm.extractvalue [[d]][0] : !llvm.struct<(f64, f64)>
   // CHECK-DAG: llvm.extractvalue [[d]][1] : !llvm.struct<(f64, f64)>
   // CHECK-COUNT-2: llvm.insertelement {{.*}} : vector<2xf64>
   // CHECK-DAG: llvm.insertvalue {{%.+}}, {{%.+}}[0] : !llvm.array<1 x vector<2xf64>>
   // CHECK: return
   return %d : vector<1x2xf64>
 }
 
 // -----

 }
 
 // -----
 
 // CHECK-LABEL: @ldmatrix_x1
 func.func @ldmatrix_x1(%arg0: memref<128x128xf16, 3>) ->  vector<1x2xf16> {
   %c0  = arith.constant 0 : index
   // CHECK: nvvm.ldmatrix {{%.+}} {layout = #nvvm.mma_layout<row>, num = 1 : i32} {{.*}} -> i32
-  %a = nvgpu.ldmatrix %arg0[%c0, %c0] {transpose = false, numTiles = 1 : i32} : memref<128x128xf16, 3> -> vector<1x2xf16>    
+  %a = nvgpu.ldmatrix %arg0[%c0, %c0] {transpose = false, numTiles = 1 : i32} : memref<128x128xf16, 3> -> vector<1x2xf16>
   // CHECK: llvm.bitcast
-  // CHECK: llvm.insertvalue    
+  // CHECK: llvm.insertvalue
   return %a : vector<1x2xf16>
 }
 
 // -----
 
 // CHECK-LABEL: @m16n8k4_tf32
-func.func @m16n8k4_tf32(%arg0: vector<2x1xf32>, %arg1: vector<1x1xf32>, %arg2: vector<2x2xf32>) -> vector<2x2xf32> {  
+func.func @m16n8k4_tf32(%arg0: vector<2x1xf32>, %arg1: vector<1x1xf32>, %arg2: vector<2x2xf32>) -> vector<2x2xf32> {
   // The A, B operand should be bitcast to i32
   // CHECK: llvm.extractvalue
-  // CHECK: llvm.bitcast {{.*}} : vector<1xf32> to i32  
+  // CHECK: llvm.bitcast {{.*}} : vector<1xf32> to i32
   // CHECK: llvm.extractvalue
   // CHECK: llvm.bitcast {{.*}} : vector<1xf32> to i32
   // CHECK: llvm.extractvalue
   // CHECK: llvm.bitcast {{.*}} : vector<1xf32> to i32
 
   // CHECK: [[d:%.+]] = nvvm.mma.sync A[{{%.+}}, {{%.+}}] B[{{%.+}}] C[{{%.+}}, {{%.+}}, {{%.+}}, {{%.+}}]
   // CHECK-SAME: multiplicandAPtxType = #nvvm.mma_type<tf32>
   // CHECK-SAME: multiplicandBPtxType = #nvvm.mma_type<tf32>
   // CHECK-SAME: shape = #nvvm.shape<m = 16, n = 8, k = 4>
-  // CHECK-SAME: -> !llvm.struct<(f32, f32, f32, f32)>  
-  %d = nvgpu.mma.sync (%arg0, %arg1, %arg2) {mmaShape = [16, 8, 4], tf32Enabled} : (vector<2x1xf32>, vector<1x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>  
+  // CHECK-SAME: -> !llvm.struct<(f32, f32, f32, f32)>
+  %d = nvgpu.mma.sync (%arg0, %arg1, %arg2) {mmaShape = [16, 8, 4], tf32Enabled} : (vector<2x1xf32>, vector<1x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
   // CHECK: [[undef:%.+]] = llvm.mlir.undef : vector<2xf32>
   // CHECK-DAG: llvm.extractvalue [[d]][0] : !llvm.struct<(f32, f32, f32, f32)>
   // CHECK-DAG: llvm.extractvalue [[d]][1] : !llvm.struct<(f32, f32, f32, f32)>
   // CHECK: [[d00:%.+]] = llvm.insertelement {{%.+}}, [[undef]][{{.*}}] : vector<2xf32>
   // CHECK: [[d01:%.+]] = llvm.insertelement {{%.+}}, [[d00]][{{.*}}] : vector<2xf32>
 
-  // CHECK: [[undef:%.+]] = llvm.mlir.undef : vector<2xf32>  
+  // CHECK: [[undef:%.+]] = llvm.mlir.undef : vector<2xf32>
   // CHECK-DAG: llvm.extractvalue [[d]][2] : !llvm.struct<(f32, f32, f32, f32)>
   // CHECK-DAG: llvm.extractvalue [[d]][3] : !llvm.struct<(f32, f32, f32, f32)>
   // CHECK: [[d10:%.+]] = llvm.insertelement {{%.+}}, [[undef]][{{.*}}] : vector<2xf32>
   // CHECK: [[d11:%.+]] = llvm.insertelement {{%.+}}, [[d10]][{{.*}}] : vector<2xf32>
-  
   // CHECK-DAG: llvm.insertvalue [[d01]], {{%.+}}[0] : !llvm.array<2 x vector<2xf32>>
-  // CHECK-DAG: llvm.insertvalue [[d11]], {{%.+}}[1] : !llvm.array<2 x vector<2xf32>>   
+  // CHECK-DAG: llvm.insertvalue [[d11]], {{%.+}}[1] : !llvm.array<2 x vector<2xf32>>
   return %d : vector<2x2xf32>
 }
 
 // -----
 
 // CHECK-LABEL: @async_cp(
 // CHECK-SAME: %[[IDX:[a-zA-Z0-9_]+]]: index)
 func.func @async_cp(

 
 // CHECK-LABEL: @async_cp_i4(
 // CHECK-SAME: %[[IDX:[a-zA-Z0-9_]+]]: index)
 func.func @async_cp_i4(
   %src: memref<128x64xi4>, %dst: memref<128x128xi4, 3>, %i : index) -> !nvgpu.device.async.token {
   // CHECK: %[[IDX1:.*]] = builtin.unrealized_conversion_cast %[[IDX]] : index to i64
   // CHECK-DAG: %[[BASEDST:.*]] = llvm.extractvalue %{{.*}}[1] : !llvm.struct<(ptr<i4, 3>, ptr<i4, 3>, i64, array<2 x i64>, array<2 x i64>)>
   // CHECK-DAG: %[[S0:.*]] = llvm.mlir.constant(128 : index) : i64
-  // CHECK-DAG: %[[LI:.*]] = llvm.mul %[[IDX1]], %[[S0]] : i64    
+  // CHECK-DAG: %[[LI:.*]] = llvm.mul %[[IDX1]], %[[S0]] : i64
   // CHECK-DAG: %[[FI1:.*]] = llvm.add %[[LI]], %[[IDX1]] : i64
   // CHECK-DAG: %[[ADDRESSDST:.*]] = llvm.getelementptr %[[BASEDST]][%[[FI1]]] : (!llvm.ptr<i4, 3>, i64) -> !llvm.ptr<i4, 3>
   // CHECK-DAG: %[[CAST0:.*]] = llvm.bitcast %[[ADDRESSDST]] : !llvm.ptr<i4, 3> to !llvm.ptr<i8, 3>
   // CHECK-DAG: %[[BASESRC:.*]] = llvm.extractvalue %{{.*}}[1] : !llvm.struct<(ptr<i4>, ptr<i4>, i64, array<2 x i64>, array<2 x i64>)>
   // CHECK-DAG: %[[S2:.*]] = llvm.mlir.constant(64 : index) : i64
   // CHECK-DAG: %[[FI2:.*]] = llvm.mul %[[IDX1]], %[[S2]]  : i64
   // CHECK-DAG: %[[FI3:.*]] = llvm.add %[[FI2]], %[[IDX1]]  : i64
   // CHECK-DAG: %[[ADDRESSSRC:.*]] = llvm.getelementptr %[[BASESRC]][%[[FI3]]] : (!llvm.ptr<i4>, i64) -> !llvm.ptr<i4>
func.func @mma_sp_sync_f16_16832(%arg0: vector<4x2xf16>,
   // CHECK: %[[sparseMetadata:.+]] = llvm.bitcast %{{.+}} : vector<2xi16> to i32
   // CHECK: %[[sparseSelector:.+]] = llvm.mlir.constant(0 : i32) : i32
 
   // CHECK: %[[d:.+]] = llvm.inline_asm has_side_effects asm_dialect = att
   // CHECK-SAME: "mma.sp.sync.aligned.m16n8k32.row.col.f16.f16.f16.f16 {$0,$1},{$2,$3,$4,$5},{$6,$7,$8,$9},{$10,$11},$12,$13;"
   // CHECK-SAME: "=r,=r,r,r,r,r,r,r,r,r,r,r,r,r"
   // CHECK-SAME: %[[sparseMetadata]], %[[sparseSelector]] :
   // CHECK-SAME: -> !llvm.struct<(vector<2xf16>, vector<2xf16>)>
-  
   %d = nvgpu.mma.sp.sync(%arg0, %arg1, %arg2) metadata(%arg3) {mmaShape = [16, 8, 32]} :
     (vector<4x2xf16>, vector<4x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
 
-  // CHECK-DAG: llvm.extractvalue %[[d]][0] : !llvm.struct<(vector<2xf16>, vector<2xf16>)>    
+  // CHECK-DAG: llvm.extractvalue %[[d]][0] : !llvm.struct<(vector<2xf16>, vector<2xf16>)>
   // CHECK-DAG: llvm.extractvalue %[[d]][1] : !llvm.struct<(vector<2xf16>, vector<2xf16>)>
   //     CHECK: llvm.mlir.undef : !llvm.array<2 x vector<2xf16>>
   //     CHECK: llvm.insertvalue %{{.+}}, %{{.+}}[0] : !llvm.array<2 x vector<2xf16>>
   //     CHECK: llvm.insertvalue %{{.+}}, %{{.+}}[1] : !llvm.array<2 x vector<2xf16>>
   return %d : vector<2x2xf16>
 }
 
 // -----
 
 // CHECK-LABEL: func @mma_sp_sync_f16_16816(
 func.func @mma_sp_sync_f16_16816(%arg0: vector<2x2xf16>,
                                  %arg1: vector<2x2xf16>,
                                  %arg2: vector<2x2xf16>,
                                  %arg3: vector<2xi16>) -> vector<2x2xf16> {
 
   // CHECK: llvm.extractvalue %{{.*}}[0] : !llvm.array<2 x vector<2xf16>>
-  // CHECK: llvm.extractvalue %{{.*}}[1] : !llvm.array<2 x vector<2xf16>>  
+  // CHECK: llvm.extractvalue %{{.*}}[1] : !llvm.array<2 x vector<2xf16>>
 
   // CHECK: llvm.extractvalue %{{.*}}[0] : !llvm.array<2 x vector<2xf16>>
-  // CHECK: llvm.extractvalue %{{.*}}[1] : !llvm.array<2 x vector<2xf16>>  
+  // CHECK: llvm.extractvalue %{{.*}}[1] : !llvm.array<2 x vector<2xf16>>
 
   // CHECK: llvm.extractvalue %{{.*}}[0] : !llvm.array<2 x vector<2xf16>>
   // CHECK: llvm.extractvalue %{{.*}}[1] : !llvm.array<2 x vector<2xf16>>
 
   // CHECK-NOT llvm.extractvalue
 
   // CHECK: %[[sparseMetadata:.+]] = llvm.bitcast %{{.+}} : vector<2xi16> to i32
   // CHECK: %[[sparseSelector:.+]] = llvm.mlir.constant(0 : i32) : i32
func.func @mma_sp_sync_i8_16864(%arg0: vector<4x4xi8>,
   // CHECK: llvm.bitcast %{{.+}} : vector<4xi8> to i32
   // CHECK: llvm.extractvalue %{{.*}}[2] : !llvm.array<4 x vector<4xi8>>
   // CHECK: llvm.bitcast %{{.+}} : vector<4xi8> to i32
   // CHECK: llvm.extractvalue %{{.*}}[3] : !llvm.array<4 x vector<4xi8>>
 
 
   // CHECK: llvm.extractvalue %{{.*}}[0] : !llvm.array<4 x vector<4xi8>>
   // CHECK: llvm.bitcast %{{.+}} : vector<4xi8> to i32
-  // CHECK: llvm.extractvalue %{{.*}}[1] : !llvm.array<4 x vector<4xi8>>  
+  // CHECK: llvm.extractvalue %{{.*}}[1] : !llvm.array<4 x vector<4xi8>>
   // CHECK: llvm.bitcast %{{.+}} : vector<4xi8> to i32
 
   // CHECK: llvm.extractvalue %{{.*}}[{{.*}}] : !llvm.array<2 x vector<2xi32>>
   // CHECK: llvm.extractvalue %{{.*}}[{{.*}}] : !llvm.array<2 x vector<2xi32>>
 
   // CHECK-NOT llvm.extractvalue
 
   // CHECK: %[[sparseMetadata:.+]] = llvm.bitcast %{{.+}} : vector<2xi16> to i32

mlir/test/Conversion/TosaToArith/tosa-to-arith.mlir

func.func @apply_scale_test_i32(%arg0 : i32, %arg1 : i32, %arg2 : i8) -> (i32) {
   // Apply high-bit rounding.
   // CHECK-DAG: %[[HISHRM1:.+]] = arith.subi %[[HISHR]], %[[C1]]
   // CHECK-DAG: %[[LHISHFT:.+]] = arith.shli %[[C1]], %[[HISHRM1]]
   // CHECK-DAG: %[[LHI:.+]] = arith.select %[[OVER32]], %[[LHISHFT]], %[[C0]]
   // CHECK-DAG: %[[FHI:.+]] = arith.addi %[[LRNDED]], %[[LHI]]
 
   // Combine hi-low into the final result.
   // CHECK-DAG: %[[HIL:.+]] = arith.shli %[[FHI]], %[[HISHL]]
-  // CHECK-DAG: %[[HIALIGN:.+]] = arith.shrsi %[[HIL:.+]], %[[HISHR]] 
+  // CHECK-DAG: %[[HIALIGN:.+]] = arith.shrsi %[[HIL:.+]], %[[HISHR]]
   // CHECK-DAG: %[[LOR:.+]] = arith.shrui %[[LADD]], %[[S32]]
   // CHECK-DAG: %[[LOWALIGN:.+]] = arith.select %[[OVER31]], %[[C0]], %[[LOR]]
   // CHECK-DAG: %[[RESULT:.+]] = arith.addi %[[LOWALIGN]], %[[HIALIGN]]
   // CHECK: return %[[RESULT]]
   %res = "tosa.apply_scale"(%arg0, %arg1, %arg2) {double_round = true} : (i32, i32, i8) -> i32
   return %res : i32
 }
 

mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-named.mlir

 func.func @depthwise_conv_strides(%arg0 : tensor<1x11x9x3xf32>, %arg1 : tensor<3x1x3x11xf32>, %arg2 : tensor<33xf32>) -> () {
   // CHECK: [[INIT:%.+]] = tensor.empty()
   // CHECK: [[CST0:%.+]] = arith.constant 0
   // CHECK: [[FILL:%.+]] = linalg.fill ins([[CST0]]{{.*}}outs([[INIT]]
   // CHECK: [[OUT:%.+]] = tensor.empty()
   // CHECK: [[DEPTH:%.+]] = linalg.depthwise_conv_2d_nhwc_hwcm {dilations = dense<1> : tensor<2xi64>, strides = dense<2> : tensor<2xi64>} ins(%arg0, %arg1 : tensor<1x11x9x3xf32>, tensor<3x1x3x11xf32>) outs([[FILL]] : tensor<1x5x5x3x11xf32>)
   // CHECK: [[COLLAPSED:%.+]] = tensor.collapse_shape [[DEPTH]] {{\[}}[0], [1], [2], [3, 4]]
   // CHECK: [[BIAS:%.+]] = linalg.generic {indexing_maps = [#[[$MAP0]], #[[$MAP1]], #[[$MAP1]]], iterator_types = ["parallel", "parallel", "parallel", "parallel"]} ins(%arg2, [[COLLAPSED]] : tensor<33xf32>, tensor<1x5x5x33xf32>) outs([[OUT]] : tensor<1x5x5x33xf32>) {
-  // CHECK: ^bb0(%[[ARG3:[0-9a-zA-Z_]+]]: f32, %[[ARG4:[0-9a-zA-Z_]+]]: f32, %[[ARG5:[0-9a-zA-Z_]+]]: f32):  
+  // CHECK: ^bb0(%[[ARG3:[0-9a-zA-Z_]+]]: f32, %[[ARG4:[0-9a-zA-Z_]+]]: f32, %[[ARG5:[0-9a-zA-Z_]+]]: f32):
   // CHECK:   [[ADD:%.+]] = arith.addf %[[ARG3]], %[[ARG4]] : f32
   // CHECK:   linalg.yield [[ADD]] : f32
   // CHECK: } -> tensor<1x5x5x33xf32>
   %2 = "tosa.depthwise_conv2d"(%arg0, %arg1, %arg2) { pad = [0, 0, 0, 0], stride = [2, 2], dilation = [1, 1] } : (tensor<1x11x9x3xf32>, tensor<3x1x3x11xf32>, tensor<33xf32>)  -> (tensor<1x5x5x33xf32>)
   return
 }
 
 // -----
func.func @depthwise_conv_quant(%arg0 : tensor<1x12x12x4xi8>, %arg1 : tensor<3x3x4x128xi8>, %arg2 : tensor<512xi32>) -> () {
   // CHECK: [[CST0:%.+]] = arith.constant 0
   // CHECK: [[FILL:%.+]] = linalg.fill ins([[CST0]]{{.*}}outs([[INIT]]
   // CHECK: [[OUT:%.+]] = tensor.empty()
   // CHECK: [[C128:%.+]] = arith.constant -128
   // CHECK: [[C42:%.+]] = arith.constant 42
   // CHECK: [[DEPTH:%.+]] = linalg.depthwise_conv_2d_nhwc_hwcm_q {dilations = dense<1> : tensor<2xi64>, strides = dense<1> : tensor<2xi64>} ins([[PAD]], %arg1, [[C128]], [[C42]] : tensor<1x14x14x4xi8>, tensor<3x3x4x128xi8>, i32, i32) outs([[FILL]] : tensor<1x12x12x4x128xi32>)
   // CHECK: [[COLLAPSED:%.+]] = tensor.collapse_shape [[DEPTH]] {{\[}}[0], [1], [2], [3, 4]]
   // CHECK: [[BIAS:%.+]] = linalg.generic {indexing_maps = [#[[$MAP0]], #[[$MAP1]], #[[$MAP1]]], iterator_types = ["parallel", "parallel", "parallel", "parallel"]} ins(%arg2, [[COLLAPSED]] : tensor<512xi32>, tensor<1x12x12x512xi32>) outs([[OUT]] : tensor<1x12x12x512xi32>) {
-  // CHECK: ^bb0(%[[ARG3:[0-9a-zA-Z_]+]]: i32, %[[ARG4:[0-9a-zA-Z_]+]]: i32, %[[ARG5:[0-9a-zA-Z_]+]]: i32):  
+  // CHECK: ^bb0(%[[ARG3:[0-9a-zA-Z_]+]]: i32, %[[ARG4:[0-9a-zA-Z_]+]]: i32, %[[ARG5:[0-9a-zA-Z_]+]]: i32):
   // CHECK:   [[ADD:%.+]] = arith.addi %[[ARG3]], %[[ARG4]] : i32
   // CHECK:   linalg.yield [[ADD]] : i32
   // CHECK: } -> tensor<1x12x12x512xi32>
   %0 = "tosa.depthwise_conv2d"(%arg0, %arg1, %arg2) {pad = [1, 1, 1, 1], quantization_info = #tosa.conv_quant<input_zp = -128, weight_zp = 42>, stride = [1, 1], dilation = [1, 1] } : (tensor<1x12x12x4xi8>, tensor<3x3x4x128xi8>, tensor<512xi32>)  -> tensor<1x12x12x512xi32>
   return
 }
 
 // -----
 
 // CHECK: #[[$MAP0:.*]] = affine_map<(d0, d1, d2, d3) -> (d3)>
 // CHECK: #[[$MAP1:.*]] = affine_map<(d0, d1, d2, d3) -> (d0, d1, d2, d3)>
 
 // CHECK-LABEL: @depthwise_conv_quant_dilations
 func.func @depthwise_conv_quant_dilations(%arg0 : tensor<1x14x14x4xi8>, %arg1 : tensor<3x3x4x128xi8>, %arg2 : tensor<512xi32>) -> () {
   // CHECK: [[INIT:%.+]] = tensor.empty()
   // CHECK: [[CST0:%.+]] = arith.constant 0
   // CHECK: [[FILL:%.+]] = linalg.fill ins([[CST0]]{{.*}}outs([[INIT]]
   // CHECK: [[OUT:%.+]] = tensor.empty()
   // CHECK: [[C128:%.+]] = arith.constant -128
   // CHECK: [[C42:%.+]] = arith.constant 42
   // CHECK: [[DEPTH:%.+]] = linalg.depthwise_conv_2d_nhwc_hwcm_q {dilations = dense<2> : tensor<2xi64>, strides = dense<1> : tensor<2xi64>} ins(%arg0, %arg1, [[C128]], [[C42]] : tensor<1x14x14x4xi8>, tensor<3x3x4x128xi8>, i32, i32) outs([[FILL]] : tensor<1x10x10x4x128xi32>)
   // CHECK: [[COLLAPSED:%.+]] = tensor.collapse_shape [[DEPTH]] {{\[}}[0], [1], [2], [3, 4]]
   // CHECK: [[BIAS:%.+]] = linalg.generic {indexing_maps = [#[[$MAP0]], #[[$MAP1]], #[[$MAP1]]], iterator_types = ["parallel", "parallel", "parallel", "parallel"]} ins(%arg2, [[COLLAPSED]] : tensor<512xi32>, tensor<1x10x10x512xi32>) outs([[OUT]] : tensor<1x10x10x512xi32>) {
-  // CHECK: ^bb0(%[[ARG3:[0-9a-zA-Z_]+]]: i32, %[[ARG4:[0-9a-zA-Z_]+]]: i32, %[[ARG5:[0-9a-zA-Z_]+]]: i32):  
+  // CHECK: ^bb0(%[[ARG3:[0-9a-zA-Z_]+]]: i32, %[[ARG4:[0-9a-zA-Z_]+]]: i32, %[[ARG5:[0-9a-zA-Z_]+]]: i32):
   // CHECK:   [[ADD:%.+]] = arith.addi %[[ARG3]], %[[ARG4]] : i32
   // CHECK:   linalg.yield [[ADD]] : i32
   // CHECK: } -> tensor<1x10x10x512xi32>
   %0 = "tosa.depthwise_conv2d"(%arg0, %arg1, %arg2) {pad = [0, 0, 0, 0], quantization_info = #tosa.conv_quant<input_zp = -128, weight_zp = 42>, stride = [1, 1], dilation = [2, 2] } : (tensor<1x14x14x4xi8>, tensor<3x3x4x128xi8>, tensor<512xi32>)  -> tensor<1x10x10x512xi32>
   return
 }
 
 // CHECK-LABEL: @depthwise_conv2d_dyn_w_h

mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-resize.mlir

 // RUN: mlir-opt --split-input-file -pass-pipeline="builtin.module(func.func(tosa-to-linalg))" %s -o -| FileCheck %s
 
 // CHECK: #map = affine_map<(d0, d1, d2, d3) -> (d0, d3)>
 // CHECK: #map1 = affine_map<(d0, d1, d2, d3) -> (d0, d1, d2, d3)>
 // CHECK-LABEL: @broadcast_resize_nearest_fp
 func.func @broadcast_resize_nearest_fp(%arg0 : tensor<3x1x1x7xf32>) -> tensor<3x15x13x7xf32> {
-  // CHECK: %[[COLLAPSE:.+]] = tensor.collapse_shape %arg0 
+  // CHECK: %[[COLLAPSE:.+]] = tensor.collapse_shape %arg0
   // CHECK-SAME{literal}: [[0], [1, 2, 3]]
   // CHECK: %[[EMPTY:.+]] = tensor.empty() : tensor<3x15x13x7xf32>
-  // CHECK: %[[GENERIC:.+]] = linalg.generic 
+  // CHECK: %[[GENERIC:.+]] = linalg.generic
   // CHECK-SAME: indexing_maps = [#map, #map1]
   // CHECK-SAME: iterator_types = ["parallel", "parallel", "parallel", "parallel"]}
   // CHECK-SAME: ins(%[[COLLAPSE]] : tensor<3x7xf32>)
   // CHECK-SAME: outs(%[[EMPTY]] : tensor<3x15x13x7xf32>)
   // CHECK-NEXT: ^bb0(%[[IN:.+]]: f32, %[[OUT:.+]]: f32):
   // CHECK:   linalg.yield %[[IN]]
   %resize = "tosa.resize"(%arg0) {mode = "NEAREST_NEIGHBOR", scale = [2, 2, 1, 1], offset = [0, 0], border = [0, 0]} : (tensor<3x1x1x7xf32>) -> tensor<3x15x13x7xf32>
 
   // CHECK: return %[[GENERIC]]
   return %resize : tensor<3x15x13x7xf32>
 }
 
 // -----
 
 // CHECK: #map = affine_map<(d0, d1, d2, d3) -> (d0, d3)>
 // CHECK: #map1 = affine_map<(d0, d1, d2, d3) -> (d0, d1, d2, d3)>
 // CHECK-LABEL: @broadcast_resize_bilinear_fp
 func.func @broadcast_resize_bilinear_fp(%arg0 : tensor<3x1x1x7xf32>) -> tensor<3x15x13x7xf32> {
   // CHECK: %[[COLLAPSE:.+]] = tensor.collapse_shape %arg0
   // CHECK-SAME{literal}: [[0], [1, 2, 3]]
   // CHECK: %[[EMPTY:.+]] = tensor.empty() : tensor<3x15x13x7xf32>
-  // CHECK: %[[GENERIC:.+]] = linalg.generic 
+  // CHECK: %[[GENERIC:.+]] = linalg.generic
   // CHECK-SAME: indexing_maps = [#map, #map1]
   // CHECK-SAME: iterator_types = ["parallel", "parallel", "parallel", "parallel"]}
   // CHECK-SAME: ins(%[[COLLAPSE]] : tensor<3x7xf32>)
   // CHECK-SAME: outs(%[[EMPTY]] : tensor<3x15x13x7xf32>)
   // CHECK-NEXT: ^bb0(%[[IN:.+]]: f32, %[[OUT:.+]]: f32):
   // CHECK:   linalg.yield %[[IN]]
   %resize = "tosa.resize"(%arg0) {mode = "BILINEAR", scale = [2, 2, 1, 1], offset = [0, 0], border = [0, 0]} : (tensor<3x1x1x7xf32>) -> tensor<3x15x13x7xf32>
 
   // CHECK: return %[[GENERIC]]
   return %resize : tensor<3x15x13x7xf32>
 }
 
 // -----
 
 // CHECK: #map = affine_map<(d0, d1, d2, d3) -> (d0, d3)>
 // CHECK: #map1 = affine_map<(d0, d1, d2, d3) -> (d0, d1, d2, d3)>
 // CHECK-LABEL: @broadcast_resize_nearest_i8
 func.func @broadcast_resize_nearest_i8(%arg0 : tensor<3x1x1x7xi8>) -> tensor<3x15x13x7xi8> {
   // CHECK: %[[COLLAPSE:.+]] = tensor.collapse_shape %arg0
   // CHECK-SAME{literal}: [[0], [1, 2, 3]]
   // CHECK: %[[EMPTY:.+]] = tensor.empty() : tensor<3x15x13x7xi8>
-  // CHECK: %[[GENERIC:.+]] = linalg.generic 
+  // CHECK: %[[GENERIC:.+]] = linalg.generic
   // CHECK-SAME: indexing_maps = [#map, #map1]
   // CHECK-SAME: iterator_types = ["parallel", "parallel", "parallel", "parallel"]}
   // CHECK-SAME: ins(%[[COLLAPSE]] : tensor<3x7xi8>)
   // CHECK-SAME: outs(%[[EMPTY]] : tensor<3x15x13x7xi8>)
   // CHECK-NEXT: ^bb0(%[[IN:.+]]: i8, %[[OUT:.+]]: i8):
   // CHECK:   linalg.yield %[[IN]]
   %resize = "tosa.resize"(%arg0) {mode = "NEAREST_NEIGHBOR", scale = [2, 2, 1, 1], offset = [0, 0], border = [0, 0]} : (tensor<3x1x1x7xi8>) -> tensor<3x15x13x7xi8>
 
   // CHECK: return %[[GENERIC]]
   return %resize : tensor<3x15x13x7xi8>
 }
 
 // -----
 
 // CHECK: #map = affine_map<(d0, d1, d2, d3) -> (d0, d3)>
 // CHECK: #map1 = affine_map<(d0, d1, d2, d3) -> (d0, d1, d2, d3)>
 // CHECK-LABEL: @broadcast_resize_nearest_i32
 func.func @broadcast_resize_nearest_i32(%arg0 : tensor<3x1x1x7xi8>) -> tensor<3x15x13x7xi32> {
-  // CHECK: %[[COLLAPSE:.+]] = tensor.collapse_shape %arg0 
+  // CHECK: %[[COLLAPSE:.+]] = tensor.collapse_shape %arg0
   // CHECK-SAME{literal}: [[0], [1, 2, 3]]
   // CHECK: %[[EMPTY:.+]] = tensor.empty() : tensor<3x15x13x7xi32>
-  // CHECK: %[[GENERIC:.+]] = linalg.generic 
+  // CHECK: %[[GENERIC:.+]] = linalg.generic
   // CHECK-SAME: indexing_maps = [#map, #map1]
   // CHECK-SAME: iterator_types = ["parallel", "parallel", "parallel", "parallel"]}
   // CHECK-SAME: ins(%[[COLLAPSE]] : tensor<3x7xi8>)
   // CHECK-SAME: outs(%[[EMPTY]] : tensor<3x15x13x7xi32>)
   // CHECK-NEXT: ^bb0(%[[IN:.+]]: i8, %[[OUT:.+]]: i32):
-  // CHECK:   %[[EXT:.+]] = arith.extsi %[[IN]] : i8 to i32 
+  // CHECK:   %[[EXT:.+]] = arith.extsi %[[IN]] : i8 to i32
   // CHECK:   linalg.yield %[[EXT]]
   %resize = "tosa.resize"(%arg0) {mode = "NEAREST_NEIGHBOR", scale = [2, 2, 1, 1], offset = [0, 0], border = [0, 0]} : (tensor<3x1x1x7xi8>) -> tensor<3x15x13x7xi32>
 
   // CHECK: return %[[GENERIC]]
   return %resize : tensor<3x15x13x7xi32>
 }
 
 // -----
 
 // CHECK: #map = affine_map<(d0, d1, d2, d3) -> (d0, d3)>
 // CHECK: #map1 = affine_map<(d0, d1, d2, d3) -> (d0, d1, d2, d3)>
 // CHECK-LABEL: @broadcast_resize_bilinear_i32
 func.func @broadcast_resize_bilinear_i32(%arg0 : tensor<3x1x1x7xi8>) -> tensor<3x15x13x7xi32> {
   // CHECK: %[[COLLAPSE:.+]] = tensor.collapse_shape %arg0
   // CHECK-SAME{literal}: [[0], [1, 2, 3]]
   // CHECK: %[[EMPTY:.+]] = tensor.empty() : tensor<3x15x13x7xi32>
-  // CHECK: %[[GENERIC:.+]] = linalg.generic 
+  // CHECK: %[[GENERIC:.+]] = linalg.generic
   // CHECK-SAME: indexing_maps = [#map, #map1]
   // CHECK-SAME: iterator_types = ["parallel", "parallel", "parallel", "parallel"]}
   // CHECK-SAME: ins(%[[COLLAPSE]] : tensor<3x7xi8>)
   // CHECK-SAME: outs(%[[EMPTY]] : tensor<3x15x13x7xi32>)
   // CHECK-NEXT: ^bb0(%[[IN:.+]]: i8, %[[OUT:.+]]: i32):
-  // CHECK: %[[EXT:.+]] = arith.extsi %[[IN]] : i8 to i32 
+  // CHECK: %[[EXT:.+]] = arith.extsi %[[IN]] : i8 to i32
   // CHECK-DAG: %[[C2:.+]] = arith.constant 2 : i32
   // CHECK: %[[MUL1:.+]] = arith.muli %[[EXT]], %[[C2]] : i32
   // CHECK-DAG: %[[C1:.+]] = arith.constant 1 : i32
   // CHECK: %[[MUL2:.+]] = arith.muli %[[MUL1]], %[[C1]] : i32
   // CHECK: linalg.yield %[[MUL2]]
   %resize = "tosa.resize"(%arg0) {mode = "BILINEAR", scale = [2, 2, 1, 1], offset = [0, 0], border = [0, 0]} : (tensor<3x1x1x7xi8>) -> tensor<3x15x13x7xi32>
 
   // CHECK: return %[[GENERIC]]

mlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir

func.func @concat(%arg0: tensor<5x1xf32>, %arg1: tensor<6x1xf32>) -> () {
   // CHECK: [[INSERT1:%.+]] = tensor.insert_slice %[[ARG0]] into [[INSERT0]][0, 1] [5, 1] [1, 1]
   %1 = "tosa.concat"(%arg0, %arg0) { axis = 1 : i64} : (tensor<5x1xf32>, tensor<5x1xf32>)  -> (tensor<5x2xf32>)
   return
 }
 
 // -----
 
 // CHECK-LABEL: @concat_non_axis_dyn
-// CHECK-SAME: (%[[ARG0:[0-9a-zA-Z_]*]]: 
+// CHECK-SAME: (%[[ARG0:[0-9a-zA-Z_]*]]:
 // CHECK-SAME:  %[[ARG1:[0-9a-zA-Z_]*]]
 func.func @concat_non_axis_dyn(%arg0: tensor<5x?xf32>, %arg1: tensor<6x?xf32>) -> () {
   // CHECK: %[[AXIS:.+]] = arith.constant 0
   // CHECK: %[[STRIDE:.+]]   = arith.constant 1
   // CHECK: %[[OFFSET:.+]] = arith.constant 0 : index
   // CHECK: %[[IDX0:.+]] = arith.constant 0 : index
   // CHECK: %[[IDX1:.+]] = arith.constant 1 : index
   // CHECK: %[[SIZE:.+]] = tensor.dim %[[ARG0]], %[[IDX1]]
   // CHECK: %[[IDX1_2:.+]] = arith.constant 1 : index
   // CHECK: %[[DYN:.+]] = tensor.dim %[[ARG0]], %[[IDX1_2]]
   // CHECK: %[[INIT:.+]] = tensor.empty(%[[DYN]]) : tensor<11x?xf32>
   // CHECK: %[[INSERT0:.+]] = tensor.insert_slice %[[ARG0]] into %[[INIT]][0, 0] [5, %[[SIZE]]] [1, 1]
   // CHECK: %[[INSERT1:.+]] = tensor.insert_slice %[[ARG1]] into %[[INSERT0]][5, 0] [6, %[[SIZE]]] [1, 1]
   %0 = "tosa.concat"(%arg0, %arg1) { axis = 0 : i64} : (tensor<5x?xf32>, tensor<6x?xf32>)  -> (tensor<11x?xf32>)
   return
 }
 
 // -----
 
 // CHECK-LABEL: @concat_axis_dyn
-// CHECK-SAME: (%[[ARG0:[0-9a-zA-Z_]*]]: 
-// CHECK-SAME:  %[[ARG1:[0-9a-zA-Z_]*]]: 
+// CHECK-SAME: (%[[ARG0:[0-9a-zA-Z_]*]]:
+// CHECK-SAME:  %[[ARG1:[0-9a-zA-Z_]*]]:
 func.func @concat_axis_dyn(%arg0: tensor<?x3xf32>, %arg1: tensor<?x3xf32>) -> () {
   // CHECK: %[[AXIS:.+]] = arith.constant 0
   // CHECK: %[[STRIDE:.+]]   = arith.constant 1
   // CHECK: %[[OFFSET:.+]] = arith.constant 0 : index
   // CHECK: %[[IDX0:.+]] = arith.constant 0 : index
   // CHECK: %[[SIZE:.+]] = tensor.dim %[[ARG0]], %[[IDX0]]
   // CHECK: %[[IDX0_2:.+]] = arith.constant 0 : index
   // CHECK: %[[DYN:.+]] = tensor.dim %[[ARG0]], %[[IDX0_2]]
   // CHECK: %[[IDX1:.+]] = arith.constant 1 : index
   // CHECK: %[[INIT:.+]] = tensor.empty(%[[DYN]]) : tensor<?x3xf32>
   // CHECK: %[[DYN1:.+]] = tensor.dim %[[ARG0]], %[[AXIS]]
   // CHECK: %[[INSERT0:.+]] = tensor.insert_slice %[[ARG0]] into %[[INIT]][0, 0] [%[[DYN1]], 3] [1, 1]
   // CHECK: %[[SUM:.+]]  = arith.addi %[[OFFSET]], %[[DYN1]]
   // CHECK: %[[DYN2:.+]] = tensor.dim %[[ARG1]], %[[AXIS]]
   // CHECK: %[[INSERT1:.+]] = tensor.insert_slice %[[ARG1]] into %[[INSERT0]][%[[SUM]], 0] [%[[DYN2]], 3] [1, 1]
   %0 = "tosa.concat"(%arg0, %arg1) { axis = 0 : i64} : (tensor<?x3xf32>, tensor<?x3xf32>)  -> (tensor<?x3xf32>)
   return
 }
 
 // -----
 // CHECK: #[[$MAP0:.*]] = affine_map<(d0) -> (d0)>
 
 // CHECK-LABEL: @rescale_i8
-// CHECK-SAME: (%[[ARG0:[0-9a-zA-Z_]*]]: 
+// CHECK-SAME: (%[[ARG0:[0-9a-zA-Z_]*]]:
 func.func @rescale_i8(%arg0 : tensor<2xi8>) -> () {
   // CHECK: [[C0:%.+]] = arith.constant 19689
   // CHECK: [[C1:%.+]] = arith.constant 15
   // CHECK: [[INIT:%.+]] = tensor.empty()
   // CHECK: [[GENERIC:%.+]] = linalg.generic {indexing_maps = [#[[$MAP0]], #[[$MAP0]]], iterator_types = ["parallel"]} ins(%[[ARG0]] : tensor<2xi8>) outs([[INIT]] : tensor<2xi8>)
   // CHECK: ^bb0([[IN:%.+]]: i8, [[UNUSED:%.+]]: i8):
   // CHECK: [[C17:%.+]] = arith.constant 17
   // CHECK: [[C22:%.+]] = arith.constant 22
func.func @rescale_i8(%arg0 : tensor<2xi8>) -> () {
   return
 }
 
 // -----
 
 // CHECK: #[[$MAP0:.*]] = affine_map<(d0, d1) -> (d0, d1)>
 
 // CHECK-LABEL: @rescale_i8_dyn_batch
-// CHECK-SAME: (%[[ARG0:[0-9a-zA-Z_]*]]: 
+// CHECK-SAME: (%[[ARG0:[0-9a-zA-Z_]*]]:
 func.func @rescale_i8_dyn_batch(%arg0 : tensor<?x2xi8>) -> () {
   // CHECK: %[[C0:.+]] = arith.constant 0
   // CHECK: %[[BATCH:.+]] = tensor.dim %[[ARG0]], %[[C0]]
   // CHECK: %[[INIT:.+]] = tensor.empty(%[[BATCH]]) : tensor<?x2xi8>
   // CHECK: [[GENERIC:%.+]] = linalg.generic {indexing_maps = [#[[$MAP0]], #[[$MAP0]]], iterator_types = ["parallel", "parallel"]} ins(%[[ARG0]] : tensor<?x2xi8>) outs(%[[INIT]] : tensor<?x2xi8>)
   %0 = "tosa.rescale"(%arg0) {input_zp = 17 : i32, output_zp = 22 : i32, multiplier = [19689 : i32], shift = [15 : i32], scale32 = false, double_round = false, per_channel = false} : (tensor<?x2xi8>)  -> (tensor<?x2xi8>)
 
   // CHECK: %[[C0:.+]] = arith.constant 0
   // CHECK: %[[BATCH:.+]] = tensor.dim %[[ARG0]], %[[C0]]
   // CHECK: %[[INIT:.+]] = tensor.empty(%[[BATCH]]) : tensor<?x2xui8>
   // CHECK: [[GENERIC:%.+]] = linalg.generic {indexing_maps = [#[[$MAP0]], #[[$MAP0]]], iterator_types = ["parallel", "parallel"]} ins(%[[ARG0]] : tensor<?x2xi8>) outs(%[[INIT]] : tensor<?x2xui8>)
   %1 = "tosa.rescale"(%arg0) {input_zp = 17 : i32, output_zp = 22 : i32, multiplier = [19689 : i32], shift = [15 : i32], scale32 = false, double_round = false, per_channel = false} : (tensor<?x2xi8>)  -> (tensor<?x2xui8>)
 
   return
 }
 
 // -----
 
 // CHECK: #[[$MAP1:.*]] = affine_map<(d0, d1, d2, d3) -> (d0, d1, d2, d3)>
 
 // CHECK-LABEL: @rescale_dyn
-// CHECK-SAME: (%[[ARG0:[0-9a-zA-Z_]*]]: 
+// CHECK-SAME: (%[[ARG0:[0-9a-zA-Z_]*]]:
 func.func @rescale_dyn(%arg0 : tensor<1x?x?x32xi32>) -> () {
   // CHECK: %[[C1:.+]] = arith.constant 1
   // CHECK: %[[DIM1:.+]] = tensor.dim %[[ARG0]], %[[C1]]
   // CHECK: %[[C2:.+]] = arith.constant 2
   // CHECK: %[[DIM2:.+]] = tensor.dim %[[ARG0]], %[[C2]]
   // CHECK: %[[INIT:.+]] = tensor.empty(%[[DIM1]], %[[DIM2]])
   // CHECK: [[GENERIC:%.+]] = linalg.generic {indexing_maps = [#[[$MAP1]], #[[$MAP1]]], iterator_types = ["parallel", "parallel", "parallel", "parallel"]} ins(%[[ARG0]] : tensor<1x?x?x32xi32>) outs(%[[INIT]] : tensor<1x?x?x32xi8>)
   %0 = "tosa.rescale"(%arg0) {double_round = true, input_zp = 0 : i32, multiplier = [1376784203 : i32], output_zp = 0 : i32, per_channel = false, scale32 = true, shift = [38 : i32]} : (tensor<1x?x?x32xi32>) -> tensor<1x?x?x32xi8>
   return
 }
 
 // -----
 
 // CHECK: #[[$MAP0:.*]] = affine_map<(d0) -> (d0)>
 
 // CHECK-LABEL: @rescale_ui8
-// CHECK-SAME: (%[[ARG0:[0-9a-zA-Z_]*]]: 
+// CHECK-SAME: (%[[ARG0:[0-9a-zA-Z_]*]]:
 func.func @rescale_ui8(%arg0 : tensor<2xui8>) -> () {
   // CHECK: [[C0:%.+]] = arith.constant 19689
   // CHECK: [[C1:%.+]] = arith.constant 15
   // CHECK: [[INIT:%.+]] = tensor.empty()
   // CHECK: [[GENERIC:%.+]] = linalg.generic {indexing_maps = [#[[$MAP0]], #[[$MAP0]]], iterator_types = ["parallel"]} ins(%[[ARG0]] : tensor<2xui8>) outs([[INIT]] : tensor<2xi8>)
   // CHECK: ^bb0([[IN:%.+]]: ui8, [[UNUSED:%.+]]: i8):
   // CHECK: [[C17:%.+]] = arith.constant 17
   // CHECK: [[C22:%.+]] = arith.constant 22
func.func @rescale_ui8(%arg0 : tensor<2xui8>) -> () {
   return
 }
 
 // -----
 
 // CHECK: #[[$MAP0:.*]] = affine_map<(d0) -> (d0)>
 
 // CHECK-LABEL: @rescale_per_channel
-// CHECK-SAME: (%[[ARG0:[0-9a-zA-Z_]*]]: 
+// CHECK-SAME: (%[[ARG0:[0-9a-zA-Z_]*]]:
 func.func @rescale_per_channel(%arg0 : tensor<3xi8>) -> (tensor<3xi8>) {
   // CHECK: [[MULTIPLIERS:%.+]] = arith.constant dense<[42, 43, 0]>
   // CHECK: [[SHIFTS:%.+]] = arith.constant dense<[14, 15, 0]>
   // CHECK: [[INIT:%.+]] = tensor.empty()
   // CHECK: [[GENERIC:%.+]] = linalg.generic {indexing_maps = [#[[$MAP0]], #[[$MAP0]], #[[$MAP0]], #[[$MAP0]]], iterator_types = ["parallel"]} ins(%[[ARG0]], [[MULTIPLIERS]], [[SHIFTS]] : tensor<3xi8>, tensor<3xi32>, tensor<3xi8>) outs([[INIT]] : tensor<3xi8>)
   // CHECK: ^bb0([[IN:%.+]]: i8, [[MULTIPLIER:%.+]]: i32, [[SHIFT:%.+]]: i8, [[UNUSED:%.+]]: i8):
   // CHECK: [[C243:%.+]] = arith.constant 243
   // CHECK: [[C252:%.+]] = arith.constant 252
func.func @rescaleUnnecessaryDoubleRound(%arg0 : tensor<2xi8>) -> (tensor<2xi8>) {
   return %0 : tensor<2xi8>
 }
 
 // -----
 
 // CHECK: #[[$MAP0:.*]] = affine_map<(d0, d1) -> (d0, d1)>
 
 // CHECK-LABEL: @reverse
-// CHECK-SAME: (%[[ARG0:[0-9a-zA-Z_]*]]: 
+// CHECK-SAME: (%[[ARG0:[0-9a-zA-Z_]*]]:
 func.func @reverse(%arg0: tensor<5x4xi32>) -> () {
   // CHECK: %[[C0:.+]] = arith.constant 0
   // CHECK: %[[RDIM:.+]] = tensor.dim %[[ARG0]], %[[C0]]
   // CHECK: %[[INIT:.+]] = tensor.empty()
   // CHECK: %[[GENERIC:.+]] = linalg.generic {indexing_maps = [#[[$MAP0]]], iterator_types = ["parallel", "parallel"]} outs(%[[INIT]] : tensor<5x4xi32>)
   // CHECK-DAG:   %[[I0:.+]] = linalg.index 0
   // CHECK-DAG:   %[[I1:.+]] = linalg.index 1
   // CHECK-DAG:   %[[SUB1:.+]] = arith.constant 1
func.func @reverse(%arg0: tensor<5x4xi32>) -> () {
   return
 }
 
 // -----
 
 // CHECK: #[[$MAP0:.*]] = affine_map<(d0) -> (d0)>
 
 // CHECK-LABEL: @reverse_dyn
-// CHECK-SAME: (%[[ARG0:[0-9a-zA-Z_]*]]: 
+// CHECK-SAME: (%[[ARG0:[0-9a-zA-Z_]*]]:
 func.func @reverse_dyn(%arg0: tensor<?xi32>) -> () {
   // CHECK: %[[C0_1:.+]] = arith.constant 0
   // CHECK: %[[D0_1:.+]] = tensor.dim %[[ARG0]], %[[C0_1]]
   // CHECK: %[[C0_2:.+]] = arith.constant 0
   // CHECK: %[[D0_2:.+]] = tensor.dim %[[ARG0]], %[[C0_2]]
   // CHECK: %[[INIT:.+]] = tensor.empty(%[[D0_1]])
   // CHECK: %[[GENERIC:.+]] = linalg.generic {indexing_maps = [#[[$MAP0]]], iterator_types = ["parallel"]} outs(%[[INIT]] : tensor<?xi32>)
   // CHECK-DAG:   %[[I0:.+]] = linalg.index 0

 }
 
 // -----
 
 // CHECK-DAG: #[[$MAP0:.*]] = affine_map<(d0, d1, d2, d3) -> (d1, d3)>
 // CHECK-DAG: #[[$MAP1:.*]] = affine_map<(d0, d1, d2, d3) -> (d0, d1, d2, d3)>
 
 // CHECK-LABEL: @tile_dyn_input
-// CHECK-SAME: (%[[ARG0:[0-9a-zA-Z_]*]]: 
+// CHECK-SAME: (%[[ARG0:[0-9a-zA-Z_]*]]:
 func.func @tile_dyn_input(%arg0 : tensor<?x3xi8>) -> () {
   // CHECK: %[[CST0:.+]] = arith.constant 0
   // CHECK: %[[DYN:.+]] = tensor.dim %[[ARG0]], %[[CST0]] : tensor<?x3xi8>
   // CHECK: %[[INIT:.+]] = tensor.empty(%[[DYN]])
   // CHECK: %[[GENERIC:.+]] = linalg.generic {indexing_maps = [#[[$MAP0]], #[[$MAP1]]], iterator_types = ["parallel", "parallel", "parallel", "parallel"]} ins(%[[ARG0]] : tensor<?x3xi8>) outs(%[[INIT]] : tensor<2x?x1x3xi8>)
   // CHECK: ^bb0(%[[ARG1:.+]]: i8,
   // CHECK:   linalg.yield %[[ARG1]] : i8
   // CHECK: %[[COLLAPSED:.+]] = tensor.collapse_shape %[[GENERIC]] {{\[}}[0, 1, 2, 3]]
   // CHECK: tensor.expand_shape %[[COLLAPSED]] {{\[}}[0, 1]]
   %0 = "tosa.tile"(%arg0) {multiples = [2, 1]} : (tensor<?x3xi8>)  -> (tensor<?x3xi8>)
 
   return
 }
 
 // -----
 
 // CHECK-DAG: #[[$MAP0:.*]] = affine_map<(d0, d1, d2, d3) -> (d1, d3)>
 // CHECK-DAG: #[[$MAP1:.*]] = affine_map<(d0, d1, d2, d3) -> (d0, d1, d2, d3)>
 
 // CHECK-LABEL: @tile_dyn_multiples
-// CHECK-SAME: (%[[ARG0:[0-9a-zA-Z_]*]]: 
+// CHECK-SAME: (%[[ARG0:[0-9a-zA-Z_]*]]:
 func.func @tile_dyn_multiples(%arg0 : tensor<2x3xi8>) -> () {
   // CHECK: %[[CST1:.+]] = arith.constant 1
   // CHECK: %[[DYN:.+]] = tensor.dim %[[ARG0]], %[[CST1]] : tensor<2x3xi8>
   // CHECK: %[[INIT:.+]] = tensor.empty(%[[DYN]])
   // CHECK: %[[GENERIC:.+]] = linalg.generic {indexing_maps = [#[[$MAP0]], #[[$MAP1]]], iterator_types = ["parallel", "parallel", "parallel", "parallel"]} ins(%[[ARG0]] : tensor<2x3xi8>) outs(%[[INIT]] : tensor<2x2x?x3xi8>)
   // CHECK: ^bb0(%[[ARG1:.+]]: i8,
   // CHECK:   linalg.yield %[[ARG1]] : i8
   // CHECK: %[[COLLAPSED:.+]] = tensor.collapse_shape %[[GENERIC]] {{\[}}[0, 1, 2, 3]]
   // CHECK: tensor.expand_shape %[[COLLAPSED]] {{\[}}[0, 1]]
   %0 = "tosa.tile"(%arg0) {multiples = [2, -1]} : (tensor<2x3xi8>)  -> (tensor<2x?xi8>)
 
   return
 }
 
 // -----
 
 // CHECK-LABEL: @pad_float
-// CHECK-SAME: (%[[ARG0:[0-9a-zA-Z_]*]]: 
+// CHECK-SAME: (%[[ARG0:[0-9a-zA-Z_]*]]:
 func.func @pad_float(%arg0 : tensor<1x2xf32>) -> (tensor<4x9xf32>) {
   %0 = arith.constant dense<[[1, 2], [3, 4]]> : tensor<2x2xi32>
   // TODO: Output contains multiple "arith.constant 1 : index".
   // CHECK-DAG: [[INDEX1:%.+]] = arith.constant 1 : index
   // CHECK-DAG: [[INDEX2:%.+]] = arith.constant 2 : index
   // CHECK-DAG: [[INDEX3:%.+]] = arith.constant 3 : index
   // CHECK-DAG: [[INDEX4:%.+]] = arith.constant 4 : index
   // CHECK-DAG: [[CST:%.+]] = arith.constant 0.000000e+00 : f32

mlir/test/Conversion/VectorToGPU/vector-to-mma-ops-mma-sync.mlir

 #map2 = affine_map<(d0, d1, d2) -> (d1, d2)>
 #map3 = affine_map<(d0, d1, d2) -> (d0, d1)>
 
 // CHECK-LABEL: func @m16n8k32_int8_row_row_row
 func.func @m16n8k32_int8_row_row_row(%arg0: memref<128x128xi8, 3>, %arg1: memref<128x128xi8, 3>, %arg2: memref<128x128xi32>) {
   %cst_0 = arith.constant dense<0> : vector<32x8xi8>
   %c0 = arith.constant 0 : index
   %c1 = arith.constant 1 : index
-  %c17 = arith.constant 17 : index  
-  %c39 = arith.constant 39 : index  
-  %c40 = arith.constant 40 : index  
-  %c49 = arith.constant 49 : index  
-  %c50 = arith.constant 50 : index  
+  %c17 = arith.constant 17 : index
+  %c39 = arith.constant 39 : index
+  %c40 = arith.constant 40 : index
+  %c49 = arith.constant 49 : index
+  %c50 = arith.constant 50 : index
   %cst = arith.constant 0 : i8
   %cst0 = arith.constant 0 : i32
 
   // Verify that the operand A is distributed to loads correctly.
 
   // CHECK: [[row:%.+]] = affine.apply [[$rowA0_map]]()[{{%.+}}]
   // CHECK: [[col:%.+]] = affine.apply [[$colA0_map]]()[{{%.+}}]
   // CHECK: nvgpu.ldmatrix %arg0[[[row]], [[col]]] {numTiles = 4 : i32, transpose = false} : memref<128x128xi8, 3> -> vector<4x4xi8>
func.func @m16n8k32_int8_row_row_row(%arg0: memref<128x128xi8, 3>, %arg1: memref<128x128xi8, 3>, %arg2: memref<128x128xi32>) {
   // CHECK: memref.load %arg1[[[row]], [[col]]] : memref<128x128xi8, 3>
   // CHECK-DAG: [[row:%.+]] = affine.apply [[$rowB2_map]]()[{{%.+}}]
   // CHECK-DAG: [[col:%.+]] = affine.apply [[$colB0_map]]()[{{%.+}}]
   // CHECK: memref.load %arg1[[[row]], [[col]]] : memref<128x128xi8, 3>
   // CHECK-DAG: [[row:%.+]] = affine.apply [[$rowB3_map]]()[{{%.+}}]
   // CHECK-DAG: [[col:%.+]] = affine.apply [[$colB0_map]]()[{{%.+}}]
   // CHECK: memref.load %arg1[[[row]], [[col]]] : memref<128x128xi8, 3>
   // CHECK-DAG: [[col:%.+]] = affine.apply [[$colB0_map]]()[{{%.+}}]
-  // CHECK-DAG: [[row:%.+]] = affine.apply [[$rowB4_map]]()[{{%.+}}]  
+  // CHECK-DAG: [[row:%.+]] = affine.apply [[$rowB4_map]]()[{{%.+}}]
   // CHECK: memref.load %arg1[[[row]], [[col]]] : memref<128x128xi8, 3>
   // CHECK-DAG: [[row:%.+]] = affine.apply [[$rowB5_map]]()[{{%.+}}]
   // CHECK-DAG: [[col:%.+]] = affine.apply [[$colB0_map]]()[{{%.+}}]
   // CHECK: memref.load %arg1[[[row]], [[col]]] : memref<128x128xi8, 3>
   // CHECK-DAG: [[row:%.+]] = affine.apply [[$rowB6_map]]()[{{%.+}}]
   // CHECK-DAG: [[col:%.+]] = affine.apply [[$colB0_map]]()[{{%.+}}]
   // CHECK: memref.load %arg1[[[row]], [[col]]] : memref<128x128xi8, 3>
   // CHECK-DAG: [[row:%.+]] = affine.apply [[$rowB7_map]]()[{{%.+}}]

 #map2 = affine_map<(d0, d1, d2) -> (d1, d2)>
 #map3 = affine_map<(d0, d1, d2) -> (d0, d1)>
 
 // CHECK-LABEL: func @m8n8k4_f64_row_row_row
 func.func @m8n8k4_f64_row_row_row(%arg0: memref<128x128xf64>, %arg1: memref<128x128xf64>, %arg2: memref<128x128xf64>) {
   %cst_0 = arith.constant dense<0.0> : vector<4x8xf64>
   %c0 = arith.constant 0 : index
   %c1 = arith.constant 1 : index
-  %c17 = arith.constant 17 : index  
-  %c39 = arith.constant 39 : index  
-  %c40 = arith.constant 40 : index  
-  %c49 = arith.constant 49 : index  
-  %c50 = arith.constant 50 : index  
+  %c17 = arith.constant 17 : index
+  %c39 = arith.constant 39 : index
+  %c40 = arith.constant 40 : index
+  %c49 = arith.constant 49 : index
+  %c50 = arith.constant 50 : index
   %cst = arith.constant 0.0 : f64
   %cst0 = arith.constant 0.0 : f64
 
   // Verify that the operand A is distributed to loads correctly.
 
   // CHECK-DAG: [[row:%.+]] = affine.apply [[$rowA0_map]]
   // CHECK-DAG: [[col:%.+]] = affine.apply [[$colA0_map]]
   // CHECK: vector.load %arg0[[[row]], [[col]]] : memref<128x128xf64>, vector<1xf64>
 
   // Verify that the operand B is distributed to loads correctly. It's elements
   // must be loaded in a non-vectorized manner to do the transpose.
 
   // CHECK-DAG: [[row:%.+]] = affine.apply [[$rowb0_map]]
   // CHECK-DAG: [[col:%.+]] = affine.apply [[$colb0_map]]
   // CHECK: memref.load %arg1[[[row]], [[col]]] : memref<128x128xf64>
 
   // CHECK-DAG: [[row:%.+]] = affine.apply [[$rowC0_map]]
   // CHECK-DAG: [[col:%.+]] = affine.apply [[$colC0_map]]
-  // CHECK: vector.load %arg2[[[row]], [[col]]] : memref<128x128xf64>, vector<2xf64>  
+  // CHECK: vector.load %arg2[[[row]], [[col]]] : memref<128x128xf64>, vector<2xf64>
 
   %A = vector.transfer_read %arg0[%c1, %c1], %cst {in_bounds = [true, true]} : memref<128x128xf64>, vector<8x4xf64>
   %B = vector.transfer_read %arg1[%c39, %c40], %cst {in_bounds = [true, true], permutation_map = #map0} : memref<128x128xf64>, vector<8x4xf64>
   %C = vector.transfer_read %arg2[%c49, %c40], %cst0 {in_bounds = [true, true]} : memref<128x128xf64>, vector<8x8xf64>
   // CHECK: [[d:%.+]] = nvgpu.mma.sync({{.*}}) {mmaShape = [8, 8, 4]} : (vector<1x1xf64>, vector<1x1xf64>, vector<1x2xf64>) -> vector<1x2xf64>
   %D = vector.contract {indexing_maps = [#map1, #map2, #map3], iterator_types = ["parallel", "parallel", "reduction"], kind = #vector.kind<add>} %A, %B, %C : vector<8x4xf64>, vector<8x4xf64> into vector<8x8xf64>
 
   // CHECK-DAG: [[row:%.+]] = affine.apply [[$rowC0_map]]
   // CHECK-DAG: [[col:%.+]] = affine.apply [[$colC0_map]]
-  // CHECK: vector.store {{%.+}}, %arg2[[[row]], [[col]]] : memref<128x128xf64>, vector<2xf64>  
+  // CHECK: vector.store {{%.+}}, %arg2[[[row]], [[col]]] : memref<128x128xf64>, vector<2xf64>
   vector.transfer_write %D, %arg2[%c49, %c40] {in_bounds = [true, true]} : vector<8x8xf64>, memref<128x128xf64>
   return
 }
 
 // -----
 
 //#########################################################################
 // FP16 row-row-row (ldmatrix x4 for matrixA and ldmatrix x2 for matrixB)

 func.func @m16n8k16_fp16_row_row_row(%arg0: memref<20x20xf16, 3>, %arg1: memref<20x20xf16, 3>, %arg2: memref<20x20xf16, 3>) {
   %cst_0 = arith.constant dense<0.000000e+00> : vector<16x8xf16>
   %c0 = arith.constant 0 : index
   %c1 = arith.constant 1 : index
   %c3 = arith.constant 3 : index
   %cst = arith.constant 0.000000e+00 : f16
   // CHECK-DAG: [[row:%.+]] = affine.apply [[$rowA_map]]
   // CHECK-DAG: [[col:%.+]] = affine.apply [[$colA_map]]
-  // CHECK: nvgpu.ldmatrix %arg0[[[row]], [[col]]] {numTiles = 4 : i32, transpose = false}  
+  // CHECK: nvgpu.ldmatrix %arg0[[[row]], [[col]]] {numTiles = 4 : i32, transpose = false}
 
   // CHECK-DAG: [[row:%.+]] = affine.apply [[$rowB_map]]
   // CHECK-DAG: [[col:%.+]] = affine.apply [[$colB_map]]
   // CHECK: nvgpu.ldmatrix %arg1[[[row]], [[col]]] {numTiles = 2 : i32, transpose = true}
   %A = vector.transfer_read %arg0[%c1, %c3], %cst {in_bounds = [true, true]} : memref<20x20xf16, 3>, vector<16x16xf16>
   %B = vector.transfer_read %arg1[%c3, %c3], %cst {permutation_map = #map0, in_bounds = [true, true]} : memref<20x20xf16, 3>, vector<8x16xf16>
   %C = vector.transfer_read %arg2[%c0, %c0], %cst {in_bounds = [true, true]} : memref<20x20xf16, 3>, vector<16x8xf16>
   %D = vector.contract {indexing_maps = [#map1, #map2, #map3], iterator_types = ["parallel", "parallel", "reduction"], kind = #vector.kind<add>} %A, %B, %C : vector<16x16xf16>, vector<8x16xf16> into vector<16x8xf16>

 func.func @m16n16k16_mmasync16816_fp16_f16_row_row_row(%arg0: memref<42x32xf16, 3>, %arg1: memref<32x64xf16, 3>, %arg2: memref<42x64xf16, 3>) {
   %cst_0 = arith.constant dense<0.000000e+00> : vector<16x8xf16>
   %c0 = arith.constant 0 : index
   %c8 = arith.constant 8 : index
   %cst = arith.constant 0.000000e+00 : f16
 
   // CHECK-DAG: [[row:%.+]] = affine.apply [[$rowA_map]]
   // CHECK-DAG: [[col:%.+]] = affine.apply [[$colA_map]]
-  // CHECK: [[fragmentA:%.+]] = nvgpu.ldmatrix %arg0[[[row]], [[col]]] {numTiles = 4 : i32, transpose = false}  
+  // CHECK: [[fragmentA:%.+]] = nvgpu.ldmatrix %arg0[[[row]], [[col]]] {numTiles = 4 : i32, transpose = false}
   %A = vector.transfer_read %arg0[%c0, %c0], %cst {in_bounds = [true, true]} : memref<42x32xf16, 3>, vector<16x16xf16>
 
   // CHECK-DAG: [[row:%.+]] = affine.apply [[$rowB_map]]
   // CHECK-DAG: [[col:%.+]] = affine.apply [[$colB_map]]
   // CHECK-DAG: [[fragmentB:%.+]] = nvgpu.ldmatrix %arg1[[[col]], [[row]]] {numTiles = 4 : i32, transpose = true}
   %B = vector.transfer_read %arg1[%c0, %c0], %cst {permutation_map = #map0, in_bounds = [true, true]} : memref<32x64xf16, 3>, vector<16x16xf16>
 
   // CHECK-DAG: [[row:%.+]] = affine.apply [[$rowA_map]]

 // CHECK-LABEL: func @batch_m16n8k16_fp16_row_row_row
 func.func @batch_m16n8k16_fp16_row_row_row(%arg0: memref<2x20x20xf16, 3>, %arg1: memref<2x20x20xf16, 3>, %arg2: memref<2x20x20xf16, 3>) {
   %cst_0 = arith.constant dense<0.000000e+00> : vector<20x20xf16>
   // CHECK: [[C0:%.+]] = arith.constant 0 : index
   %c0 = arith.constant 0 : index
   %c1 = arith.constant 1 : index
   %c3 = arith.constant 3 : index
   %cst = arith.constant 0.000000e+00 : f16
-  
   // CHECK-DAG: [[row:%.+]] = affine.apply [[$Arow_map]]
   // CHECK-DAG: [[col:%.+]] = affine.apply [[$Acol_map]]
   // CHECK: nvgpu.ldmatrix %arg0[[[C0]], [[row]], [[col]]] {numTiles = 4 : i32, transpose = false} : memref<2x20x20xf16, 3> -> vector<4x2xf16>
   %A = vector.transfer_read %arg0[%c0, %c1, %c3], %cst {in_bounds = [true, true]} : memref<2x20x20xf16, 3>, vector<16x16xf16>
-  
   // CHECK-DAG: [[row:%.+]] = affine.apply [[$Brow_map]]
-  // CHECK-DAG: [[col:%.+]] = affine.apply [[$Bcol_map]]  
+  // CHECK-DAG: [[col:%.+]] = affine.apply [[$Bcol_map]]
   // CHECK: nvgpu.ldmatrix %arg1[[[C0]], [[row]], [[col]]] {numTiles = 2 : i32, transpose = true} : memref<2x20x20xf16, 3> -> vector<2x2xf16>
   %B = vector.transfer_read %arg1[%c0, %c3, %c3], %cst {permutation_map = #map0, in_bounds = [true, true]} : memref<2x20x20xf16, 3>, vector<8x16xf16>
-  
   // CHECK-DAG: [[row:%.+]] = affine.apply [[$Arow_map]]
   // CHECK-DAG: [[col:%.+]] = affine.apply [[$Acol_map]]
   // CHECK: nvgpu.ldmatrix %arg2[[[C0]], [[row]], [[col]]] {numTiles = 2 : i32, transpose = false} : memref<2x20x20xf16, 3> -> vector<2x2xf16>
   %C = vector.transfer_read %arg2[%c0, %c1, %c3], %cst {in_bounds = [true, true]} : memref<2x20x20xf16, 3>, vector<16x8xf16>
   %D = vector.contract {indexing_maps = [#map1, #map2, #map3], iterator_types = ["parallel", "parallel", "reduction"], kind = #vector.kind<add>} %A, %B, %C : vector<16x16xf16>, vector<8x16xf16> into vector<16x8xf16>
   vector.transfer_write %D, %arg2[%c0, %c1, %c3] {in_bounds = [true, true]} : vector<16x8xf16>, memref<2x20x20xf16, 3>
   return
 }
func.func @m16n8k16_fp16_row_col_row(%arg0: memref<20x20xf16, 3>, %arg1: memref<20x20xf16, 3>, %arg2: memref<20x20xf16, 3>) {
   %c0 = arith.constant 0 : index
   %c1 = arith.constant 1 : index
   %c3 = arith.constant 3 : index
   %cst = arith.constant 0.000000e+00 : f16
   // CHECK-DAG: [[row:%.+]] = affine.apply [[$rowA_map]]
   // CHECK-DAG: [[col:%.+]] = affine.apply [[$colA_map]]
   // CHECK: nvgpu.ldmatrix %arg0[[[row]], [[col]]] {numTiles = 4 : i32
   // CHECK-SAME: transpose = false
-  
   // CHECK-DAG: [[row:%.+]] = affine.apply [[$rowB_map]]
   // CHECK-DAG: [[col:%.+]] = affine.apply [[$colB_map]]
   // CHECK: nvgpu.ldmatrix %arg1[[[row]], [[col]]] {numTiles = 2 : i32
   // CHECK-SAME: transpose = false
 
   // CHECK-DAG: [[row:%.+]] = affine.apply [[$rowA_map]]
-  // CHECK-DAG: [[col:%.+]] = affine.apply [[$colA_map]]   
+  // CHECK-DAG: [[col:%.+]] = affine.apply [[$colA_map]]
   // CHECK: nvgpu.ldmatrix %arg2[[[row]], [[col]]] {numTiles = 2 : i32
   // CHECK-SAME: transpose = false
   %A = vector.transfer_read %arg0[%c1, %c3], %cst {in_bounds = [true, true]} : memref<20x20xf16, 3>, vector<16x16xf16>
   %B = vector.transfer_read %arg1[%c1, %c3], %cst {in_bounds = [true, true]} : memref<20x20xf16, 3>, vector<8x16xf16>
   %C = vector.transfer_read %arg2[%c1, %c3], %cst {in_bounds = [true, true]} : memref<20x20xf16, 3>, vector<16x8xf16>
   %D = vector.contract {indexing_maps = [#map1, #map2, #map3], iterator_types = ["parallel", "parallel", "reduction"], kind = #vector.kind<add>} %A, %B, %C : vector<16x16xf16>, vector<8x16xf16> into vector<16x8xf16>
   vector.transfer_write %D, %arg2[%c0, %c0] {in_bounds = [true, true]} : vector<16x8xf16>, memref<20x20xf16, 3>
   return
func.func @m16n8k4_tf32_f32_row_row_row(%arg0: memref<20x20xf32, 3>, %arg1: memref<20x20xf32, 3>, %arg2: memref<20x20xf32>) {
   %c1 = arith.constant 1 : index
   %c3 = arith.constant 3 : index
   %cst = arith.constant 0.000000e+00 : f32
 
   // CHECK: [[c_frag:%.+]] = arith.constant {{.*}} : vector<2x2xf32>
 
   // CHECK-DAG: [[row:%.+]] = affine.apply [[$rowA_map]]
   // CHECK-DAG: [[col:%.+]] = affine.apply [[$colA_map]]
-  // CHECK: [[a_frag:%.+]] = nvgpu.ldmatrix %arg0[[[row]], [[col]]] {numTiles = 2 : i32, transpose = false}  
+  // CHECK: [[a_frag:%.+]] = nvgpu.ldmatrix %arg0[[[row]], [[col]]] {numTiles = 2 : i32, transpose = false}
 
   // b and c are not loaded by ldmatrix in this test.
   // CHECK-NOT: nvgpu.ldmatrix
 
   // CHECK-DAG: [[row:%.+]] = affine.apply [[$rowB_map]]
   // CHECK-DAG: [[col:%.+]] = affine.apply [[$colB_map]]
-  // CHECK: [[b_el:%.+]] = memref.load {{%.+}} : memref<20x20xf32, 3>  
+  // CHECK: [[b_el:%.+]] = memref.load {{%.+}} : memref<20x20xf32, 3>
   // CHECK: [[b_frag:%.+]] = vector.insert [[b_el]], {{.*}} : f32 into vector<1x1xf32>
 
   // CHECK: [[d_frag:%.+]] = nvgpu.mma.sync([[a_frag]], [[b_frag]], [[c_frag]])
   // CHECK-SAME: mmaShape = [16, 8, 4]
   // CHECK-SAME: -> vector<2x2xf32>
   %A = vector.transfer_read %arg0[%c1, %c3], %cst {in_bounds = [true, true]} : memref<20x20xf32, 3>, vector<16x4xf32>
-  %B = vector.transfer_read %arg1[%c3, %c3], %cst {permutation_map = #map0, in_bounds = [true, true]} : memref<20x20xf32, 3>, vector<8x4xf32>  
+  %B = vector.transfer_read %arg1[%c3, %c3], %cst {permutation_map = #map0, in_bounds = [true, true]} : memref<20x20xf32, 3>, vector<8x4xf32>
   %D = vector.contract {indexing_maps = [#map1, #map2, #map3], iterator_types = ["parallel", "parallel", "reduction"], kind = #vector.kind<add>} %A, %B, %cst_0 : vector<16x4xf32>, vector<8x4xf32> into vector<16x8xf32>
 
   // CHECK: vector.extract [[d_frag]][0] : vector<2x2xf32>
   // CHECK: affine.apply [[$rowC_map]]
   // CHECK: affine.apply [[$colC_map]]
   // CHECK: vector.store
   // CHECK: vector.extract [[d_frag]][1] : vector<2x2xf32>
   // CHECK: affine.apply [[$rowC8_map]]
func.func @m16n8k64_int4_row_col_row(%arg0: memref<128x128xi4, 3>, %arg1: memref<128x128xi4, 3>, %arg2: memref<128x128xi32>) {
   // CHECK: [[row:%.+]] = affine.apply [[$rowA0_map]]()[[[lane]]]
   // CHECK: [[col:%.+]] = affine.apply [[$colA0_map]]()[[[lane]]]
   // CHECK: nvgpu.ldmatrix %arg0[[[row]], [[col]]] {numTiles = 4 : i32, transpose = false} : memref<128x128xi4, 3> -> vector<4x8xi4>
 
   // CHECK: [[lane:%.+]] = gpu.lane_id
   // CHECK: [[row:%.+]] = affine.apply [[$rowB0_map]]()[[[lane]]]
   // CHECK: [[col:%.+]] = affine.apply [[$colB0_map]]()[[[lane]]]
   // CHECK: nvgpu.ldmatrix %arg1[[[row]], [[col]]] {numTiles = 2 : i32, transpose = false} : memref<128x128xi4, 3> -> vector<2x8xi4>
-  
   // CHECK: [[lane:%.+]] = gpu.lane_id
   // CHECK: [[row:%.+]] = affine.apply [[$rowC0_map]]()[{{%.+}}]
   // CHECK: [[col:%.+]] = affine.apply [[$colC0_map]]()[{{%.+}}]
   // CHECK: vector.load %arg2[[[row]], [[col]]] : memref<128x128xi32>, vector<2xi32>
 
   // CHECK: [[row:%.+]] = affine.apply [[$rowC8_map]]()[{{%.+}}]
   // CHECK: [[col:%.+]] = affine.apply [[$colC0_map]]()[{{%.+}}]
   // CHECK: vector.load %arg2[[[row]], [[col]]] : memref<128x128xi32>, vector<2xi32>
   // CHECK-NOT: vector.load
 
   %A = vector.transfer_read %arg0[%c0, %c0], %cst {in_bounds = [true, true]} : memref<128x128xi4, 3>, vector<16x64xi4>
   %B = vector.transfer_read %arg1[%c0, %c0], %cst {in_bounds = [true, true]} : memref<128x128xi4, 3>, vector<8x64xi4>
   %C = vector.transfer_read %arg2[%c0, %c0], %cst0 {in_bounds = [true, true]} : memref<128x128xi32>, vector<16x8xi32>
   // CHECK: [[d:%.+]] = nvgpu.mma.sync({{.*}}) {mmaShape = [16, 8, 64]} : (vector<4x8xi4>, vector<2x8xi4>, vector<2x2xi32>) -> vector<2x2xi32>
   %D = vector.contract {indexing_maps = [#map1, #map2, #map3], iterator_types = ["parallel", "parallel", "reduction"], kind = #vector.kind<add>} %A, %B, %C : vector<16x64xi4>, vector<8x64xi4> into vector<16x8xi32>
 
   // CHECK: [[lane:%.+]] = gpu.lane_id
-  // CHECK: [[v:%.+]] = vector.extract [[d]][0] : vector<2x2xi32>  
+  // CHECK: [[v:%.+]] = vector.extract [[d]][0] : vector<2x2xi32>
   // CHECK: [[row:%.+]] = affine.apply [[$rowC0_map]]()[[[lane]]]
   // CHECK: [[col:%.+]] = affine.apply [[$colC0_map]]()[[[lane]]]
   // CHECK: vector.store [[v]], %arg2[[[row]], [[col]]] : memref<128x128xi32>, vector<2xi32>
-  
   // CHECK: [[v:%.+]] = vector.extract [[d]][1] : vector<2x2xi32>
   // CHECK: [[row:%.+]] = affine.apply [[$rowC8_map]]()[[[lane]]]
   // CHECK: [[col:%.+]] = affine.apply [[$colC0_map]]()[[[lane]]]
   // CHECK: vector.store [[v]], %arg2[[[row]], [[col]]] : memref<128x128xi32>, vector<2xi32>
   vector.transfer_write %D, %arg2[%c0, %c0] {in_bounds = [true, true]} : vector<16x8xi32>, memref<128x128xi32>
   return
 }
 
func.func @m16n8k32_int8_row_col_row(%arg0: memref<128x128xi8, 3>, %arg1: memref<128x128xi8, 3>, %arg2: memref<128x128xi32>) {
   // CHECK: [[row:%.+]] = affine.apply [[$rowA0_map]]()[[[lane]]]
   // CHECK: [[col:%.+]] = affine.apply [[$colA0_map]]()[[[lane]]]
   // CHECK: nvgpu.ldmatrix %arg0[[[row]], [[col]]] {numTiles = 4 : i32, transpose = false} : memref<128x128xi8, 3> -> vector<4x4xi8>
 
   // CHECK: [[lane:%.+]] = gpu.lane_id
   // CHECK: [[row:%.+]] = affine.apply [[$rowB0_map]]()[[[lane]]]
   // CHECK: [[col:%.+]] = affine.apply [[$colB0_map]]()[[[lane]]]
   // CHECK: nvgpu.ldmatrix %arg1[[[row]], [[col]]] {numTiles = 2 : i32, transpose = false} : memref<128x128xi8, 3> -> vector<2x4xi8>
-  
   // CHECK: [[lane:%.+]] = gpu.lane_id
   // CHECK: [[row:%.+]] = affine.apply [[$rowC0_map]]()[[[lane]]]
   // CHECK: [[col:%.+]] = affine.apply [[$colC0_map]]()[[[lane]]]
   // CHECK: vector.load %arg2[[[row]], [[col]]] : memref<128x128xi32>, vector<2xi32>
   // CHECK: [[row:%.+]] = affine.apply [[$rowC8_map]]()[[[lane]]]
   // CHECK: [[col:%.+]] = affine.apply [[$colC0_map]]()[[[lane]]]
   // CHECK: vector.load %arg2[[[row]], [[col]]] : memref<128x128xi32>, vector<2xi32>
   // CHECK-NOT: vector.load %arg2{{.*}}
 
   %A = vector.transfer_read %arg0[%c0, %c0], %cst {in_bounds = [true, true]} : memref<128x128xi8, 3>, vector<16x32xi8>
   %B = vector.transfer_read %arg1[%c0, %c0], %cst {in_bounds = [true, true]} : memref<128x128xi8, 3>, vector<8x32xi8>
   %C = vector.transfer_read %arg2[%c0, %c0], %cst0 {in_bounds = [true, true]} : memref<128x128xi32>, vector<16x8xi32>
   // CHECK: [[d:%.+]] = nvgpu.mma.sync({{.*}}) {mmaShape = [16, 8, 32]} : (vector<4x4xi8>, vector<2x4xi8>, vector<2x2xi32>) -> vector<2x2xi32>
   %D = vector.contract {indexing_maps = [#map1, #map2, #map3], iterator_types = ["parallel", "parallel", "reduction"], kind = #vector.kind<add>} %A, %B, %C : vector<16x32xi8>, vector<8x32xi8> into vector<16x8xi32>
 
   // CHECK: [[lane:%.+]] = gpu.lane_id
-  // CHECK: [[v:%.+]] = vector.extract [[d]][0] : vector<2x2xi32>  
+  // CHECK: [[v:%.+]] = vector.extract [[d]][0] : vector<2x2xi32>
   // CHECK: [[row:%.+]] = affine.apply [[$rowC0_map]]()[[[lane]]]
   // CHECK: [[col:%.+]] = affine.apply [[$colC0_map]]()[[[lane]]]
   // CHECK: vector.store [[v]], %arg2[[[row]], [[col]]] : memref<128x128xi32>, vector<2xi32>
   // CHECK: [[v:%.+]] = vector.extract [[d]][1] : vector<2x2xi32>
   // CHECK: [[row:%.+]] = affine.apply [[$rowC8_map]]()[[[lane]]]
   // CHECK: [[col:%.+]] = affine.apply [[$colC0_map]]()[[[lane]]]
   // CHECK: vector.store [[v]], %arg2[[[row]], [[col]]] : memref<128x128xi32>, vector<2xi32>
   vector.transfer_write %D, %arg2[%c0, %c0] {in_bounds = [true, true]} : vector<16x8xi32>, memref<128x128xi32>
func.func @m16n8k8_tf32_f32_col_col_row(%arg0: memref<20x20xf32, 3>, %arg1: memref<20x20xf32, 3>, %arg2: memref<20x20xf32>) {
   // CHECK-DAG: [[col:%.+]] = affine.apply [[$colB0_map]]
   // CHECK: [[b_frag:%.+]] = nvgpu.ldmatrix %arg1[[[row]], [[col]]] {numTiles = 2 : i32, transpose = false}
 
   // CHECK: [[d_frag:%.+]] = nvgpu.mma.sync([[a_frag]], [[b_frag]], [[c_frag]])
   // CHECK-SAME: mmaShape = [16, 8, 8]
   // CHECK-SAME: -> vector<2x2xf32>
   %A = vector.transfer_read %arg0[%c0, %c0], %cst {in_bounds = [true, true], permutation_map = #map0} : memref<20x20xf32, 3>, vector<16x8xf32>
   %B = vector.transfer_read %arg1[%c0, %c0], %cst {in_bounds = [true, true]} : memref<20x20xf32, 3>, vector<8x8xf32>
-  %D = vector.contract {indexing_maps = [#map1, #map2, #map3], iterator_types = ["parallel", "parallel", "reduction"], 
+  %D = vector.contract {indexing_maps = [#map1, #map2, #map3], iterator_types = ["parallel", "parallel", "reduction"],
     kind = #vector.kind<add>} %A, %B, %cst_0 : vector<16x8xf32>, vector<8x8xf32> into vector<16x8xf32>
 
   // CHECK: vector.extract [[d_frag]][0] : vector<2x2xf32>
   // CHECK: affine.apply [[$rowC_map]]
   // CHECK: affine.apply [[$colC_map]]
   // CHECK: vector.store
   // CHECK: vector.extract [[d_frag]][1] : vector<2x2xf32>
   // CHECK: affine.apply [[$rowC8_map]]
   // CHECK: affine.apply [[$colC_map]]
   // CHECK: vector.store
   vector.transfer_write %D, %arg2[%c16, %c8] {in_bounds = [true, true]} : vector<16x8xf32>, memref<20x20xf32>
   return
 }

mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir

 // CHECK:       %[[T16:.*]] = llvm.extractvalue %[[T7]][1] : !llvm.array<2 x vector<3xf32>>
 // CHECK:       %[[T17:.*]] = llvm.intr.fmuladd(%[[T14]], %[[B]], %[[T16]]) : (vector<3xf32>, vector<3xf32>, vector<3xf32>) -> vector<3xf32>
 // CHECK:       %[[T18:.*]] = llvm.insertvalue %[[T17]], %[[T11]][1] : !llvm.array<2 x vector<3xf32>>
 // CHECK:       %[[T19:.*]] = builtin.unrealized_conversion_cast %[[T18]] : !llvm.array<2 x vector<3xf32>> to vector<2x3xf32>
 // CHECK:       return %[[T19]] : vector<2x3xf32>
 
 
 // -----
- 
 func.func @shuffle_0D_direct(%arg0: vector<f32>) -> vector<3xf32> {
   %1 = vector.shuffle %arg0, %arg0 [0, 1, 0] : vector<f32>, vector<f32>
   return %1 : vector<3xf32>
 }
 // CHECK-LABEL: @shuffle_0D_direct(
 //  CHECK-SAME:     %[[A:.*]]: vector<f32>
 //       CHECK:   %[[c:.*]] = builtin.unrealized_conversion_cast %[[A]] : vector<f32> to vector<1xf32>
 //       CHECK:   %[[s:.*]] = llvm.shufflevector %[[c]], %[[c]] [0, 1, 0] : vector<1xf32>

mlir/test/Dialect/Affine/affine-loop-invariant-code-motion.mlir

affine.for %arg0 = 0 to 10 {
 
     }
   }
 
   // CHECK: memref.alloc() : memref<10xf32>
   // CHECK-NEXT: %[[cst:.*]] = arith.constant 8.000000e+00 : f32
   // CHECK-NEXT: affine.for %{{.*}} = 0 to 10 {
   // CHECK-NEXT: affine.apply #map{{[0-9]*}}(%arg0)
-  // CHECK-NEXT: affine.if 
+  // CHECK-NEXT: affine.if
   // CHECK-NEXT: arith.addf %[[cst]], %[[cst]] : f32
-  // CHECK-NEXT: affine.store 
+  // CHECK-NEXT: affine.store
   // CHECK-NEXT: }
 
 
   return
 }
 
 // -----
 
func.func @dependent_stores() {
   // CHECK-NEXT: %[[cst:.*]] = arith.constant 7.000000e+00 : f32
   // CHECK-NEXT: %[[cst_0:.*]] = arith.constant 8.000000e+00 : f32
   // CHECK-NEXT: arith.addf %[[cst]], %[[cst_0]] : f32
   // CHECK-NEXT: %[[mul:.*]] = arith.mulf %[[cst]], %[[cst]] : f32
   // CHECK-NEXT: affine.for %{{.*}} = 0 to 10 {
 
   // CHECK-NEXT: affine.for %{{.*}} = 0 to 10 {
   // CHECK-NEXT:   affine.store %[[mul]]
-  // CHECK-NEXT:   affine.store 
+  // CHECK-NEXT:   affine.store
 
   return
 }
 
 // -----
 
 func.func @independent_stores() {
   %m = memref.alloc() : memref<10xf32>
func.func @load_dependent_store() {
   }
 
   // CHECK: memref.alloc() : memref<10xf32>
   // CHECK-NEXT: %[[cst:.*]] = arith.constant 7.000000e+00 : f32
   // CHECK-NEXT: %[[cst_0:.*]] = arith.constant 8.000000e+00 : f32
   // CHECK-NEXT: arith.addf %[[cst]], %[[cst_0]] : f32
   // CHECK-NEXT: arith.addf %[[cst]], %[[cst]] : f32
   // CHECK-NEXT: affine.for %{{.*}} = 0 to 10 {
-  // CHECK-NEXT: affine.for 
-  // CHECK-NEXT:   affine.store 
+  // CHECK-NEXT: affine.for
+  // CHECK-NEXT:   affine.store
   // CHECK-NEXT:   affine.load
 
   return
 }
 
 // -----
 
 func.func @load_after_load() {
affine.for %arg0 = 0 to 10 {
     }
   }
 
   // CHECK: memref.alloc() : memref<10xf32>
   // CHECK-NEXT: %[[cst:.*]] = arith.constant 8.000000e+00 : f32
   // CHECK-NEXT: affine.for %{{.*}} = 0 to 10 {
   // CHECK-NEXT: }
   // CHECK-NEXT: affine.for %{{.*}} = 0 to 10 {
-  // CHECK-NEXT: affine.if 
+  // CHECK-NEXT: affine.if
   // CHECK-NEXT: arith.addf %[[cst]], %[[cst]] : f32
   // CHECK-NEXT: affine.store
   // CHECK-NEXT: }
 
 
   return
 }
 
affine.for %arg1 = 0 to 10 {
       }
     }
   }
 
   // CHECK: memref.alloc() : memref<10xf32>
   // CHECK-NEXT: %[[cst:.*]] = arith.constant 8.000000e+00 : f32
   // CHECK-NEXT: affine.for %{{.*}} = 0 to 10 {
   // CHECK-NEXT: affine.for %{{.*}} = 0 to 10 {
-  // CHECK-NEXT: affine.if 
+  // CHECK-NEXT: affine.if
   // CHECK-NEXT:   arith.addf %[[cst]], %[[cst]] : f32
-  // CHECK-NEXT:   affine.store 
+  // CHECK-NEXT:   affine.store
   // CHECK-NEXT: }
   // CHECK-NEXT: }
 
 
   return
 }
 
 // -----
affine.for %arg1 = 0 to 10 {
       }
     }
   }
 
   // CHECK: memref.alloc() : memref<10xf32>
   // CHECK-NEXT: %[[cst:.*]] = arith.constant 8.000000e+00 : f32
   // CHECK-NEXT: affine.for %[[arg0:.*]] = 0 to 10 {
   // CHECK-NEXT: affine.for %[[arg1:.*]] = 0 to 10 {
-  // CHECK-NEXT: affine.if 
+  // CHECK-NEXT: affine.if
   // CHECK-NEXT: arith.addf %[[cst]], %[[cst]] : f32
   // CHECK-NEXT: affine.store {{.*}}[%[[arg0]]] : memref<10xf32>
-  // CHECK-NEXT: affine.if 
+  // CHECK-NEXT: affine.if
   // CHECK-NEXT: affine.store {{.*}}[%[[arg1]]] : memref<10xf32>
   // CHECK-NEXT: }
   // CHECK-NEXT: }
   // CHECK-NEXT: }
 
 
   return
 }
affine.for %arg1 = 0 to 10 {
       }
     }
   }
 
   // CHECK: memref.alloc() : memref<10xf32>
   // CHECK-NEXT: %[[cst:.*]] = arith.constant 8.000000e+00 : f32
   // CHECK-NEXT: affine.for %[[arg0:.*]] = 0 to 10 {
   // CHECK-NEXT: affine.for %[[arg1:.*]] = 0 to 10 {
-  // CHECK-NEXT: affine.if 
+  // CHECK-NEXT: affine.if
   // CHECK-NEXT: arith.addf %[[cst]], %[[cst]] : f32
   // CHECK-NEXT: affine.store {{.*}}[%[[arg0]]] : memref<10xf32>
-  // CHECK-NEXT: affine.if 
+  // CHECK-NEXT: affine.if
   // CHECK-NEXT: affine.store {{.*}}[%[[arg0]]] : memref<10xf32>
   // CHECK-NEXT: } else {
   // CHECK-NEXT: affine.store {{.*}}[%[[arg1]]] : memref<10xf32>
   // CHECK-NEXT: }
   // CHECK-NEXT: }
   // CHECK-NEXT: }
 
 
func.func @invariant_affine_nested_if_else2() {
   }
 
   // CHECK: memref.alloc() : memref<10xf32>
   // CHECK-NEXT: memref.alloc() : memref<10xf32>
   // CHECK-NEXT: %[[cst:.*]] = arith.constant 8.000000e+00 : f32
   // CHECK-NEXT: affine.for %[[arg0:.*]] = 0 to 10 {
   // CHECK-NEXT: }
   // CHECK-NEXT: affine.for %{{.*}} = 0 to 10 {
-  // CHECK-NEXT: affine.if 
+  // CHECK-NEXT: affine.if
   // CHECK-NEXT: arith.addf %[[cst]], %[[cst]] : f32
   // CHECK-NEXT: affine.load {{.*}}[%[[arg0]]] : memref<10xf32>
-  // CHECK-NEXT: affine.if 
+  // CHECK-NEXT: affine.if
   // CHECK-NEXT: affine.store {{.*}}[%[[arg0]]] : memref<10xf32>
   // CHECK-NEXT: } else {
   // CHECK-NEXT: affine.load {{.*}}[%[[arg0]]] : memref<10xf32>
   // CHECK-NEXT: }
   // CHECK-NEXT: }
 
 
   return
affine.for %arg0 = 0 to 10 {
     }
   }
 
   // CHECK: memref.alloc() : memref<10xf32>
   // CHECK-NEXT: %[[cst:.*]] = arith.constant 8.000000e+00 : f32
   // CHECK-NEXT: affine.for %{{.*}} = 0 to 10 {
   // CHECK-NEXT: }
   // CHECK-NEXT: affine.for %[[arg0:.*]] = 0 to 10 {
-  // CHECK-NEXT: affine.if 
+  // CHECK-NEXT: affine.if
   // CHECK-NEXT: arith.addf %[[cst]], %[[cst]] : f32
   // CHECK-NEXT: affine.load {{.*}}[%[[arg0]]] : memref<10xf32>
-  // CHECK-NEXT: affine.if 
+  // CHECK-NEXT: affine.if
   // CHECK-NEXT: affine.load {{.*}}[%[[arg0]]] : memref<10xf32>
   // CHECK-NEXT: }
   // CHECK-NEXT: }
 
 
   return
 }
 
affine.for %arg1 = 0 to 10 {
       }
     }
   }
 
   // CHECK: memref.alloc() : memref<10xf32>
   // CHECK-NEXT: %[[cst:.*]] = arith.constant 8.000000e+00 : f32
   // CHECK-NEXT: affine.for %[[arg0:.*]] = 0 to 10 {
   // CHECK-NEXT: affine.for %[[arg1:.*]] = 0 to 10 {
-  // CHECK-NEXT: affine.if 
+  // CHECK-NEXT: affine.if
   // CHECK-NEXT: arith.addf %[[cst]], %[[cst]] : f32
   // CHECK-NEXT: affine.store {{.*}}[%[[arg0]]] : memref<10xf32>
   // CHECK-NEXT: affine.for %[[arg2:.*]] = 0 to 10 {
   // CHECK-NEXT: affine.store {{.*}}[%[[arg2]]] : memref<10xf32>
   // CHECK-NEXT: }
   // CHECK-NEXT: }
   // CHECK-NEXT: }
 
affine.for %arg0 = 0 to 5 {
     %c0 = arith.constant 0 : index
     %v = affine.load %m2[%c0] : memref<100xf32>
     affine.store %v, %m[%arg0] : memref<100xf32>
   }
 
   // CHECK: memref.alloc() : memref<100xf32>
   // CHECK-NEXT: memref.alloc() : memref<100xf32>
   // CHECK-NEXT: arith.constant 0 : index
-  // CHECK-NEXT: affine.load 
+  // CHECK-NEXT: affine.load
   // CHECK-NEXT: affine.for %{{.*}} = 0 to 5 {
   // CHECK-NEXT:  affine.store
 
 
   return
 }
 
 // -----
affine.for %arg0 = 0 to 10 {
     }
   }
 
   // CHECK: memref.alloc() : memref<10xf32>
   // CHECK-NEXT: %[[cst:.*]] = arith.constant 8.000000e+00 : f32
   // CHECK-NEXT: arith.constant 0 : index
   // CHECK-NEXT: affine.for %{{.*}} = 0 to 10 {
   // CHECK-NEXT:   affine.load
-  // CHECK-NEXT:   affine.for 
+  // CHECK-NEXT:   affine.for
   // CHECK-NEXT:    affine.store %[[cst]]
 
 
   return
 }
 
 // -----
 

mlir/test/Dialect/Affine/affine-loop-normalize.mlir

 // CHECK-NEXT:            %[[IIIV:.*]] = affine.apply [[$INTRAIV]](%[[IIV]], %[[II]])
 // CHECK-NEXT:            affine.for %[[JJ:.*]] = 0 to min [[$INTRAUB]](%[[JIV]])[%[[DIM1]]] {
 // CHECK-NEXT:              %[[JJIV:.*]] = affine.apply [[$INTRAIV]](%[[JIV]], %[[JJ]])
 // CHECK-NEXT:              affine.for %[[KK:.*]] = 0 to min [[$INTRAUB]](%[[KIV]])[%[[DIM2]]] {
 // CHECK-NEXT:                %[[KKIV:.*]] = affine.apply [[$INTRAIV]](%[[KIV]], %[[KK]])
 // CHECK-NEXT:                %{{.*}} = affine.load %[[ARG0]][%[[IIIV]], %[[KKIV]]] : memref<1024x1024xf32>
 // CHECK-NEXT:                %{{.*}} = affine.load %[[ARG1]][%[[KKIV]], %[[JJIV]]] : memref<1024x1024xf32>
 // CHECK-NEXT:                %{{.*}} = affine.load %[[ARG2]][%[[IIIV]], %[[JJIV]]] : memref<1024x1024xf32>
-// CHECK-NEXT:                %{{.*}} = arith.mulf 
-// CHECK-NEXT:                %{{.*}} = arith.addf 
+// CHECK-NEXT:                %{{.*}} = arith.mulf
+// CHECK-NEXT:                %{{.*}} = arith.addf
 // CHECK-NEXT:                affine.store %{{.*}}, %[[ARG2]]{{.*}} : memref<1024x1024xf32>
 // CHECK-NEXT:              }
 // CHECK-NEXT:            }
 // CHECK-NEXT:          }
 // CHECK-NEXT:        }
 // CHECK-NEXT:      }
 // CHECK-NEXT:    }
 // CHECK-NEXT:    return

mlir/test/Dialect/Affine/ops.mlir

 // Check that an explicit affine.yield is not printed in custom format.
 // Check that no extra terminator is introduced.
 // CHECK-LABEL: @affine.yield
 func.func @affine.yield() {
   // CHECK: affine.for
   // CHECK-NEXT: }
   //
   // GENERIC:      "affine.for"() ({
-  // GENERIC-NEXT: ^bb0(%{{.*}}: index):  
+  // GENERIC-NEXT: ^bb0(%{{.*}}: index):
   // GENERIC-NEXT:   "affine.yield"() : () -> ()
   // GENERIC-NEXT: }) {lower_bound = #map, step = 1 : index, upper_bound = #map1} : () -> ()
   affine.for %i = 0 to 10 {
     "affine.yield"() : () -> ()
   }
   return
 }
 

mlir/test/Dialect/GPU/transform-gpu-failing.mlir

-// RUN: mlir-opt --test-transform-dialect-interpreter --split-input-file  -canonicalize -cse --verify-diagnostics %s 
+// RUN: mlir-opt --test-transform-dialect-interpreter --split-input-file  -canonicalize -cse --verify-diagnostics %s
 
-func.func @map_nested_foreach_to_threads_not_gpu_launch() -> () {  
+func.func @map_nested_foreach_to_threads_not_gpu_launch() -> () {
   %1 = tensor.empty() : tensor<4xf32>
-  return 
+  return
 }
 transform.sequence failures(propagate) {
 ^bb0(%arg0: !pdl.operation):
-  %funcop = transform.structured.match ops{["tensor.empty"]} in %arg0    
+  %funcop = transform.structured.match ops{["tensor.empty"]} in %arg0
   // expected-error @below {{Given target is not gpu.launch}}
   %1 = transform.gpu.map_nested_foreach_to_threads %funcop
 }
 
 // -----
 
 func.func @map_nested_foreach_to_threads_excessive_threads(%x: memref<2 x 32 x f32>, %y: memref<2 x 32 x f32>, %t: memref<32 x f32>, %alpha : f32, %stream : !gpu.async.token) -> memref<2 x 32 x f32> {
   %one = arith.constant 1 : index

 
 func.func @map_nested_foreach_to_threads_not_buffer(%x: tensor<32x32xf32>, %y: tensor<32x32xf32>, %z: tensor<32x32xf32>, %stream : !gpu.async.token) {
   %one = arith.constant 1 : index
   %name = gpu.launch async[%stream] blocks(%arg3, %arg4, %arg5) in (%arg9 = %one, %arg10 = %one, %arg11 = %one)
             threads(%arg6, %arg7, %arg8) in (%arg12 = %one, %arg13 = %one, %arg14 = %one)
   {
     %t = linalg.matmul ins(%x, %y: tensor<32x32xf32>, tensor<32x32xf32>) outs(%z : tensor<32x32xf32>) -> tensor<32x32xf32>
     gpu.terminator
-  }  
-  return 
+  }
+  return
 }
 
 transform.sequence failures(propagate) {
 ^bb1(%arg0: !pdl.operation):
   %matmul = transform.structured.match ops{["linalg.matmul"]} in %arg0
   %foreach, %tiled = transform.structured.tile_to_foreach_thread_op %matmul num_threads [10, 20, 30] (mapping = [ #gpu.thread<y>, #gpu.thread<x>, #gpu.thread<z> ] )
   %funcop = transform.structured.match ops{["gpu.launch"]} in %arg0
-  // expected-error @below {{only bufferized scf.foreach_thread lowers to gpu.thread_id}}    
+  // expected-error @below {{only bufferized scf.foreach_thread lowers to gpu.thread_id}}
   transform.gpu.map_nested_foreach_to_threads %funcop { blockDim = [128, 4, 1] }
 }
 
 // -----
 
 
-func.func @map_foreach_to_blocks_not_gpu_launch() -> () {  
+func.func @map_foreach_to_blocks_not_gpu_launch() -> () {
   // expected-note @below {{when applied to this payload op}}
   %1 = tensor.empty() : tensor<4xf32>
-  return 
+  return
 }
 transform.sequence failures(propagate) {
 ^bb0(%arg0: !pdl.operation):
-  %funcop = transform.structured.match ops{["tensor.empty"]} in %arg0    
+  %funcop = transform.structured.match ops{["tensor.empty"]} in %arg0
   // expected-error @below {{Given target is not gpu.launch}}
   %1 = transform.gpu.map_foreach_to_blocks %funcop
 }
 
 // -----
 
 func.func @map_foreach_to_blocks_not_unique(%x: memref<2 x 32 x f32>, %y: memref<2 x 32 x f32>, %t: memref<32 x f32>, %alpha : f32, %stream : !gpu.async.token) -> memref<2 x 32 x f32> {
   %one = arith.constant 1 : index
%name = gpu.launch async[%stream] blocks(%arg3, %arg4, %arg5) in (%arg9 = %one, %arg10 = %one, %arg11 = %one)
      }  { mapping = [#gpu.thread<y>, #gpu.thread<x>] }
     gpu.terminator
   }
 
   return %y : memref<2 x 32 x f32>
 }
 
 transform.sequence failures(propagate) {
-^bb0(%arg0: !pdl.operation):  
-  %funcop = transform.structured.match ops{["gpu.launch"]} in %arg0    
-  // expected-error @below {{could not find a unique topLevel scf.foreach_thread}}  
+^bb0(%arg0: !pdl.operation):
+  %funcop = transform.structured.match ops{["gpu.launch"]} in %arg0
+  // expected-error @below {{could not find a unique topLevel scf.foreach_thread}}
   %1 = transform.gpu.map_foreach_to_blocks %funcop
 }
 
 // -----
 
 // expected-note @below {{when applied to this payload op}}
 func.func @map_foreach_to_blocks_large_loop(%x: memref<2 x 32 x f32>, %y: memref<2 x 32 x f32>, %t: memref<32 x f32>, %alpha : f32, %stream : !gpu.async.token) -> memref<2 x 32 x f32> {
   %one = arith.constant 1 : index
func.func @map_foreach_to_blocks_large_loop(%x: memref<2 x 32 x f32>, %y: memref<2 x 32 x f32>, %t: memref<32 x f32>, %alpha : f32, %stream : !gpu.async.token) -> memref<2 x 32 x f32> {
   }  { mapping = [#gpu.thread<x>, #gpu.thread<y>] }
 
   scf.foreach_thread (%i, %j) in (%c7, %c9) {
       %4 = memref.load %x[%i, %j] : memref<2 x 32 x f32>
       %5 = memref.load %y[%i, %j] : memref<2 x 32 x f32>
       %6 = math.fma %alpha, %4, %5 : f32
       memref.store %6, %y[%i, %j] : memref<2 x 32 x f32>
   }  { mapping = [#gpu.thread<y>, #gpu.thread<x>] }
-  
   return %y : memref<2 x 32 x f32>
 }
 
 transform.sequence failures(propagate) {
-^bb0(%arg0: !pdl.operation):  
-  %funcop = transform.structured.match ops{["func.func"]} in %arg0   
-  // expected-error @below {{could not find a unique topLevel scf.foreach_thread}}   
+^bb0(%arg0: !pdl.operation):
+  %funcop = transform.structured.match ops{["func.func"]} in %arg0
+  // expected-error @below {{could not find a unique topLevel scf.foreach_thread}}
   %1 = transform.gpu.map_foreach_to_blocks %funcop { generate_gpu_launch }
 }
 
 // -----
 
 func.func @map_foreach_to_blocks_large_loop(%x: memref<2 x 32 x f32>, %y: memref<2 x 32 x f32>, %t: memref<32 x f32>, %alpha : f32, %stream : !gpu.async.token) -> memref<2 x 32 x f32> {
   %one = arith.constant 1 : index
   %c65535 = arith.constant 65535 : index
   scf.foreach_thread (%i, %j) in (%c65535, %c65535) {
       %4 = memref.load %x[%i, %j] : memref<2 x 32 x f32>
       %5 = memref.load %y[%i, %j] : memref<2 x 32 x f32>
       %6 = math.fma %alpha, %4, %5 : f32
       memref.store %6, %y[%i, %j] : memref<2 x 32 x f32>
   }  { mapping = [#gpu.block<x>, #gpu.block<y>] }
   return %y : memref<2 x 32 x f32>
 }
 
 transform.sequence failures(propagate) {
-^bb0(%arg0: !pdl.operation):  
-  %funcop = transform.structured.match ops{["func.func"]} in %arg0   
+^bb0(%arg0: !pdl.operation):
+  %funcop = transform.structured.match ops{["func.func"]} in %arg0
   // expected-error @below {{Trying to launch a GPU kernel with gridDim = (65535, 65535, 1) blockDim = (1, 1, 1). It is larger than the limits.}}
   %1 = transform.gpu.map_foreach_to_blocks %funcop { generate_gpu_launch }
 }
 
 // -----
 
 !type = memref<32x32xf32>
 func.func @saxpy2d_singleloop(%x: !type, %y: !type, %stream : !gpu.async.token) -> !type {

mlir/test/Dialect/LLVMIR/nvvm.mlir

func.func @nvvm_vote(%arg0 : i32, %arg1 : i1) -> i32 {
   llvm.return %0 : i32
 }
 
 // CHECK-LABEL: @llvm_nvvm_bar_warp_sync
 func.func @llvm_nvvm_bar_warp_sync(%mask : i32) {
   // CHECK: nvvm.bar.warp.sync %{{.*}}
   nvvm.bar.warp.sync %mask : i32
   llvm.return
-}  
+}
 
 // CHECK-LABEL: @nvvm_mma_m8n8k4_row_col_f32_f32
 func.func @nvvm_mma_m8n8k4_row_col_f32_f32(%a0 : vector<2xf16>, %a1 : vector<2xf16>,
                %b0 : vector<2xf16>, %b1 : vector<2xf16>,
                %c0 : f32, %c1 : f32, %c2 : f32, %c3 : f32, %c4 : f32, %c5 : f32, %c6 : f32, %c7 : f32) {
   // CHECK: nvvm.mma.sync
   %0 = nvvm.mma.sync A[%a0, %a1] B[%b0, %b1] C[%c0, %c1, %c2, %c3, %c4, %c5, %c6, %c7]
     {layoutA = #nvvm.mma_layout<row>, layoutB = #nvvm.mma_layout<col>,

mlir/test/Dialect/Linalg/collapse-dim.mlir

func.func @collapse_reduction(
   return %0 : tensor<2x32xf32>
 }
 
 // CHECK-DAG: #[[$MAP0:.*]] = affine_map<(d0, d1, d2) -> (d0, d1, d2)>
 // CHECK-DAG: #[[$MAP1:.*]] = affine_map<(d0, d1, d2) -> (d0, d1)>
 
 // CHECK-LABEL: func @collapse_reduction
 //       CHECK:   %[[T:.*]] = tensor.collapse_shape %{{.*}} {{\[}}[0], [1], [2, 3]] : tensor<2x32x10x4096xf32> into tensor<2x32x40960xf32>
-//       CHECK:   linalg.generic {indexing_maps = [#[[$MAP0]], #[[$MAP1]]], 
-//  CHECK-SAME:     iterator_types = ["parallel", "parallel", "reduction"]} 
+//       CHECK:   linalg.generic {indexing_maps = [#[[$MAP0]], #[[$MAP1]]],
+//  CHECK-SAME:     iterator_types = ["parallel", "parallel", "reduction"]}
 //  CHECK-SAME:     ins(%[[T]] : tensor<2x32x40960xf32>) outs(%{{.*}} : tensor<2x32xf32>) {
 //       CHECK:   } -> tensor<2x32xf32>
 
 // -----
 
 func.func @collapse_parallel(
     %arg0: tensor<32x2x10x4096xf32>, %arg1: tensor<2x32x10x4096xf32>) -> tensor<2x32x10x4096xf32> {
   %0 = linalg.generic {

 }
 
 // CHECK-DAG: #[[$MAP0:.*]] = affine_map<(d0, d1, d2) -> (d1, d0, d2)>
 // CHECK-DAG: #[[$MAP1:.*]] = affine_map<(d0, d1, d2) -> (d0, d1, d2)>
 
 // CHECK-LABEL: func @collapse_parallel
 //   CHECK-DAG:  %[[S:.*]] = tensor.collapse_shape %{{.*}} {{\[}}[0], [1], [2, 3]] : tensor<32x2x10x4096xf32> into tensor<32x2x40960xf32>
 //   CHECK-DAG:  %[[D:.*]] = tensor.collapse_shape %{{.*}} {{\[}}[0], [1], [2, 3]] : tensor<2x32x10x4096xf32> into tensor<2x32x40960xf32>
-//       CHECK:  %[[R:.*]] = linalg.generic {indexing_maps = [#[[$MAP0]], #[[$MAP1]]], 
-//  CHECK-SAME:     iterator_types = ["parallel", "parallel", "parallel"]} 
+//       CHECK:  %[[R:.*]] = linalg.generic {indexing_maps = [#[[$MAP0]], #[[$MAP1]]],
+//  CHECK-SAME:     iterator_types = ["parallel", "parallel", "parallel"]}
 //  CHECK-SAME:     ins(%[[S]] : tensor<32x2x40960xf32>) outs(%[[D]] : tensor<2x32x40960xf32>) {
 //       CHECK:   } -> tensor<2x32x40960xf32>
 //       CHECK:  tensor.expand_shape %[[R]] {{\[}}[0], [1], [2, 3]] : tensor<2x32x40960xf32> into tensor<2x32x10x4096xf32>

mlir/test/Dialect/Linalg/decompose-ops.mlir

 // RUN: mlir-opt -test-linalg-decompose-ops -cse -split-input-file %s | FileCheck %s
 // RUN: mlir-opt -test-linalg-decompose-ops=remove-dead-args-and-results -cse -split-input-file %s | FileCheck %s --check-prefix=CANONICALIZECHECK
 
 func.func @simple_op(%arg0 : tensor<?x?xf32>, %arg1 : tensor<?xf32>, %arg2 : tensor<?xf32>)
     -> (tensor<?x?xf32>, tensor<?x?xf32>) {
   %c0 = arith.constant 0 : index
   %c1 = arith.constant 1 : index
   %d0 = tensor.dim %arg0, %c0 : tensor<?x?xf32>
   %d1 = tensor.dim %arg0, %c1 : tensor<?x?xf32>
   %init1 = tensor.empty(%d1, %d0) : tensor<?x?xf32>
   %init2 = tensor.empty(%d0, %d1) : tensor<?x?xf32>
   %result:2 = linalg.generic {
-    indexing_maps = [affine_map<(d0, d1) -> (d0, d1)>, affine_map<(d0, d1) -> (d0)>, 
+    indexing_maps = [affine_map<(d0, d1) -> (d0, d1)>, affine_map<(d0, d1) -> (d0)>,
                      affine_map<(d0, d1) -> (d1)>, affine_map<(d0, d1) -> (d1, d0)>,
                      affine_map<(d0, d1) -> (d0, d1)>],
     iterator_types = ["parallel", "parallel"]}
     ins(%arg0, %arg1, %arg2 : tensor<?x?xf32>, tensor<?xf32>, tensor<?xf32>)
     outs(%init1, %init2 : tensor<?x?xf32>, tensor<?x?xf32>) {
     ^bb0(%b0 : f32, %b1 : f32, %b2 : f32, %b3 : f32, %b4 : f32) :
       %0 = arith.addf %b0, %b1 : f32
       %1 = arith.mulf %0, %b2 : f32
func.func @simple_op_permuted_outputs(%arg0 : tensor<?x?xf32>, %arg1 : tensor<?xf32>, %arg2 : tensor<?xf32>)
     -> (tensor<?x?xf32>, tensor<?x?xf32>, tensor<?x?xf32>) {
   %c0 = arith.constant 0 : index
   %c1 = arith.constant 1 : index
   %d0 = tensor.dim %arg0, %c0 : tensor<?x?xf32>
   %d1 = tensor.dim %arg0, %c1 : tensor<?x?xf32>
   %init1 = tensor.empty(%d1, %d0) : tensor<?x?xf32>
   %init2 = tensor.empty(%d0, %d1) : tensor<?x?xf32>
   %result:3 = linalg.generic {
-    indexing_maps = [affine_map<(d0, d1) -> (d0, d1)>, affine_map<(d0, d1) -> (d0)>, 
+    indexing_maps = [affine_map<(d0, d1) -> (d0, d1)>, affine_map<(d0, d1) -> (d0)>,
                      affine_map<(d0, d1) -> (d1)>, affine_map<(d0, d1) -> (d1, d0)>,
                      affine_map<(d0, d1) -> (d0, d1)>, affine_map<(d0, d1) -> (d0, d1)>],
     iterator_types = ["parallel", "parallel"]}
     ins(%arg0, %arg1, %arg2 : tensor<?x?xf32>, tensor<?xf32>, tensor<?xf32>)
     outs(%init1, %init2, %init2 : tensor<?x?xf32>, tensor<?x?xf32>, tensor<?x?xf32>) {
     ^bb0(%b0 : f32, %b1 : f32, %b2 : f32, %b3 : f32, %b4 : f32, %b5 : f32) :
       %0 = arith.addf %b0, %b1 : f32
       %1 = arith.mulf %0, %b2 : f32

mlir/test/Dialect/Linalg/detensorize_0d.mlir

 // RUN: mlir-opt %s -allow-unregistered-dialect -pass-pipeline="builtin.module(func.func(linalg-detensorize{aggressive-mode}))" | FileCheck %s
 
 #map = affine_map<() -> ()>
 
 func.func @detensor_simple(%arg1: tensor<f32>, %arg2: tensor<f32>) -> tensor<f32> attributes {iree.module.export} {
   %0 = tensor.empty() : tensor<f32>
   %1 = linalg.generic {indexing_maps = [#map, #map, #map], iterator_types = []}
     ins(%arg1, %arg2 : tensor<f32>, tensor<f32>)
     outs(%0 : tensor<f32>) {
-  ^bb0(%arg3: f32, %arg4: f32, %arg5: f32):  
+  ^bb0(%arg3: f32, %arg4: f32, %arg5: f32):
     %2 = arith.addf %arg3, %arg4 : f32
     linalg.yield %2 : f32
   } -> tensor<f32>
   return %1: tensor<f32>
 }
 // CHECK-LABEL: func @detensor_simple
 // CHECK-SAME:    (%[[arg1:.*]]: tensor<f32>, %[[arg2:.*]]: tensor<f32>)
 // CHECK-DAG:     %[[arg1_val:.*]] = tensor.extract %[[arg1]]
 // CHECK-DAG:     %[[arg2_val:.*]] = tensor.extract %[[arg2]]
 // CHECK:         %[[detensored_res:.*]] = arith.addf %[[arg1_val]], %[[arg2_val]]
 // CHECK:         %[[new_tensor_res:.*]] = tensor.from_elements %[[detensored_res]]
 // CHECK:         return %[[new_tensor_res]]
 
 func.func @detensor_op_sequence(%arg1: tensor<f32>, %arg2: tensor<f32>) -> tensor<f32> attributes {iree.module.export} {
   %0 = tensor.empty() : tensor<f32>
   %1 = linalg.generic {indexing_maps = [#map, #map, #map], iterator_types = []}
     ins(%arg1, %arg2 : tensor<f32>, tensor<f32>)
     outs(%0 : tensor<f32>) {
-  ^bb0(%arg3: f32, %arg4: f32, %arg5: f32):  
+  ^bb0(%arg3: f32, %arg4: f32, %arg5: f32):
     %2 = arith.addf %arg3, %arg4 : f32
     linalg.yield %2 : f32
   } -> tensor<f32>
 
   %3 = tensor.empty() : tensor<f32>
   %4 = linalg.generic {indexing_maps = [#map, #map, #map], iterator_types = []}
     ins(%arg1, %1 : tensor<f32>, tensor<f32>)
     outs(%3 : tensor<f32>) {
-  ^bb0(%arg3: f32, %arg4: f32, %arg5: f32):  
+  ^bb0(%arg3: f32, %arg4: f32, %arg5: f32):
     %5 = arith.mulf %arg3, %arg4 : f32
     linalg.yield %5 : f32
   } -> tensor<f32>
 
   %6 = tensor.empty() : tensor<f32>
   %7 = linalg.generic {indexing_maps = [#map, #map, #map], iterator_types = []}
     ins(%1, %4 : tensor<f32>, tensor<f32>)
     outs(%6 : tensor<f32>) {
-  ^bb0(%arg3: f32, %arg4: f32, %arg5: f32):  
+  ^bb0(%arg3: f32, %arg4: f32, %arg5: f32):
     %5 = arith.divf %arg3, %arg4 : f32
     linalg.yield %5 : f32
   } -> tensor<f32>
 
   return %7: tensor<f32>
 }
 // CHECK-LABEL: func @detensor_op_sequence
 // CHECK-SAME:    (%[[arg1:.*]]: tensor<f32>, %[[arg2:.*]]: tensor<f32>)
 // CHECK-DAG:     %[[arg1_val:.*]] = tensor.extract %[[arg1]]
 // CHECK-DAG:     %[[arg2_val:.*]] = tensor.extract %[[arg2]]
 // CHECK:         %[[detensored_res:.*]] = arith.addf %[[arg1_val]], %[[arg2_val]]
 // CHECK:         %[[detensored_res2:.*]] = arith.mulf %[[arg1_val]], %[[detensored_res]]
 // CHECK:         %[[detensored_res3:.*]] = arith.divf %[[detensored_res]], %[[detensored_res2]]
 // CHECK:         %[[new_tensor_res:.*]] = tensor.from_elements %[[detensored_res3]]
 // CHECK:         return %[[new_tensor_res]]
 
 func.func @detensor_multiple_ops(%arg1: tensor<f32>, %arg2: tensor<f32>) -> tensor<f32> attributes {iree.module.export} {
   %0 = tensor.empty() : tensor<f32>
   %1 = linalg.generic {indexing_maps = [#map, #map, #map], iterator_types = []}
     ins(%arg1, %arg2 : tensor<f32>, tensor<f32>)
     outs(%0 : tensor<f32>) {
-  ^bb0(%arg3: f32, %arg4: f32, %arg5: f32):  
+  ^bb0(%arg3: f32, %arg4: f32, %arg5: f32):
     %2 = arith.addf %arg3, %arg4 : f32
     %3 = arith.mulf %2, %arg4 : f32
     linalg.yield %3 : f32
   } -> tensor<f32>
   return %1: tensor<f32>
 }
 // CHECK-LABEL: func @detensor_multiple_ops
 // CHECK-SAME:    (%[[arg1:.*]]: tensor<f32>, %[[arg2:.*]]: tensor<f32>)
 // CHECK-DAG:     %[[arg1_val:.*]] = tensor.extract %[[arg1]]
 // CHECK-DAG:     %[[arg2_val:.*]] = tensor.extract %[[arg2]]
 // CHECK:         %[[detensored_res:.*]] = arith.addf %[[arg1_val]], %[[arg2_val]]
 // CHECK:         %[[detensored_res2:.*]] = arith.mulf %[[detensored_res]], %[[arg2_val]]
 // CHECK:         %[[new_tensor_res:.*]] = tensor.from_elements %[[detensored_res2]]
 // CHECK:         return %[[new_tensor_res]]
 
 func.func @detensor_foreign_op(%arg1: tensor<f32>, %arg2: tensor<f32>) -> tensor<f32> attributes {iree.module.export} {
   %0 = tensor.empty() : tensor<f32>
   %1 = linalg.generic {indexing_maps = [#map, #map, #map], iterator_types = []}
     ins(%arg1, %arg2 : tensor<f32>, tensor<f32>)
     outs(%0 : tensor<f32>) {
-  ^bb0(%arg3: f32, %arg4: f32, %arg5: f32):  
+  ^bb0(%arg3: f32, %arg4: f32, %arg5: f32):
     %2 = "foreign.do_something"(%arg3, %arg4) {} : (f32, f32) -> f32
     linalg.yield %2 : f32
   } -> tensor<f32>
   return %1: tensor<f32>
 }
 // CHECK-LABEL: func @detensor_foreign_op
 // CHECK-SAME:    (%[[arg1:.*]]: tensor<f32>, %[[arg2:.*]]: tensor<f32>)
 // CHECK-DAG:     %[[arg1_val:.*]] = tensor.extract %[[arg1]]
 // CHECK-DAG:     %[[arg2_val:.*]] = tensor.extract %[[arg2]]
 // CHECK:         %[[detensored_res:.*]] = "foreign.do_something"(%[[arg1_val]], %[[arg2_val]])
 // CHECK:         %[[new_tensor_res:.*]] = tensor.from_elements %[[detensored_res]]
 // CHECK:         return %[[new_tensor_res]]

mlir/test/Dialect/Linalg/detensorize_br_operands.mlir

 // RUN: mlir-opt %s -split-input-file -allow-unregistered-dialect -pass-pipeline="builtin.module(func.func(linalg-detensorize))" | FileCheck %s
 
 // TODO: Detensoring breaks if %arg0 or %arg1 are passed directly as tensors. Fix that.
 func.func @if_true_test(%arg0: i1, %arg1: i32) -> tensor<i32> attributes {} {
   %arg0_t = tensor.from_elements %arg0 : tensor<i1>
   %arg1_t = tensor.from_elements %arg1 : tensor<i32>
 
   %cst = arith.constant dense<10> : tensor<i32>
   %2 = tensor.empty() : tensor<i8>
   %3 = linalg.generic
     {indexing_maps = [affine_map<() -> ()>, affine_map<() -> ()>], iterator_types = []}
     ins(%arg0_t : tensor<i1>)
     outs(%2 : tensor<i8>) {
-  ^bb0(%arg2: i1, %arg3: i8):  
+  ^bb0(%arg2: i1, %arg3: i8):
     %10 = arith.extui %arg2 : i1 to i8
     linalg.yield %10 : i8
   } -> tensor<i8>
   %4 = tensor.extract %3[] : tensor<i8>
   %5 = arith.trunci %4 : i8 to i1
   cf.cond_br %5, ^bb1, ^bb2(%arg1_t : tensor<i32>)
 ^bb1:
   %6 = tensor.empty() : tensor<i32>
   %7 = linalg.generic
     {indexing_maps = [affine_map<() -> ()>, affine_map<() -> ()>, affine_map<() -> ()>], iterator_types = []}
     ins(%arg1_t, %cst : tensor<i32>, tensor<i32>)
     outs(%6 : tensor<i32>) {
-  ^bb0(%arg2: i32, %arg3: i32, %arg4: i32):  
+  ^bb0(%arg2: i32, %arg3: i32, %arg4: i32):
     %10 = arith.addi %arg2, %arg3 : i32
     linalg.yield %10 : i32
   } -> tensor<i32>
   cf.br ^bb2(%7 : tensor<i32>)
 ^bb2(%8: tensor<i32>):
   return %8 : tensor<i32>
 }
 

mlir/test/Dialect/Linalg/detensorize_if.mlir

func.func @main() -> (tensor<i32>) attributes {} {
   %1 = tensor.from_elements %c10 : tensor<i32>
   cf.br ^bb1(%0 : tensor<i32>)
 
 ^bb1(%2: tensor<i32>):  // 2 preds: ^bb0, ^bb2
   %3 = tensor.empty() : tensor<i1>
   %4 = linalg.generic #attrs
     ins(%2, %1 : tensor<i32>, tensor<i32>)
     outs(%3 : tensor<i1>) {
-    ^bb0(%arg0: i32, %arg1: i32, %arg2: i1):  
+    ^bb0(%arg0: i32, %arg1: i32, %arg2: i1):
       %8 = arith.cmpi slt, %arg0, %arg1 : i32
       linalg.yield %8 : i1
   } -> tensor<i1>
   %5 = tensor.extract %4[] : tensor<i1>
   cf.cond_br %5, ^bb2(%2 : tensor<i32>), ^bb3(%2 : tensor<i32>)
 
 ^bb2(%6: tensor<i32>):  // pred: ^bb1
   %7 = tensor.empty() : tensor<i32>
   %8 = linalg.generic #attrs
     ins(%6, %6 : tensor<i32>, tensor<i32>)
     outs(%7 : tensor<i32>) {
-    ^bb0(%arg0: i32, %arg1: i32, %arg2: i32):  
+    ^bb0(%arg0: i32, %arg1: i32, %arg2: i32):
       %9 = arith.addi %arg0, %arg1 : i32
       linalg.yield %9 : i32
   } -> tensor<i32>
   cf.br ^bb3(%8 : tensor<i32>)
 
 ^bb3(%10: tensor<i32>):  // pred: ^bb1
   return %10 : tensor<i32>
 }
func.func @main() -> (tensor<i32>) attributes {} {
   %1 = tensor.from_elements %c10 : tensor<i32>
   cf.br ^bb1(%0 : tensor<i32>)
 
 ^bb1(%2: tensor<i32>):  // 2 preds: ^bb0, ^bb2
   %3 = tensor.empty() : tensor<i1>
   %4 = linalg.generic #attrs
     ins(%2, %1 : tensor<i32>, tensor<i32>)
     outs(%3 : tensor<i1>) {
-    ^bb0(%arg0: i32, %arg1: i32, %arg2: i1):  
+    ^bb0(%arg0: i32, %arg1: i32, %arg2: i1):
       %8 = arith.cmpi slt, %arg0, %arg1 : i32
       linalg.yield %8 : i1
   } -> tensor<i1>
   %5 = tensor.extract %4[] : tensor<i1>
   cf.cond_br %5, ^bb2(%2 : tensor<i32>), ^bb3(%2 : tensor<i32>)
 
 ^bb2(%6: tensor<i32>):  // pred: ^bb1
   %7 = tensor.empty() : tensor<i32>
   %8 = linalg.generic #attrs
     ins(%6, %6 : tensor<i32>, tensor<i32>)
     outs(%7 : tensor<i32>) {
-    ^bb0(%arg0: i32, %arg1: i32, %arg2: i32):  
+    ^bb0(%arg0: i32, %arg1: i32, %arg2: i32):
       %9 = arith.addi %arg0, %arg1 : i32
       linalg.yield %9 : i32
   } -> tensor<i32>
   cf.br ^bb3(%8 : tensor<i32>)
 
 ^bb3(%10: tensor<i32>):  // pred: ^bb1
   cf.br ^bb4(%10 : tensor<i32>)
 
func.func @main() -> (tensor<i32>) attributes {} {
   %1 = tensor.from_elements %c10 : tensor<i32>
   cf.br ^bb1(%0 : tensor<i32>)
 
 ^bb1(%2: tensor<i32>):  // 2 preds: ^bb0, ^bb2
   %3 = tensor.empty() : tensor<i1>
   %4 = linalg.generic #attrs
     ins(%2, %1 : tensor<i32>, tensor<i32>)
     outs(%3 : tensor<i1>) {
-    ^bb0(%arg0: i32, %arg1: i32, %arg2: i1):  
+    ^bb0(%arg0: i32, %arg1: i32, %arg2: i1):
       %8 = arith.cmpi slt, %arg0, %arg1 : i32
       linalg.yield %8 : i1
   } -> tensor<i1>
   %5 = tensor.extract %4[] : tensor<i1>
   // This cf.cond_br intentionally has bb2 as it's target for both branches. This
   // is to make sure that the "forward phase" of the cost-model correctly adds
   // the users of a block argument (in this case bb2's argument) to the work
   // list.
   cf.cond_br %5, ^bb2(%2 : tensor<i32>), ^bb2(%2 : tensor<i32>)
 
 ^bb2(%6: tensor<i32>):  // pred: ^bb1
   %12 = tensor.from_elements %c10 : tensor<i32>
   %7 = tensor.empty() : tensor<i32>
   %8 = linalg.generic #attrs
     ins(%6, %12 : tensor<i32>, tensor<i32>)
     outs(%7 : tensor<i32>) {
-    ^bb0(%arg0: i32, %arg1: i32, %arg2: i32):  
+    ^bb0(%arg0: i32, %arg1: i32, %arg2: i32):
       %9 = arith.addi %arg0, %arg1 : i32
       linalg.yield %9 : i32
   } -> tensor<i32>
   cf.br ^bb3(%8 : tensor<i32>)
 
 ^bb3(%10: tensor<i32>):  // pred: ^bb1
   return %10 : tensor<i32>
 }

mlir/test/Dialect/Linalg/detensorize_while.mlir

 func.func @main(%farg0: tensor<i32>, %farg1: tensor<i32>) -> tensor<i32> attributes {} {
   cf.br ^bb1(%farg0 : tensor<i32>)
 
 ^bb1(%0: tensor<i32>):  // 2 preds: ^bb0, ^bb2
   %1 = tensor.empty() : tensor<i1>
   %2 = linalg.generic #attrs
     ins(%0, %farg1 : tensor<i32>, tensor<i32>)
     outs(%1 : tensor<i1>) {
-    ^bb0(%arg0: i32, %arg1: i32, %arg2: i1):  
+    ^bb0(%arg0: i32, %arg1: i32, %arg2: i1):
       %8 = arith.cmpi slt, %arg0, %arg1 : i32
       linalg.yield %8 : i1
   } -> tensor<i1>
   %3 = tensor.extract %2[] : tensor<i1>
   cf.cond_br %3, ^bb2(%0 : tensor<i32>), ^bb3(%0 : tensor<i32>)
 
 ^bb2(%4: tensor<i32>):  // pred: ^bb1
   %5 = tensor.empty() : tensor<i32>
   %6 = linalg.generic #attrs
     ins(%4, %4 : tensor<i32>, tensor<i32>)
     outs(%5 : tensor<i32>) {
-    ^bb0(%arg0: i32, %arg1: i32, %arg2: i32):  
+    ^bb0(%arg0: i32, %arg1: i32, %arg2: i32):
       %8 = arith.addi %arg0, %arg1 : i32
       linalg.yield %8 : i32
   } -> tensor<i32>
   cf.br ^bb1(%6 : tensor<i32>)
 
 ^bb3(%7: tensor<i32>):  // pred: ^bb1
   return %7 : tensor<i32>
 }

mlir/test/Dialect/Linalg/detensorize_while_impure_cf.mlir

outs(%1: tensor<i32>) {
         %b = arith.addi %x, %a : i32
         linalg.yield %b : i32
   } -> tensor<i32>
 
   %3 = tensor.empty() : tensor<i1>
   %4 = linalg.generic #attrs
     ins(%2, %farg1 : tensor<i32>, tensor<i32>)
     outs(%3 : tensor<i1>) {
-    ^bb0(%arg0: i32, %arg1: i32, %arg2: i1):  
+    ^bb0(%arg0: i32, %arg1: i32, %arg2: i1):
       %8 = arith.cmpi slt, %arg0, %arg1 : i32
       linalg.yield %8 : i1
   } -> tensor<i1>
   %5 = tensor.extract %4[] : tensor<i1>
   cf.cond_br %5, ^bb2(%2 : tensor<i32>), ^bb3(%2 : tensor<i32>)
 
 ^bb2(%6: tensor<i32>):  // pred: ^bb1
   %7 = tensor.empty() : tensor<10xi32>

 // Test aggresively detensoring all detensorable ops.
 //
 // DET-ALL-LABEL: func @main
 // DET-ALL-SAME:    (%{{.*}}: tensor<10xi32>, %{{.*}}: tensor<i32>)
 // DET-ALL:         cf.br ^[[bb1:.*]](%{{.*}} : tensor<10xi32>)
 // DET-ALL:       ^[[bb1]](%{{.*}}: tensor<10xi32>)
 // DET-ALL:         tensor.empty() : tensor<i32>
 // DET-ALL:         linalg.generic {{{.*}}} ins(%{{.*}} : tensor<10xi32>) outs(%{{.*}} : tensor<i32>) {
-// DET-ALL:         ^bb0(%{{.*}}: i32, %{{.*}}: i32):  
+// DET-ALL:         ^bb0(%{{.*}}: i32, %{{.*}}: i32):
 // DET-ALL:           %{{.*}} = arith.addi %{{.*}}, %{{.*}}
 // DET-ALL:           linalg.yield %{{.*}} : i32
 // DET-ALL:         } -> tensor<i32>
 // DET-ALL:         tensor.extract %{{.*}}[] : tensor<i32>
 // DET-ALL:         cmpi slt, %{{.*}}, %{{.*}} : i32
 // DET-ALL:         cf.cond_br %{{.*}}, ^[[bb2:.*]](%{{.*}} : i32), ^[[bb3:.*]](%{{.*}} : i32)
 // DET-ALL:       ^[[bb2]](%{{.*}}: i32)
 // DET-ALL:         tensor.from_elements %{{.*}} : tensor<i32>

mlir/test/Dialect/Linalg/detensorize_while_pure_cf.mlir

func.func @main() -> () attributes {} {
   %reshaped1 = tensor.collapse_shape %1 [] : tensor<1xi32> into tensor<i32>
   cf.br ^bb1(%reshaped0 : tensor<i32>)
 
 ^bb1(%2: tensor<i32>):  // 2 preds: ^bb0, ^bb2
   %3 = tensor.empty() : tensor<i1>
   %4 = linalg.generic #attrs
     ins(%2, %reshaped1 : tensor<i32>, tensor<i32>)
     outs(%3 : tensor<i1>) {
-    ^bb0(%arg0: i32, %arg1: i32, %arg2: i1):  
+    ^bb0(%arg0: i32, %arg1: i32, %arg2: i1):
       %8 = arith.cmpi slt, %arg0, %arg1 : i32
       linalg.yield %8 : i1
   } -> tensor<i1>
   %5 = tensor.extract %4[] : tensor<i1>
   cf.cond_br %5, ^bb2(%2 : tensor<i32>), ^bb3
 
 ^bb2(%6: tensor<i32>):  // pred: ^bb1
   %7 = tensor.empty() : tensor<i32>
   %8 = linalg.generic #attrs
     ins(%6, %6 : tensor<i32>, tensor<i32>)
     outs(%7 : tensor<i32>) {
-    ^bb0(%arg0: i32, %arg1: i32, %arg2: i32):  
+    ^bb0(%arg0: i32, %arg1: i32, %arg2: i32):
       %9 = arith.addi %arg0, %arg1 : i32
       linalg.yield %9 : i32
   } -> tensor<i32>
   cf.br ^bb1(%8 : tensor<i32>)
 
 ^bb3:  // pred: ^bb1
   return
 }

mlir/test/Dialect/Linalg/drop-unit-extent-dims.mlir

linalg.generic #trait
     outs(%arg0 : memref<1x1xf32, 3>) {
        ^bb0(%arg1: f32, %arg2: f32) :
          linalg.yield %arg1 : f32
        }
   return %arg0 : memref<1x1xf32, 3>
 }
 
 // CHECK-LABEL: func @drop_all_loops
-//       CHECK:   memref.collapse_shape 
+//       CHECK:   memref.collapse_shape
 //  CHECK-SAME:     [] : memref<1x1xf32, 3> into memref<f32, 3>
 //       CHECK:   linalg.generic{{.*}}memref<f32, 3>

mlir/test/Dialect/Linalg/erase-unused-operands-and-results.mlir

%0:4 = linalg.generic {
       iterator_types = ["parallel", "parallel", "parallel"]}
       ins(%arg0 : tensor<?x?x?xf32>)
       outs(%arg0, %arg0, %arg0, %arg0
           : tensor<?x?x?xf32>, tensor<?x?x?xf32>, tensor<?x?x?xf32>, tensor<?x?x?xf32>) {
     ^bb0(%b0 : f32, %b1 : f32, %b2 : f32, %b3 : f32, %b4 : f32) :
       %1 = arith.addf %b0, %b0: f32
       linalg.yield %1, %1, %1, %1 : f32, f32, f32, f32
     } -> (tensor<?x?x?xf32>, tensor<?x?x?xf32>, tensor<?x?x?xf32>, tensor<?x?x?xf32>)
-  return %0#0, %0#2 : tensor<?x?x?xf32>, tensor<?x?x?xf32>     
+  return %0#0, %0#2 : tensor<?x?x?xf32>, tensor<?x?x?xf32>
 }
 //  CHECK-DAG: #[[MAP0:.+]] = affine_map<(d0, d1, d2) -> (d0, d1, d2)>
 //  CHECK-DAG: #[[MAP1:.+]] = affine_map<(d0, d1, d2) -> (d0, d2, d1)>
 //  CHECK-DAG: #[[MAP2:.+]] = affine_map<(d0, d1, d2) -> (d1, d0, d2)>
 //      CHECK: func @drop_dead_results(
 // CHECK-SAME:     %[[ARG0:.+]]: tensor<?x?x?xf32>)
 //      CHECK:   %[[GENERIC:.+]]:2 = linalg.generic
 // CHECK-SAME:       indexing_maps = [#[[MAP0]], #[[MAP1]], #[[MAP2]]]
%0:4 = linalg.generic {
       indexing_maps = [#map0, #map1, #map2, #map3, #map4],
       iterator_types = ["parallel", "parallel", "parallel"]}
       ins(%arg0 : tensor<?x?x?xf32>)
       outs(%arg0, %arg0, %init0, %init0
           : tensor<?x?x?xf32>, tensor<?x?x?xf32>, tensor<?x?x?xf32>, tensor<?x?x?xf32>) {
     ^bb0(%b0 : f32, %b1 : f32, %b2 : f32, %b3 : f32, %b4 : f32) :
       linalg.yield %b0, %b0, %b3, %b4 : f32, f32, f32, f32
     } -> (tensor<?x?x?xf32>, tensor<?x?x?xf32>, tensor<?x?x?xf32>, tensor<?x?x?xf32>)
-  return %0#0, %0#1 : tensor<?x?x?xf32>, tensor<?x?x?xf32>     
+  return %0#0, %0#1 : tensor<?x?x?xf32>, tensor<?x?x?xf32>
 }
 
 //  CHECK-DAG: #[[MAP0:.+]] = affine_map<(d0, d1, d2) -> (d0, d1, d2)>
 //  CHECK-DAG: #[[MAP1:.+]] = affine_map<(d0, d1, d2) -> (d0, d2, d1)>
 //  CHECK-DAG: #[[MAP2:.+]] = affine_map<(d0, d1, d2) -> (d1, d2, d0)>
 //      CHECK: func @drop_dead_results_with_different_tensors(
 // CHECK-SAME:     %[[ARG0:.+]]: tensor<?x?x?xf32>)
 //      CHECK:   %[[GENERIC:.+]]:2 = linalg.generic
%0:4 = linalg.generic {
       outs(%arg0, %arg0, %init0, %init0
           : tensor<?x?x?xf32>, tensor<?x?x?xf32>, tensor<?x?x?xf32>, tensor<?x?x?xf32>) {
     ^bb0(%b0 : f32, %b1 : f32, %b2 : f32, %b3 : f32, %b4 : f32) :
       %1 = arith.addf %b0, %b0: f32
       %2 = arith.addf %b0, %b3: f32
       %3 = arith.addf %b0, %b4: f32
       linalg.yield %1, %1, %2, %3 : f32, f32, f32, f32
     } -> (tensor<?x?x?xf32>, tensor<?x?x?xf32>, tensor<?x?x?xf32>, tensor<?x?x?xf32>)
-  return %0#0, %0#1 : tensor<?x?x?xf32>, tensor<?x?x?xf32>     
+  return %0#0, %0#1 : tensor<?x?x?xf32>, tensor<?x?x?xf32>
 }
 
 //  CHECK-DAG: #[[MAP0:.+]] = affine_map<(d0, d1, d2) -> (d0, d1, d2)>
 //  CHECK-DAG: #[[MAP1:.+]] = affine_map<(d0, d1, d2) -> (d0, d2, d1)>
 //  CHECK-DAG: #[[MAP2:.+]] = affine_map<(d0, d1, d2) -> (d1, d2, d0)>
 //      CHECK: func @drop_dead_results_with_unused_cycles(
 // CHECK-SAME:     %[[ARG0:.+]]: tensor<?x?x?xf32>)
 //      CHECK:   %[[GENERIC:.+]]:2 = linalg.generic

mlir/test/Dialect/Linalg/fold-unit-trip-loops.mlir

#trait = {
   iterator_types = ["parallel", "parallel"],
   library_call = "some_external_fn"
 }
 
 func.func @leading_dim_1_canonicalization(%arg0: tensor<1x5xf32>, %shape: tensor<5xf32>) -> tensor<5xf32> {
   %0 = linalg.generic #trait
        ins(%arg0 : tensor<1x5xf32>)
       outs(%shape : tensor<5xf32>) {
-    ^bb0(%arg2: f32, %arg3: f32):     
+    ^bb0(%arg2: f32, %arg3: f32):
       linalg.yield %arg2 : f32
   } -> tensor<5xf32>
   return %0 : tensor<5xf32>
 }
 //   CHECK-DAG: #[[$MAP0:.*]] = affine_map<(d0) -> (0, d0)>
 //   CHECK-DAG: #[[$MAP1:.*]] = affine_map<(d0) -> (d0)>
 // CHECK-LABEL: func @leading_dim_1_canonicalization
 //       CHECK:   linalg.generic
 //  CHECK-SAME:     indexing_maps = [#[[$MAP0]], #[[$MAP1]]]
 //  CHECK-SAME:     iterator_types = ["parallel"]

mlir/test/Dialect/Linalg/fuse-with-reshape-by-collapsing.mlir

 // RUN: mlir-opt %s -test-linalg-elementwise-fusion-patterns=fuse-with-reshape-by-collapsing -split-input-file | FileCheck %s
 // RUN: mlir-opt %s -test-linalg-elementwise-fusion-patterns=fuse-with-reshape-by-collapsing-control -split-input-file | FileCheck %s --check-prefix=CONTROL
 
-// Static problem sizes. Checks all aspects of fusion by collapsing. Rest of the 
+// Static problem sizes. Checks all aspects of fusion by collapsing. Rest of the
 // tests only check a subset of conditions.
 #map0 = affine_map<(d0, d1, d2, d3, d4, d5, d6, d7) -> (d0, d1, d2, d3, d4, d5, d6, d7)>
 #map1 = affine_map<(d0, d1, d2, d3, d4, d5, d6, d7) -> (d0, d1, d2)>
 #map2 = affine_map<(d0, d1, d2, d3, d4, d5, d6, d7) -> (d3, d4, d5, d6)>
 #map3 = affine_map<(d0, d1, d2, d3, d4, d5, d6, d7) -> (d0, d1, d2, d3, d4, d5, d6, d7)>
 func.func @fuse_by_collapsing(%arg0 : tensor<2x12x5x336x9xi32>,
     %arg1 : tensor<2x3x4xi32>, %arg2 : tensor<5x6x7x8xi32>) -> tensor<2x3x4x5x6x7x8x9xi32> {
   %expand = tensor.expand_shape %arg0 [[0], [1, 2], [3], [4, 5, 6], [7]]

mlir/test/Dialect/Linalg/fusion-elementwise-ops.mlir

 // RUN: mlir-opt %s -linalg-fuse-elementwise-ops -split-input-file | FileCheck %s
 
 // CHECK-DAG: [[$MAP0:#[a-zA-Z0-9_]*]] = affine_map<(d0, d1) -> (d0, d1)>
 #map0 = affine_map<(d0, d1) -> (d0, d1)>
 
 // CHECK-LABEL: @add_mul_fusion
 func.func @add_mul_fusion(%arg0: tensor<?x?xf32>, %arg1 : tensor<?x?xf32>, %arg2 : tensor<?x?xf32>) -> tensor<?x?xf32>
 {
   %c0 = arith.constant 0 : index
   %c1 = arith.constant 1 : index
   %0 = tensor.dim %arg0, %c0 : tensor<?x?xf32>
   %1 = tensor.dim %arg0, %c1 : tensor<?x?xf32>
   %2 = tensor.empty(%0, %1) : tensor<?x?xf32>
   %3 = linalg.generic {indexing_maps = [#map0, #map0, #map0], iterator_types = ["parallel", "parallel"]}
       ins(%arg0, %arg1 : tensor<?x?xf32>, tensor<?x?xf32>)
       outs(%2 : tensor<?x?xf32>) {
-    ^bb0(%arg3: f32, %arg4: f32, %arg5: f32):       
+    ^bb0(%arg3: f32, %arg4: f32, %arg5: f32):
       %4 = arith.addf %arg3, %arg4 : f32
       linalg.yield %4 : f32
   } -> tensor<?x?xf32>
   // CHECK: linalg.generic {
   // CHECK-SAME: indexing_maps = {{\[}}[[$MAP0]], [[$MAP0]], [[$MAP0]], [[$MAP0]]{{\]}}
   %4 = linalg.generic {indexing_maps = [#map0, #map0, #map0], iterator_types = ["parallel", "parallel"]}
       ins(%3, %arg2 : tensor<?x?xf32>, tensor<?x?xf32>)
       outs(%2 : tensor<?x?xf32>) {
     // CHECK: ^{{[a-zA-Z0-9_]*}}
     // CHECK-SAME: [[ARG0:%[a-zA-Z0-9_]*]]
     // CHECK-SAME: [[ARG1:%[a-zA-Z0-9_]*]]
     // CHECK-SAME: [[ARG2:%[a-zA-Z0-9_]*]]
-    ^bb0(%arg5: f32, %arg6: f32, %arg7: f32):       
+    ^bb0(%arg5: f32, %arg6: f32, %arg7: f32):
       // CHECK: [[T1:%[a-zA-Z0-9_]*]] = arith.addf [[ARG0]], [[ARG1]]
       // CHECK-NOT: linalg.yield
       // CHECK: arith.mulf [[T1]], [[ARG2]]
       // CHECK: linalg.yield
       %5 = arith.mulf %arg5, %arg6 : f32
       linalg.yield %5 : f32
     } -> tensor<?x?xf32>
   return %4 : tensor<?x?xf32>
func.func @scalar_add_mul_fusion(%arg0: tensor<?x?xf32>, %arg1 : f32, %arg2 : f32) -> tensor<?x?xf32>
   %c0 = arith.constant 0 : index
   %c1 = arith.constant 1 : index
   %0 = tensor.dim %arg0, %c0 : tensor<?x?xf32>
   %1 = tensor.dim %arg0, %c1 : tensor<?x?xf32>
   %2 = tensor.empty(%0, %1) : tensor<?x?xf32>
   %3 = linalg.generic {indexing_maps = [#map0, #map1, #map0], iterator_types = ["parallel", "parallel"]}
       ins(%arg0, %arg1 : tensor<?x?xf32>, f32)
       outs(%2 : tensor<?x?xf32>) {
-    ^bb0(%arg3: f32, %arg4: f32, %arg5: f32):       
+    ^bb0(%arg3: f32, %arg4: f32, %arg5: f32):
       %4 = arith.addf %arg3, %arg4 : f32
       linalg.yield %4 : f32
   } -> tensor<?x?xf32>
   // CHECK: linalg.generic {
   // CHECK-SAME: indexing_maps = {{\[}}[[$MAP0]], [[$MAP1]], [[$MAP1]], [[$MAP0]]{{\]}}
   %4 = linalg.generic {indexing_maps = [#map0, #map1, #map0], iterator_types = ["parallel", "parallel"]}
       ins(%3, %arg2 : tensor<?x?xf32>, f32)
       outs(%2 : tensor<?x?xf32>) {
     // CHECK: ^{{[a-zA-Z0-9_]*}}
     // CHECK-SAME: [[ARG3:%[a-zA-Z0-9_]*]]
     // CHECK-SAME: [[ARG4:%[a-zA-Z0-9_]*]]
     // CHECK-SAME: [[ARG5:%[a-zA-Z0-9_]*]]
-    ^bb0(%arg5: f32, %arg6: f32, %arg7: f32):       
+    ^bb0(%arg5: f32, %arg6: f32, %arg7: f32):
       // CHECK: [[T1:%[a-zA-Z0-9_]*]] = arith.addf [[ARG3]], [[ARG4]]
       // CHECK-NOT: linalg.yield
       // CHECK: arith.mulf [[T1]], [[ARG5]]
       // CHECK: linalg.yield
       %5 = arith.mulf %arg5, %arg6 : f32
       linalg.yield %5 : f32
     } -> tensor<?x?xf32>
   return %4 : tensor<?x?xf32>
func.func @transpose_add_mul_fusion(%arg0: tensor<?x?xf32>, %arg1 : tensor<?x?xf32>, %arg2 : tensor<?x?xf32>) -> tensor<?x?xf32>
   %c0 = arith.constant 0 : index
   %c1 = arith.constant 1 : index
   %0 = tensor.dim %arg0, %c0 : tensor<?x?xf32>
   %1 = tensor.dim %arg0, %c1 : tensor<?x?xf32>
   %2 = tensor.empty(%0, %1) : tensor<?x?xf32>
   %3 = linalg.generic {indexing_maps = [#map0, #map1, #map0], iterator_types = ["parallel", "parallel"]}
       ins(%arg0, %arg1 : tensor<?x?xf32>, tensor<?x?xf32>)
       outs(%2 : tensor<?x?xf32>) {
-    ^bb0(%arg3: f32, %arg4: f32, %arg5: f32):       
+    ^bb0(%arg3: f32, %arg4: f32, %arg5: f32):
       %4 = arith.addf %arg3, %arg4 : f32
       linalg.yield %4 : f32
   } -> tensor<?x?xf32>
   // CHECK: linalg.generic {
   // CHECK-SAME: indexing_maps = {{\[}}[[$MAP0]], [[$MAP1]], [[$MAP0]], [[$MAP0]]{{\]}}
   %4 = linalg.generic {indexing_maps = [#map0, #map0, #map0], iterator_types = ["parallel", "parallel"]}
       ins(%3, %arg2 : tensor<?x?xf32>, tensor<?x?xf32>)
       outs(%2 : tensor<?x?xf32>) {
-    ^bb0(%arg5: f32, %arg6: f32, %arg7: f32):       
+    ^bb0(%arg5: f32, %arg6: f32, %arg7: f32):
       %5 = arith.mulf %arg5, %arg6 : f32
       linalg.yield %5 : f32
     } -> tensor<?x?xf32>
   return %4 : tensor<?x?xf32>
 }
 
 // -----
 
 // CHECK-DAG: [[$MAP0:#[a-zA-Z0-9_]*]] = affine_map<(d0, d1) -> (d0, d1)>
 // CHECK-DAG: [[$MAP1:#[a-zA-Z0-9_]*]] = affine_map<(d0, d1) -> (d1, d0)>
 #map0 = affine_map<(d0, d1) -> (d0, d1)>
 #map1 = affine_map<(d0, d1) -> (d1, d0)>
 
 // CHECK-LABEL: @add_transpose_mul_fusion
 func.func @add_transpose_mul_fusion(%arg0: tensor<?x?xf32>, %arg1 : tensor<?x?xf32>, %arg2 : tensor<?x?xf32>) -> tensor<?x?xf32>
 {
   %c0 = arith.constant 0 : index
   %c1 = arith.constant 1 : index
   %0 = tensor.dim %arg0, %c0 : tensor<?x?xf32>
   %1 = tensor.dim %arg0, %c1 : tensor<?x?xf32>
   %2 = tensor.empty(%0, %1) : tensor<?x?xf32>
   %3 = linalg.generic {indexing_maps = [#map0, #map1, #map0], iterator_types = ["parallel", "parallel"]}
       ins(%arg0, %arg1 : tensor<?x?xf32>, tensor<?x?xf32>)
       outs(%2 : tensor<?x?xf32>) {
-    ^bb0(%arg3: f32, %arg4: f32, %arg5: f32):       
+    ^bb0(%arg3: f32, %arg4: f32, %arg5: f32):
       %4 = arith.addf %arg3, %arg4 : f32
       linalg.yield %4 : f32
   } -> tensor<?x?xf32>
   // CHECK: linalg.generic {
   // CHECK-SAME: indexing_maps = {{\[}}[[$MAP1]], [[$MAP0]], [[$MAP0]], [[$MAP0]]{{\]}}
   %4 = linalg.generic {indexing_maps = [#map1, #map0, #map0], iterator_types = ["parallel", "parallel"]}
       ins(%3, %arg2 : tensor<?x?xf32>, tensor<?x?xf32>)
       outs(%2 : tensor<?x?xf32>){
-    ^bb0(%arg5: f32, %arg6: f32, %arg7: f32):       
+    ^bb0(%arg5: f32, %arg6: f32, %arg7: f32):
       %5 = arith.mulf %arg5, %arg6 : f32
       linalg.yield %5 : f32
     } -> tensor<?x?xf32>
   return %4 : tensor<?x?xf32>
 }
 
 // -----
 
 // CHECK-DAG: [[$MAP0:#[a-zA-Z0-9_]*]] = affine_map<(d0, d1) -> (d0, d1)>
 // CHECK-DAG: [[$MAP1:#[a-zA-Z0-9_]*]] = affine_map<(d0, d1) -> (d0)>
 #map0 = affine_map<(d0, d1) -> (d0, d1)>
 #map1 = affine_map<(d0, d1) -> (d0)>
 #map2 = affine_map<(d0) -> (d0)>
 
 // CHECK-LABEL: @add_broadcast_mul_fusion
 func.func @add_broadcast_mul_fusion(%arg0: tensor<?xf32>, %arg1 : tensor<?xf32>, %arg2 : tensor<?x?xf32>) -> tensor<?x?xf32>
 {
   %c0 = arith.constant 0 : index
   %c1 = arith.constant 1 : index
   %0 = tensor.dim %arg0, %c0 : tensor<?xf32>
   %1 = tensor.empty(%0) : tensor<?xf32>
   %2 = linalg.generic {indexing_maps = [#map2, #map2, #map2], iterator_types = ["parallel"]}
       ins(%arg0, %arg1 : tensor<?xf32>, tensor<?xf32>)
       outs(%1 : tensor<?xf32>) {
-    ^bb0(%arg3: f32, %arg4: f32, %arg5: f32):       
+    ^bb0(%arg3: f32, %arg4: f32, %arg5: f32):
       %3 = arith.addf %arg3, %arg4 : f32
       linalg.yield %3 : f32
   } -> tensor<?xf32>
   // CHECK: linalg.generic {
   // CHECK-SAME: indexing_maps = {{\[}}[[$MAP1]], [[$MAP1]], [[$MAP0]], [[$MAP0]]
   %3 = tensor.dim %arg2, %c1 : tensor<?x?xf32>
   %4 = tensor.empty(%0, %3) : tensor<?x?xf32>
   %5 = linalg.generic {indexing_maps = [#map1, #map0, #map0], iterator_types = ["parallel", "parallel"]}
       ins(%2, %arg2 : tensor<?xf32>, tensor<?x?xf32>)
       outs(%4 : tensor<?x?xf32>){
-    ^bb0(%arg5: f32, %arg6: f32, %arg7: f32):       
+    ^bb0(%arg5: f32, %arg6: f32, %arg7: f32):
       %6 = arith.mulf %arg5, %arg6 : f32
       linalg.yield %6 : f32
     } -> tensor<?x?xf32>
   return %5 : tensor<?x?xf32>
 }
 
 // -----
 
 // CHECK: #[[$MAP0:.*]] = affine_map<() -> ()>
 #map0 = affine_map<() -> ()>
 
 // CHECK-LABEL: @add_mul_scalar_fusion
 func.func @add_mul_scalar_fusion(%arg0: tensor<f32>, %arg1: tensor<f32>, %arg2: tensor<f32>) -> tensor<f32>
 {
   %0 = tensor.empty() : tensor<f32>
   %1 = linalg.generic {indexing_maps = [#map0, #map0, #map0], iterator_types = []}
       ins(%arg0, %arg1 : tensor<f32>, tensor<f32>)
       outs(%0 : tensor<f32>) {
-    ^bb0(%arg3: f32, %arg4: f32, %arg5: f32):       
+    ^bb0(%arg3: f32, %arg4: f32, %arg5: f32):
       %2 = arith.addf %arg3, %arg4 : f32
       linalg.yield %2 : f32
   } -> tensor<f32>
   // CHECK: linalg.generic {
   // CHECK: arith.addf
   // CHECK: arith.mulf
   %2 = linalg.generic {indexing_maps = [#map0, #map0, #map0], iterator_types = []}
       ins(%1, %arg2 : tensor<f32>, tensor<f32>)
       outs(%0 : tensor<f32>) {
-    ^bb0(%arg3: f32, %arg4: f32, %arg5: f32):       
+    ^bb0(%arg3: f32, %arg4: f32, %arg5: f32):
       %3 = arith.mulf %arg3, %arg4 : f32
       linalg.yield %3 : f32
   } -> tensor<f32>
 
   return %2 : tensor<f32>
 }
 
 // -----
func.func @producer_indexed_consumer_fusion(%arg0: tensor<?x?xi32>,
   %0 = tensor.dim %arg0, %c0 : tensor<?x?xi32>
   %1 = tensor.dim %arg0, %c1 : tensor<?x?xi32>
   %2 = tensor.empty(%0, %1) : tensor<?x?xi32>
   %3 = linalg.generic {
     indexing_maps = [#map0, #map0, #map0],
     iterator_types = ["parallel", "parallel"] }
     ins(%arg0, %arg1  : tensor<?x?xi32>, tensor<?x?xi32>)
     outs(%2 : tensor<?x?xi32>) {
-    ^bb0(%arg2: i32, %arg3: i32, %arg4: i32):       
+    ^bb0(%arg2: i32, %arg3: i32, %arg4: i32):
       %10 = arith.addi %arg2, %arg3 : i32
       linalg.yield %10 : i32
     } -> tensor<?x?xi32>
   %4 = linalg.generic {
     indexing_maps = [#map0, #map0],
     iterator_types = ["parallel", "parallel"] }
     ins(%3 : tensor<?x?xi32>)
     outs(%2 : tensor<?x?xi32>) {
-    ^bb0(%arg2: i32, %arg3: i32):       
+    ^bb0(%arg2: i32, %arg3: i32):
       %idx0 = linalg.index 0 : index
       %idx1 = linalg.index 1 : index
       %5 = arith.index_cast %idx0 : index to i32
       %6 = arith.index_cast %idx1 : index to i32
       %7 = arith.addi %arg2, %5 : i32
       %8 = arith.subi %7, %6 : i32
       linalg.yield %8 : i32
     } -> tensor<?x?xi32>
func.func @indexed_producer_consumer_fusion(%arg0: tensor<?x?xi32>) -> tensor<?x?xi32> {
   %0 = tensor.dim %arg0, %c0 : tensor<?x?xi32>
   %1 = tensor.dim %arg0, %c1 : tensor<?x?xi32>
   %2 = tensor.empty(%0, %1) : tensor<?x?xi32>
   %3 = linalg.generic {
     indexing_maps = [#map0, #map0],
     iterator_types = ["parallel", "parallel"] }
     ins(%arg0 : tensor<?x?xi32>)
     outs(%2 : tensor<?x?xi32>) {
-    ^bb0(%arg4: i32, %arg5: i32):       
+    ^bb0(%arg4: i32, %arg5: i32):
       %idx0 = linalg.index 0 : index
       %idx1 = linalg.index 1 : index
       %4 = arith.index_cast %idx0 : index to i32
       %5 = arith.index_cast %idx1 : index to i32
       %6 = arith.addi %arg4, %4 : i32
       %7 = arith.subi %6, %5 : i32
       linalg.yield %7 : i32
     } -> tensor<?x?xi32>
   %4 = linalg.generic {
     indexing_maps = [#map0, #map0, #map0],
     iterator_types = ["parallel", "parallel"] }
     ins(%3, %arg0 : tensor<?x?xi32>, tensor<?x?xi32>)
     outs(%2 : tensor<?x?xi32>) {
-    ^bb0(%arg2: i32, %arg3: i32, %arg4: i32):       
+    ^bb0(%arg2: i32, %arg3: i32, %arg4: i32):
       %10 = arith.addi %arg2, %arg3 : i32
       linalg.yield %10 : i32
     } -> tensor<?x?xi32>
   return %4 : tensor<?x?xi32>
 }
 //   CHECK-DAG: #[[$MAP0:.*]] = affine_map<(d0, d1) -> (d0, d1)>
 // CHECK-LABEL: func @indexed_producer_consumer_fusion
 //       CHECK: linalg.generic
func.func @indexed_producer_indexed_consumer_fusion(%arg0: tensor<?x?xi32>)
   %0 = tensor.dim %arg0, %c0 : tensor<?x?xi32>
   %1 = tensor.dim %arg0, %c1 : tensor<?x?xi32>
   %2 = tensor.empty(%0, %1) : tensor<?x?xi32>
   %3 = linalg.generic {
     indexing_maps = [#map0, #map0],
     iterator_types = ["parallel", "parallel"] }
     ins(%arg0 : tensor<?x?xi32>)
     outs(%2 : tensor<?x?xi32>) {
-    ^bb0(%arg2: i32, %arg3: i32):       
+    ^bb0(%arg2: i32, %arg3: i32):
       %idx0 = linalg.index 0 : index
       %idx1 = linalg.index 1 : index
       %4 = arith.index_cast %idx0 : index to i32
       %5 = arith.index_cast %idx1 : index to i32
       %6 = arith.addi %arg2, %4 : i32
       %7 = arith.subi %5, %6 : i32
       linalg.yield %7 : i32
     } -> tensor<?x?xi32>
   %4= linalg.generic {
     indexing_maps = [#map1, #map1],
     iterator_types = ["parallel", "parallel"] }
     ins(%3 : tensor<?x?xi32>)
     outs(%2 : tensor<?x?xi32>) {
-    ^bb0(%arg2: i32, %arg3: i32):       
+    ^bb0(%arg2: i32, %arg3: i32):
       %idx0 = linalg.index 0 : index
       %idx1 = linalg.index 1 : index
       %5 = arith.index_cast %idx0 : index to i32
       %6 = arith.index_cast %idx1 : index to i32
       %7 = arith.addi %arg2, %5 : i32
       %8 = arith.subi %7, %6 : i32
       linalg.yield %8 : i32
     } -> tensor<?x?xi32>

 {
   %c0 = arith.constant 0 : index
   %cst = arith.constant dense<1.000000e+00> : tensor<10xf32>
   %0 = tensor.empty() : tensor<f32>
   %1 = linalg.generic
     {indexing_maps = [affine_map<() -> ()>, affine_map<() -> ()>],
      iterator_types = []}
     ins(%arg1 : tensor<i32>) outs(%0 : tensor<f32>) {
-    ^bb0(%arg2: i32, %arg3: f32):  
+    ^bb0(%arg2: i32, %arg3: f32):
       %3 = arith.index_cast %arg2 : i32 to index
       %4 = tensor.extract %arg0[%3, %c0, %c0] : tensor<5x1x1xf32>
       linalg.yield %4 : f32
     } -> tensor<f32>
   %2 = tensor.empty() : tensor<10xf32>
   %3 = linalg.generic
    {indexing_maps = [affine_map<(d0) -> ()>, affine_map<(d0) -> (d0)>,
                      affine_map<(d0) -> (d0)>],
     iterator_types = ["parallel"]}
     ins(%1, %cst : tensor<f32>, tensor<10xf32>) outs(%2 : tensor<10xf32>) {
-    ^bb0(%arg2: f32, %arg3: f32, %arg4: f32):  
+    ^bb0(%arg2: f32, %arg3: f32, %arg4: f32):
       %4 = arith.mulf %arg2, %arg3 : f32
       linalg.yield %4 : f32
     } -> tensor<10xf32>
   return %3 : tensor<10xf32>
 }
 //   CHECK-DAG: #[[MAP0:.+]] = affine_map<(d0) -> ()>
 //   CHECK-DAG: #[[MAP1:.+]] = affine_map<(d0) -> (d0)>
 //       CHECK: func @scalar_generic_fusion
func.func @consumer_with_reduction(%arg0: tensor<1x10xf32>,
                               %arg1: tensor<1x10xf32>,
                               %arg2: tensor<1xf32>) -> tensor<1xf32> {
   %init = tensor.empty() : tensor<1x10xf32>
   %0 = linalg.generic
     {indexing_maps = [#map0, #map0, #map0],
      iterator_types = ["parallel", "parallel"]}
     ins(%arg0, %arg1 : tensor<1x10xf32>, tensor<1x10xf32>)
     outs(%init : tensor<1x10xf32>) {
-  ^bb0(%arg3: f32, %arg4: f32, %arg5: f32):  
+  ^bb0(%arg3: f32, %arg4: f32, %arg5: f32):
     %2 = arith.addf %arg3, %arg4 : f32
     linalg.yield %2 : f32
   } -> tensor<1x10xf32>
   %1 = linalg.generic
     {indexing_maps = [#map1, #map2],
      iterator_types = ["reduction"]}
     ins(%0 : tensor<1x10xf32>)
     outs(%arg2 : tensor<1xf32>)  {
-  ^bb0(%arg3: f32, %arg4: f32):  
+  ^bb0(%arg3: f32, %arg4: f32):
     %2 = arith.addf %arg3, %arg4 : f32
     linalg.yield %2 : f32
   } -> tensor<1xf32>
   return %1 : tensor<1xf32>
 }
 //  CHECK-DAG: #[[MAP0:.+]] = affine_map<(d0) -> (0, d0)>
 //  CHECK-DAG: #[[MAP1:.+]] = affine_map<(d0) -> (0)>
 //      CHECK: func @consumer_with_reduction(%[[ARG0:.+]]: tensor<1x10xf32>, %[[ARG1:.+]]: tensor<1x10xf32>, %[[ARG2:.+]]: tensor<1xf32>)
func.func @sigmoid_dynamic_dim(%0: tensor<?x1xf32>) -> tensor<?x1xf32> {
   %extend = shape.to_extent_tensor %shape : tensor<?xindex> -> tensor<2xindex>
   %extracted = tensor.extract %extend[%c0] : tensor<2xindex>
   %init0 = tensor.empty(%extracted) : tensor<?x1xf32>
   %1 = linalg.generic {indexing_maps = [
     affine_map<(d0, d1) -> (d0, d1)>],
     iterator_types = ["parallel", "parallel"]
   }
      outs(%init0 : tensor<?x1xf32>) {
-    ^bb0(%a: f32):  
+    ^bb0(%a: f32):
       linalg.yield %cp5 : f32
   } -> tensor<?x1xf32>
   %d0 = tensor.dim %0, %c0 : tensor<?x1xf32>
   %init1 = tensor.empty(%d0) : tensor<?x1xf32>
   %2 = linalg.generic {indexing_maps = [
     affine_map<(d0, d1) -> (d0, d1)>,
     affine_map<(d0, d1) -> (d0, d1)>,
     affine_map<(d0, d1) -> (d0, d1)>],
     iterator_types = ["parallel", "parallel"]
   }
       ins(%0, %1 : tensor<?x1xf32>, tensor<?x1xf32>)
      outs(%init1 : tensor<?x1xf32>) {
-  ^bb0(%a: f32, %b: f32, %c: f32):  
+  ^bb0(%a: f32, %b: f32, %c: f32):
       %m = arith.mulf %a, %b : f32
       linalg.yield %m : f32
   } -> tensor<?x1xf32>
   return %2 : tensor<?x1xf32>
 }
 
 // -----
 

 // CHECK: linalg.generic
 func.func @no_fusion_missing_reduction_shape(%arg0: tensor<f32>, %arg1: index) -> tensor<?xf32> {
   %cst = arith.constant 0xFF800000 : f32
   %4 = tensor.empty(%arg1, %arg1) : tensor<?x?xf32>
   %5 = linalg.generic {
     indexing_maps = [#map0, #map1],
     iterator_types = ["parallel", "parallel"]
   } ins(%arg0 : tensor<f32>) outs(%4 : tensor<?x?xf32>) {
-  ^bb0(%arg2: f32, %arg3: f32):  
+  ^bb0(%arg2: f32, %arg3: f32):
     linalg.yield %arg2 : f32
   } -> tensor<?x?xf32>
   %6 = tensor.empty(%arg1) : tensor<?xf32>
   %7 = linalg.fill ins(%cst : f32) outs(%6 : tensor<?xf32>) -> tensor<?xf32>
   %8 = linalg.generic {
     indexing_maps = [#map2, #map3],
     iterator_types = ["parallel", "reduction"]
   } ins(%5 : tensor<?x?xf32>) outs(%7 : tensor<?xf32>) {
-  ^bb0(%arg2: f32, %arg3: f32):  
+  ^bb0(%arg2: f32, %arg3: f32):
     %9 = arith.maxf %arg2, %arg3 : f32
     linalg.yield %9 : f32
   } -> tensor<?xf32>
   return %8 : tensor<?xf32>
 }
 
 // -----
 

 //  CHECK-DAG:     %[[CAST2:.+]] = arith.index_cast %[[CAST1]] : i64 to index
 //      CHECK:     %[[EXTRACT:.+]] = tensor.extract %[[ARG1]][%[[CAST2]]]
 //      CHECK:     linalg.yield %[[CAST1]], %[[EXTRACT]]
 //      CHECK:   return %[[RESULT]]#1
 
 // -----
 
 // CHECK-LABEL: func @fold_fill_generic_basic
-//  CHECK-SAME: (%[[ARG0:.*]]: tensor<?xf32>) -> tensor<?xf32> { 
+//  CHECK-SAME: (%[[ARG0:.*]]: tensor<?xf32>) -> tensor<?xf32> {
 //   CHECK-NOT: linalg.fill
 //       CHECK: %[[GENERIC_OP:.*]] = linalg.generic
 //  CHECK-SAME: ins(%[[ARG0]] : tensor<?xf32>)
 //  CHECK-SAME: outs({{.*}} : tensor<?xf32>) {
 #map0 = affine_map<(d0) -> (d0)>
 func.func @fold_fill_generic_basic(%arg0: tensor<?xf32>) -> (tensor<?xf32>) {
   %c0 = arith.constant 0 : index
   %cst = arith.constant 7.0 : f32
   %0 = tensor.dim %arg0, %c0 : tensor<?xf32>
   %1 = tensor.empty(%0) : tensor<?xf32>
   %2 = linalg.fill ins(%cst : f32) outs(%1 : tensor<?xf32>) -> tensor<?xf32>
   %3 = tensor.empty(%0) : tensor<?xf32>
   %4 = linalg.generic {indexing_maps = [#map0, #map0, #map0], iterator_types=["parallel"]} ins(%arg0, %2 : tensor<?xf32>, tensor<?xf32>) outs (%3:tensor<?xf32>) {
   ^bb0(%arg1: f32, %arg2: f32, %arg3: f32):
     %5 = arith.addf  %arg1, %arg2 : f32
         linalg.yield %5 : f32
   } -> tensor<?xf32>
   return %4 : tensor<?xf32>
 }
 
 // -----
 
 // CHECK-LABEL: func @fold_fill_generic_different_dtype
-//  CHECK-SAME: (%[[ARG0:.*]]: tensor<?xf16>) -> tensor<?xf16> { 
+//  CHECK-SAME: (%[[ARG0:.*]]: tensor<?xf16>) -> tensor<?xf16> {
 //   CHECK-NOT: linalg.fill
 //       CHECK: %[[GENERIC_OP:.*]] = linalg.generic
 //  CHECK-SAME: ins(%[[ARG0]] : tensor<?xf16>)
 //  CHECK-SAME: outs({{.*}} : tensor<?xf16>) {
 #map0 = affine_map<(d0) -> (d0)>
 func.func @fold_fill_generic_different_dtype(%arg0: tensor<?xf16>) -> (tensor<?xf16>) {
   %c0 = arith.constant 0 : index
   %cst = arith.constant 7.0 : f32

mlir/test/Dialect/Linalg/fusion-indexed.mlir

 // RUN: mlir-opt %s -test-linalg-greedy-fusion -split-input-file | FileCheck %s
 
 #id_2d = affine_map<(d0, d1) -> (d0, d1)>
 #pointwise_2d_trait = {
   indexing_maps = [#id_2d, #id_2d, #id_2d],
   iterator_types = ["parallel", "parallel"]
 }
 func.func @fuse_indexed_consumer(%A: memref<?x?xf32>,
                                     %B: memref<?x?xf32>,
                                     %C: memref<?x?xf32>,
                                     %D: memref<?x?xf32>) {
   linalg.generic #pointwise_2d_trait
     ins(%A, %B: memref<?x?xf32>, memref<?x?xf32>)
    outs(%C : memref<?x?xf32>) {
-  ^bb0(%e: f32, %arg5: f32, %arg6: f32):   
+  ^bb0(%e: f32, %arg5: f32, %arg6: f32):
     %2 = arith.addf %e, %arg5 : f32
     linalg.yield %2 : f32
   }
   %c1 = arith.constant 1 : index
   %c0 = arith.constant 0 : index
   %c25 = arith.constant 25 : index
   %c10 = arith.constant 10 : index
   %0 = memref.dim %C, %c0 : memref<?x?xf32>
func.func @fuse_indexed_producer(%A: memref<?x?xindex>,
   %c1 = arith.constant 1 : index
   %c0 = arith.constant 0 : index
   %c25 = arith.constant 25 : index
   %c10 = arith.constant 10 : index
   linalg.generic {
     indexing_maps = [affine_map<(i, j) -> (j, i)>],
     iterator_types = ["parallel", "parallel"]}
     outs(%A : memref<?x?xindex>) {
-  ^bb0(%a: index):   
+  ^bb0(%a: index):
     %idx0 = linalg.index 0 : index
     %idx1 = linalg.index 1 : index
     %0 = arith.addi %idx0, %idx1 : index
     linalg.yield %0 : index
   }
   %A_X = memref.dim %A, %c0 : memref<?x?xindex>
   %A_Y = memref.dim %A, %c1 : memref<?x?xindex>
   scf.parallel (%arg2, %arg3) = (%c0, %c0) to (%A_X, %A_Y) step (%c10, %c25) {
func.func @fuse_indexed_producer_tiled_second_dim_only(%A: memref<?x?xindex>,
                                                   %B: memref<?x?xindex>) {
   %c1 = arith.constant 1 : index
   %c0 = arith.constant 0 : index
   %c25 = arith.constant 25 : index
   linalg.generic {
     indexing_maps = [affine_map<(i, j) -> (i, j)>],
     iterator_types = ["parallel", "parallel"]}
     outs(%A : memref<?x?xindex>) {
-  ^bb0(%a: index):   
+  ^bb0(%a: index):
     %idx0 = linalg.index 0 : index
     %idx1 = linalg.index 1 : index
     %0 = arith.addi %idx0, %idx1 : index
     linalg.yield %0 : index
   }
   %A_X = memref.dim %A, %c0 : memref<?x?xindex>
   %A_Y = memref.dim %A, %c1 : memref<?x?xindex>
   scf.parallel (%arg3) = (%c0) to (%A_Y) step (%c25) {

mlir/test/Dialect/Linalg/fusion-push-reshape.mlir

func.func @reshape(%A: tensor<?x16xf32>, %B: tensor<16xf32>, %init: tensor<?x112x16xf32>) -> tensor<?x112x16xf32> {
   %0 = tensor.expand_shape %A [[0, 1], [2]]
       : tensor<?x16xf32> into tensor<?x112x16xf32>
   %2 = linalg.generic {indexing_maps = [
     affine_map<(d0, d1, d2) -> (d0, d1, d2)>, affine_map<(d0, d1, d2) -> (d2)>,
     affine_map<(d0, d1, d2) -> (d0, d1, d2)>],
     iterator_types = ["parallel", "parallel", "parallel"]}
   ins(%0, %B : tensor<?x112x16xf32>, tensor<16xf32>)
   outs(%init : tensor<?x112x16xf32>) {
-  ^bb0(%arg1: f32, %arg2: f32, %arg3: f32):  
+  ^bb0(%arg1: f32, %arg2: f32, %arg3: f32):
     %s = arith.subf %arg1, %arg2 : f32
     linalg.yield %s : f32
   } -> tensor<?x112x16xf32>
   return %2 : tensor<?x112x16xf32>
 }
 
 // -----
 
func.func @reshape_multiple(%A: tensor<12544x16xf32>, %B: tensor<12544x16xf32>,
   %3 = linalg.generic {indexing_maps = [
     affine_map<(d0, d1, d2) -> (d0, d1, d2)>,
     affine_map<(d0, d1, d2) -> (d0, d1, d2)>,
     affine_map<(d0, d1, d2) -> (d2)>,
     affine_map<(d0, d1, d2) -> (d0, d1, d2)>],
     iterator_types = ["parallel", "parallel", "parallel"]}
   ins(%0, %1, %C : tensor<112x112x16xf32>, tensor<112x112x16xf32>, tensor<16xf32>)
   outs(%2 : tensor<112x112x16xf32>) {
-  ^bb0(%arg1: f32, %arg2: f32, %arg3: f32, %arg4: f32):  
+  ^bb0(%arg1: f32, %arg2: f32, %arg3: f32, %arg4: f32):
     %s = arith.subf %arg1, %arg2 : f32
     %m = arith.mulf %s, %arg3 : f32
     linalg.yield %m : f32
   } -> tensor<112x112x16xf32>
   return %3 : tensor<112x112x16xf32>
 }
 
 // -----
%20 = tensor.expand_shape %A [[0, 1], [2]]
       : tensor<12544x16xf32> into tensor<112x112x16xf32>
   %21 = tensor.empty() : tensor<112x112x16xf32>
   %22 = linalg.generic {indexing_maps = [
     affine_map<(d0, d1, d2) -> (d0, d1, d2)>, affine_map<(d0, d1, d2) -> (d1)>,
     affine_map<(d0, d1, d2) -> (d0, d1, d2)>],
     iterator_types = ["parallel", "parallel", "parallel"]}
   ins(%20, %B : tensor<112x112x16xf32>, tensor<112xf32>)
   outs(%21 : tensor<112x112x16xf32>) {
-  ^bb0(%arg1: f32, %arg2: f32, %arg3: f32):  
+  ^bb0(%arg1: f32, %arg2: f32, %arg3: f32):
     %s = arith.subf %arg1, %arg2 : f32
     linalg.yield %s : f32
   } -> tensor<112x112x16xf32>
   return %22 : tensor<112x112x16xf32>
 }
 
 // -----
 
 func.func @type_correctness(%arg0 : tensor<6x5xi32>, %arg1 : tensor<5xf32>,
     %arg2 : tensor<5xf32>) -> tensor<2x3x5xf32> {
   %cst_6 = arith.constant 1.000000e+00 : f32
   %cst_7 = arith.constant 7.000000e+00 : f32
   %cst_8 = arith.constant 1.1920929E-7 : f32
   %25 = tensor.expand_shape %arg0 [[0, 1], [2]]
       : tensor<6x5xi32> into tensor<2x3x5xi32>
   %26 = tensor.empty() : tensor<2x3x5xf32>
   %28 = linalg.generic {
       indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d1, d2)>,
                        affine_map<(d0, d1, d2) -> (d2)>,
                        affine_map<(d0, d1, d2) -> (d2)>,
                        affine_map<(d0, d1, d2) -> (d0, d1, d2)>],
       iterator_types = ["parallel", "parallel", "parallel"]}
       ins(%25, %arg1, %arg2 : tensor<2x3x5xi32>, tensor<5xf32>, tensor<5xf32>)
       outs(%26 : tensor<2x3x5xf32>) {
-      ^bb0(%arg6: i32, %arg7: f32, %arg8: f32, %arg9: f32):  
+      ^bb0(%arg6: i32, %arg7: f32, %arg8: f32, %arg9: f32):
         %29 = arith.sitofp %arg6 : i32 to f32
         %30 = arith.addf %arg7, %cst_8 : f32
         %31 = arith.divf %cst_7, %30 : f32
         %32 = arith.divf %cst_6, %31 : f32
         %33 = arith.mulf %29, %32 : f32
         %34 = arith.addf %33, %arg8 : f32
         linalg.yield %34 : f32
       } -> tensor<2x3x5xf32>
   return %28 : tensor<2x3x5xf32>
 }
 // CHECK-LABEL: func @type_correctness
 //       CHECK:   %[[OP:.+]] = linalg.generic
 //  CHECK-SAME:   ins(%{{.+}}, %{{.+}}, %{{.+}} : tensor<6x5xi32>, tensor<5xf32>, tensor<5xf32>)
 //  CHECK-SAME:   outs(%{{.+}} : tensor<6x5xf32>)
 //       CHECK:   tensor.expand_shape %[[OP]]
 //  CHECK-SAME:   tensor<6x5xf32> into tensor<2x3x5xf32>

mlir/test/Dialect/Linalg/generalize-named-ops.mlir

 // CHECK:            %[[BBARG1_F32:.+]] = arith.sitofp %[[BBARG1]] : i8 to f32
 // CHECK:            %[[MUL:.+]] = arith.mulf %[[BBARG0_F32]], %[[BBARG1_F32]]
 // CHECK:            %[[ADD:.+]] = arith.addf %[[BBARG2]], %[[MUL]]
 // CHECK:            linalg.yield %[[ADD]] : f32
 
 // -----
 
 func.func @batch_reduce_gemm(%lhs: memref<7x8x9xf32>, %rhs: memref<7x9x8xf32>, %out: memref<8x8xf32>) {
-  linalg.batch_reduce_matmul ins(%lhs, %rhs: memref<7x8x9xf32>, memref<7x9x8xf32>)  
+  linalg.batch_reduce_matmul ins(%lhs, %rhs: memref<7x8x9xf32>, memref<7x9x8xf32>)
                              outs(%out: memref<8x8xf32>)
   return
 }
 
 // CHECK-DAG: #[[MAP0:.+]] = affine_map<(d0, d1, d2, d3) -> (d0, d1, d3)>
 // CHECK-DAG: #[[MAP1:.+]] = affine_map<(d0, d1, d2, d3) -> (d0, d3, d2)>
 // CHECK-DAG: #[[MAP2:.+]] = affine_map<(d0, d1, d2, d3) -> (d1, d2)>
 

mlir/test/Dialect/Linalg/generalize-pad-tensor.mlir

 // RUN: mlir-opt -split-input-file --test-linalg-transform-patterns="test-generalize-pad-tensor"  %s | FileCheck --check-prefix=CHECK %s
 
 // CHECK-LABEL:   func @generalize_pad_tensor_static_shape(
 // CHECK-SAME:                                             %[[IN:.*]]: tensor<1x28x28x1xf32>) -> tensor<1x32x32x1xf32> {
 // CHECK:           %[[C0:.*]] = arith.constant 0.000000e+00 : f32
 // CHECK:           %[[INIT:.*]] = tensor.empty() : tensor<1x32x32x1xf32>
 // CHECK:           %[[FILL:.*]] = linalg.fill ins(%[[C0]] : f32) outs(%[[INIT]] : tensor<1x32x32x1xf32>) -> tensor<1x32x32x1xf32>
 // CHECK:           %[[PADDED:.*]] = tensor.insert_slice %[[IN]] into %[[FILL]][0, 2, 2, 0] [1, 28, 28, 1] [1, 1, 1, 1] : tensor<1x28x28x1xf32> into tensor<1x32x32x1xf32>
 // CHECK:           return %[[PADDED]] : tensor<1x32x32x1xf32>
 func.func @generalize_pad_tensor_static_shape(%arg0: tensor<1x28x28x1xf32>) -> tensor<1x32x32x1xf32> {
   %cst = arith.constant 0.000000e+00 : f32
   %0 = tensor.pad %arg0 low[0, 2, 2, 0] high[0, 2, 2, 0]  {
-  ^bb0(%arg1: index, %arg2: index, %arg3: index, %arg4: index):  
+  ^bb0(%arg1: index, %arg2: index, %arg3: index, %arg4: index):
     tensor.yield %cst : f32
   } : tensor<1x28x28x1xf32> to tensor<1x32x32x1xf32>
   return %0 : tensor<1x32x32x1xf32>
 }
 
 // CHECK-LABEL:   func @generalize_pad_tensor_dynamic_shape(
 // CHECK-SAME:                                              %[[IN:.*]]: tensor<4x?x2x?xf32>,
 // CHECK-SAME:                                              %[[OFFSET:.*]]: index) -> tensor<4x?x?x?xf32> {

 // CHECK:           %[[DIM3_1:.*]] = tensor.dim %[[IN]], %[[C3]] : tensor<4x?x2x?xf32>
 // CHECK:           %[[PADDED:.*]] = tensor.insert_slice %[[IN]] into %[[FILL]]{{\[}}%[[C0]], %[[C0]], %[[OFFSET]], %[[C0]]] [4, %[[DIM1_1]], 2, %[[DIM3_1]]] [1, 1, 1, 1] : tensor<4x?x2x?xf32> into tensor<4x?x?x?xf32>
 // CHECK:           return %[[PADDED]] : tensor<4x?x?x?xf32>
 // CHECK:         }
 func.func @generalize_pad_tensor_dynamic_shape(%arg0: tensor<4x?x2x?xf32>, %arg1: index) -> tensor<4x?x?x?xf32> {
   %c0 = arith.constant 0 : index
   %cst = arith.constant 0.0 : f32
   %out = tensor.pad %arg0 low[%c0, %c0, %arg1, %c0] high[%c0, %c0, %c0, %arg1]  {
-  ^bb0(%gen_arg1: index, %gen_arg2: index, %gen_arg3: index, %gen_arg4: index):  
+  ^bb0(%gen_arg1: index, %gen_arg2: index, %gen_arg3: index, %gen_arg4: index):
     tensor.yield %cst : f32
   } : tensor<4x?x2x?xf32> to tensor<4x?x?x?xf32>
   return %out : tensor<4x?x?x?xf32>
 }

mlir/test/Dialect/Linalg/inline-scalar-operands.mlir

 // RUN: mlir-opt %s -linalg-inline-scalar-operands -split-input-file | FileCheck %s
 
 // CHECK: #[[MAP:.*]] = affine_map<(d0) -> (d0)>
 #map2 = affine_map<(d0) -> (d0)>
 #map3 = affine_map<(d0) -> ()>
 
 // CHECK: func @inline_zerod(%[[ARG:.*]]: tensor<4xf32>, %[[SCALAR:.*]]: tensor<f32>)
 func.func @inline_zerod(%arg0: tensor<4xf32>, %scalar: tensor<f32>) -> tensor<4xf32> {
     %0 = tensor.empty() : tensor<4xf32>
     // CHECK: linalg.generic {indexing_maps = [#[[MAP]], #[[MAP]]],
     // CHECK-SAME: iterator_types = ["parallel"]} ins(%[[ARG]] : tensor<4xf32>)
     %1 = linalg.generic {indexing_maps = [#map2, #map3, #map2],
                          iterator_types = ["parallel"]}
                          ins(%arg0, %scalar : tensor<4xf32>, tensor<f32>)
                          outs(%0 : tensor<4xf32>) {
     // CHECK: ^bb0(%{{.*}}: f32, %{{.*}}: f32)
-    ^bb0(%arg1: f32, %arg2: f32, %arg3: f32):  
+    ^bb0(%arg1: f32, %arg2: f32, %arg3: f32):
       // CHECK: tensor.extract %[[SCALAR]][]
       %2 = arith.divf %arg1, %arg2 : f32
       linalg.yield %2 : f32
     } -> tensor<4xf32>
   return %1 : tensor<4xf32>
 }
 
 // -----
 
 // CHECK: #[[MAP:.*]] = affine_map<(d0) -> (d0)>
 #map2 = affine_map<(d0) -> (d0)>
 #map3 = affine_map<(d0) -> (0)>
 
 // CHECK: func @inline_oned(%[[ARG:.*]]: tensor<4xf32>, %[[SCALAR:.*]]: tensor<1xf32>)
 func.func @inline_oned(%arg0: tensor<4xf32>, %scalar: tensor<1xf32>) -> tensor<4xf32> {
     // CHECK: %[[ZERO:.*]] = arith.constant 0 : index
     %0 = tensor.empty() : tensor<4xf32>
     // CHECK: linalg.generic {indexing_maps = [#[[MAP]], #[[MAP]]],
     // CHECK-SAME: iterator_types = ["parallel"]} ins(%[[ARG]] : tensor<4xf32>)
     %1 = linalg.generic {indexing_maps = [#map2, #map3, #map2],
                          iterator_types = ["parallel"]}
                          ins(%arg0, %scalar : tensor<4xf32>, tensor<1xf32>)
                          outs(%0 : tensor<4xf32>) {
     // CHECK: ^bb0(%{{.*}}: f32, %{{.*}}: f32)
-    ^bb0(%arg1: f32, %arg2: f32, %arg3: f32):  
+    ^bb0(%arg1: f32, %arg2: f32, %arg3: f32):
       // CHECK: tensor.extract %[[SCALAR]][%[[ZERO]]]
       %2 = arith.divf %arg1, %arg2 : f32
       linalg.yield %2 : f32
     } -> tensor<4xf32>
   return %1 : tensor<4xf32>
 }

mlir/test/Dialect/Linalg/library-calls.mlir

func.func @matmul(%A: memref<?x?xf32>, %B: memref<?x?xf32>) -> (memref<?x?xf32>) {
   // CHECK: call @linalg_fill_f32_viewsxsxf32({{.*}}) : (f32, memref<?x?xf32, {{.*}}>)
   linalg.fill ins(%f0 : f32) outs(%C : memref<?x?xf32>)
 
   // CHECK:  call @linalg_matmul_viewsxsxf32_viewsxsxf32_viewsxsxf32({{.*}}) : (memref<?x?xf32, {{.*}}>, memref<?x?xf32, {{.*}}>, memref<?x?xf32, {{.*}}>) -> ()
   linalg.matmul ins(%A, %B: memref<?x?xf32>, memref<?x?xf32>)
                 outs(%C: memref<?x?xf32>)
   return %C : memref<?x?xf32>
 }
-  

mlir/test/Dialect/Linalg/loops.mlir

#trait_const_fill = {
   args_out = 1,
   indexing_maps = [affine_map<(i) -> (i)>],
   iterator_types = ["parallel"],
   library_call = "some_external_fn"
 }
 func.func @generic_const_init(%arg0: memref<?xf32>) {
         %cst = arith.constant 1.0 : f32
   linalg.generic #trait_const_fill outs(%arg0 : memref<?xf32>) {
-    ^bb0(%arg1: f32):   
+    ^bb0(%arg1: f32):
       linalg.yield %cst : f32
     }
     return
 }
 // CHECK-LABEL: @generic_const_init
 //  CHECK-SAME: %[[ARG0:.*]]: memref<?xf32>
 //       CHECK: %[[CONST:.*]] = arith.constant 1.000000e+00 : f32
 //       CHECK: scf.for %[[i:.*]] = {{.*}}

mlir/test/Dialect/Linalg/lower-pad-tensor.mlir

 // RUN: mlir-opt -split-input-file --test-linalg-transform-patterns="test-transform-pad-tensor"  %s | FileCheck --check-prefix=CHECK %s
 
 // CHECK-DAG:   #[[$MAP0:.*]] = affine_map<(d0, d1, d2, d3) -> (d0, d1, d2, d3)>
 // CHECK-DAG:   #[[$MAP1:.*]] = affine_map<(d0, d1, d2, d3) -> (d0 + 1, d1 + 1, d2 + 1, d3 + 2)>
 // CHECK-LABEL: func @pad_tensor_with_memrefs
 func.func @pad_tensor_with_memrefs(%arg0: memref<1x28x28x1xf32>) -> memref<2x31x31x3xf32> {
   %cst = arith.constant 0.000000e+00 : f32
   %0 = bufferization.to_tensor %arg0 : memref<1x28x28x1xf32>
   %1 = tensor.pad %0 low[1, 1, 1, 2] high[0, 2, 2, 0]  {
-  ^bb0(%arg1: index, %arg2: index, %arg3: index, %arg4: index):  
+  ^bb0(%arg1: index, %arg2: index, %arg3: index, %arg4: index):
     tensor.yield %cst : f32
   } : tensor<1x28x28x1xf32> to tensor<2x31x31x3xf32>
   %2 = bufferization.to_memref %1 : memref<2x31x31x3xf32>
   return %2 : memref<2x31x31x3xf32>
 }
 
 // CHECK:       linalg.fill
 // CHECK:       linalg.generic
 // CHECK-SAME:     indexing_maps = [#[[$MAP0]], #[[$MAP1]]]
 
 // -----
 
 // CHECK-DAG:   #[[$MAP2:.*]] = affine_map<(d0, d1, d2) -> (d0, d1, d2)>
 // CHECK-DAG:   #[[$MAP3:.*]] = affine_map<(d0, d1, d2) -> (d0 + 1, d1 + 2, d2 + 2)>
 // CHECK-LABEL: func @pad_tensor_no_memrefs
 func.func @pad_tensor_no_memrefs(%arg0: tensor<1x28x28xf32>) -> tensor<2x32x32xf32> {
   %cst = arith.constant 0.000000e+00 : f32
   %0 = tensor.pad %arg0 low[1, 2, 2] high[0, 2, 2]  {
-  ^bb0(%arg1: index, %arg2: index, %arg3: index):  
+  ^bb0(%arg1: index, %arg2: index, %arg3: index):
     tensor.yield %cst : f32
   } : tensor<1x28x28xf32> to tensor<2x32x32xf32>
   return %0 : tensor<2x32x32xf32>
 }
 
 // CHECK:       linalg.fill
 // CHECK:       linalg.generic
 // CHECK-SAME:      indexing_maps = [#[[$MAP2]], #[[$MAP3]]]
 
 // -----
 
 // CHECK-DAG:   #[[$MAP4:.*]] = affine_map<(d0, d1, d2, d3) -> (d0, d1, d2, d3)>
 // CHECK-DAG:   #[[$MAP5:.*]] = affine_map<(d0, d1, d2, d3) -> (d0, d1 + 2, d2 + 2, d3)>
 // CHECK-LABEL: func @pad_tensor_detailed
 func.func @pad_tensor_detailed(%arg0: tensor<1x28x28x1xf32>) -> tensor<1x32x32x1xf32> {
   %cst = arith.constant 0.000000e+00 : f32
   %0 = tensor.pad %arg0 low[0, 2, 2, 0] high[0, 2, 2, 0]  {
-  ^bb0(%arg1: index, %arg2: index, %arg3: index, %arg4: index):  
+  ^bb0(%arg1: index, %arg2: index, %arg3: index, %arg4: index):
     tensor.yield %cst : f32
   } : tensor<1x28x28x1xf32> to tensor<1x32x32x1xf32>
   return %0 : tensor<1x32x32x1xf32>
 }
 
 // CHECK:      %[[ARG0:[a-zA-Z0-9_]+]]: tensor<1x28x28x1xf32>) -> tensor<1x32x32x1xf32>
 // CHECK:      %[[CTE:.+]] = arith.constant 0.000000e+00 : f32
 // CHECK:      %[[TMP:.+]] = tensor.empty() : tensor<1x32x32x1xf32>
 // CHECK:      %[[R1c:.+]] = linalg.fill
 // CHECK:      %[[R2c:.+]] = linalg.generic
 // CHECK-SAME:   indexing_maps = [#[[$MAP4]], #[[$MAP5]]]
 // CHECK-SAME:   iterator_types = ["parallel", "parallel", "parallel", "parallel"]
 // CHECK:        ins(%{{.*}} : tensor<1x28x28x1xf32>) outs(%{{.*}} : tensor<1x32x32x1xf32>)
 // CHECK:      ^bb0(%[[VAL:.+]]: f32, %{{.*}}: f32)
 // CHECK:        linalg.yield %[[VAL]] : f32
 // CHECK:      return %[[R2c:.+]]

mlir/test/Dialect/Linalg/pad_fusion.mlir

 // RUN: mlir-opt -test-linalg-pad-fusion -split-input-file %s | FileCheck %s
 
 func.func @dynamic_pad_fusion(%arg0 : tensor<?x?xf32>, %arg1 : index, %arg2 : index,
     %arg3 : index, %arg4 : index, %arg5 : f32) -> tensor<?x?xf32> {
   %c0 = arith.constant 0 : index
   %c1 = arith.constant 1 : index
   %d0 = tensor.dim %arg0, %c0 : tensor<?x?xf32>
   %d1 = tensor.dim %arg0, %c1 : tensor<?x?xf32>
   %init = tensor.empty(%d0, %d1) : tensor<?x?xf32>
   %0 = linalg.generic {
     indexing_maps = [affine_map<(d0, d1) -> (d0, d1)>, affine_map<(d0, d1) -> (d0, d1)>],
-    iterator_types = ["parallel", "parallel"]} 
+    iterator_types = ["parallel", "parallel"]}
     ins(%arg0 : tensor<?x?xf32>) outs(%init : tensor<?x?xf32>) {
     ^bb0(%arg6 : f32, %arg7 : f32):
       %1 = arith.mulf %arg6, %arg6 : f32
       linalg.yield %1 : f32
     } -> tensor<?x?xf32>
   %1 = tensor.pad %0 low [%arg1, %arg2] high [%arg3, %arg4] {
     ^bb0(%arg6: index, %arg7 : index):
       tensor.yield %arg5 : f32

 // CHECK-SAME:     %[[ARG5:[a-zA-Z0-9]+]]: f32
 //  CHECK-DAG:   %[[C0:.+]] = arith.constant 0 : index
 //  CHECK-DAG:   %[[C1:.+]] = arith.constant 1 : index
 //  CHECK-DAG:   %[[SOURCE:.+]] = linalg.generic
 //  CHECK-DAG:   %[[SOURCE_D0:.+]] = tensor.dim %[[SOURCE]], %[[C0]]
 //  CHECK-DAG:   %[[TARGET_D0:.+]] = affine.apply #[[MAP]]()[%[[ARG1]], %[[ARG3]], %[[SOURCE_D0]]]
 //  CHECK-DAG:   %[[SOURCE_D1:.+]] = tensor.dim %[[SOURCE]], %[[C1]]
 //  CHECK-DAG:   %[[TARGET_D1:.+]] = affine.apply #[[MAP]]()[%[[ARG2]], %[[ARG4]], %[[SOURCE_D1]]]
-//      CHECK:   %[[INIT:.+]] = tensor.empty(%[[TARGET_D0]], %[[TARGET_D1]]) 
+//      CHECK:   %[[INIT:.+]] = tensor.empty(%[[TARGET_D0]], %[[TARGET_D1]])
 //      CHECK:   %[[FILL:.+]] = linalg.fill ins(%[[ARG5]]{{.*}}outs(%[[INIT]]
 //  CHECK-DAG:   %[[SIZE_D0:.+]] = tensor.dim %[[SOURCE]], %[[C0]]
 //  CHECK-DAG:   %[[SIZE_D1:.+]] = tensor.dim %[[SOURCE]], %[[C1]]
 //      CHECK:   %[[SLICE:.+]] = tensor.extract_slice %[[FILL]]
 // CHECK-SAME:       [%[[ARG1]], %[[ARG2]]] [%[[SIZE_D0]], %[[SIZE_D1]]] [1, 1]
 //      CHECK:   %[[SOURCE:.+]] = linalg.generic
 // CHECK-SAME:       outs(%[[SLICE]] : tensor<?x?xf32>)
 //      CHECK:   %[[RESULT:.+]] = tensor.insert_slice %[[SOURCE]] into %[[FILL]]
 // CHECK-SAME:       [%[[ARG1]], %[[ARG2]]] [%[[SIZE_D0]], %[[SIZE_D1]]] [1, 1]
 //      CHECK:   return %[[RESULT]]
 
 // -----
 
 func.func @mixed_pad_fusion(%arg0 : tensor<?x42xf32>, %arg1 : index, %arg2 : index,
     %arg3 : f32) -> tensor<49x?xf32> {
   %c0 = arith.constant 0 : index
   %d0 = tensor.dim %arg0, %c0 : tensor<?x42xf32>
   %init = tensor.empty(%d0) : tensor<42x?xf32>
   %0 = linalg.generic {
     indexing_maps = [affine_map<(d0, d1) -> (d0, d1)>, affine_map<(d0, d1) -> (d1, d0)>],
-    iterator_types = ["parallel", "parallel"]} 
+    iterator_types = ["parallel", "parallel"]}
     ins(%arg0 : tensor<?x42xf32>) outs(%init : tensor<42x?xf32>) {
     ^bb0(%arg4 : f32, %arg5 : f32):
       %1 = arith.mulf %arg4, %arg4 : f32
       linalg.yield %1 : f32
     } -> tensor<42x?xf32>
   %1 = tensor.pad %0 low [3, %arg1] high [4, %arg2] {
     ^bb0(%arg4: index, %arg5 : index):
       tensor.yield %arg3 : f32

mlir/test/Dialect/Linalg/parallel-loops.mlir

 // RUN: mlir-opt %s -convert-linalg-to-parallel-loops -split-input-file | FileCheck %s
 
 #map0 = affine_map<(d0, d1) -> (d0, d1)>
 func.func @linalg_generic_sum(%lhs: memref<2x2xf32>,
                          %rhs: memref<2x2xf32>,
                          %sum: memref<2x2xf32>) {
   linalg.generic {
     indexing_maps = [#map0, #map0, #map0],
     iterator_types = ["parallel", "parallel"]}
       ins(%lhs, %rhs : memref<2x2xf32>, memref<2x2xf32>)
      outs(%sum : memref<2x2xf32>) {
-    ^bb0(%lhs_in: f32, %rhs_in: f32, %sum_out: f32):   
+    ^bb0(%lhs_in: f32, %rhs_in: f32, %sum_out: f32):
       %0 = arith.addf %lhs_in, %rhs_in : f32
       linalg.yield %0 : f32
   }
   return
 }
 // CHECK-LABEL: @linalg_generic_sum
 // CHECK:   (%[[LHS:.*]]:{{.*}}, %[[RHS:.*]]:{{.*}}, %[[SUM:.*]]:{{.*}})
 // CHECK-DAG: %[[C2:.*]] = arith.constant 2

mlir/test/Dialect/Linalg/reshape_fusion.mlir

 {
   %0 = tensor.collapse_shape %arg0 [[0], [1, 2], [3]] :
     tensor<?x?x4x?xf32> into tensor<?x?x?xf32>
   %1 = linalg.generic {
      indexing_maps = [#map0, #map1, #map2, #map1],
      iterator_types = ["parallel", "parallel", "parallel"]}
        ins(%0, %arg1, %arg2 : tensor<?x?x?xf32>, tensor<?x?x?xf32>, f32)
        outs(%arg1 : tensor<?x?x?xf32>) {
-    ^bb0(%arg3: f32, %arg4: f32, %arg5: f32, %s: f32):       
+    ^bb0(%arg3: f32, %arg4: f32, %arg5: f32, %s: f32):
       %1 = arith.mulf %arg3, %arg4 : f32
       %2 = arith.addf %1, %arg5 : f32
       linalg.yield %2 : f32
   } -> tensor<?x?x?xf32>
   return %1 : tensor<?x?x?xf32>
 }
 
 //  CHECK-DAG: #[[MAP5:.+]] = affine_map<(d0, d1, d2, d3) -> (d3, d0, d1, d2)>
func.func @generic_op_reshape_consumer_fusion(%arg0 : tensor<?x?xf32>,
                                          %arg2 : f32) ->
                                          tensor<?x4x?x5xf32>
 {
   %0 = linalg.generic {
      indexing_maps = [#map0, #map0, #map1, #map0],
      iterator_types = ["parallel", "parallel"]}
        ins(%arg0, %arg1, %arg2 : tensor<?x?xf32>, tensor<?x?xf32>, f32)
        outs(%arg0 : tensor<?x?xf32>) {
-    ^bb0(%arg3: f32, %arg4: f32, %arg5: f32, %s: f32):       
+    ^bb0(%arg3: f32, %arg4: f32, %arg5: f32, %s: f32):
       %1 = arith.mulf %arg3, %arg4 : f32
       %2 = arith.addf %1, %arg5 : f32
       linalg.yield %2 : f32
   } -> tensor<?x?xf32>
   %1 = tensor.expand_shape %0 [[0], [1, 2, 3]] :
     tensor<?x?xf32> into tensor<?x4x?x5xf32>
   return %1 : tensor<?x4x?x5xf32>
 }
func.func @generic_op_reshape_consumer_static(%arg0: tensor<264x4xf32>)
                                             -> tensor<8x33x4xf32> {
   %cst = arith.constant dense<2.000000e+00> : tensor<264x4xf32>
   %0 = tensor.empty() : tensor<264x4xf32>
   %1 = linalg.generic {
      indexing_maps = [#map0, #map0, #map0],
      iterator_types = ["parallel", "parallel"]}
        ins(%arg0, %cst : tensor<264x4xf32>, tensor<264x4xf32>)
        outs(%0 : tensor<264x4xf32>) {
-    ^bb0(%arg1: f32, %arg2: f32, %s: f32):  
+    ^bb0(%arg1: f32, %arg2: f32, %s: f32):
       %2 = arith.mulf %arg1, %arg2 : f32
       linalg.yield %2 : f32
     } -> tensor<264x4xf32>
   %2 = tensor.expand_shape %1 [[0, 1], [2]] :
     tensor<264x4xf32> into tensor<8x33x4xf32>
   return %2 : tensor<8x33x4xf32>
 }
 
func.func @indexed_producer_reshape_consumer_fusion(%arg0 : tensor<?x?xi32>,
                                          %arg1 : tensor<?x?xi32>) ->
                                          tensor<?x?x4x5xi32>
 {
   %0 = linalg.generic {
      indexing_maps = [#map0, #map0, #map0],
      iterator_types = ["parallel", "parallel"]}
        ins(%arg0, %arg1 : tensor<?x?xi32>, tensor<?x?xi32>)
       outs(%arg0 : tensor<?x?xi32>) {
-    ^bb0(%arg3: i32, %arg4: i32, %s: i32):       
+    ^bb0(%arg3: i32, %arg4: i32, %s: i32):
       %idx0 = linalg.index 0 : index
       %idx1 = linalg.index 1 : index
       %1 = arith.muli %arg3, %arg4 : i32
       %2 = arith.index_cast %idx0 : index to i32
       %3 = arith.addi %1, %2 : i32
       %4 = arith.index_cast %idx1 : index to i32
       %5 = arith.addi %3, %4 : i32
       linalg.yield %5 : i32
func.func @reshape_as_producer_projected_permutation(
   %0 = tensor.collapse_shape %arg0 [[0, 1], [2]]
     : tensor<33x8x?xi32> into tensor<264x?xi32>
   %1 = linalg.generic
     {indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d1)>,
                       affine_map<(d0, d1, d2) -> (d0, d1, d2)>],
      iterator_types = ["parallel", "parallel", "parallel"]}
      ins(%0 : tensor<264x?xi32>)
     outs(%shape : tensor<264x?x4xi32>) {
-  ^bb0(%arg1: i32, %s: i32):  
+  ^bb0(%arg1: i32, %s: i32):
     %idx0 = linalg.index 0 : index
     %idx1 = linalg.index 1 : index
     %idx2 = linalg.index 2 : index
     %2 = arith.index_cast %idx0 : index to i32
     %3 = arith.addi %arg1, %2 : i32
     %4 = arith.index_cast %idx1 : index to i32
     %5 = arith.addi %3, %4 : i32
     %6 = arith.index_cast %idx2 : index to i32
func.func @generic_op_reshape_consumer_fusion_projected(%arg0 : tensor<?x?xf32>,
                                                    %arg1 : tensor<?x?xf32>) ->
                                                    tensor<?x?x4x5xf32>
 {
   %0 = linalg.generic {
      indexing_maps = [#map0, #map0, #map1],
      iterator_types = ["parallel", "parallel"]}
        ins(%arg0, %arg1 : tensor<?x?xf32>, tensor<?x?xf32>)
        outs(%arg0 : tensor<?x?xf32>) {
-    ^bb0(%arg3: f32, %arg4: f32, %s: f32):       
+    ^bb0(%arg3: f32, %arg4: f32, %s: f32):
       %1 = arith.mulf %arg3, %arg4 : f32
       linalg.yield %1 : f32
   } -> tensor<?x?xf32>
   %1 = tensor.expand_shape %0 [[0], [1, 2, 3]] :
     tensor<?x?xf32> into tensor<?x?x4x5xf32>
   return %1 : tensor<?x?x4x5xf32>
 }
 
func.func @no_fuse_mismatched_dynamism(%arg0: tensor<2x1xi64>, %arg1: tensor<?xi64>) -> tensor<2xi64> {
   %1 = tensor.empty() : tensor<2xi64>
   %2 = linalg.generic
     {indexing_maps = [affine_map<(d0) -> (d0)>,
                       affine_map<(d0) -> (d0)>,
                       affine_map<(d0) -> (d0)>],
      iterator_types = ["parallel"]}
     ins(%0, %arg1 : tensor<2xi64>, tensor<?xi64>)
     outs(%1 : tensor<2xi64>) {
-  ^bb0(%arg4: i64, %arg5: i64, %arg6: i64):  
+  ^bb0(%arg4: i64, %arg5: i64, %arg6: i64):
     %3 = arith.addi %arg4, %arg5 : i64
     linalg.yield %3 : i64
   } -> tensor<2xi64>
   return %2 : tensor<2xi64>
 }
 
 //      CHECK: func @no_fuse_mismatched_dynamism
 // CHECK-SAME:     %[[ARG0:.+]]: tensor<2x1xi64>

mlir/test/Dialect/Linalg/tile-pad-tensor-op.mlir

 //   CHECK-DAG:   %[[C3:.*]] = arith.constant 3 : index
 //   CHECK-DAG:   %[[C16:.*]] = arith.constant 16 : index
 //       CHECK:   %[[RESULT:.*]] = scf.for {{.*}} = %[[C0]] to %[[C16]] step %[[C3]] iter_args(%[[INNER_OUT:.*]] =
 //       CHECK:     %[[SWAP_RESULT:.*]] = scf.if
 //       CHECK:       tensor.generate
 //       CHECK:     else
 //       CHECK:       %[[SLICE:.*]] = tensor.extract_slice %[[IN]][0, {{.*}}] [7, {{.*}}] [1, 1]
 //       CHECK:       %[[PAD:.*]] = tensor.pad %[[SLICE]] low[3, %{{.*}}] high[5, {{.*}}]
-//       CHECK:     %[[CAST_SWAP_RESULT:.*]] = tensor.cast %[[SWAP_RESULT]] : tensor<?x?xf32> to tensor<15x?xf32> 
+//       CHECK:     %[[CAST_SWAP_RESULT:.*]] = tensor.cast %[[SWAP_RESULT]] : tensor<?x?xf32> to tensor<15x?xf32>
 //       CHECK:     tensor.insert_slice %[[CAST_SWAP_RESULT]] into %[[INNER_OUT]][0, {{.*}}] [15, {{.*}}] [1, 1]
 //       CHECK:   return %[[RESULT]]
 
 func.func @static_pad_tensor_0_3(%input_tensor: tensor<7x9xf32>,
                         %pad_value: f32) -> tensor<15x16xf32> {
   %0 = tensor.pad %input_tensor low[3, 4] high[5, 3] {
     ^bb0(%arg1: index, %arg2: index):
       tensor.yield %pad_value : f32

mlir/test/Dialect/Linalg/transform-op-multitile-sizes.mlir

func.func @multitile_sizes_dynamic(
   // CHECK: affine.apply #[[$MAP_S]]()[%[[DIM]]]
   // CHECK: affine.apply #[[$MAP_V]]()[%[[DIM]]]
   // CHECK: affine.apply #[[$MAP_U]]()[%[[DIM]]]
   %arg0: tensor<?x?xf32>, %arg1: tensor<?x?xf32>, %arg2: tensor<?x?xf32>)
     -> tensor<?x?xf32> {
   %0 = linalg.matmul  ins(%arg0, %arg1: tensor<?x?xf32>, tensor<?x?xf32>)
                      outs(%arg2: tensor<?x?xf32>)
     -> tensor<?x?xf32>
-  
   return %0 : tensor<?x?xf32>
 }

mlir/test/Dialect/Linalg/transform-op-pad.mlir

^bb1(%arg1: !pdl.operation):
   %1 = transform.structured.pad %0 {padding_values=[0.0 : f32, 0.0 : f32, 0.0 : f32], padding_dimensions=[0, 1, 2], pack_paddings=[1, 1, 0]}
 }
 
 // -----
 
 func.func @pad(%arg0: tensor<24x12xf32>,
                %arg1: tensor<12x25xf32>,
                %arg2: tensor<24x25xf32>) -> tensor<24x25xf32> {
-  // expected-note @below {{when applied to this op}} 
+  // expected-note @below {{when applied to this op}}
   %0 = linalg.matmul ins(%arg0, %arg1 : tensor<24x12xf32>, tensor<12x25xf32>) outs(%arg2 : tensor<24x25xf32>) -> tensor<24x25xf32>
   func.return %0 : tensor<24x25xf32>
 }
 
 transform.sequence failures(propagate) {
 ^bb1(%arg1: !pdl.operation):
   %0 = transform.structured.match ops{["linalg.matmul"]} in %arg1
   // expected-error @below {{op expects a padding value of type 'f32', got 0 : i32}}

mlir/test/Dialect/Linalg/transform-op-split-reduction.mlir

%0 = linalg.generic {
     ^bb0(%arg0: f32, %arg1: f32, %arg2: f32):
       %3 = arith.addf %arg0, %arg1 : f32
       %4 = arith.minf %3, %arg2 : f32
       linalg.yield %4 : f32
     } -> tensor<5x2xf32>
   return %0 : tensor<5x2xf32>
 }
 
-//  CHECK-DAG: #[[$MAP0:.*]] = affine_map<(d0, d1, d2, d3) -> (d1, d2, d0)>  
-//  CHECK-DAG: #[[$MAP1:.*]] = affine_map<(d0, d1, d2, d3) -> (d3, d1, d2)>  
-//  CHECK-DAG: #[[$MAP2:.*]] = affine_map<(d0, d1, d2, d3) -> (d3, d0, d2)>  
-//  CHECK-DAG: #[[$MAP3:.*]] = affine_map<(d0, d1, d2) -> (d0, d1, d2)>  
-//  CHECK-DAG: #[[$MAP4:.*]] = affine_map<(d0, d1, d2) -> (d0, d1)>  
-// CHECK-LABEL:  func @generic_split_3d 
+//  CHECK-DAG: #[[$MAP0:.*]] = affine_map<(d0, d1, d2, d3) -> (d1, d2, d0)>
+//  CHECK-DAG: #[[$MAP1:.*]] = affine_map<(d0, d1, d2, d3) -> (d3, d1, d2)>
+//  CHECK-DAG: #[[$MAP2:.*]] = affine_map<(d0, d1, d2, d3) -> (d3, d0, d2)>
+//  CHECK-DAG: #[[$MAP3:.*]] = affine_map<(d0, d1, d2) -> (d0, d1, d2)>
+//  CHECK-DAG: #[[$MAP4:.*]] = affine_map<(d0, d1, d2) -> (d0, d1)>
+// CHECK-LABEL:  func @generic_split_3d
 //  CHECK-DAG: %[[ID:.*]] = arith.constant 0x7F800000 : f32
-//  CHECK-DAG: %[[I1:.*]] = tensor.expand_shape %{{.*}}[0, 1], [2]] : tensor<32x2xf32> into tensor<8x4x2xf32> 
-//  CHECK-DAG: %[[I2:.*]] = tensor.expand_shape %{{.*}}[0], [1, 2]] : tensor<5x32xf32> into tensor<5x8x4xf32> 
-//  CHECK-DAG: %[[INI:.*]] = tensor.empty() : tensor<5x2x4xf32> 
-//      CHECK: %[[F:.*]] = linalg.fill ins(%[[ID]] : f32) outs(%[[INI]] : tensor<5x2x4xf32>) -> tensor<5x2x4xf32>  
-//      CHECK: %[[G:.*]] = linalg.generic {indexing_maps = [#[[$MAP0]], #[[$MAP1]], #[[$MAP2]]], iterator_types = ["parallel", "reduction", "parallel", "parallel"]}  
-// CHECK-SAME:   ins(%[[I1]], %[[I2]] : tensor<8x4x2xf32>, tensor<5x8x4xf32>) outs(%[[F]] : tensor<5x2x4xf32>) {  
-//      CHECK:   arith.addf 
+//  CHECK-DAG: %[[I1:.*]] = tensor.expand_shape %{{.*}}[0, 1], [2]] : tensor<32x2xf32> into tensor<8x4x2xf32>
+//  CHECK-DAG: %[[I2:.*]] = tensor.expand_shape %{{.*}}[0], [1, 2]] : tensor<5x32xf32> into tensor<5x8x4xf32>
+//  CHECK-DAG: %[[INI:.*]] = tensor.empty() : tensor<5x2x4xf32>
+//      CHECK: %[[F:.*]] = linalg.fill ins(%[[ID]] : f32) outs(%[[INI]] : tensor<5x2x4xf32>) -> tensor<5x2x4xf32>
+//      CHECK: %[[G:.*]] = linalg.generic {indexing_maps = [#[[$MAP0]], #[[$MAP1]], #[[$MAP2]]], iterator_types = ["parallel", "reduction", "parallel", "parallel"]}
+// CHECK-SAME:   ins(%[[I1]], %[[I2]] : tensor<8x4x2xf32>, tensor<5x8x4xf32>) outs(%[[F]] : tensor<5x2x4xf32>) {
+//      CHECK:   arith.addf
 //      CHECK:   arith.minf
-//      CHECK:   linalg.yield 
-//      CHECK: } -> tensor<5x2x4xf32>  
-//      CHECK: %[[R:.*]] = linalg.generic {indexing_maps = [#[[$MAP3]], #[[$MAP4]]], iterator_types = ["parallel", "parallel", "reduction"]}  
-// CHECK-SAME:   ins(%[[G]] : tensor<5x2x4xf32>) outs(%{{.*}} : tensor<5x2xf32>) {  
+//      CHECK:   linalg.yield
+//      CHECK: } -> tensor<5x2x4xf32>
+//      CHECK: %[[R:.*]] = linalg.generic {indexing_maps = [#[[$MAP3]], #[[$MAP4]]], iterator_types = ["parallel", "parallel", "reduction"]}
+// CHECK-SAME:   ins(%[[G]] : tensor<5x2x4xf32>) outs(%{{.*}} : tensor<5x2xf32>) {
 //      CHECK:   arith.minf
-//      CHECK:   linalg.yield 
-//      CHECK:  } -> tensor<5x2xf32> 
-//      CHECK: return %[[R]] : tensor<5x2xf32>  
+//      CHECK:   linalg.yield
+//      CHECK:  } -> tensor<5x2xf32>
+//      CHECK: return %[[R]] : tensor<5x2xf32>
 
 transform.sequence failures(propagate) {
 ^bb1(%arg1: !pdl.operation):
   %0 = transform.structured.match ops{["linalg.generic"]} in %arg1
   %1:4 = transform.structured.split_reduction %0 { split_factor = 4, insert_split_dimension = 2, inner_parallel}
 }

mlir/test/Dialect/Linalg/transform-op-vectorize.mlir

 
 // CHECK-LABEL: @vectorize_pad
 // CHECK-SAME: %[[A:.+]]: tensor<24x12xf32>
 // CHECK-SAME: %[[B:.+]]: tensor<12x25xf32>
 // CHECK-SAME: %[[C:.+]]: tensor<24x25xf32>
 func.func @vectorize_pad(
     %arg0: tensor<24x12xf32>, %arg1: tensor<12x25xf32>,
     %arg2: tensor<24x25xf32>, %arg3: index, %arg4: index,
-    %arg5: index) -> tensor<24x25xf32> {    
+    %arg5: index) -> tensor<24x25xf32> {
   %c0 = arith.constant 0 : index
   %cst = arith.constant 0.000000e+00 : f32
   %0 = affine.min #map0()[%arg5]
   // CHECK: %[[sA:.+]] = tensor.extract_slice %[[A]]
   // CHECK: %[[sB:.+]] = tensor.extract_slice %[[B]]
   %1 = tensor.extract_slice %arg0[%arg3, %arg5] [4, %0] [1, 1] : tensor<24x12xf32> to tensor<4x?xf32>
   %2 = tensor.extract_slice %arg1[%arg5, %arg4] [%0, 5] [1, 1] : tensor<12x25xf32> to tensor<?x5xf32>
   %3 = tensor.extract_slice %arg2[%arg3, %arg4] [4, 5] [1, 1] : tensor<24x25xf32> to tensor<4x5xf32>

mlir/test/Dialect/Linalg/transform-promotion.mlir

func.func @aligned_promote_fill_complex(%arg0: memref<?x?xcomplex<f32>, strided<[?, 1], offset: ?>>) {
   %c2000 = arith.constant 2000 : index
   %c4000 = arith.constant 4000 : index
   %c0 = arith.constant 0 : index
   %c1 = arith.constant 1 : index
   %cf = arith.constant 1.0 : f32
   %cc = complex.create %cf, %cf : complex<f32>
   %3 = memref.subview %arg0[%c0, %c0][%c2000, %c4000][%c1, %c1] :
    memref<?x?xcomplex<f32>, strided<[?, 1], offset: ?>> to memref<?x?xcomplex<f32>, strided<[?, ?], offset: ?>>
-  linalg.fill ins(%cc : complex<f32>) 
+  linalg.fill ins(%cc : complex<f32>)
              outs(%3 : memref<?x?xcomplex<f32>, strided<[?, ?], offset: ?>>)
   return
 }
 // CHECK-LABEL: func @aligned_promote_fill_complex
 // CHECK:   %[[cc:.*]] = complex.create {{.*}} : complex<f32>
 // CHECK:         %[[s0:.*]] = memref.subview {{.*}}: memref<?x?xcomplex<f32>, strided{{.*}}> to memref<?x?xcomplex<f32>, strided{{.*}}>
 // CHECK:         %[[a0:.*]] = memref.alloc() {alignment = 32 : i64} : memref<64000000xi8>
 // CHECK:         %[[v0:.*]] = memref.view %[[a0]]{{.*}} : memref<64000000xi8> to memref<?x?xcomplex<f32>>

mlir/test/Dialect/Linalg/transform-tile-reduction.mlir

 //     CHECK:   linalg.fill {{.*}} : tensor<5x?xf32>) -> tensor<5x?xf32>
 //     CHECK:   scf.for
 //     CHECK:     linalg.generic
 //     CHECK:     %[[D3:.*]] = tensor.dim %{{.*}}, %[[C0]] : tensor<?x?xf32>
 //     CHECK:     %[[D4:.*]] = tensor.dim %{{.*}}, %[[C1]] : tensor<?x?xf32>
 //     CHECK:     %[[INS:.*]] = tensor.insert_slice %[[PR]] into %[[ARG3]][0, 0] [%[[D3]], %[[D4]]] [1, 1] : tensor<?x?xf32> into tensor<5x?xf32>
 //     CHECK:     scf.yield {{.*}} : tensor<5x?xf32>
 //     CHECK:   }
-//     CHECK:   linalg.generic 
+//     CHECK:   linalg.generic
 //     CHECK:   return
 
 // -----
 
 func.func @reduction_tile_parallel(
   %arg0: tensor<?x?xf32>, %out: tensor<?xf32>) -> tensor<?xf32> {
   %red = linalg.generic {indexing_maps = [affine_map<(d0, d1) -> (d0, d1)>,
                                           affine_map<(d0, d1) -> (d0)>],

mlir/test/Dialect/Linalg/vectorize-convolution.mlir

 //      CHECK:   %[[V_INPUT_0:.+]] = vector.extract_strided_slice %[[V_INPUT_R]]
 // CHECK-SAME:     {offsets = [0, 0, 0], sizes = [3, 2, 4], strides = [1, 1, 1]} : vector<3x4x4xi8> to vector<3x2x4xi8>
 //      CHECK:   %[[V_INPUT_1:.+]] = vector.extract_strided_slice %[[V_INPUT_R]]
 // CHECK-SAME:     {offsets = [0, 2, 0], sizes = [3, 2, 4], strides = [1, 1, 1]} : vector<3x4x4xi8> to vector<3x2x4xi8>
 
 //      CHECK:  %[[V_FILTER_0:.+]] = vector.extract %[[V_FILTER_R]][0] : vector<2x4xi8>
 //      CHECK:  %[[V_FILTER_1:.+]] = vector.extract %[[V_FILTER_R]][1] : vector<2x4xi8>
 
-/// w == 0, kw = 
+/// w == 0, kw =
 //      CHECK:  %[[EXT_INPUT_0:.*]] = arith.extsi %[[V_INPUT_0]] : vector<3x2x4xi8> to vector<3x2x4xi32>
 //      CHECK:  %[[B_FILTER_0:.*]] = vector.broadcast %[[V_FILTER_0]] : vector<4xi8> to vector<3x2x4xi8>
 //      CHECK:  %[[EXT_FILTER_0:.*]] = arith.extsi %[[B_FILTER_0]] : vector<3x2x4xi8> to vector<3x2x4xi32>
 //      CHECK:  %[[MUL_0:.*]] = arith.muli %[[EXT_INPUT_0]], %[[EXT_FILTER_0]] : vector<3x2x4xi32>
 //      CHECK:  %[[ADD_0:.*]] = arith.addi %[[MUL_0]], %[[V_OUTPUT_R]] : vector<3x2x4xi32>
 
 /// w == 0, kw = 1
 //      CHECK:  %[[EXT_INPUT_1:.*]] = arith.extsi %[[V_INPUT_1]] : vector<3x2x4xi8> to vector<3x2x4xi32>

mlir/test/Dialect/MemRef/expand-strided-metadata.mlir

 // RUN: mlir-opt --expand-strided-metadata -split-input-file %s -o - | FileCheck %s
 
 // CHECK-LABEL: func @extract_strided_metadata_constants
 //  CHECK-SAME: (%[[ARG:.*]]: memref<5x4xf32, strided<[4, 1], offset: 2>>)
 func.func @extract_strided_metadata_constants(%base: memref<5x4xf32, strided<[4, 1], offset: 2>>)
     -> (memref<f32>, index, index, index, index, index) {
   //   CHECK-DAG: %[[C1:.*]] = arith.constant 1 : index
   //   CHECK-DAG: %[[C2:.*]] = arith.constant 2 : index
   //   CHECK-DAG: %[[C4:.*]] = arith.constant 4 : index
   //   CHECK-DAG: %[[C5:.*]] = arith.constant 5 : index
-  
   //       CHECK: %[[BASE:.*]], %[[OFFSET:.*]], %[[SIZES:.*]]:2, %[[STRIDES:.*]]:2 = memref.extract_strided_metadata %[[ARG]]
   %base_buffer, %offset, %sizes:2, %strides:2 = memref.extract_strided_metadata %base :
     memref<5x4xf32, strided<[4,1], offset:2>>
     -> memref<f32>, index, index, index, index, index
 
   // CHECK: %[[BASE]], %[[C2]], %[[C5]], %[[C4]], %[[C4]], %[[C1]]
   return %base_buffer, %offset, %sizes#0, %sizes#1, %strides#0, %strides#1 :
     memref<f32>, index, index, index, index, index

mlir/test/Dialect/MemRef/fold-memref-alias-ops.mlir

 // CHECK-SAME:   %[[ARG6:[a-zA-Z0-9_]+]]: index
 //  CHECK-DAG:   %[[I1:.+]] = affine.apply #[[MAP]](%[[ARG3]])[%[[ARG5]], %[[ARG1]]]
 //  CHECK-DAG:   %[[I2:.+]] = affine.apply #[[MAP]](%[[ARG4]])[%[[ARG6]], %[[ARG2]]]
 //      CHECK:   vector.transfer_read %[[ARG0]][%[[I1]], %[[I2]]]
 
 // -----
 
 func.func @fold_static_stride_subview_with_transfer_write_0d(
-    %arg0 : memref<12x32xf32>, %arg1 : index, %arg2 : index, %arg3 : index, 
+    %arg0 : memref<12x32xf32>, %arg1 : index, %arg2 : index, %arg3 : index,
     %v : vector<f32>) {
   %f1 = arith.constant 1.0 : f32
   %0 = memref.subview %arg0[%arg1, %arg2][1, 1][2, %arg3] : memref<12x32xf32> to memref<f32, strided<[], offset: ?>>
   vector.transfer_write %v, %0[] {in_bounds = []} : vector<f32>, memref<f32, strided<[], offset: ?>>
   return
 }
 //  CHECK-DAG: #[[MAP0:.+]] = affine_map<(d0)[s0] -> (d0 * 2 + s0)>
 //  CHECK-DAG: #[[MAP1:.+]] = affine_map<(d0)[s0, s1] -> (d0 * s0 + s1)>

mlir/test/Dialect/MemRef/ops.mlir

func.func @expand_collapse_shape_transposed_layout(
   %r0 = memref.expand_shape %m0 [[0], [1, 2]] :
     memref<?x?xf32, strided<[1, 10], offset: 0>> into
     memref<?x?x5xf32, strided<[1, 50, 10], offset: 0>>
   %rr0 = memref.collapse_shape %r0 [[0], [1, 2]] :
     memref<?x?x5xf32, strided<[1, 50, 10], offset: 0>> into
     memref<?x?xf32, strided<[1, 10], offset: 0>>
 
   %r1 = memref.expand_shape %m1 [[0, 1], [2], [3, 4]] :
-    memref<4x5x6xf32, strided<[1, ?, 1000], offset: 0>> into 
+    memref<4x5x6xf32, strided<[1, ?, 1000], offset: 0>> into
     memref<2x2x5x2x3xf32, strided<[2, 1, ?, 3000, 1000], offset: 0>>
   %rr1 = memref.collapse_shape %r1 [[0, 1], [2], [3, 4]] :
     memref<2x2x5x2x3xf32, strided<[2, 1, ?, 3000, 1000], offset: 0>> into
     memref<4x5x6xf32, strided<[1, ?, 1000], offset: 0>>
   return
 }
 
 // -----
^bb0(%old_value : f32):
       memref.atomic_yield %out : f32
   // CHECK: index_attr = 8 : index
   } { index_attr = 8 : index }
   return
 }
 
 // -----
 
-func.func @extract_strided_metadata(%memref : memref<10x?xf32>) 
+func.func @extract_strided_metadata(%memref : memref<10x?xf32>)
   -> memref<?x?xf32, strided<[?, ?], offset: ?>> {
 
   %base, %offset, %sizes:2, %strides:2 = memref.extract_strided_metadata %memref
     : memref<10x?xf32> -> memref<f32>, index, index, index, index, index
 
   %m2 = memref.reinterpret_cast %base to
       offset: [%offset],
       sizes: [%sizes#0, %sizes#1],

mlir/test/Dialect/MemRef/subview.mlir

func.func @memref_subview(%arg0 : index, %arg1 : index, %arg2 : index) {
 
   // CHECK: memref.subview {{%.*}}[{{%.*}}, {{%.*}}] [4, 4] [2, 2] :
   // CHECK-SAME: memref<16x4xf32>
   // CHECK-SAME: to memref<4x4xf32, strided<[8, 2], offset: ?>>
   %11 = memref.subview %9[%arg1, %arg2][4, 4][2, 2]
     : memref<16x4xf32> to memref<4x4xf32, strided<[8, 2], offset: ?>>
 
   %12 = memref.alloc() : memref<1x9x1x4x1xf32, strided<[36, 36, 4, 4, 1]>>
-  // CHECK: memref.subview 
+  // CHECK: memref.subview
   // CHECK-SAME: [1, 9, 1, 4, 1]
   // CHECK-SAME: memref<1x9x1x4x1xf32, strided<[36, 36, 4, 4, 1]>> to memref<9x4xf32, strided<[?, ?], offset: ?>>
   %13 = memref.subview %12[%arg1, %arg1, %arg1, %arg1, %arg1][1, 9, 1, 4, 1][%arg2, %arg2, %arg2, %arg2, %arg2] : memref<1x9x1x4x1xf32, strided<[36, 36, 4, 4, 1], offset: 0>> to memref<9x4xf32, strided<[?, ?], offset: ?>>
   // CHECK: memref.subview
   // CHECK-SAME: [1, 9, 1, 4, 1]
   // CHECK-SAME: memref<1x9x1x4x1xf32, strided<[36, 36, 4, 4, 1]>> to memref<1x9x4xf32, strided<[?, ?, ?], offset: ?>>
   %14 = memref.subview %12[%arg1, %arg1, %arg1, %arg1, %arg1][1, 9, 1, 4, 1][%arg2, %arg2, %arg2, %arg2, %arg2] : memref<1x9x1x4x1xf32, strided<[36, 36, 4, 4, 1], offset: 0>> to memref<1x9x4xf32, strided<[?, ?, ?], offset: ?>>
 

mlir/test/Dialect/NVGPU/invalid.mlir

func.func @ldmatrix_type_x4(%arg0: memref<128x128xf32, 3>) ->  vector<4x2xf16> {
   // expected-error @+1 {{'nvgpu.ldmatrix' op failed to verify that srcMemref and res have same element type}}
   %a = nvgpu.ldmatrix %arg0[%c0, %c0] {transpose = false, numTiles = 4 : i32} : memref<128x128xf32, 3> -> vector<4x2xf16>
   return %a : vector<4x2xf16>
 }
 // -----
 
 func.func @m16n8k16_fp16_vector_shape_a(%arg0: vector<4x4xf16>, %arg1: vector<2x2xf16>, %arg2: vector<2x2xf16>) -> vector<2x2xf16> {
   // expected-error @+1 {{expected 256 warp-wide matrix A elements}}
-  %d = nvgpu.mma.sync (%arg0, %arg1, %arg2) {mmaShape = [16, 8, 16]} : (vector<4x4xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>    
+  %d = nvgpu.mma.sync (%arg0, %arg1, %arg2) {mmaShape = [16, 8, 16]} : (vector<4x4xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
   return %d : vector<2x2xf16>
 }
 // -----
 
 func.func @m16n8k16_fp16_vector_shape_b(%arg0: vector<4x2xf16>, %arg1: vector<2x4xf16>, %arg2: vector<2x2xf16>) -> vector<2x2xf16> {
   // expected-error @+1 {{expected 128 warp-wide matrix B elements}}
-  %d = nvgpu.mma.sync (%arg0, %arg1, %arg2) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x4xf16>, vector<2x2xf16>) -> vector<2x2xf16>    
+  %d = nvgpu.mma.sync (%arg0, %arg1, %arg2) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x4xf16>, vector<2x2xf16>) -> vector<2x2xf16>
   return %d : vector<2x2xf16>
 }
 // -----
 
 func.func @m16n8k16_fp16_vector_shape_c(%arg0: vector<4x2xf16>, %arg1: vector<2x2xf16>, %arg2: vector<2x4xf16>) -> vector<2x4xf16> {
   // expected-error @+1 {{expected 128 warp-wide matrix C elements}}
-  %d = nvgpu.mma.sync (%arg0, %arg1, %arg2) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x4xf16>) -> vector<2x4xf16>    
+  %d = nvgpu.mma.sync (%arg0, %arg1, %arg2) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x4xf16>) -> vector<2x4xf16>
   return %d : vector<2x4xf16>
 }
 // -----
 
 func.func @m16n8k16_fp16_vector_shape_a_extended(%arg0: vector<2x4xf16>, %arg1: vector<2x2xf16>, %arg2: vector<2x2xf16>) -> vector<2x2xf16> {
   // expected-error @+1 {{expected matrix A to be shaped (4 x 2)}}
-  %d = nvgpu.mma.sync (%arg0, %arg1, %arg2) {mmaShape = [16, 8, 16]} : (vector<2x4xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>    
+  %d = nvgpu.mma.sync (%arg0, %arg1, %arg2) {mmaShape = [16, 8, 16]} : (vector<2x4xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
   return %d : vector<2x2xf16>
 }
 // -----
 
 func.func @m16n8k16_fp16_tf32Enabled(%arg0: vector<4x2xf16>, %arg1: vector<2x2xf16>, %arg2: vector<2x2xf16>) -> vector<2x2xf16> {
   // expected-error @+1 {{expected tf32 tensor cores only for F32 operands}}
-  %d = nvgpu.mma.sync (%arg0, %arg1, %arg2) {mmaShape = [16, 8, 16], tf32Enabled} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>    
+  %d = nvgpu.mma.sync (%arg0, %arg1, %arg2) {mmaShape = [16, 8, 16], tf32Enabled} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
   return %d : vector<2x2xf16>
 }
 // -----
 
 func.func @m16n8k8_fp32_vector_shape_a(%arg0: vector<4x2xf32>, %arg1: vector<2x1xf32>, %arg2: vector<2x2xf32>) -> vector<2x2xf32> {
   // expected-error @+1 {{expected 128 warp-wide matrix A elements}}
-  %d = nvgpu.mma.sync (%arg0, %arg1, %arg2) {mmaShape = [16, 8, 8]} : (vector<4x2xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>    
+  %d = nvgpu.mma.sync (%arg0, %arg1, %arg2) {mmaShape = [16, 8, 8]} : (vector<4x2xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
   return %d : vector<2x2xf32>
 }
 // -----
 
 func.func @m16n8k8_fp32_vector_shape_a_extended(%arg0: vector<1x4xf32>, %arg1: vector<2x1xf32>, %arg2: vector<2x2xf32>) -> vector<2x2xf32> {
   // expected-error @+1 {{expected matrix A to be shaped (4 x 1)}}
-  %d = nvgpu.mma.sync (%arg0, %arg1, %arg2) {mmaShape = [16, 8, 8]} : (vector<1x4xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>    
+  %d = nvgpu.mma.sync (%arg0, %arg1, %arg2) {mmaShape = [16, 8, 8]} : (vector<1x4xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
   return %d : vector<2x2xf32>
 }
 // -----
 
 func.func @m8n8k4_fp64_vector_shape_a(%arg0: vector<1x2xf64>, %arg1: vector<1x1xf64>, %arg2: vector<1x2xf64>) -> vector<1x2xf64> {
   // expected-error @+1 {{expected 32 warp-wide matrix A elements}}
-  %d = nvgpu.mma.sync (%arg0, %arg1, %arg2) {mmaShape = [8, 8, 4]} : (vector<1x2xf64>, vector<1x1xf64>, vector<1x2xf64>) -> vector<1x2xf64>    
+  %d = nvgpu.mma.sync (%arg0, %arg1, %arg2) {mmaShape = [8, 8, 4]} : (vector<1x2xf64>, vector<1x1xf64>, vector<1x2xf64>) -> vector<1x2xf64>
   return %d : vector<1x2xf64>
 }
 // -----
 
 func.func @m8n8k4_fp64_vector_shape_c_extended(%arg0: vector<1x1xf64>, %arg1: vector<1x1xf64>, %arg2: vector<2x1xf64>) -> vector<2x1xf64> {
   // expected-error @+1 {{expected matrix C to be shaped (1 x 2)}}
-  %d = nvgpu.mma.sync (%arg0, %arg1, %arg2) {mmaShape = [8, 8, 4]} : (vector<1x1xf64>, vector<1x1xf64>, vector<2x1xf64>) -> vector<2x1xf64>    
+  %d = nvgpu.mma.sync (%arg0, %arg1, %arg2) {mmaShape = [8, 8, 4]} : (vector<1x1xf64>, vector<1x1xf64>, vector<2x1xf64>) -> vector<2x1xf64>
   return %d : vector<2x1xf64>
 }
 // -----
 
 func.func @m16n8k32_int8_vector_shape_b(%arg0: vector<4x4xi8>, %arg1: vector<4x4xi8>, %arg2: vector<2x2xi32>) -> vector<2x2xi32> {
   // expected-error @+1 {{expected 256 warp-wide matrix B elements}}
   %d = nvgpu.mma.sync (%arg0, %arg1, %arg2) {mmaShape = [16, 8, 32]} : (vector<4x4xi8>, vector<4x4xi8>, vector<2x2xi32>) -> vector<2x2xi32>
   return %d : vector<2x2xi32>

mlir/test/Dialect/NVGPU/mma-sync-f32-to-tf32.mlir

 // RUN: mlir-opt %s -test-nvgpu-mmasync-f32-to-tf32-patterns="precision=tf32" -split-input-file | FileCheck %s
 
 // CHECK-LABEL: m16n8k4_tf32
-func.func @m16n8k4_tf32(%arg0: vector<2x1xf32>, %arg1: vector<1x1xf32>, %arg2: vector<2x2xf32>) -> vector<2x2xf32> {  
+func.func @m16n8k4_tf32(%arg0: vector<2x1xf32>, %arg1: vector<1x1xf32>, %arg2: vector<2x2xf32>) -> vector<2x2xf32> {
   // CHECK: nvgpu.mma.sync
   // CHECK-SAME: tf32Enabled
-  %d = nvgpu.mma.sync (%arg0, %arg1, %arg2) {mmaShape = [16, 8, 4]} : (vector<2x1xf32>, vector<1x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>  
+  %d = nvgpu.mma.sync (%arg0, %arg1, %arg2) {mmaShape = [16, 8, 4]} : (vector<2x1xf32>, vector<1x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
   return %d : vector<2x2xf32>
 }
 
 // -----
 
 // CHECK-LABEL: m16n8k8_tf32
 func.func @m16n8k8_tf32(%arg0: vector<4x1xf32>, %arg1: vector<2x1xf32>, %arg2: vector<2x2xf32>) -> vector<2x2xf32> {
   // CHECK: nvgpu.mma.sync
   // CHECK-SAME: tf32Enabled
-  %d = nvgpu.mma.sync (%arg0, %arg1, %arg2) {mmaShape = [16, 8, 8]} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>    
+  %d = nvgpu.mma.sync (%arg0, %arg1, %arg2) {mmaShape = [16, 8, 8]} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
   return %d : vector<2x2xf32>
 }
 // -----
 
 // Negative test for non f32 case.
 // CHECK-LABEL: mma_sync_f16
 //   CHECK-NOT: tf32Enabled
 //       CHECK: return
 func.func @mma_sync_f16(%arg0: vector<4x2xf16>, %arg1: vector<2x2xf16>, %arg2: vector<2x2xf16>) -> vector<2x2xf16> {
   %d = nvgpu.mma.sync (%arg0, %arg1, %arg2) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
   return %d : vector<2x2xf16>
 }

mlir/test/Dialect/NVGPU/mma-sync-f32-to-tf32x3.mlir

 // RUN: mlir-opt %s -test-nvgpu-mmasync-f32-to-tf32-patterns="precision=tf32x3" -split-input-file | FileCheck %s
 
 // CHECK-LABEL: m16n8k4_tf32
-func.func @m16n8k4_tf32(%arg0: vector<2x1xf32>, %arg1: vector<1x1xf32>, %arg2: vector<2x2xf32>) -> vector<2x2xf32> {  
+func.func @m16n8k4_tf32(%arg0: vector<2x1xf32>, %arg1: vector<1x1xf32>, %arg2: vector<2x2xf32>) -> vector<2x2xf32> {
   // expected-error @+1 {{TF32x3 is not supported at the moment for nvgpu.mma.sync on f32 datatype}}
-  %d = nvgpu.mma.sync (%arg0, %arg1, %arg2) {mmaShape = [16, 8, 4]} : (vector<2x1xf32>, vector<1x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>  
+  %d = nvgpu.mma.sync (%arg0, %arg1, %arg2) {mmaShape = [16, 8, 4]} : (vector<2x1xf32>, vector<1x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
   return %d : vector<2x2xf32>
 }
 
 // -----
 
 // CHECK-LABEL: m16n8k8_tf32
 func.func @m16n8k8_tf32(%arg0: vector<4x1xf32>, %arg1: vector<2x1xf32>, %arg2: vector<2x2xf32>) -> vector<2x2xf32> {
   // expected-error @+1 {{TF32x3 is not supported at the moment for nvgpu.mma.sync on f32 datatype}}
-  %d = nvgpu.mma.sync (%arg0, %arg1, %arg2) {mmaShape = [16, 8, 8]} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>    
+  %d = nvgpu.mma.sync (%arg0, %arg1, %arg2) {mmaShape = [16, 8, 8]} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
   return %d : vector<2x2xf32>
 }
 // -----

mlir/test/Dialect/NVGPU/optimize-shared-memory.mlir

func.func @optimize_128x32xf16_32x128xf16(%arg0: memref<128x128xf16>,
   // CHECK: [[shmB:%.+]] = memref.alloc
   %shm = memref.alloc() : memref<128x32xf16, 3>
   %shmB = memref.alloc() : memref<32x128xf16, 3>
 
   // CHECK: [[c6:%.+]] = arith.constant 6 : index
   // CHECK: [[src_bits:%.+]] = arith.andi [[stRow]], [[c6]]
   // CHECK: [[c2:%.+]] = arith.constant 2 : index
   // CHECK: [[xorBits:%.+]] = arith.shli [[src_bits]], [[c2]]
-  // CHECK: [[stColPerm:%.+]] = arith.xori [[stCol]], [[xorBits]] 
+  // CHECK: [[stColPerm:%.+]] = arith.xori [[stCol]], [[xorBits]]
   // CHECK: nvgpu.device_async_copy [[arg0]][[[ldRow]], [[ldCol]]], [[shm]][[[stRow]], [[stColPerm]]]
   %0 = nvgpu.device_async_copy %arg0[%ldRow, %ldCol], %shm[%stRow, %stCol], 8
       : memref<128x128xf16> to memref<128x32xf16, 3>
   %1 = nvgpu.device_async_create_group %0
   nvgpu.device_async_wait %1 { numGroups = 1 : i32}
 
   // CHECK: [[c6:%.+]] = arith.constant 6 : index
   // CHECK: [[srcBits:%.+]] = arith.andi [[fragRow]], [[c6]]
   // CHECK: [[c2:%.+]] = arith.constant 2 : index
   // CHECK: [[xorBits:%.+]] = arith.shli [[srcBits]], [[c2]]
   // CHECK: [[fragColPerm:%.+]] = arith.xori [[fragCol]], [[xorBits]]
   // CHECK: nvgpu.ldmatrix [[shm]][[[fragRow]], [[fragColPerm]]]
   %mat = nvgpu.ldmatrix %shm[%fragRow, %fragCol] {numTiles = 4 : i32, transpose = false}
       : memref<128x32xf16, 3> -> vector<4x2xf16>
 
   // CHECK: [[c15:%.+]] = arith.constant 15 : index
   // CHECK: [[src_bits:%.+]] = arith.andi [[stRow]], [[c15]]
   // CHECK: [[c3:%.+]] = arith.constant 3 : index
   // CHECK: [[xorBits:%.+]] = arith.shli [[src_bits]], [[c3]]
-  // CHECK: [[stColPerm:%.+]] = arith.xori [[stCol]], [[xorBits]]  
+  // CHECK: [[stColPerm:%.+]] = arith.xori [[stCol]], [[xorBits]]
   // CHECK: nvgpu.device_async_copy [[arg0]][[[ldRow]], [[ldCol]]], [[shmB]][[[stRow]], [[stColPerm]]]
   %2 = nvgpu.device_async_copy %arg0[%ldRow, %ldCol], %shmB[%stRow, %stCol], 8
       : memref<128x128xf16> to memref<32x128xf16, 3>
   %3 = nvgpu.device_async_create_group %0
   nvgpu.device_async_wait %1 { numGroups = 1 : i32}
 
   // CHECK: [[c15:%.+]] = arith.constant 15 : index
   // CHECK: [[srcBits:%.+]] = arith.andi [[fragRow]], [[c15]]
   // CHECK: [[c3:%.+]] = arith.constant 3 : index
   // CHECK: [[xorBits:%.+]] = arith.shli [[srcBits]], [[c3]]
   // CHECK: [[fragColPerm:%.+]] = arith.xori [[fragCol]], [[xorBits]]
-  // CHECK: nvgpu.ldmatrix [[shmB]][[[fragRow]], [[fragColPerm]]]      
+  // CHECK: nvgpu.ldmatrix [[shmB]][[[fragRow]], [[fragColPerm]]]
   %matB = nvgpu.ldmatrix %shmB[%fragRow, %fragCol] {numTiles = 4 : i32, transpose = false}
       : memref<32x128xf16, 3> -> vector<4x2xf16>
 
   return %mat, %matB: vector<4x2xf16>, vector<4x2xf16>
 }
 
 
 // -----
 
 // CHECK: @optimize_64x16xf32_16x64xf32([[arg0:%.+]]: memref<{{.*}}>, [[ldRow:%.+]]: index, [[ldCol:%.+]]: index, [[stRow:%.+]]: index, [[stCol:%.+]]: index, [[fragRow:%.+]]: index, [[fragCol:%.+]]: index)
 func.func @optimize_64x16xf32_16x64xf32(%arg0: memref<128x128xf32>,
                                %ldRow: index, %ldCol: index,
                                %stRow: index, %stCol: index,
                                %fragRow: index, %fragCol :index)
                                 -> (vector<4x1xf32>, vector<4x1xf32>, f32, vector<4xf32>, f32) {
   // CHECK: [[shm:%.+]] = memref.alloc
   // CHECK: [[shmB:%.+]] = memref.alloc
   %shm = memref.alloc() : memref<64x16xf32, 3>
   %shmB = memref.alloc() : memref<16x64xf32, 3>
-  
   // CHECK: [[c6:%.+]] = arith.constant 6 : index
   // CHECK: [[src_bits:%.+]] = arith.andi [[stRow]], [[c6]]
   // CHECK: [[c1:%.+]] = arith.constant 1 : index
   // CHECK: [[xorBits:%.+]] = arith.shli [[src_bits]], [[c1]]
-  // CHECK: [[stColPerm:%.+]] = arith.xori [[stCol]], [[xorBits]]  
+  // CHECK: [[stColPerm:%.+]] = arith.xori [[stCol]], [[xorBits]]
   // CHECK: nvgpu.device_async_copy [[arg0]][[[ldRow]], [[ldCol]]], [[shm]][[[stRow]], [[stColPerm]]]
   %0 = nvgpu.device_async_copy %arg0[%ldRow, %ldCol], %shm[%stRow, %stCol], 8
       : memref<128x128xf32> to memref<64x16xf32, 3>
   %1 = nvgpu.device_async_create_group %0
   nvgpu.device_async_wait %1 { numGroups = 1 : i32}
 
   // CHECK: [[c6:%.+]] = arith.constant 6 : index
   // CHECK: [[srcBits:%.+]] = arith.andi [[fragRow]], [[c6]]
   // CHECK: [[c1:%.+]] = arith.constant 1 : index
   // CHECK: [[xorBits:%.+]] = arith.shli [[srcBits]], [[c1]]
   // CHECK: [[fragColPerm:%.+]] = arith.xori [[fragCol]], [[xorBits]]
-  // CHECK: nvgpu.ldmatrix [[shm]][[[fragRow]], [[fragColPerm]]]  
+  // CHECK: nvgpu.ldmatrix [[shm]][[[fragRow]], [[fragColPerm]]]
   %mat = nvgpu.ldmatrix %shm[%fragRow, %fragCol] {numTiles = 4 : i32, transpose = false}
       : memref<64x16xf32, 3> -> vector<4x1xf32>
 
   // CHECK: [[c6:%.+]] = arith.constant 6 : index
   // CHECK: [[srcBits:%.+]] = arith.andi [[fragRow]], [[c6]]
   // CHECK: [[c1:%.+]] = arith.constant 1 : index
   // CHECK: [[xorBits:%.+]] = arith.shli [[srcBits]], [[c1]]
   // CHECK: [[fragColPerm:%.+]] = arith.xori [[fragCol]], [[xorBits]]
func.func @optimize_64x16xf32_16x64xf32(%arg0: memref<128x128xf32>,
   %elem2 = vector.load %shm[%fragRow, %fragCol] : memref<64x16xf32, 3>, vector<4xf32>
 
   // CHECK: [[c6:%.+]] = arith.constant 6 : index
   // CHECK: [[srcBits:%.+]] = arith.andi [[fragRow]], [[c6]]
   // CHECK: [[c1:%.+]] = arith.constant 1 : index
   // CHECK: [[xorBits:%.+]] = arith.shli [[srcBits]], [[c1]]
   // CHECK: [[fragColPerm:%.+]] = arith.xori [[fragCol]], [[xorBits]]
   // CHECK: vector.store %{{.+}}, [[shm]][[[fragRow]], [[fragColPerm]]]
-  vector.store %elem2, %shm[%fragRow, %fragCol] : memref<64x16xf32, 3>, vector<4xf32>  
+  vector.store %elem2, %shm[%fragRow, %fragCol] : memref<64x16xf32, 3>, vector<4xf32>
 
   // CHECK: [[c6:%.+]] = arith.constant 6 : index
   // CHECK: [[srcBits:%.+]] = arith.andi [[fragRow]], [[c6]]
   // CHECK: [[c1:%.+]] = arith.constant 1 : index
   // CHECK: [[xorBits:%.+]] = arith.shli [[srcBits]], [[c1]]
   // CHECK: [[fragColPerm:%.+]] = arith.xori [[fragCol]], [[xorBits]]
   // CHECK: memref.store %{{.+}}, [[shm]][[[fragRow]], [[fragColPerm]]]
   memref.store %elem, %shm[%fragRow, %fragCol] : memref<64x16xf32, 3>
func.func @optimize_64x16xf32_16x64xf32(%arg0: memref<128x128xf32>,
   %3 = nvgpu.device_async_create_group %0
   nvgpu.device_async_wait %1 { numGroups = 1 : i32}
 
   // CHECK: [[c15:%.+]] = arith.constant 15 : index
   // CHECK: [[srcBits:%.+]] = arith.andi [[fragRow]], [[c15]]
   // CHECK: [[c2:%.+]] = arith.constant 2 : index
   // CHECK: [[xorBits:%.+]] = arith.shli [[srcBits]], [[c2]]
   // CHECK: [[fragColPerm:%.+]] = arith.xori [[fragCol]], [[xorBits]]
-  // CHECK: nvgpu.ldmatrix [[shmB]][[[fragRow]], [[fragColPerm]]]  
+  // CHECK: nvgpu.ldmatrix [[shmB]][[[fragRow]], [[fragColPerm]]]
   %matB = nvgpu.ldmatrix %shmB[%fragRow, %fragCol] {numTiles = 4 : i32, transpose = false}
       : memref<16x64xf32, 3> -> vector<4x1xf32>
 
   // CHECK: [[c15:%.+]] = arith.constant 15 : index
   // CHECK: [[srcBits:%.+]] = arith.andi [[fragRow]], [[c15]]
   // CHECK: [[c2:%.+]] = arith.constant 2 : index
   // CHECK: [[xorBits:%.+]] = arith.shli [[srcBits]], [[c2]]
   // CHECK: [[fragColPerm:%.+]] = arith.xori [[fragCol]], [[xorBits]]
   // CHECK: memref.load [[shmB]][[[fragRow]], [[fragColPerm]]]
-  %elemB = memref.load %shmB[%fragRow, %fragCol] : memref<16x64xf32, 3>  
+  %elemB = memref.load %shmB[%fragRow, %fragCol] : memref<16x64xf32, 3>
 
   return %mat, %matB, %elem, %elem2, %elemB: vector<4x1xf32>, vector<4x1xf32>, f32, vector<4xf32>, f32
 }
 
 
 // -----
 
 // Small column edge cases
 
 // CHECK: @small_column_size_f64([[arg0:%.+]]: memref<{{.*}}>, [[ldRow:%.+]]: index, [[ldCol:%.+]]: index, [[stRow:%.+]]: index, [[stCol:%.+]]: index, [[fragRow:%.+]]: index, [[fragCol:%.+]]: index)
 func.func @small_column_size_f64(%arg0: memref<32x32xf64>,
                                %ldRow: index, %ldCol: index,
                                %stRow: index, %stCol: index,
                                %fragRow: index, %fragCol :index)
                                 -> f64 {
   // CHECK: [[shm:%.+]] = memref.alloc
   %shm = memref.alloc() : memref<32x4xf64, 3>
 
   // CHECK: [[c4:%.+]] = arith.constant 4 : index
   // CHECK: [[src_bits:%.+]] = arith.andi [[stRow]], [[c4]]
   // CHECK: [[c1:%.+]] = arith.constant 1 : index
   // CHECK: [[xorBits:%.+]] = arith.shrui [[src_bits]], [[c1]]
-  // CHECK: [[stColPerm:%.+]] = arith.xori [[stCol]], [[xorBits]] 
+  // CHECK: [[stColPerm:%.+]] = arith.xori [[stCol]], [[xorBits]]
   // CHECK: nvgpu.device_async_copy [[arg0]][[[ldRow]], [[ldCol]]], [[shm]][[[stRow]], [[stColPerm]]]
   %0 = nvgpu.device_async_copy %arg0[%ldRow, %ldCol], %shm[%stRow, %stCol], 8
       : memref<32x32xf64> to memref<32x4xf64, 3>
   %1 = nvgpu.device_async_create_group %0
   nvgpu.device_async_wait %1 { numGroups = 1 : i32}
 
   // CHECK: [[c6:%.+]] = arith.constant 4 : index
   // CHECK: [[srcBits:%.+]] = arith.andi [[fragRow]], [[c6]]

mlir/test/Dialect/OpenMP/canonicalize.mlir

 func.func @parallel_maybe_side_effects(%a: i32, %b: i32) {
   omp.parallel {
     func.call @foo() : () -> ()
     omp.terminator
   }
   return
 }
 
-func.func private @foo() -> () 
+func.func private @foo() -> ()
 
 // CHECK: omp.parallel
 // CHECK: func.call @foo() : () -> ()
 // CHECK: omp.terminator

mlir/test/Dialect/PDL/invalid.mlir

 //===----------------------------------------------------------------------===//
 // pdl::RangeOp
 //===----------------------------------------------------------------------===//
 
 pdl.pattern : benefit(1) {
   %operand = pdl.operand
   %resultType = pdl.type
   %root = pdl.operation "baz.op"(%operand : !pdl.value) -> (%resultType : !pdl.type)
-  
   rewrite %root {
     // expected-error @below {{expected operand to have element type '!pdl.value', but got '!pdl.type'}}
     %range = pdl.range %operand, %resultType : !pdl.value, !pdl.type
   }
 }
 
 // -----
 

mlir/test/Dialect/PDL/ops.mlir

 
 // Check that we don't treat the trailing location of a pdl.attribute as the
 // attribute value.
 
 pdl.pattern @attribute_with_loc : benefit(1) {
   // CHECK-GENERIC: "pdl.attribute"
   // CHECK-GENERIC-NOT: value = loc
   %attr = attribute loc("bar")
-  
   %root = operation {"attribute" = %attr}
   rewrite %root with "rewriter"
 }

mlir/test/Dialect/SCF/foreach-thread-canonicalization.mlir

func.func @reduce() {
   scf.foreach_thread (%arg0) in (%c2) {
     %7 = affine.min affine_map<(d0) -> (d0 * -64 + 128, 64)>(%arg0)
     %8 = affine.max affine_map<(d0) -> (0, d0)>(%7)
     %9 = affine.apply affine_map<(d0) -> (d0 * 64)>(%arg0)
     %10 = affine.min affine_map<(d0, d1) -> (d1 * -64 + 128, d0)>(%8, %arg0)
 
     // CHECK: memref.subview %{{.*}}[%{{.*}}, 0] [%[[C64]], 384] [1, 1] : memref<128x384xf32> to memref<?x384xf32, {{.*}}>
     // CHECK: memref.subview %{{.*}}[%{{.*}}] [%[[C64]]] [1] : memref<128xf32> to memref<?xf32, {{.*}}>
-    %11 = memref.subview %0[%9, 0] [%10, 384] [1, 1] : 
+    %11 = memref.subview %0[%9, 0] [%10, 384] [1, 1] :
       memref<128x384xf32> to memref<?x384xf32, affine_map<(d0, d1)[s0] -> (d0 * 384 + s0 + d1)>>
-    %12 = memref.subview %2[%9] [%10] [1] : 
+    %12 = memref.subview %2[%9] [%10] [1] :
       memref<128xf32> to memref<?xf32, affine_map<(d0)[s0] -> (d0 + s0)>>
 
     // CHECK: linalg.generic {{.*}} ins(%{{.*}} : memref<?x384xf32, {{.*}}>) outs(%{{.*}} : memref<?xf32, {{.*}}>)
-    linalg.generic {indexing_maps = [affine_map<(d0, d1) -> (d0, d1)>, 
-                                      affine_map<(d0, d1) -> (d0)>], 
-                     iterator_types = ["parallel", "reduction"]} 
-      ins(%11 : memref<?x384xf32, affine_map<(d0, d1)[s0] -> (d0 * 384 + s0 + d1)>>) 
+    linalg.generic {indexing_maps = [affine_map<(d0, d1) -> (d0, d1)>,
+                                      affine_map<(d0, d1) -> (d0)>],
+                     iterator_types = ["parallel", "reduction"]}
+      ins(%11 : memref<?x384xf32, affine_map<(d0, d1)[s0] -> (d0 * 384 + s0 + d1)>>)
       outs(%12 : memref<?xf32, affine_map<(d0)[s0] -> (d0 + s0)>>) {
         ^bb0(%arg1: f32, %arg2: f32):
           %14 = arith.addf %arg1, %arg2 : f32
           linalg.yield %14 : f32
       }
   }
   return
 }

mlir/test/Dialect/SCF/loop-pipelining.mlir

 // -----
 
 // CHECK-LABEL: simple_pipeline_region(
 //  CHECK-SAME:   %[[A:.*]]: memref<?xf32>, %[[R:.*]]: memref<?xf32>) {
 //   CHECK-DAG:   %[[C0:.*]] = arith.constant 0 : index
 //   CHECK-DAG:   %[[C1:.*]] = arith.constant 1 : index
 //   CHECK-DAG:   %[[C3:.*]] = arith.constant 3 : index
 // Prologue:
-//       CHECK:   %[[L0:.*]] = scf.execute_region 
+//       CHECK:   %[[L0:.*]] = scf.execute_region
 //  CHECK-NEXT:     memref.load %[[A]][%[[C0]]] : memref<?xf32>
 // Kernel:
 //       CHECK:   %[[L1:.*]] = scf.for %[[IV:.*]] = %[[C0]] to %[[C3]]
 //  CHECK-SAME:     step %[[C1]] iter_args(%[[LARG:.*]] = %[[L0]]) -> (f32) {
 //  CHECK-NEXT:     %[[ADD0:.*]] = scf.execute_region
 //  CHECK-NEXT:       arith.addf %[[LARG]], %{{.*}} : f32
 //       CHECK:     memref.store %[[ADD0]], %[[R]][%[[IV]]] : memref<?xf32>
 //  CHECK-NEXT:     %[[IV1:.*]] = arith.addi %[[IV]], %[[C1]] : index

 //  CHECK-NEXT:     %[[L3:.*]] = memref.load %[[A]][%[[IV3]]] : memref<?xf32>
 //  CHECK-NEXT:     scf.yield %[[LA2]], %[[L3]], %[[ADD2]], %[[MUL1]] : f32, f32, f32, f32
 //  CHECK-NEXT:   }
 // Epilogue:
 //  CHECK-NEXT:   %[[ADD3:.*]] = arith.addf %[[LR]]#1, %{{.*}} : f32
 //  CHECK-NEXT:   %[[MUL2:.*]] = scf.execute_region
 // arith.mulf %[[LR]]#2, %[[LR]]#0 : f32
 //       CHECK:   memref.store %[[LR]]#3, %[[R]][%[[C7]]] : memref<?xf32>
-//  CHECK-NEXT:   %[[MUL3:.*]] = scf.execute_region 
+//  CHECK-NEXT:   %[[MUL3:.*]] = scf.execute_region
 /// %[[ADD3]], %[[LR]]#1 : f32
 //       CHECK:   memref.store %[[MUL2]], %[[R]][%[[C8]]] : memref<?xf32>
 //  CHECK-NEXT:   memref.store %[[MUL3]], %[[R]][%[[C9]]] : memref<?xf32>
 
 func.func @region_multiple_uses(%A: memref<?xf32>, %result: memref<?xf32>) {
   %c0 = arith.constant 0 : index
   %c1 = arith.constant 1 : index
   %c10 = arith.constant 10 : index
func.func @region_backedge_different_stage(%A: memref<?xf32>) -> f32 {
   %c0 = arith.constant 0 : index
   %c1 = arith.constant 1 : index
   %c4 = arith.constant 4 : index
   %cf = arith.constant 1.0 : f32
   %r = scf.for %i0 = %c0 to %c4 step %c1 iter_args(%arg0 = %cf) -> (f32) {
     %A_elem = scf.execute_region -> f32 {
       %A_elem1 = memref.load %A[%i0] : memref<?xf32>
       scf.yield %A_elem1 : f32
-    } { __test_pipelining_stage__ = 0, __test_pipelining_op_order__ = 2 }    
+    } { __test_pipelining_stage__ = 0, __test_pipelining_op_order__ = 2 }
     %A1_elem = scf.execute_region -> f32 {
       %inner = arith.addf %A_elem, %arg0 : f32
-      scf.yield %inner : f32 
+      scf.yield %inner : f32
     }  { __test_pipelining_stage__ = 1, __test_pipelining_op_order__ = 1 }
     %A2_elem = arith.mulf %cf, %A1_elem { __test_pipelining_stage__ = 2, __test_pipelining_op_order__ = 0 } : f32
     scf.yield %A2_elem : f32
   }  { __test_pipelining_loop__ }
   return %r : f32
 }
 
 

 // -----
 
 // CHECK: @pipeline_op_with_region(%[[ARG0:.+]]: memref<?xf32>, %[[ARG1:.+]]: memref<?xf32>, %[[ARG2:.+]]: memref<?xf32>) {
 // CHECK:   %[[C0:.+]] = arith.constant 0 :
 // CHECK:   %[[C3:.+]] = arith.constant 3 :
 // CHECK:   %[[C1:.+]] = arith.constant 1 :
 // CHECK:   %[[APRO:.+]] = memref.alloc() :
 // CHECK:   %[[BPRO:.+]] = memref.alloc() :
-// CHECK:   %[[ASV0:.+]] = memref.subview %[[ARG0]][%[[C0]]] [8] [1] : 
-// CHECK:   %[[BSV0:.+]] = memref.subview %[[ARG1]][%[[C0]]] [8] [1] : 
+// CHECK:   %[[ASV0:.+]] = memref.subview %[[ARG0]][%[[C0]]] [8] [1] :
+// CHECK:   %[[BSV0:.+]] = memref.subview %[[ARG1]][%[[C0]]] [8] [1] :
 
 // Prologue:
 // CHECK:   %[[PAV0:.+]] = memref.subview %[[APRO]][%[[C0]], 0] [1, 8] [1, 1] :
 // CHECK:   %[[PBV0:.+]] = memref.subview %[[BPRO]][%[[C0]], 0] [1, 8] [1, 1] :
-// CHECK:   memref.copy %[[ASV0]], %[[PAV0]] : 
-// CHECK:   memref.copy %[[BSV0]], %[[PBV0]] : 
+// CHECK:   memref.copy %[[ASV0]], %[[PAV0]] :
+// CHECK:   memref.copy %[[BSV0]], %[[PBV0]] :
 
 // Kernel:
-// CHECK:   %[[R:.+]]:2 = scf.for %[[IV:.+]] = %[[C0]] to %[[C3]] step %[[C1]] 
+// CHECK:   %[[R:.+]]:2 = scf.for %[[IV:.+]] = %[[C0]] to %[[C3]] step %[[C1]]
 // CHECK-SAME: iter_args(%[[IA:.+]] = %[[PAV0]], %[[IB:.+]] = %[[PBV0:.+]])
 // CHECK:     %[[CV:.+]] = memref.subview %[[ARG2]]
 // CHECK:     linalg.generic
 // CHECK-SAME:  ins(%[[IA]], %[[IB]], %{{.*}} : {{.*}}) outs(%[[CV]] :
-// CHECK:     %[[NEXT:.+]] = arith.addi %[[IV]], %[[C1]] 
+// CHECK:     %[[NEXT:.+]] = arith.addi %[[IV]], %[[C1]]
 // CHECK:     %[[ASV:.+]] = memref.subview %[[ARG0]][%[[NEXT]]] [8] [1] :
 // CHECK:     %[[NEXT:.+]] = arith.addi %[[IV]], %[[C1]] :
 // CHECK:     %[[BSV:.+]] = memref.subview %[[ARG1]][%[[NEXT]]] [8] [1] :
 // CHECK:     %[[NEXT:.+]] = arith.addi %[[IV]], %[[C1]] :
 // CHECK:     %[[BUFIDX:.+]] = affine.apply
-// CHECK:     %[[APROSV:.+]] = memref.subview %[[APRO]][%[[BUFIDX]], 0] [1, 8] [1, 1] : 
-// CHECK:     %[[BPROSV:.+]] = memref.subview %[[BPRO]][%[[BUFIDX]], 0] [1, 8] [1, 1] : 
+// CHECK:     %[[APROSV:.+]] = memref.subview %[[APRO]][%[[BUFIDX]], 0] [1, 8] [1, 1] :
+// CHECK:     %[[BPROSV:.+]] = memref.subview %[[BPRO]][%[[BUFIDX]], 0] [1, 8] [1, 1] :
 // CHECK:     memref.copy %[[ASV]], %[[APROSV]] :
 // CHECK:     memref.copy %[[BSV]], %[[BPROSV]] :
 // CHECK:     scf.yield %[[APROSV]], %[[BPROSV]] :
 // CHECK:   }
 // CHECK:   %[[CV:.+]] = memref.subview %[[ARG2]][%[[C3]]] [8] [1] :
-// CHECK:   linalg.generic 
+// CHECK:   linalg.generic
 // CHECK-SAME: ins(%[[R]]#0, %[[R]]#1, %{{.*}} : {{.*}}) outs(%[[CV]] :
 
 
 #map = affine_map<(d0)[s0]->(d0 + s0)>
 #map1 = affine_map<(d0)->(d0)>
 #map2 = affine_map<(d0)->()>
 #linalg_attrs = {
   indexing_maps = [
       #map1,
       #map1,
       #map2,
-      #map1        
+      #map1
     ],
   iterator_types = ["parallel"],
   __test_pipelining_stage__ = 1,
   __test_pipelining_op_order__ = 2
 }
 func.func @pipeline_op_with_region(%A: memref<?xf32>, %B: memref<?xf32>, %result: memref<?xf32>) {
   %c0 = arith.constant 0 : index
   %c1 = arith.constant 1 : index
   %c4 = arith.constant 4 : index
   %cf = arith.constant 1.0 : f32
   %a_buf = memref.alloc() : memref<2x8xf32>
   %b_buf = memref.alloc() : memref<2x8xf32>
   scf.for %i0 = %c0 to %c4 step %c1 {
-    %A_view = memref.subview %A[%i0][8][1] { __test_pipelining_stage__ = 0, __test_pipelining_op_order__ = 3 } : memref<?xf32> to memref<8xf32, #map>    
+    %A_view = memref.subview %A[%i0][8][1] { __test_pipelining_stage__ = 0, __test_pipelining_op_order__ = 3 } : memref<?xf32> to memref<8xf32, #map>
     %B_view = memref.subview %B[%i0][8][1] { __test_pipelining_stage__ = 0, __test_pipelining_op_order__ = 4 } : memref<?xf32> to memref<8xf32, #map>
     %buf_idx = affine.apply  affine_map<(d0)->(d0 mod 2)> (%i0)[] { __test_pipelining_stage__ = 0, __test_pipelining_op_order__ = 5 }
     %a_buf_view = memref.subview %a_buf[%buf_idx,0][1,8][1,1] { __test_pipelining_stage__ = 0, __test_pipelining_op_order__ = 6 } : memref<2x8xf32> to memref<8xf32, #map>
     %b_buf_view = memref.subview %b_buf[%buf_idx,0][1,8][1,1] { __test_pipelining_stage__ = 0, __test_pipelining_op_order__ = 7 } : memref<2x8xf32> to memref<8xf32, #map>
     memref.copy %A_view , %a_buf_view {__test_pipelining_stage__ = 0, __test_pipelining_op_order__ = 8} : memref<8xf32, #map> to memref<8xf32, #map>
     memref.copy %B_view , %b_buf_view {__test_pipelining_stage__ = 0, __test_pipelining_op_order__ = 9} : memref<8xf32, #map> to memref<8xf32, #map>
     %C_view = memref.subview %result[%i0][8][1] { __test_pipelining_stage__ = 1, __test_pipelining_op_order__ = 0 } : memref<?xf32> to memref<8xf32, #map>
     %scalar = arith.addf %cf, %cf {__test_pipelining_stage__ = 1, __test_pipelining_op_order__ = 1} : f32
     linalg.generic #linalg_attrs ins(%a_buf_view, %b_buf_view, %scalar : memref<8xf32, #map>, memref<8xf32, #map>, f32)
       outs(%C_view: memref<8xf32, #map>) {
       ^bb0(%a: f32, %b: f32, %s: f32, %c: f32):
         %add = arith.addf %a, %b : f32
-        %accum = arith.addf %add, %c : f32 
+        %accum = arith.addf %add, %c : f32
         %accum1 = arith.addf %scalar, %accum : f32
-        %accum2 = arith.addf %s, %accum1 : f32        
+        %accum2 = arith.addf %s, %accum1 : f32
         linalg.yield %accum2 : f32
     }
     scf.yield
   }  { __test_pipelining_loop__ }
   return
 }

mlir/test/Dialect/SCF/one-shot-bufferize-analysis.mlir

%4 = scf.foreach_thread (%arg0) in (%c320) shared_outs(%arg1 = %2) -> (tensor<320xf32>) {
     %7 = linalg.fill ins(%cst : f32) outs(%6 : tensor<1xf32>) -> tensor<1xf32>
     // CHECK: linalg.fill {__inplace_operands_attr__ = ["none", "true"]}
     %8 = linalg.fill ins(%cst : f32) outs(%7 : tensor<1xf32>) -> tensor<1xf32>
 
     scf.foreach_thread.perform_concurrently {
       // CHECK: tensor.parallel_insert_slice {{.*}} {__inplace_operands_attr__ = ["true", "true", "none"]}
       tensor.parallel_insert_slice %8 into %arg1[%arg0] [1] [1] : tensor<1xf32> into tensor<320xf32>
     }
-  } 
+  }
   return %4 : tensor<320xf32>
 }
 
 // -----
 
 // CHECK-LABEL: different_repetitive_region_via_alias
 func.func @different_repetitive_region_via_alias(%arg0: tensor<4xf32>,
                                                  %arg1: tensor<4xf32>,

mlir/test/Dialect/SCF/one-shot-bufferize.mlir

 
 // -----
 
 // CHECK-LABEL: func.func @parallel_insert_slice_with_conflict(
 //  CHECK-SAME:     %[[idx:.*]]: index, %[[idx2:.*]]: index,
 //  CHECK-SAME:     %[[arg1:.*]]: memref<?xf32, strided{{.*}}>,
 //  CHECK-SAME:     %[[arg2:.*]]: memref<?xf32, strided{{.*}}>
 func.func @parallel_insert_slice_with_conflict(
-    %idx: index, 
-    %idx2: index, 
+    %idx: index,
+    %idx2: index,
     %arg1: tensor<?xf32> {bufferization.writable = true},
     %arg2: tensor<?xf32> {bufferization.writable = true}) -> (f32, f32)
 {
   %cst = arith.constant 4.200000e+01 : f32
   %c0 = arith.constant 0 : index
   %c1 = arith.constant 1 : index
 
   // The parallel_insert_slice_op bufferizes out-of-place due to a RAW conflict
func.func @scf_while_buffer_type_mismatch(%sz: index, %sz2: index) -> f32 {
   }
   %x = tensor.extract %r[%c1] : tensor<?xf32>
   return %x : f32
 }
 
 // -----
 
 // CHECK-LABEL: func @non_tensor_for_arg
-func.func @non_tensor_for_arg(%A : tensor<?xf32> {bufferization.writable = true}) 
+func.func @non_tensor_for_arg(%A : tensor<?xf32> {bufferization.writable = true})
     -> tensor<?xf32> {
   %c0 = arith.constant 0 : index
   %c1 = arith.constant 1 : index
   %c2 = arith.constant 2.0 : f32
   %c10 = arith.constant 10 : index
   %r1:2 = scf.for %i = %c0 to %c10 step %c1 iter_args(%idx = %c1, %t = %A) -> (index, tensor<?xf32>) {
     %t2 = tensor.insert %c2 into %t[%idx] : tensor<?xf32>
     scf.yield %idx, %t2 : index, tensor<?xf32>
   }
   return %r1#1 : tensor<?xf32>
 }
 
 // -----
 
 // This is a regression test. Just check that the IR bufferizes.
-  
 // CHECK-LABEL: func @buffer_type_of_collapse_shape
 func.func @buffer_type_of_collapse_shape(%arg0: tensor<f64>) {
   %true = arith.constant true
   %0 = scf.while (%arg1 = %arg0) : (tensor<f64>) -> (tensor<f64>) {
     scf.condition(%true) %arg1 : tensor<f64>
   } do {
   ^bb0(%_: tensor<f64>):
     %3 = bufferization.alloc_tensor() : tensor<1xf64>
     %16 = tensor.collapse_shape %3 [] : tensor<1xf64> into tensor<f64>
     scf.yield %16 : tensor<f64>
   }
   return
 }
 
 // -----
 
 // This is a regression test. Just check that the IR bufferizes.
-  
 // CHECK-LABEL: func @non_block_argument_yield
 func.func @non_block_argument_yield() {
-  %true = arith.constant true 
+  %true = arith.constant true
   %0 = bufferization.alloc_tensor() : tensor<i32>
   %1 = scf.while (%arg0 = %0) : (tensor<i32>) -> (tensor<i32>) {
     scf.condition(%true) %arg0 : tensor<i32>
   } do {
   ^bb0(%arg0: tensor<i32>):
     %ret = scf.while (%arg1 = %0) : (tensor<i32>) -> (tensor<i32>) {
       scf.condition(%true) %arg1 : tensor<i32>
     } do {
     ^bb0(%arg7: tensor<i32>):
       scf.yield %0 : tensor<i32>
     }
     scf.yield %ret : tensor<i32>
   }
   return
 }

mlir/test/Dialect/SPIRV/IR/asm-op-interface.mlir

func.func @const() -> () {
   // CHECK: %cst43_i64
   %3 = spirv.Constant 43 : i64
 
   // CHECK: %cst_f32
   %4 = spirv.Constant 0.5 : f32
   // CHECK: %cst_f64
   %5 = spirv.Constant 0.5 : f64
 
-  // CHECK: %cst_vec_3xi32 
+  // CHECK: %cst_vec_3xi32
   %6 = spirv.Constant dense<[1, 2, 3]> : vector<3xi32>
 
   // CHECK: %cst
   %8 = spirv.Constant [dense<3.0> : vector<2xf32>] : !spirv.array<1xvector<2xf32>>
 
   return
 }
 
 // -----
 
 spirv.module Logical GLSL450 {
   spirv.GlobalVariable @global_var : !spirv.ptr<f32, Input>
 
   spirv.func @addressof() -> () "None" {
-    // CHECK: %global_var_addr = spirv.mlir.addressof 
+    // CHECK: %global_var_addr = spirv.mlir.addressof
     %0 = spirv.mlir.addressof @global_var : !spirv.ptr<f32, Input>
     spirv.Return
   }
 }
 

mlir/test/Dialect/SPIRV/IR/group-ops.mlir

func.func @group_broadcast_vector(%value: vector<4xf32>, %localid: vector<3xi32> ) -> vector<4xf32> {
   // CHECK: spirv.GroupBroadcast <Subgroup> %{{.*}}, %{{.*}} : vector<4xf32>, vector<3xi32>
   %0 = spirv.GroupBroadcast <Subgroup> %value, %localid : vector<4xf32>, vector<3xi32>
   return %0: vector<4xf32>
 }
 
 // -----
 
 func.func @group_broadcast_negative_scope(%value: f32, %localid: vector<3xi32> ) -> f32 {
-  // expected-error @+1 {{execution scope must be 'Workgroup' or 'Subgroup'}} 
+  // expected-error @+1 {{execution scope must be 'Workgroup' or 'Subgroup'}}
   %0 = spirv.GroupBroadcast <Device> %value, %localid : f32, vector<3xi32>
   return %0: f32
 }
 
 // -----
 
 func.func @group_broadcast_negative_locid_dtype(%value: f32, %localid: vector<3xf32> ) -> f32 {
   // expected-error @+1 {{operand #1 must be 8/16/32/64-bit integer or vector of 8/16/32/64-bit integer values}}

mlir/test/Dialect/SparseTensor/buffer_rewriting.mlir

 //       CHECK: %[[M:.*]] = scf.if %[[T]] -> (memref<?xf64>) {
 //       CHECK:   %[[P2:.*]] = scf.while (%[[I:.*]] = %[[P1]]) : (index) -> index {
 //       CHECK:     %[[P3:.*]] = arith.muli %[[I]], %[[C2]] : index
 //       CHECK:     %[[T2:.*]] = arith.cmpi ugt, %[[S2]], %[[P3]] : index
 //       CHECK:     scf.condition(%[[T2]]) %[[P3]] : index
 //       CHECK:   } do {
 //       CHECK:     ^bb0(%[[I2:.*]]: index):
 //       CHECK:     scf.yield %[[I2]] : index
-//       CHECK:   }  
+//       CHECK:   }
 //       CHECK:  %[[M2:.*]] = memref.realloc %[[B]](%[[P2]])
 //       CHECK:  scf.yield %[[M2]] : memref<?xf64>
 //       CHECK: } else {
 //       CHECK:  scf.yield %[[B]] : memref<?xf64>
 //       CHECK: }
 //       CHECK: %[[S:.*]] = memref.subview %[[M]]{{\[}}%[[S1]]] {{\[}}%[[D]]] [1]
 //       CHECK: linalg.fill ins(%[[C]] : f64) outs(%[[S]]
 //       CHECK: memref.store %[[S2]], %[[A]]{{\[}}%[[C2]]]

mlir/test/Dialect/SparseTensor/one_shot_bufferize_tensor_copy_insertion.mlir

#trait = {
   indexing_maps = [
     affine_map<(i) -> (i)>,  // A (in)
     affine_map<(i) -> (i)>   // X (out)
   ],
   iterator_types = ["parallel"]
 }
 
 // CHECK-LABEL: func @update_notinplace(
-//  CHECK-SAME:    %[[argb:.*]]: tensor<10xf32> 
+//  CHECK-SAME:    %[[argb:.*]]: tensor<10xf32>
 // CHECK-FUNC-LABEL: func @update_notinplace(
-//  CHECK-FUNC-SAME:    %[[argb:.*]]: tensor<10xf32> 
+//  CHECK-FUNC-SAME:    %[[argb:.*]]: tensor<10xf32>
 func.func @update_notinplace(%argb: tensor<10xf32>, %arga: tensor<10xf32, #SV>)
   -> (tensor<10xf32>, tensor<10xf32>)
 {
   // CHECK: %[[alloc:.*]] = bufferization.alloc_tensor() copy(%[[argb]]) {bufferization.escape = [false]} : tensor<10xf32>
   // CHECK: linalg.generic {{.*}} outs(%[[alloc]]
   // CHECK-FUNC: %[[alloc:.*]] = bufferization.alloc_tensor() copy(%[[argb]]) {bufferization.escape = [true]} : tensor<10xf32>
   // CHECK-FUNC: linalg.generic {{.*}} outs(%[[alloc]]
   %0 = linalg.generic #trait
   ins(%arga: tensor<10xf32, #SV>)
   outs(%argb: tensor<10xf32>) {
     ^bb(%a: f32, %x : f32):
       %up = arith.addf %a, %x : f32
       linalg.yield %up : f32
   } -> tensor<10xf32>
   return %0, %argb : tensor<10xf32>, tensor<10xf32>
 }

mlir/test/Dialect/SparseTensor/rewriting_for_codegen.mlir

 // CHECK:           scf.for  {{.*}} {
 // CHECK:             func.call @outSparseTensorWriterNextF32(%[[W]], %[[C2]], %[[DS]], %[[V]])
 // CHECK:           }
 // CHECK:         }
 // CHECK:         call @delSparseTensorWriter(%[[W]])
 // CHECK:         return
 // CHECK:         }
 func.func @sparse_out( %arg0: tensor<10x20xf32, #CSR>, %arg1: !llvm.ptr<i8>) -> () {
-  sparse_tensor.out %arg0, %arg1 : tensor<10x20xf32, #CSR>, !llvm.ptr<i8> 
+  sparse_tensor.out %arg0, %arg1 : tensor<10x20xf32, #CSR>, !llvm.ptr<i8>
   return
 }

mlir/test/Dialect/SparseTensor/roundtrip.mlir

 }
 
 // -----
 
 #DCSR = #sparse_tensor.encoding<{dimLevelType = ["compressed", "compressed"]}>
 
 // CHECK-LABEL: func @sparse_tensor_foreach(
 //  CHECK-SAME: %[[A0:.*]]: tensor<2x4xf64
-//       CHECK: sparse_tensor.foreach in %[[A0]] : 
+//       CHECK: sparse_tensor.foreach in %[[A0]] :
 //       CHECK:  ^bb0(%arg1: index, %arg2: index, %arg3: f64):
 func.func @sparse_tensor_foreach(%arg0: tensor<2x4xf64, #DCSR>) -> () {
   sparse_tensor.foreach in %arg0 : tensor<2x4xf64, #DCSR> do {
     ^bb0(%1: index, %2: index, %v: f64) :
   }
   return
 }
 
 // -----
 
 #DCSR = #sparse_tensor.encoding<{dimLevelType = ["compressed", "compressed"]}>
 
 // CHECK-LABEL: func @sparse_tensor_foreach(
-//  CHECK-SAME:   %[[A0:.*]]: tensor<2x4xf64, #sparse_tensor.encoding<{{{.*}}}>>, 
+//  CHECK-SAME:   %[[A0:.*]]: tensor<2x4xf64, #sparse_tensor.encoding<{{{.*}}}>>,
 //  CHECK-SAME:   %[[A1:.*]]: f32
 //  CHECK-NEXT:   %[[RET:.*]] = sparse_tensor.foreach in %[[A0]] init(%[[A1]])
 //  CHECK-NEXT:    ^bb0(%[[TMP_1:.*]]: index, %[[TMP_2:.*]]: index, %[[TMP_v:.*]]: f64, %[[TMP_r:.*]]: f32)
 //       CHECK:      sparse_tensor.yield %[[TMP_r]] : f32
 //       CHECK:  }
 func.func @sparse_tensor_foreach(%arg0: tensor<2x4xf64, #DCSR>, %arg1: f32) -> () {
   %ret = sparse_tensor.foreach in %arg0 init(%arg1): tensor<2x4xf64, #DCSR>, f32 -> f32
   do {
-    ^bb0(%1: index, %2: index, %v: f64, %r: f32) : 
+    ^bb0(%1: index, %2: index, %v: f64, %r: f32) :
       sparse_tensor.yield %r : f32
   }
   return
 }
 
 // ----
 
 // CHECK-LABEL: func @sparse_sort_1d0v(

mlir/test/Dialect/SparseTensor/sparse_affine.mlir

indexing_maps = [
     affine_map<(i,j) -> (i,3)>,  // b
     affine_map<(i,j) -> (i,j)>     // x (out)
   ],
   iterator_types = ["parallel","parallel"],
   doc = "x(i,j) += a(2,j) * b(i,3)"
 }
 
 // CHECK-LABEL:   func.func @mul_const_affine_dense_dim_2d(
-// CHECK-SAME:                                             %[[VAL_0:.*]]: tensor<34x16xf64, 
+// CHECK-SAME:                                             %[[VAL_0:.*]]: tensor<34x16xf64,
 // CHECK-SAME:                                             %[[VAL_1:.*]]: tensor<32x19xf64, #sparse_tensor.encoding<{{{.*}}}>>,
 // CHECK-SAME:                                             %[[VAL_2:.*]]: tensor<32x16xf64>) -> tensor<32x16xf64> {
 // CHECK-DAG:       %[[VAL_3:.*]] = arith.constant 19 : index
 // CHECK-DAG:       %[[VAL_4:.*]] = arith.constant 2 : index
 // CHECK-DAG:       %[[VAL_5:.*]] = arith.constant 0 : index
 // CHECK-DAG:       %[[VAL_6:.*]] = arith.constant 1 : index
 // CHECK-DAG:       %[[VAL_7:.*]] = arith.constant 3 : index
 // CHECK:           %[[VAL_8:.*]] = sparse_tensor.pointers %[[VAL_0]] {dimension = 1 : index} : tensor<34x16xf64, #sparse_tensor.encoding<{{{.*}}}>> to memref<?xindex>

 // CHECK:             %[[VAL_23:.*]] = memref.load %[[VAL_8]]{{\[}}%[[VAL_7]]] : memref<?xindex>
 // CHECK:             scf.for %[[VAL_24:.*]] = %[[VAL_22]] to %[[VAL_23]] step %[[VAL_6]] {
 // CHECK:               %[[VAL_25:.*]] = memref.load %[[VAL_9]]{{\[}}%[[VAL_24]]] : memref<?xindex>
 // CHECK:               %[[VAL_26:.*]] = memref.load %[[VAL_14]]{{\[}}%[[VAL_18]], %[[VAL_25]]] : memref<32x16xf64>
 // CHECK:               %[[VAL_27:.*]] = memref.load %[[VAL_10]]{{\[}}%[[VAL_24]]] : memref<?xf64>
 // CHECK:               %[[VAL_28:.*]] = arith.mulf %[[VAL_27]], %[[VAL_21]] : f64
 // CHECK:               %[[VAL_29:.*]] = arith.addf %[[VAL_26]], %[[VAL_28]] : f64
 // CHECK:               memref.store %[[VAL_29]], %[[VAL_14]]{{\[}}%[[VAL_18]], %[[VAL_25]]] : memref<32x16xf64>
-// CHECK:             } 
-// CHECK:           } 
+// CHECK:             }
+// CHECK:           }
 // CHECK:           %[[VAL_30:.*]] = bufferization.to_tensor %[[VAL_14]] : memref<32x16xf64>
 // CHECK:           return %[[VAL_30]] : tensor<32x16xf64>
 // CHECK:         }
 func.func @mul_const_affine_dense_dim_2d(%arga: tensor<34x16xf64, #CSR>,
                                          %argb: tensor<32x19xf64, #Row>,
                                          %argx: tensor<32x16xf64>) -> tensor<32x16xf64> {
   %0 = linalg.generic #trait5
      ins(%arga, %argb: tensor<34x16xf64, #CSR>, tensor<32x19xf64, #Row>)

mlir/test/Dialect/SparseTensor/sparse_concat.mlir

 func.func @concat_mix_dense_perm_dim1(%arg0: tensor<4x2xf64>, %arg1: tensor<4x3xf64, #SparseMatrix_P>) -> tensor<4x5xf64> {
   %0 = sparse_tensor.concatenate %arg0, %arg1 {dimension = 1 : index}
        : tensor<4x2xf64>, tensor<4x3xf64, #SparseMatrix_P> to tensor<4x5xf64>
   return %0 : tensor<4x5xf64>
 }
 
 // CHECK-LABEL: func.func @concat_mix_dense_perm_dim1_dyn(
 // CHECK-SAME:      %[[TMP_arg0:.*]]: tensor<3x2xf64>,
-// CHECK-SAME:      %[[TMP_arg1:.*]]: !llvm.ptr<i8>) 
+// CHECK-SAME:      %[[TMP_arg1:.*]]: !llvm.ptr<i8>)
 // CHECK-DAG:       %[[TMP_c2:.*]] = arith.constant 2 : index
 // CHECK-DAG:       %[[TMP_c6_i32:.*]] = arith.constant 6 : i32
 // CHECK-DAG:       %[[TMP_c1_i32:.*]] = arith.constant 1 : i32
 // CHECK-DAG:       %[[TMP_c0_i32:.*]] = arith.constant 0 : i32
 // CHECK-DAG:       %[[TMP_c8_i8:.*]] = arith.constant 8 : i8
 // CHECK-DAG:       %[[TMP_cst:.*]] = arith.constant 0.000000e+00 : f64
 // CHECK-DAG:       %[[TMP_c0:.*]] = arith.constant 0 : index
 // CHECK-DAG:       %[[TMP_c3:.*]] = arith.constant 3 : index

mlir/test/Dialect/Tensor/extract-slice-from-collapse-shape.mlir

 // CHECK-DAG: %[[c20:.+]] = arith.constant 20 : index
 // CHECK-DAG: %[[c1:.+]] = arith.constant 1 : index
 // CHECK-DAG: %[[c3:.+]] = arith.constant 3 : index
 // CHECK-DAG: %[[c5:.+]] = arith.constant 5 : index
 // CHECK-DAG: %[[c7:.+]] = arith.constant 7 : index
 // CHECK-DAG: %[[init:.+]] = tensor.empty() : tensor<20x11xf32>
 // CHECK-DAG: %[[tile:.+]] = scf.for %[[iv:.+]] = %[[c0]] to %[[c20]] step %[[c1]] iter_args(%[[iterArg:.+]] = %[[init]])
 //     CHECK:   %[[multiIndex:.+]]:3 = affine.delinearize_index %[[iv]] into (%[[c3]], %[[c5]], %[[c7]]
-//     CHECK:   %[[slice:.+]] = tensor.extract_slice %[[arg0]][%[[multiIndex]]#0, %[[multiIndex]]#1, %[[multiIndex]]#2, 0] [1, 1, 1, 11] [1, 1, 1, 1] : 
-//     CHECK:   %[[sliceFlat:.+]] = tensor.collapse_shape %[[slice]] {{\[}}[0, 1, 2], [3]{{\]}} : 
-//     CHECK:   %[[update:.+]] = tensor.insert_slice %[[sliceFlat]] into %[[iterArg]][%[[iv]], 0] [1, 11] [1, 1] : 
+//     CHECK:   %[[slice:.+]] = tensor.extract_slice %[[arg0]][%[[multiIndex]]#0, %[[multiIndex]]#1, %[[multiIndex]]#2, 0] [1, 1, 1, 11] [1, 1, 1, 1] :
+//     CHECK:   %[[sliceFlat:.+]] = tensor.collapse_shape %[[slice]] {{\[}}[0, 1, 2], [3]{{\]}} :
+//     CHECK:   %[[update:.+]] = tensor.insert_slice %[[sliceFlat]] into %[[iterArg]][%[[iv]], 0] [1, 11] [1, 1] :
 //     CHECK:   scf.yield %[[update]] :
 //     CHECK: return %[[tile]]
 
 //     FOREACH: func.func @extract_slice_static(%[[arg0:.+]]:
 // FOREACH-DAG: %[[c20:.+]] = arith.constant 20 : index
 // FOREACH-DAG: %[[c3:.+]] = arith.constant 3 : index
 // FOREACH-DAG: %[[c5:.+]] = arith.constant 5 : index
 // FOREACH-DAG: %[[c7:.+]] = arith.constant 7 : index
 // FOREACH-DAG: %[[init:.+]] = tensor.empty() : tensor<20x11xf32>
 //     FOREACH: %[[tile:.+]] = scf.foreach_thread (%[[iv:.+]]) in (%[[c20]]) shared_outs(%[[dest:.+]] = %[[init]])
 //     FOREACH:   %[[multiIndex:.+]]:3 = affine.delinearize_index %[[iv]] into (%[[c3]], %[[c5]], %[[c7]]
-//     FOREACH:   %[[slice:.+]] = tensor.extract_slice %[[arg0]][%[[multiIndex]]#0, %[[multiIndex]]#1, %[[multiIndex]]#2, 0] [1, 1, 1, 11] [1, 1, 1, 1] : 
-//     FOREACH:   %[[sliceFlat:.+]] = tensor.collapse_shape %[[slice]] {{\[}}[0, 1, 2], [3]{{\]}} : 
+//     FOREACH:   %[[slice:.+]] = tensor.extract_slice %[[arg0]][%[[multiIndex]]#0, %[[multiIndex]]#1, %[[multiIndex]]#2, 0] [1, 1, 1, 11] [1, 1, 1, 1] :
+//     FOREACH:   %[[sliceFlat:.+]] = tensor.collapse_shape %[[slice]] {{\[}}[0, 1, 2], [3]{{\]}} :
 //     FOREACH:   perform_concurrently
 // FOREACH-NEXT:   tensor.parallel_insert_slice %[[sliceFlat]] into %[[dest]][%[[iv]], 0] [1, 11] [1, 1] :
 //     FOREACH: return %[[tile]]
 
 // -----
 
 
 func.func @extract_slice_static_strided(%input: tensor<3x5x7x11xf32>) -> tensor<10x5xf32> {

 // CHECK-DAG: %[[c10:.+]] = arith.constant 10 : index
 // CHECK-DAG: %[[c3:.+]] = arith.constant 3 : index
 // CHECK-DAG: %[[c5:.+]] = arith.constant 5 : index
 // CHECK-DAG: %[[c7:.+]] = arith.constant 7 : index
 //     CHECK: %[[init:.+]] = tensor.empty() : tensor<10x5xf32>
 //     CHECK: %[[tile:.+]] = scf.for %[[iv:.+]] = %[[c0]] to %[[c10]] step %[[c1]] iter_args(%[[iterArg:.+]] = %[[init]])
 //     CHECK:   %[[inputIv:.+]] = affine.apply #[[$map0]](%[[iv]])
 //     CHECK:   %[[multiIndex:.+]]:3 = affine.delinearize_index %[[inputIv]] into (%[[c3]], %[[c5]], %[[c7]]
-//     CHECK:   %[[slice:.+]] = tensor.extract_slice %[[arg0]][%[[multiIndex]]#0, %[[multiIndex]]#1, %[[multiIndex]]#2, 0] [1, 1, 1, 5] [1, 1, 1, 2] : 
-//     CHECK:   %[[sliceFlat:.+]] = tensor.collapse_shape %[[slice]] {{\[}}[0, 1, 2], [3]{{\]}} : 
-//     CHECK:   %[[update:.+]] = tensor.insert_slice %[[sliceFlat]] into %[[iterArg]][%[[iv]], 0] [1, 5] [1, 1] : 
+//     CHECK:   %[[slice:.+]] = tensor.extract_slice %[[arg0]][%[[multiIndex]]#0, %[[multiIndex]]#1, %[[multiIndex]]#2, 0] [1, 1, 1, 5] [1, 1, 1, 2] :
+//     CHECK:   %[[sliceFlat:.+]] = tensor.collapse_shape %[[slice]] {{\[}}[0, 1, 2], [3]{{\]}} :
+//     CHECK:   %[[update:.+]] = tensor.insert_slice %[[sliceFlat]] into %[[iterArg]][%[[iv]], 0] [1, 5] [1, 1] :
 //     CHECK:   scf.yield %[[update]] :
 //     CHECK: return %[[tile]]
 
 
 // -----
 
 
 func.func @extract_slice_dynamic(%input: tensor<3x?x?x11xf32>, %offt: index, %size: index) -> tensor<?x5xf32> {

 //     CHECK: func.func @extract_slice_dynamic_multidim(%[[arg0:.+]]: tensor<3x?x?x11x?xf32>, %[[lb1:.+]]: index, %[[sz1:.+]]: index, %[[lb2:.+]]: index, %[[sz2:.+]]: index)
 // CHECK-DAG: %[[c0:.+]] = arith.constant 0 : index
 // CHECK-DAG: %[[c1:.+]] = arith.constant 1 : index
 // CHECK-DAG: %[[c2:.+]] = arith.constant 2 : index
 // CHECK-DAG: %[[c3:.+]] = arith.constant 3 : index
 // CHECK-DAG: %[[c4:.+]] = arith.constant 4 : index
 // CHECK-DAG: %[[c11:.+]] = arith.constant 11 : index
 //     CHECK: %[[init:.+]] = tensor.empty(%[[sz1]], %[[sz2]]) : tensor<?x?xf32>
-// CHECK-DAG: %[[d1:.+]] = tensor.dim %[[arg0]], %[[c1]] : 
-// CHECK-DAG: %[[d2:.+]] = tensor.dim %[[arg0]], %[[c2]] : 
+// CHECK-DAG: %[[d1:.+]] = tensor.dim %[[arg0]], %[[c1]] :
+// CHECK-DAG: %[[d2:.+]] = tensor.dim %[[arg0]], %[[c2]] :
 // CHECK-DAG: %[[d4:.+]] = tensor.dim %[[arg0]], %[[c4]] :
 //     CHECK: %[[tile1:.+]] = scf.for %[[iv1:.+]] = %[[c0]] to %[[sz1]] step %[[c1]] iter_args(%[[iterArg1:.+]] = %[[init]])
 //     CHECK:   %[[tile2:.+]] = scf.for %[[iv2:.+]] = %[[c0]] to %[[sz2]] step %[[c1]] iter_args(%[[iterArg2:.+]] = %[[iterArg1]])
 //     CHECK:       %[[inputIv1:.+]] = affine.apply #[[map0:.+]](%[[iv1]])[%[[lb1]]]
 //     CHECK:       %[[multiIndex1:.+]]:3 = affine.delinearize_index %[[inputIv1]] into (%[[c3]], %[[d1]], %[[d2]]) :
 //     CHECK:       %[[inputIv2:.+]] = affine.apply #[[map0:.+]](%[[iv2]])[%[[lb2]]]
 //     CHECK:       %[[multiIndex2:.+]]:2 = affine.delinearize_index %[[inputIv2]] into (%[[c11]], %[[d4]]) :
-//     CHECK:       %[[slice:.+]] = tensor.extract_slice %[[arg0]][%[[multiIndex1]]#0, %[[multiIndex1]]#1, %[[multiIndex1]]#2, %[[multiIndex2]]#0, %[[multiIndex2]]#1] [1, 1, 1, 1, 1] [1, 1, 1, 1, 1] : 
-//     CHECK:       %[[sliceFlat:.+]] = tensor.collapse_shape %[[slice]] {{\[}}[0, 1, 2], [3, 4]{{\]}} : 
-//     CHECK:       %[[update:.+]] = tensor.insert_slice %[[sliceFlat]] into %[[iterArg2]][%[[iv1]], %[[iv2]]] [1, 1] [1, 1] : 
+//     CHECK:       %[[slice:.+]] = tensor.extract_slice %[[arg0]][%[[multiIndex1]]#0, %[[multiIndex1]]#1, %[[multiIndex1]]#2, %[[multiIndex2]]#0, %[[multiIndex2]]#1] [1, 1, 1, 1, 1] [1, 1, 1, 1, 1] :
+//     CHECK:       %[[sliceFlat:.+]] = tensor.collapse_shape %[[slice]] {{\[}}[0, 1, 2], [3, 4]{{\]}} :
+//     CHECK:       %[[update:.+]] = tensor.insert_slice %[[sliceFlat]] into %[[iterArg2]][%[[iv1]], %[[iv2]]] [1, 1] [1, 1] :
 //     CHECK:       scf.yield %[[update]] :
 //     CHECK:     scf.yield %[[tile2]] :
-//     CHECK:   return %[[tile1]] : 
+//     CHECK:   return %[[tile1]] :
 
 //     FOREACH: #[[map1:.+]] = affine_map<(d0)[s0] -> (d0 + s0)>
 //     FOREACH: func.func @extract_slice_dynamic_multidim(%[[arg0:.+]]: tensor<3x?x?x11x?xf32>, %[[lb1:.+]]: index, %[[sz1:.+]]: index, %[[lb2:.+]]: index, %[[sz2:.+]]: index)
 // FOREACH-DAG: %[[c1:.+]] = arith.constant 1 : index
 // FOREACH-DAG: %[[c2:.+]] = arith.constant 2 : index
 // FOREACH-DAG: %[[c3:.+]] = arith.constant 3 : index
 // FOREACH-DAG: %[[c4:.+]] = arith.constant 4 : index
 // FOREACH-DAG: %[[c11:.+]] = arith.constant 11 : index
 //     FOREACH:     %[[init:.+]] = tensor.empty(%[[sz1]], %[[sz2]]) : tensor<?x?xf32>
-// FOREACH-DAG:     %[[d1:.+]] = tensor.dim %[[arg0]], %[[c1]] : 
-// FOREACH-DAG:     %[[d2:.+]] = tensor.dim %[[arg0]], %[[c2]] : 
+// FOREACH-DAG:     %[[d1:.+]] = tensor.dim %[[arg0]], %[[c1]] :
+// FOREACH-DAG:     %[[d2:.+]] = tensor.dim %[[arg0]], %[[c2]] :
 // FOREACH-DAG:     %[[d4:.+]] = tensor.dim %[[arg0]], %[[c4]] :
 //     FOREACH:     %[[tile1:.+]] = scf.foreach_thread (%[[tid1:.+]], %[[tid2:.+]]) in (%[[sz1]], %[[sz2]]) shared_outs(%[[dest:.+]] = %[[init]])
 // FOREACH-DAG:       %[[iv1:.+]] = affine.apply #[[map1]](%[[tid1]])[%[[lb1]]]
 //     FOREACH:       %[[multiIndex1:.+]]:3 = affine.delinearize_index %[[iv1]] into (%[[c3]], %[[d1]], %[[d2]]) :
 // FOREACH-DAG:       %[[iv2:.+]] = affine.apply #[[map1]](%[[tid2]])[%[[lb2]]]
 //     FOREACH:       %[[multiIndex2:.+]]:2 = affine.delinearize_index %[[iv2]] into (%[[c11]], %[[d4]]) :
-//     FOREACH:       %[[slice:.+]] = tensor.extract_slice %[[arg0]][%[[multiIndex1]]#0, %[[multiIndex1]]#1, %[[multiIndex1]]#2, %[[multiIndex2]]#0, %[[multiIndex2]]#1] [1, 1, 1, 1, 1] [1, 1, 1, 1, 1] : 
-//     FOREACH:       %[[sliceFlat:.+]] = tensor.collapse_shape %[[slice]] {{\[}}[0, 1, 2], [3, 4]{{\]}} : 
+//     FOREACH:       %[[slice:.+]] = tensor.extract_slice %[[arg0]][%[[multiIndex1]]#0, %[[multiIndex1]]#1, %[[multiIndex1]]#2, %[[multiIndex2]]#0, %[[multiIndex2]]#1] [1, 1, 1, 1, 1] [1, 1, 1, 1, 1] :
+//     FOREACH:       %[[sliceFlat:.+]] = tensor.collapse_shape %[[slice]] {{\[}}[0, 1, 2], [3, 4]{{\]}} :
 //     FOREACH:       perform_concurrently
 //FOREACH-NEXT:         tensor.parallel_insert_slice %[[sliceFlat]] into %[[dest]][%[[tid1]], %[[tid2]]] [1, 1] [1, 1] :
 
 // -----
 
 // Verifies that a linearized dimension that is not sliced does not generate a loop. Note that this
 // only works for static shapes.
 
 // CHECK: @extract_slice_non_sliced_linearized_dim(%[[arg0:.+]]: tensor<{{.*}}>,
 func.func @extract_slice_non_sliced_linearized_dim(%input: tensor<3x?x?x11x2xf32>, %offt: index, %size: index) -> tensor<?x22xf32> {
-  %collapsed = tensor.collapse_shape %input [[0, 1, 2], [3, 4]] : tensor<3x?x?x11x2xf32> into tensor<?x22xf32>  
+  %collapsed = tensor.collapse_shape %input [[0, 1, 2], [3, 4]] : tensor<3x?x?x11x2xf32> into tensor<?x22xf32>
   %slice = tensor.extract_slice %collapsed [%offt, 0] [%size, 22] [1, 1] : tensor<?x22xf32> to tensor<?x22xf32>
   // CHECK: scf.for
   // CHECK-NOT: scf.for
   // CHECK: %[[multiIndex:.+]]:3 = affine.delinearize_index
   // CHECK: tensor.extract_slice %[[arg0]][%[[multiIndex]]#0, %[[multiIndex]]#1, %[[multiIndex]]#2, 0, 0] [1, 1, 1, 11, 2] [1, 1, 1, 1, 1]
   return %slice : tensor<?x22xf32>
 }
 
 // -----
 
 // CHECK: @no_sliced_linearized_dims(%[[arg0:.+]]: tensor<{{.*}}>, %[[arg1:.+]]: index, %[[arg2:.+]]: index
 func.func @no_sliced_linearized_dims(%input: tensor<30x11x100xf32>, %offt: index, %size: index) -> tensor<330x?xf32> {
   %collapsed = tensor.collapse_shape %input [[0, 1], [2]] : tensor<30x11x100xf32> into tensor<330x100xf32>
   %slice = tensor.extract_slice %collapsed [0, %offt] [330, %size] [1, 1] : tensor<330x100xf32> to tensor<330x?xf32>
-  // CHECK-NOT: scf.for  
+  // CHECK-NOT: scf.for
   // CHECK: %[[init:.+]] = tensor.empty(%[[arg2]])
   // CHECK: %[[e:.+]] = tensor.extract_slice %[[arg0]][0, 0, %[[arg1]]] [30, 11, %[[arg2]]] [1, 1, 1]
   // CHECK: %[[c:.+]] = tensor.collapse_shape %[[e]] {{\[}}[0, 1], [2]]
   // CHECK: %[[res:.+]] = tensor.insert_slice %[[c]] into %[[init]]
   // CHECK: return %[[res]]
   return %slice : tensor<330x?xf32>
 }
 
 // -----
 
 // The below tests verify that a dimension which is the result of collapsing at
 // most one non-unit dim is handled properly.
 
 // CHECK: @collapse_and_slice_unit_dim(%[[arg0:.+]]: tensor<{{.*}}>, %[[arg1:.+]]: index, %[[arg2:.+]]: index
 func.func @collapse_and_slice_unit_dim(%input: tensor<1x11x100xf32>, %offt: index, %size: index) -> tensor<?x100xf32> {
   %collapsed = tensor.collapse_shape %input [[0, 1], [2]] : tensor<1x11x100xf32> into tensor<11x100xf32>
   %slice = tensor.extract_slice %collapsed [%offt, 0] [%size, 100] [1, 1] : tensor<11x100xf32> to tensor<?x100xf32>
   // CHECK-NOT: scf.for
   // CHECK: %[[e:.+]] = tensor.extract_slice %[[arg0]][0, 0, 0] [1, 11, 100] [1, 1, 1]
   // CHECK-SAME:           tensor<1x11x100xf32> to tensor<11x100xf32>
   // CHECK: %[[e1:.+]] = tensor.extract_slice %[[e]][%[[arg1]], 0] [%[[arg2]], 100] [1, 1]
-  // CHECK-SAME:           tensor<11x100xf32> to tensor<?x100xf32>    
+  // CHECK-SAME:           tensor<11x100xf32> to tensor<?x100xf32>
   return %slice : tensor<?x100xf32>
 }
 
 // CHECK: @collapse_and_slice_multiple_unit_dim_dynamic(%[[arg0:.+]]: tensor<{{.*}}>, %[[arg1:.+]]: index, %[[arg2:.+]]: index
 func.func @collapse_and_slice_multiple_unit_dim_dynamic(%input: tensor<1x?x1x100xf32>, %offt: index, %size: index) -> tensor<?x100xf32> {
   %collapsed = tensor.collapse_shape %input [[0, 1, 2], [3]] : tensor<1x?x1x100xf32> into tensor<?x100xf32>
   %slice = tensor.extract_slice %collapsed [%offt, 0] [%size, 100] [1, 1] : tensor<?x100xf32> to tensor<?x100xf32>
   // CHECK-NOT: scf.for
   // CHECK: %[[c1:.+]] = arith.constant 1 : index
-  // CHECK: %[[dim:.+]] = tensor.dim %[[arg0]], %[[c1]] : 
+  // CHECK: %[[dim:.+]] = tensor.dim %[[arg0]], %[[c1]] :
   // CHECK: %[[e:.+]] = tensor.extract_slice %[[arg0]][0, 0, 0, 0] [1, %[[dim]], 1, 100] [1, 1, 1, 1]
   // CHECK-SAME:           tensor<1x?x1x100xf32> to tensor<?x100xf32>
   // CHECK: %[[e1:.+]] = tensor.extract_slice %[[e]][%[[arg1]], 0] [%[[arg2]], 100] [1, 1]
-  // CHECK-SAME:           tensor<?x100xf32> to tensor<?x100xf32>  
+  // CHECK-SAME:           tensor<?x100xf32> to tensor<?x100xf32>
   return %slice : tensor<?x100xf32>
 }
 
 // CHECK: @collapse_and_slice_multiple_unit_dim_mixed(%[[arg0:.+]]: tensor<{{.*}}>, %[[arg1:.+]]: index, %[[arg2:.+]]: index
 func.func @collapse_and_slice_multiple_unit_dim_mixed(%input: tensor<1x?x1x100x10xf32>, %offt: index, %size: index) -> tensor<?x?xf32> {
   %collapsed = tensor.collapse_shape %input [[0, 1, 2], [3, 4]] : tensor<1x?x1x100x10xf32> into tensor<?x1000xf32>
   %slice = tensor.extract_slice %collapsed [%offt, %offt] [%size, %size] [1, 1] : tensor<?x1000xf32> to tensor<?x?xf32>
   // CHECK-DAG: %[[c0]] = arith.constant 0 : index
   // CHECK-DAG: %[[c1]] = arith.constant 1 : index
   // CHECK: %[[dim:.+]] = tensor.dim %[[arg0]], %[[c1]]
   // CHECK: %[[rank_reduced:.+]] = tensor.extract_slice %[[arg0]][0, 0, 0, 0, 0] [1, %[[dim]], 1, 100, 10] [1, 1, 1, 1, 1]
   // CHECK: %[[empty:.+]] = tensor.empty
   // CHECK: %[[result:.+]] = scf.for %[[iv:.+]] = %[[c0]] to %[[arg2]] step %[[c1]] iter_args(%[[ia:.+]] = %[[empty]])
   // CHECK:     %[[idx:.+]] = affine.apply
   // CHECK:     %[[multi_index:.+]] = affine.delinearize_index %[[idx]] into
   // CHECK:     %[[collapsed:.+]] = tensor.collapse_shape
   // CHECK:     %[[updated:.+]] = tensor.insert_slice
   // CHECK:     scf.yield %[[updated]]
   // CHECK: return %[[result]]
   return %slice : tensor<?x?xf32>
 }
 
-// Edge case where all collapsed dims are unit dims. This pattern can't eliminate the collapse shape, 
+// Edge case where all collapsed dims are unit dims. This pattern can't eliminate the collapse shape,
 // that should be handled by `linalg-fold-unit-extent-dims`.
 
 // CHECK: @collapse_and_slice_multiple_all_unit_dim(%[[arg0:.+]]: tensor<{{.*}}>)
 func.func @collapse_and_slice_multiple_all_unit_dim(%input: tensor<1x1x1x100xf32>) -> tensor<1x100xf32> {
   %collapsed = tensor.collapse_shape %input [[0, 1, 2], [3]] : tensor<1x1x1x100xf32> into tensor<1x100xf32>
-  %slice = tensor.extract_slice %collapsed [0, 0] [1, 100] [1, 1] : tensor<1x100xf32> to tensor<1x100xf32>  
-  return %slice : tensor<1x100xf32>  
+  %slice = tensor.extract_slice %collapsed [0, 0] [1, 100] [1, 1] : tensor<1x100xf32> to tensor<1x100xf32>
+  return %slice : tensor<1x100xf32>
   // CHECK: %[[collapse:.+]] = tensor.collapse_shape %[[arg0]] {{\[}}[0, 1, 2], [3]] : tensor<1x1x1x100xf32> into tensor<1x100xf32>
-  // CHECK: return %[[collapse]]  
+  // CHECK: return %[[collapse]]
 }

mlir/test/Dialect/Tensor/invalid.mlir

func.func @gather_wrong_result_type(
   %out = tensor.gather %source[%indices] gather_dims([0, 2]):
     (tensor<4x5x6xf32>, tensor<1x2x3xindex>) -> tensor<1x2x1xf32>
   return
 }
 
 // -----
 
 func.func @scatter_empty_dims(
-    %source : tensor<f32>, 
+    %source : tensor<f32>,
     %dest : tensor<4x5x6xf32>, %indices: tensor<1x2x3xindex>) {
   // expected-error@+1 {{scatter_dims must be non-empty}}
   %out = tensor.scatter %source into %dest[%indices] scatter_dims([]) unique:
     (tensor<f32>, tensor<4x5x6xf32>, tensor<1x2x3xindex>) -> tensor<1x2xf32>
   return
 }
 
 // -----
 
 func.func @scatter_coordinate_rank_overflow(
-    %source : tensor<f32>, 
+    %source : tensor<f32>,
     %dest : tensor<4x5x6xf32>, %indices: tensor<1x2x3xindex>) {
   // expected-error@+1 {{scatter_dims overflow dest rank}}
   %out = tensor.scatter %source into %dest[%indices] scatter_dims([0, 1, 2, 3]) unique:
     (tensor<f32>, tensor<4x5x6xf32>, tensor<1x2x3xindex>) -> tensor<1x2xf32>
   return
 }
 
 // -----
 
 func.func @scatter_coordinate_negative(
-    %source : tensor<f32>, 
+    %source : tensor<f32>,
     %dest : tensor<4x5x6xf32>, %indices: tensor<1x2x3xindex>) {
   // expected-error@+1 {{scatter_dims value must be non-negative}}
   %out = tensor.scatter %source into %dest[%indices] scatter_dims([-1]) unique:
     (tensor<f32>, tensor<4x5x6xf32>, tensor<1x2x3xindex>) -> tensor<1x2x1x1x1xf32>
   return
 }
 
 // -----
 
 func.func @scatter_coordinate_overflow(
-    %source : tensor<f32>, 
+    %source : tensor<f32>,
     %dest : tensor<4x5x6xf32>, %indices: tensor<1x2x3xindex>) {
   // expected-error@+1 {{scatter_dims value must be smaller than dest rank}}
   %out = tensor.scatter %source into %dest[%indices] scatter_dims([42]) unique:
     (tensor<f32>, tensor<4x5x6xf32>, tensor<1x2x3xindex>) -> tensor<1x2x1x1x1xf32>
   return
 }
 
 // -----
 
 func.func @scatter_coordinate_overflow(
-    %source : tensor<f32>, 
+    %source : tensor<f32>,
     %dest : tensor<4x5x6xf32>, %indices: tensor<1x2x3xindex>) {
   // expected-error@+1 {{scatter_dims values must be strictly increasing}}
   %out = tensor.scatter %source into %dest[%indices] scatter_dims([1, 0]) unique:
     (tensor<f32>, tensor<4x5x6xf32>, tensor<1x2x3xindex>) -> tensor<1x2x1x1x1xf32>
   return
 }
 
 // -----
 
 func.func @scatter_missing_unique(
-    %source : tensor<f32>, 
+    %source : tensor<f32>,
     %dest : tensor<4x5x6xf32>, %indices: tensor<1x2x3xindex>) {
   // expected-error@+1 {{requires 'unique' attribute to be set}}
   %out = tensor.scatter %source into %dest[%indices] scatter_dims([0, 2]):
     (tensor<f32>, tensor<4x5x6xf32>, tensor<1x2x3xindex>) -> tensor<1x2x1xf32>
   return
 }
 
 // -----
 
 func.func @scatter_wrong_result_type(
-    %source : tensor<f32>, 
+    %source : tensor<f32>,
     %dest : tensor<4x5x6xf32>, %indices: tensor<1x2x3xindex>) {
   // expected-error@+1 {{source type mismatch: expected 'tensor<1x2x1x5x1xf32>' or its rank-reduced variant 'tensor<1x2x5xf32>' (got: 'tensor<f32>')}}
   %out = tensor.scatter %source into %dest[%indices] scatter_dims([0, 2]) unique:
     (tensor<f32>, tensor<4x5x6xf32>, tensor<1x2x3xindex>) -> tensor<1x2x1xf32>
   return
 }
 
 // -----

mlir/test/Dialect/Tensor/ops.mlir

 
 // -----
 
 // CHECK-LABEL: func @test_splat_op
 // CHECK-SAME: [[S:%arg[0-9]+]]: f32
 func.func @test_splat_op(%s : f32) {
   // CHECK: tensor.splat [[S]] : tensor<8xf32>
   %v = tensor.splat %s : tensor<8xf32>
-  
   // CHECK: tensor.splat [[S]] : tensor<4xf32>
   %u = "tensor.splat"(%s) : (f32) -> tensor<4xf32>
   return
 }
 
 // -----
 
 // CHECK-LABEL: func.func @gather_scatter(
 // CHECK-SAME:  %[[ARG0:.*]]: tensor<4x5x6xf32>,
 // CHECK-SAME:  %[[ARG1:.*]]: tensor<1x3x2xindex>,
 // CHECK-SAME:  %[[ARG2:.*]]: tensor<1x3x2xi32>) {
 func.func @gather_scatter(
     %dest : tensor<4x5x6xf32>, %indices: tensor<1x3x2xindex>, %indices_i32: tensor<1x3x2xi32>) {
   // CHECK: %[[GATHER:.*]] = tensor.gather %[[ARG0]][%[[ARG2]]] gather_dims([1, 2]) unique : (tensor<4x5x6xf32>, tensor<1x3x2xi32>) -> tensor<1x3x4x1x1xf32>
   %gathered = tensor.gather %dest[%indices_i32] gather_dims([1, 2]) unique:
     (tensor<4x5x6xf32>, tensor<1x3x2xi32>) -> tensor<1x3x4x1x1xf32>
   // CHECK: %[[GATHER0:.*]] = tensor.gather %[[ARG0]][%[[ARG1]]] gather_dims([1, 2]) unique : (tensor<4x5x6xf32>, tensor<1x3x2xindex>) -> tensor<1x3x4xf32>
   %rank_reduced_gathered = tensor.gather %dest[%indices] gather_dims([1, 2]) unique:
     (tensor<4x5x6xf32>, tensor<1x3x2xindex>) -> tensor<1x3x4xf32>
 
   // CHECK: %{{.*}} = tensor.scatter %[[GATHER]] into %[[ARG0]][%[[ARG1]]] scatter_dims([1, 2]) unique : (tensor<1x3x4x1x1xf32>, tensor<4x5x6xf32>, tensor<1x3x2xindex>) -> tensor<4x5x6xf32>
-  %scattered = tensor.scatter %gathered into %dest[%indices] 
+  %scattered = tensor.scatter %gathered into %dest[%indices]
       scatter_dims([1, 2]) unique:
     (tensor<1x3x4x1x1xf32>, tensor<4x5x6xf32>, tensor<1x3x2xindex>) -> tensor<4x5x6xf32>
   // CHECK: %{{.*}} = tensor.scatter %[[GATHER0]] into %[[ARG0]][%[[ARG2]]] scatter_dims([1, 2]) unique : (tensor<1x3x4xf32>, tensor<4x5x6xf32>, tensor<1x3x2xi32>) -> tensor<4x5x6xf32>
-  %rank_reduced_scattered = tensor.scatter %rank_reduced_gathered into %dest[%indices_i32] 
+  %rank_reduced_scattered = tensor.scatter %rank_reduced_gathered into %dest[%indices_i32]
       scatter_dims([1, 2]) unique:
     (tensor<1x3x4xf32>, tensor<4x5x6xf32>, tensor<1x3x2xi32>) -> tensor<4x5x6xf32>
   return
 }
 
 // -----
 
 func.func @pack_nc_to_ncnc(%source: tensor<128x256xf32>, %dest: tensor<4x16x32x16xf32>) -> tensor<128x256xf32> {

mlir/test/Dialect/Tosa/inlining.mlir

 // RUN: mlir-opt %s -inline | FileCheck %s
 
 // These tests verify that regions with operations from TOSA dialect
 // can be inlined.
 
 // CHECK-LABEL: func @inlined_if_fn
 // Check that both the calls and the functions are eliminated after inlining:
 // CHECK-NOT: @add
 // CHECK-NOT: @sub
 func.func @inlined_if_fn(%arg0: tensor<f32>, %arg1: tensor<f32>, %arg2: tensor<i1>) -> tensor<f32> {
   %0 = "tosa.cond_if"(%arg2, %arg0, %arg1) ({
-  ^bb0(%arg3: tensor<f32>, %arg4: tensor<f32>):  
+  ^bb0(%arg3: tensor<f32>, %arg4: tensor<f32>):
     %1 = call @add(%arg3, %arg4) : (tensor<f32>, tensor<f32>) -> tensor<f32>
     "tosa.yield"(%1) : (tensor<f32>) -> ()
   },  {
-  ^bb0(%arg3: tensor<f32>, %arg4: tensor<f32>):  
+  ^bb0(%arg3: tensor<f32>, %arg4: tensor<f32>):
     %1 = call @sub(%arg3, %arg4) : (tensor<f32>, tensor<f32>) -> tensor<f32>
     "tosa.yield"(%1) : (tensor<f32>) -> ()
   }) : (tensor<i1>, tensor<f32>, tensor<f32>) -> tensor<f32>
   return %0 : tensor<f32>
 }
 func.func private @add(%arg0: tensor<f32>, %arg1: tensor<f32>) -> tensor<f32> {
   %0 = "tosa.add"(%arg0, %arg1) : (tensor<f32>, tensor<f32>) -> tensor<f32>
   return %0 : tensor<f32>
 }
 func.func private @sub(%arg0: tensor<f32>, %arg1: tensor<f32>) -> tensor<f32> {
   %0 = "tosa.sub"(%arg0, %arg1) : (tensor<f32>, tensor<f32>) -> tensor<f32>
   return %0 : tensor<f32>
 }
 
 // -----
 
 // CHECK-LABEL: func @inlined_while_fn
 func.func @inlined_while_fn(%arg0: tensor<i32>, %arg1: tensor<i32>, %arg2: tensor<i32>, %arg3: tensor<10xi32>) -> tensor<10xi32> {
   // Check that calls are inlined and functions eliminated:
   // CHECK-NOT: @while
   %1:4 = "tosa.while_loop"(%arg0, %arg1, %arg2, %arg3) ({
-  ^bb0(%arg4: tensor<i32>, %arg5: tensor<i32>, %arg6: tensor<i32>, %arg7: tensor<10xi32>):  
+  ^bb0(%arg4: tensor<i32>, %arg5: tensor<i32>, %arg6: tensor<i32>, %arg7: tensor<10xi32>):
     %2 = call @while_cond_40(%arg4, %arg5, %arg6, %arg7) : (tensor<i32>, tensor<i32>, tensor<i32>, tensor<10xi32>) -> tensor<i1>
     "tosa.yield"(%2) : (tensor<i1>) -> ()
   },  {
-  ^bb0(%arg4: tensor<i32>, %arg5: tensor<i32>, %arg6: tensor<i32>, %arg7: tensor<10xi32>):  
+  ^bb0(%arg4: tensor<i32>, %arg5: tensor<i32>, %arg6: tensor<i32>, %arg7: tensor<10xi32>):
     %2:4 = call @while_body_50(%arg4, %arg5, %arg6, %arg7) : (tensor<i32>, tensor<i32>, tensor<i32>, tensor<10xi32>) -> (tensor<i32>, tensor<i32>, tensor<i32>, tensor<10xi32>)
     "tosa.yield"(%2#0, %2#1, %2#2, %2#3) : (tensor<i32>, tensor<i32>, tensor<i32>, tensor<10xi32>) -> ()
   }) : (tensor<i32>, tensor<i32>, tensor<i32>, tensor<10xi32>) -> (tensor<i32>, tensor<i32>, tensor<i32>, tensor<10xi32>)
   return %1#3 : tensor<10xi32>
 }
 func.func private @while_body_50(%arg0: tensor<i32>, %arg1: tensor<i32>, %arg2: tensor<i32>, %arg3: tensor<10xi32>) -> (tensor<i32>, tensor<i32>, tensor<i32>, tensor<10xi32>) {
   %1 = "tosa.add"(%arg0, %arg1) : (tensor<i32>, tensor<i32>) -> tensor<i32>
   %2 = "tosa.add"(%arg3, %1) : (tensor<10xi32>, tensor<i32>) -> tensor<10xi32>
   return %1, %arg1, %arg2, %2: tensor<i32>, tensor<i32>, tensor<i32>, tensor<10xi32>
 }
 func.func private @while_cond_40(%arg0: tensor<i32>, %arg1: tensor<i32>, %arg2: tensor<i32>, %arg3: tensor<10xi32>) -> tensor<i1> {
   %0 = "tosa.greater_equal"(%arg0, %arg1) : (tensor<i32>, tensor<i32>) -> tensor<i1>
   %1 = "tosa.logical_not"(%0) : (tensor<i1>) -> tensor<i1>
   return %1 : tensor<i1>
 }

mlir/test/Dialect/Transform/check-use-after-free.mlir

^bb1(%arg1: !pdl.operation):
       yield %arg1 : !pdl.operation
     }
     transform.sequence %0 : !pdl.operation failures(propagate) attributes { ord = 2 } {
     ^bb2(%arg2: !pdl.operation):
     }
     transform.sequence %0 : !pdl.operation failures(propagate) attributes { ord = 3 } {
     ^bb3(%arg3: !pdl.operation):
     }
-    
     // `transform.sequence` has recursive side effects so it has the same "free"
     // as the child op it contains.
     // expected-note @below {{freed here}}
     transform.sequence %0 : !pdl.operation failures(propagate) attributes { ord = 4 } {
     ^bb4(%arg4: !pdl.operation):
       test_consume_operand_if_matches_param_or_fail %0[42]
     }
     // expected-warning @below {{operand #0 may be used after free}}
^bb1(%arg1: !pdl.operation):
       yield %arg1 : !pdl.operation
     }
     transform.sequence %0 : !pdl.operation failures(propagate) attributes { ord = 2 } {
     ^bb2(%arg2: !pdl.operation):
     }
     transform.sequence %0 : !pdl.operation failures(propagate) attributes { ord = 3 } {
     ^bb3(%arg3: !pdl.operation):
     }
-    
     // expected-note @below {{freed here}}
     test_consume_operand_if_matches_param_or_fail %0[42]
     // expected-warning @below {{operand #0 may be used after free}}
     transform.sequence %0 : !pdl.operation failures(propagate) attributes { ord = 5 } {
     ^bb3(%arg3: !pdl.operation):
     }
   }
   return

mlir/test/Dialect/Transform/test-interpreter.mlir

^bb1(%arg1: !pdl.operation):
     transform.test_print_remark_at_operand %results, "transform applied" : !pdl.operation
   }
 }
 
 // -----
 
 func.func @get_parent_for_op_no_loop(%arg0: index, %arg1: index) {
   // expected-remark @below {{found muli}}
-  %0 = arith.muli %arg0, %arg1 : index  
-  arith.addi %0, %arg1 : index  
+  %0 = arith.muli %arg0, %arg1 : index
+  arith.addi %0, %arg1 : index
   return
 }
 
 transform.sequence failures(propagate) {
 ^bb1(%arg1: !pdl.operation):
   %addi = transform.structured.match ops{["arith.addi"]} in %arg1
   %muli = get_producer_of_operand %addi[0] : (!pdl.operation) -> !pdl.operation
   transform.test_print_remark_at_operand %muli, "found muli" : !pdl.operation
 }
 
 // -----
 
 func.func @get_parent_for_op_no_loop(%arg0: index, %arg1: index) {
   // expected-note @below {{target op}}
-  %0 = arith.muli %arg0, %arg1 : index  
+  %0 = arith.muli %arg0, %arg1 : index
   return
 }
 
 transform.sequence failures(propagate) {
 ^bb1(%arg1: !pdl.operation):
   %muli = transform.structured.match ops{["arith.muli"]} in %arg1
   // expected-error @below {{could not find a producer for operand number: 0 of}}
   %bbarg = get_producer_of_operand %muli[0] : (!pdl.operation) -> !pdl.operation
 
 }
 
 // -----
 
 func.func @split_handles(%a: index, %b: index, %c: index) {
-  %0 = arith.muli %a, %b : index  
-  %1 = arith.muli %a, %c : index  
+  %0 = arith.muli %a, %b : index
+  %1 = arith.muli %a, %c : index
   return
 }
 
 transform.sequence failures(propagate) {
 ^bb1(%fun: !pdl.operation):
   %muli = transform.structured.match ops{["arith.muli"]} in %fun
   %h:2 = split_handles %muli in [2] : (!pdl.operation) -> (!pdl.operation, !pdl.operation)
   // expected-remark @below {{1}}
   transform.test_print_number_of_associated_payload_ir_ops %h#0
   %muli_2 = transform.structured.match ops{["arith.muli"]} in %fun
   // expected-error @below {{expected to contain 3 operation handles but it only contains 2 handles}}
   %h_2:3 = split_handles %muli_2 in [3] : (!pdl.operation) -> (!pdl.operation, !pdl.operation, !pdl.operation)
 }
 
 // -----
 
 func.func @split_handles(%a: index, %b: index, %c: index) {
-  %0 = arith.muli %a, %b : index  
-  %1 = arith.muli %a, %c : index  
+  %0 = arith.muli %a, %b : index
+  %1 = arith.muli %a, %c : index
   return
 }
 
 transform.sequence failures(suppress) {
 ^bb1(%fun: !pdl.operation):
   %muli = transform.structured.match ops{["arith.muli"]} in %fun
   %h:2 = split_handles %muli in [2] : (!pdl.operation) -> (!pdl.operation, !pdl.operation)
   // expected-remark @below {{1}}
pdl.pattern @some : benefit(1) {
     pdl.rewrite %0 with "transform.dialect"
   }
 }
 
 "test.some_op"() : () -> ()
 // -----
 
 func.func @split_handles(%a: index, %b: index, %c: index) {
-  %0 = arith.muli %a, %b : index  
-  %1 = arith.muli %a, %c : index  
+  %0 = arith.muli %a, %b : index
+  %1 = arith.muli %a, %c : index
   return
 }
 
 transform.sequence -> !pdl.operation failures(propagate) {
 ^bb1(%fun: !pdl.operation):
   %muli = transform.structured.match ops{["arith.muli"]} in %fun
   // expected-error @below {{expected to contain 3 operation handles but it only contains 2 handles}}
   %h_2:3 = split_handles %muli in [3] : (!pdl.operation) -> (!pdl.operation, !pdl.operation, !pdl.operation)
   /// Test that yield does not crash in the presence of silenceable error in
   /// propagate mode.
   yield %fun : !pdl.operation
 }

mlir/test/Dialect/Vector/vector-transfer-drop-unit-dims-patterns.mlir

 // RUN: mlir-opt %s -test-vector-transfer-drop-unit-dims-patterns -split-input-file | FileCheck %s
 
 func.func @transfer_read_rank_reducing(
       %arg : memref<1x1x3x2xi8, strided<[6, 6, 2, 1], offset: ?>>) -> vector<3x2xi8> {
     %c0 = arith.constant 0 : index
     %cst = arith.constant 0 : i8
-    %v = vector.transfer_read %arg[%c0, %c0, %c0, %c0], %cst : 
+    %v = vector.transfer_read %arg[%c0, %c0, %c0, %c0], %cst :
       memref<1x1x3x2xi8, strided<[6, 6, 2, 1], offset: ?>>, vector<3x2xi8>
     return %v : vector<3x2xi8>
 }
 
 // CHECK-LABEL: func @transfer_read_rank_reducing
 //  CHECK-SAME:     %[[ARG:.+]]: memref<1x1x3x2xi8
-//       CHECK:   %[[SUBVIEW:.+]] = memref.subview %[[ARG]][0, 0, 0, 0] [1, 1, 3, 2] [1, 1, 1, 1] 
+//       CHECK:   %[[SUBVIEW:.+]] = memref.subview %[[ARG]][0, 0, 0, 0] [1, 1, 3, 2] [1, 1, 1, 1]
 //  CHECK-SAME:     memref<1x1x3x2xi8, {{.*}}> to memref<3x2xi8, {{.*}}>
 //       CHECK:   vector.transfer_read %[[SUBVIEW]]
 
 // -----
 
 func.func @transfer_write_rank_reducing(%arg : memref<1x1x3x2xi8, strided<[6, 6, 2, 1], offset: ?>>, %vec : vector<3x2xi8>) {
     %c0 = arith.constant 0 : index
-    vector.transfer_write %vec, %arg [%c0, %c0, %c0, %c0] : 
+    vector.transfer_write %vec, %arg [%c0, %c0, %c0, %c0] :
       vector<3x2xi8>, memref<1x1x3x2xi8, strided<[6, 6, 2, 1], offset: ?>>
     return
 }
 
 // CHECK-LABEL: func @transfer_write_rank_reducing
 //  CHECK-SAME:     %[[ARG:.+]]: memref<1x1x3x2xi8
-//       CHECK:   %[[SUBVIEW:.+]] = memref.subview %[[ARG]][0, 0, 0, 0] [1, 1, 3, 2] [1, 1, 1, 1] 
+//       CHECK:   %[[SUBVIEW:.+]] = memref.subview %[[ARG]][0, 0, 0, 0] [1, 1, 3, 2] [1, 1, 1, 1]
 //  CHECK-SAME:     memref<1x1x3x2xi8, {{.*}}> to memref<3x2xi8, {{.*}}>
 //       CHECK:   vector.transfer_write %{{.*}}, %[[SUBVIEW]]
 No newline at end of file

mlir/test/Dialect/Vector/vector-transfer-flatten.mlir

 // RUN: mlir-opt %s -test-vector-transfer-flatten-patterns -split-input-file | FileCheck %s
 
 func.func @transfer_read_flattenable_with_offset(
       %arg : memref<5x4x3x2xi8, strided<[24, 6, 2, 1], offset: ?>>) -> vector<5x4x3x2xi8> {
     %c0 = arith.constant 0 : index
     %cst = arith.constant 0 : i8
-    %v = vector.transfer_read %arg[%c0, %c0, %c0, %c0], %cst : 
+    %v = vector.transfer_read %arg[%c0, %c0, %c0, %c0], %cst :
       memref<5x4x3x2xi8, strided<[24, 6, 2, 1], offset: ?>>, vector<5x4x3x2xi8>
     return %v : vector<5x4x3x2xi8>
 }
 
 // CHECK-LABEL: func @transfer_read_flattenable_with_offset
 // CHECK-SAME:      %[[ARG:[0-9a-zA-Z]+]]: memref<5x4x3x2xi8
 // CHECK:         %[[COLLAPSED:.+]] = memref.collapse_shape %[[ARG]] {{.}}[0, 1, 2, 3]
 // CHECK:         %[[READ1D:.+]] = vector.transfer_read %[[COLLAPSED]]
 // CHECK:         %[[VEC2D:.+]] = vector.shape_cast %[[READ1D]] : vector<120xi8> to vector<5x4x3x2xi8>
 // CHECK:         return %[[VEC2D]]
 
 // -----
 
 func.func @transfer_write_flattenable_with_offset(
       %arg : memref<5x4x3x2xi8, strided<[24, 6, 2, 1], offset: ?>>, %vec : vector<5x4x3x2xi8>) {
     %c0 = arith.constant 0 : index
-    vector.transfer_write %vec, %arg [%c0, %c0, %c0, %c0] : 
+    vector.transfer_write %vec, %arg [%c0, %c0, %c0, %c0] :
       vector<5x4x3x2xi8>, memref<5x4x3x2xi8, strided<[24, 6, 2, 1], offset: ?>>
     return
 }
 
 // CHECK-LABEL: func @transfer_write_flattenable_with_offset
 // CHECK-SAME:      %[[ARG:[0-9a-zA-Z]+]]: memref<5x4x3x2xi8
 // CHECK-SAME:      %[[VEC:[0-9a-zA-Z]+]]: vector<5x4x3x2xi8>
 // CHECK-DAG:     %[[COLLAPSED:.+]] = memref.collapse_shape %[[ARG]] {{.}}[0, 1, 2, 3]{{.}} : memref<5x4x3x2xi8, {{.+}}> into memref<120xi8, {{.+}}>

 // CHECK-SAME:    : vector<32xi8>, memref<?x?x32xi8, {{.+}}>
 
 // -----
 
 func.func @transfer_read_flattenable_negative(
       %arg : memref<5x4x3x2xi8, strided<[24, 6, 2, 1], offset: ?>>) -> vector<2x2x2x2xi8> {
     %c0 = arith.constant 0 : index
     %cst = arith.constant 0 : i8
-    %v = vector.transfer_read %arg[%c0, %c0, %c0, %c0], %cst : 
+    %v = vector.transfer_read %arg[%c0, %c0, %c0, %c0], %cst :
       memref<5x4x3x2xi8, strided<[24, 6, 2, 1], offset: ?>>, vector<2x2x2x2xi8>
     return %v : vector<2x2x2x2xi8>
 }
 
 // CHECK-LABEL: func @transfer_read_flattenable_negative
 //       CHECK:   vector.transfer_read {{.*}} vector<2x2x2x2xi8>
 
 // -----
 
 func.func @transfer_read_flattenable_negative2(
       %arg : memref<5x4x3x2xi8, strided<[24, 8, 2, 1], offset: ?>>) -> vector<5x4x3x2xi8> {
     %c0 = arith.constant 0 : index
     %cst = arith.constant 0 : i8
-    %v = vector.transfer_read %arg[%c0, %c0, %c0, %c0], %cst : 
+    %v = vector.transfer_read %arg[%c0, %c0, %c0, %c0], %cst :
       memref<5x4x3x2xi8, strided<[24, 8, 2, 1], offset: ?>>, vector<5x4x3x2xi8>
     return %v : vector<5x4x3x2xi8>
 }
 
 // CHECK-LABEL: func @transfer_read_flattenable_negative2
 //       CHECK:   vector.transfer_read {{.*}} vector<5x4x3x2xi8>

mlir/test/Dialect/Vector/vector-transferop-opt.mlir

 //       CHECK:   vector.transfer_write
 //       CHECK:   vector.transfer_write
 //       CHECK:   vector.transfer_write
 //       CHECK:   vector.transfer_read
 //       CHECK:   vector.transfer_write
 //       CHECK:   return
 func.func @forward_dead_store_negative(%arg0: i1, %arg1 : memref<4x4xf32>,
   %v0 : vector<1x4xf32>, %v1 : vector<1x1xf32>, %v2 : vector<1x4xf32>, %i : index) -> vector<1x4xf32> {
-  %alias = memref.subview %arg1[0, 0] [2, 2] [1, 1] : 
+  %alias = memref.subview %arg1[0, 0] [2, 2] [1, 1] :
     memref<4x4xf32> to memref<2x2xf32, strided<[4, 1]>>
   %c1 = arith.constant 1 : index
   %c4 = arith.constant 4 : index
   %c0 = arith.constant 0 : index
   %cf0 = arith.constant 0.0 : f32
   vector.transfer_write %v0, %arg1[%c1, %c0] {in_bounds = [true, true]} :
     vector<1x4xf32>, memref<4x4xf32>
   // blocking write.
   vector.transfer_write %v1, %alias[%c0, %c0] {in_bounds = [true, true]} :
     vector<1x1xf32>, memref<2x2xf32, strided<[4, 1]>>
   vector.transfer_write %v2, %arg1[%c1, %c0] {in_bounds = [true, true]} :
     vector<1x4xf32>, memref<4x4xf32>
   // blocking write.
   vector.transfer_write %v1, %alias[%c1, %c0] {in_bounds = [true, true]} :
-    vector<1x1xf32>, memref<2x2xf32, strided<[4, 1]>>    
+    vector<1x1xf32>, memref<2x2xf32, strided<[4, 1]>>
   %0 = vector.transfer_read %arg1[%c1, %c0], %cf0 {in_bounds = [true, true]} :
-    memref<4x4xf32>, vector<1x4xf32>  
+    memref<4x4xf32>, vector<1x4xf32>
   vector.transfer_write %v2, %arg1[%c1, %c0] {in_bounds = [true, true]} :
     vector<1x4xf32>, memref<4x4xf32>
   return %0 : vector<1x4xf32>
 }
 No newline at end of file

mlir/test/Dialect/Vector/vector-unroll-options.mlir

%0 = vector.contract
                            affine_map<(i, j, k) -> (i, j)>],
           iterator_types = ["parallel", "parallel", "reduction"]}
        %lhs, %rhs, %init : vector<8x4xf32>, vector<8x4xf32> into vector<8x8xf32>
   return %0 : vector<8x8xf32>
 }
 // CHECK-LABEL: func @vector_contract_f32
 // CHECK-SAME: [[arg0:%.+]]: vector<8x4xf32>, [[arg1:%.+]]: vector<8x4xf32>, [[arg2:%.+]]: vector<8x8xf32>
 
-//       CHECK:   [[a:%.+]] = vector.extract_strided_slice [[arg0]] 
+//       CHECK:   [[a:%.+]] = vector.extract_strided_slice [[arg0]]
 //  CHECK-SAME:   offsets = [0, 0]
-//       CHECK:   [[b:%.+]] = vector.extract_strided_slice [[arg1]] 
+//       CHECK:   [[b:%.+]] = vector.extract_strided_slice [[arg1]]
 //  CHECK-SAME:   offsets = [0, 0]
-//       CHECK:   [[c:%.+]] = vector.extract_strided_slice [[arg2]] 
+//       CHECK:   [[c:%.+]] = vector.extract_strided_slice [[arg2]]
 //  CHECK-SAME:   offsets = [0, 0]
 //       CHECK:   [[accum1:%.+]] = vector.contract {{{.*}}} [[a]], [[b]], [[c]]
 //  CHECK-SAME:     vector<4x2xf32>, vector<4x2xf32> into vector<4x4xf32>
 
-//       CHECK:   [[a:%.+]] = vector.extract_strided_slice [[arg0]] 
+//       CHECK:   [[a:%.+]] = vector.extract_strided_slice [[arg0]]
 //  CHECK-SAME:   offsets = [0, 2]
-//       CHECK:   [[b:%.+]] = vector.extract_strided_slice [[arg1]] 
+//       CHECK:   [[b:%.+]] = vector.extract_strided_slice [[arg1]]
 //  CHECK-SAME:   offsets = [0, 2]
 //       CHECK:   [[accum2:%.+]] = vector.contract {{{.*}}} [[a]], [[b]], [[accum1]]
 //  CHECK-SAME:     vector<4x2xf32>, vector<4x2xf32> into vector<4x4xf32>
 
-//       CHECK:   [[a:%.+]] = vector.extract_strided_slice [[arg0]] 
+//       CHECK:   [[a:%.+]] = vector.extract_strided_slice [[arg0]]
 //  CHECK-SAME:   offsets = [0, 0]
-//       CHECK:   [[b:%.+]] = vector.extract_strided_slice [[arg1]] 
+//       CHECK:   [[b:%.+]] = vector.extract_strided_slice [[arg1]]
 //  CHECK-SAME:   offsets = [4, 0]
-//       CHECK:   [[c:%.+]] = vector.extract_strided_slice [[arg2]] 
+//       CHECK:   [[c:%.+]] = vector.extract_strided_slice [[arg2]]
 //  CHECK-SAME:   offsets = [0, 4]
 //       CHECK:   [[accum3:%.+]] = vector.contract {{{.*}}} [[a]], [[b]], [[c]]
 //  CHECK-SAME:     vector<4x2xf32>, vector<4x2xf32> into vector<4x4xf32>
 
-//       CHECK:   [[a:%.+]] = vector.extract_strided_slice [[arg0]] 
+//       CHECK:   [[a:%.+]] = vector.extract_strided_slice [[arg0]]
 //  CHECK-SAME:   offsets = [0, 2]
-//       CHECK:   [[b:%.+]] = vector.extract_strided_slice [[arg1]] 
+//       CHECK:   [[b:%.+]] = vector.extract_strided_slice [[arg1]]
 //  CHECK-SAME:   offsets = [4, 2]
 //       CHECK:   [[accum4:%.+]] = vector.contract {{{.*}}} [[a]], [[b]], [[accum3]]
 //  CHECK-SAME:     vector<4x2xf32>, vector<4x2xf32> into vector<4x4xf32>
 
-//       CHECK:   [[a:%.+]] = vector.extract_strided_slice [[arg0]] 
+//       CHECK:   [[a:%.+]] = vector.extract_strided_slice [[arg0]]
 //  CHECK-SAME:   offsets = [4, 0]
-//       CHECK:   [[b:%.+]] = vector.extract_strided_slice [[arg1]] 
+//       CHECK:   [[b:%.+]] = vector.extract_strided_slice [[arg1]]
 //  CHECK-SAME:   offsets = [0, 0]
-//       CHECK:   [[c:%.+]] = vector.extract_strided_slice [[arg2]] 
+//       CHECK:   [[c:%.+]] = vector.extract_strided_slice [[arg2]]
 //  CHECK-SAME:   offsets = [4, 0]
 //       CHECK:   [[accum5:%.+]] = vector.contract {{{.*}}} [[a]], [[b]], [[c]]
 //  CHECK-SAME:     vector<4x2xf32>, vector<4x2xf32> into vector<4x4xf32>
 
-//       CHECK:   [[a:%.+]] = vector.extract_strided_slice [[arg0]] 
+//       CHECK:   [[a:%.+]] = vector.extract_strided_slice [[arg0]]
 //  CHECK-SAME:   offsets = [4, 2]
-//       CHECK:   [[b:%.+]] = vector.extract_strided_slice [[arg1]] 
+//       CHECK:   [[b:%.+]] = vector.extract_strided_slice [[arg1]]
 //  CHECK-SAME:   offsets = [0, 2]
 //       CHECK:   [[accum6:%.+]] = vector.contract {{{.*}}} [[a]], [[b]], [[accum5]]
 //  CHECK-SAME:     vector<4x2xf32>, vector<4x2xf32> into vector<4x4xf32>
 
-//       CHECK:   [[a:%.+]] = vector.extract_strided_slice [[arg0]] 
+//       CHECK:   [[a:%.+]] = vector.extract_strided_slice [[arg0]]
 //  CHECK-SAME:   offsets = [4, 0]
-//       CHECK:   [[b:%.+]] = vector.extract_strided_slice [[arg1]] 
+//       CHECK:   [[b:%.+]] = vector.extract_strided_slice [[arg1]]
 //  CHECK-SAME:   offsets = [4, 0]
-//       CHECK:   [[c:%.+]] = vector.extract_strided_slice [[arg2]] 
+//       CHECK:   [[c:%.+]] = vector.extract_strided_slice [[arg2]]
 //  CHECK-SAME:   offsets = [4, 4]
 //       CHECK:   [[accum7:%.+]] = vector.contract {{{.*}}} [[a]], [[b]], [[c]]
 //  CHECK-SAME:     vector<4x2xf32>, vector<4x2xf32> into vector<4x4xf32>
 
-//       CHECK:   [[a:%.+]] = vector.extract_strided_slice [[arg0]] 
+//       CHECK:   [[a:%.+]] = vector.extract_strided_slice [[arg0]]
 //  CHECK-SAME:   offsets = [4, 2]
-//       CHECK:   [[b:%.+]] = vector.extract_strided_slice [[arg1]] 
+//       CHECK:   [[b:%.+]] = vector.extract_strided_slice [[arg1]]
 //  CHECK-SAME:   offsets = [4, 2]
 //       CHECK:   [[accum8:%.+]] = vector.contract {{{.*}}} [[a]], [[b]], [[accum7]]
 //  CHECK-SAME:     vector<4x2xf32>, vector<4x2xf32> into vector<4x4xf32>
 
 //       CHECK:   return
 
 // ORDER-LABEL: func @vector_contract_f32
 // ORDER-SAME: [[arg0:%.+]]: vector<8x4xf32>, [[arg1:%.+]]: vector<8x4xf32>, [[arg2:%.+]]: vector<8x8xf32>
 
-//       ORDER:   [[a:%.+]] = vector.extract_strided_slice [[arg0]] 
+//       ORDER:   [[a:%.+]] = vector.extract_strided_slice [[arg0]]
 //  ORDER-SAME:   offsets = [0, 0]
-//       ORDER:   [[b:%.+]] = vector.extract_strided_slice [[arg1]] 
+//       ORDER:   [[b:%.+]] = vector.extract_strided_slice [[arg1]]
 //  ORDER-SAME:   offsets = [0, 0]
-//       ORDER:   [[c:%.+]] = vector.extract_strided_slice [[arg2]] 
+//       ORDER:   [[c:%.+]] = vector.extract_strided_slice [[arg2]]
 //  ORDER-SAME:   offsets = [0, 0]
 //       ORDER:   [[accum1:%.+]] = vector.contract {{{.*}}} [[a]], [[b]], [[c]]
 //  ORDER-SAME:     vector<4x2xf32>, vector<4x2xf32> into vector<4x4xf32>
 
-//       ORDER:   [[a:%.+]] = vector.extract_strided_slice [[arg0]] 
+//       ORDER:   [[a:%.+]] = vector.extract_strided_slice [[arg0]]
 //  ORDER-SAME:   offsets = [0, 0]
-//       ORDER:   [[b:%.+]] = vector.extract_strided_slice [[arg1]] 
+//       ORDER:   [[b:%.+]] = vector.extract_strided_slice [[arg1]]
 //  ORDER-SAME:   offsets = [4, 0]
-//       ORDER:   [[c:%.+]] = vector.extract_strided_slice [[arg2]] 
+//       ORDER:   [[c:%.+]] = vector.extract_strided_slice [[arg2]]
 //  ORDER-SAME:   offsets = [0, 4]
 //       ORDER:   [[accum2:%.+]] = vector.contract {{{.*}}} [[a]], [[b]], [[c]]
 //  ORDER-SAME:     vector<4x2xf32>, vector<4x2xf32> into vector<4x4xf32>
 
-//       ORDER:   [[a:%.+]] = vector.extract_strided_slice [[arg0]] 
+//       ORDER:   [[a:%.+]] = vector.extract_strided_slice [[arg0]]
 //  ORDER-SAME:   offsets = [4, 0]
-//       ORDER:   [[b:%.+]] = vector.extract_strided_slice [[arg1]] 
+//       ORDER:   [[b:%.+]] = vector.extract_strided_slice [[arg1]]
 //  ORDER-SAME:   offsets = [0, 0]
-//       ORDER:   [[c:%.+]] = vector.extract_strided_slice [[arg2]] 
+//       ORDER:   [[c:%.+]] = vector.extract_strided_slice [[arg2]]
 //  ORDER-SAME:   offsets = [4, 0]
 //       ORDER:   [[accum3:%.+]] = vector.contract {{{.*}}} [[a]], [[b]], [[c]]
 //  ORDER-SAME:     vector<4x2xf32>, vector<4x2xf32> into vector<4x4xf32>
 
-//       ORDER:   [[a:%.+]] = vector.extract_strided_slice [[arg0]] 
+//       ORDER:   [[a:%.+]] = vector.extract_strided_slice [[arg0]]
 //  ORDER-SAME:   offsets = [4, 0]
-//       ORDER:   [[b:%.+]] = vector.extract_strided_slice [[arg1]] 
+//       ORDER:   [[b:%.+]] = vector.extract_strided_slice [[arg1]]
 //  ORDER-SAME:   offsets = [4, 0]
-//       ORDER:   [[c:%.+]] = vector.extract_strided_slice [[arg2]] 
+//       ORDER:   [[c:%.+]] = vector.extract_strided_slice [[arg2]]
 //  ORDER-SAME:   offsets = [4, 4]
 //       ORDER:   [[accum4:%.+]] = vector.contract {{{.*}}} [[a]], [[b]], [[c]]
 //  ORDER-SAME:     vector<4x2xf32>, vector<4x2xf32> into vector<4x4xf32>
 
-//       ORDER:   [[a:%.+]] = vector.extract_strided_slice [[arg0]] 
+//       ORDER:   [[a:%.+]] = vector.extract_strided_slice [[arg0]]
 //  ORDER-SAME:   offsets = [0, 2]
-//       ORDER:   [[b:%.+]] = vector.extract_strided_slice [[arg1]] 
+//       ORDER:   [[b:%.+]] = vector.extract_strided_slice [[arg1]]
 //  ORDER-SAME:   offsets = [0, 2]
 //       ORDER:   [[accum5:%.+]] = vector.contract {{{.*}}} [[a]], [[b]], [[accum1]]
 //  ORDER-SAME:     vector<4x2xf32>, vector<4x2xf32> into vector<4x4xf32>
 
-//       ORDER:   [[a:%.+]] = vector.extract_strided_slice [[arg0]] 
+//       ORDER:   [[a:%.+]] = vector.extract_strided_slice [[arg0]]
 //  ORDER-SAME:   offsets = [0, 2]
-//       ORDER:   [[b:%.+]] = vector.extract_strided_slice [[arg1]] 
+//       ORDER:   [[b:%.+]] = vector.extract_strided_slice [[arg1]]
 //  ORDER-SAME:   offsets = [4, 2]
 //       ORDER:   [[accum6:%.+]] = vector.contract {{{.*}}} [[a]], [[b]], [[accum2]]
 //  ORDER-SAME:     vector<4x2xf32>, vector<4x2xf32> into vector<4x4xf32>
 
-//       ORDER:   [[a:%.+]] = vector.extract_strided_slice [[arg0]] 
+//       ORDER:   [[a:%.+]] = vector.extract_strided_slice [[arg0]]
 //  ORDER-SAME:   offsets = [4, 2]
-//       ORDER:   [[b:%.+]] = vector.extract_strided_slice [[arg1]] 
+//       ORDER:   [[b:%.+]] = vector.extract_strided_slice [[arg1]]
 //  ORDER-SAME:   offsets = [0, 2]
 //       ORDER:   [[accum7:%.+]] = vector.contract {{{.*}}} [[a]], [[b]], [[accum3]]
 //  ORDER-SAME:     vector<4x2xf32>, vector<4x2xf32> into vector<4x4xf32>
 
-//       ORDER:   [[a:%.+]] = vector.extract_strided_slice [[arg0]] 
+//       ORDER:   [[a:%.+]] = vector.extract_strided_slice [[arg0]]
 //  ORDER-SAME:   offsets = [4, 2]
-//       ORDER:   [[b:%.+]] = vector.extract_strided_slice [[arg1]] 
+//       ORDER:   [[b:%.+]] = vector.extract_strided_slice [[arg1]]
 //  ORDER-SAME:   offsets = [4, 2]
 //       ORDER:   [[accum8:%.+]] = vector.contract {{{.*}}} [[a]], [[b]], [[accum4]]
 //  ORDER-SAME:     vector<4x2xf32>, vector<4x2xf32> into vector<4x4xf32>
 
 //       ORDER:   return
 
 
 

 //       CHECK:   %[[V6:.*]] = vector.insert_strided_slice %[[T6]], %[[V5]] {offsets = [1, 0, 4, 0], strides = [1, 1, 1, 1]} : vector<1x3x4x2xf32> into vector<2x3x8x4xf32>
 //       CHECK:   %[[E7:.*]] = vector.extract_strided_slice %{{.*}} {offsets = [1, 2, 0, 4], sizes = [1, 2, 3, 4], strides = [1, 1, 1, 1]} : vector<2x4x3x8xf32> to vector<1x2x3x4xf32>
 //       CHECK:   %[[T7:.*]] = vector.transpose %[[E7]], [0, 2, 3, 1] : vector<1x2x3x4xf32> to vector<1x3x4x2xf32>
 //       CHECK:   %[[V7:.*]] = vector.insert_strided_slice %[[T7]], %[[V6]] {offsets = [1, 0, 4, 2], strides = [1, 1, 1, 1]} : vector<1x3x4x2xf32> into vector<2x3x8x4xf32>
 //       CHECK:   return %[[V7]] : vector<2x3x8x4xf32>
 
 // -----
 
-func.func @vector_contract_batched(%lhs: vector<8x8x4xf32>, %rhs: vector<8x8x4xf32>, %init: vector<8x8x8xf32>) -> vector<8x8x8xf32> {    
+func.func @vector_contract_batched(%lhs: vector<8x8x4xf32>, %rhs: vector<8x8x4xf32>, %init: vector<8x8x8xf32>) -> vector<8x8x8xf32> {
   %0 = vector.contract
          {indexing_maps = [affine_map<(d0,d1,d2,c0) -> (d0,d1,c0)>,
                            affine_map<(d0,d1,d2,c0) -> (d0,d2,c0)>,
                            affine_map<(d0,d1,d2,c0) -> (d0,d1,d2)>],
           iterator_types = ["parallel", "parallel", "parallel", "reduction"]}
        %lhs, %rhs, %init : vector<8x8x4xf32>, vector<8x8x4xf32> into vector<8x8x8xf32>
   return %0 : vector<8x8x8xf32>
 }
 
 
 //    CHECK-LABEL: vector_contract_batched
 // CHECK-COUNT-16: vector.contract
 //      CHECK-NOT: vector.contract
-//          CHECK: return 
+//          CHECK: return
 
 //    UNROLL-LABEL: vector_contract_batched
 //  UNROLL-COUNT-1: vector.contract
 //      UNROLL-NOT: vector.contract
 //          UNROLL: return
 
 
 //    BATCHED-LABEL: vector_contract_batched
 // BATCHED-COUNT-16: vector.contract
 //      BATCHED-NOT: vector.contract
 //          BATCHED: return

mlir/test/Dialect/Vector/vector-warp-distribute.mlir

%r = vector.warp_execute_on_lane_0(%laneid)[32] -> (vector<1xf32>) {
     vector.yield %2 : vector<32xf32>
   }
   return %r : vector<1xf32>
 }
 
 // -----
 
 // CHECK-PROP:   func @dedup
-func.func @dedup(%laneid: index, %v0: vector<4xf32>, %v1: vector<4xf32>) 
+func.func @dedup(%laneid: index, %v0: vector<4xf32>, %v1: vector<4xf32>)
     -> (vector<1xf32>, vector<1xf32>) {
 
   // CHECK-PROP: %[[SINGLE_RES:.*]] = vector.warp_execute_on_lane_0{{.*}} -> (vector<1xf32>) {
   %r:2 = vector.warp_execute_on_lane_0(%laneid)[32]
       args(%v0, %v1 : vector<4xf32>, vector<4xf32>) -> (vector<1xf32>, vector<1xf32>) {
     ^bb0(%arg0: vector<128xf32>, %arg1: vector<128xf32>):
 
     // CHECK-PROP: %[[SINGLE_VAL:.*]] = "some_def"(%{{.*}}) : (vector<128xf32>) -> vector<32xf32>
     %2 = "some_def"(%arg0) : (vector<128xf32>) -> vector<32xf32>
 
     // CHECK-PROP: vector.yield %[[SINGLE_VAL]] : vector<32xf32>
     vector.yield %2, %2 : vector<32xf32>, vector<32xf32>
   }
 
   // CHECK-PROP: return %[[SINGLE_RES]], %[[SINGLE_RES]] : vector<1xf32>, vector<1xf32>
   return %r#0, %r#1 : vector<1xf32>, vector<1xf32>
 }
 
 // -----
 
 // CHECK-SCF-IF:   func @warp_execute_has_broadcast_semantics
-func.func @warp_execute_has_broadcast_semantics(%laneid: index, %s0: f32, %v0: vector<f32>, %v1: vector<1xf32>, %v2: vector<1x1xf32>) 
+func.func @warp_execute_has_broadcast_semantics(%laneid: index, %s0: f32, %v0: vector<f32>, %v1: vector<1xf32>, %v2: vector<1x1xf32>)
     -> (f32, vector<f32>, vector<1xf32>, vector<1x1xf32>) {
   // CHECK-SCF-IF-DAG: %[[C0:.*]] = arith.constant 0 : index
 
   // CHECK-SCF-IF: scf.if{{.*}}{
   %r:4 = vector.warp_execute_on_lane_0(%laneid)[32]
       args(%s0, %v0, %v1, %v2 : f32, vector<f32>, vector<1xf32>, vector<1x1xf32>) -> (f32, vector<f32>, vector<1xf32>, vector<1x1xf32>) {
     ^bb0(%bs0: f32, %bv0: vector<f32>, %bv1: vector<1xf32>, %bv2: vector<1x1xf32>):
 

 }
 
 // -----
 
 // CHECK-SCF-IF-DAG: #[[$TIMES2:.*]] = affine_map<()[s0] -> (s0 * 2)>
 
 // CHECK-SCF-IF:   func @warp_execute_nd_distribute
 // CHECK-SCF-IF-SAME: (%[[LANEID:.*]]: index
-func.func @warp_execute_nd_distribute(%laneid: index, %v0: vector<1x64x1xf32>, %v1: vector<1x2x128xf32>) 
+func.func @warp_execute_nd_distribute(%laneid: index, %v0: vector<1x64x1xf32>, %v1: vector<1x2x128xf32>)
     -> (vector<1x64x1xf32>, vector<1x2x128xf32>) {
   // CHECK-SCF-IF-DAG: %[[C0:.*]] = arith.constant 0 : index
 
   // CHECK-SCF-IF:  vector.transfer_write %{{.*}}, %{{.*}}[%[[LANEID]], %c0, %c0] {in_bounds = [true, true, true]} : vector<1x64x1xf32>, memref<32x64x1xf32, 3>
   // CHECK-SCF-IF:  %[[RID:.*]] = affine.apply #[[$TIMES2]]()[%[[LANEID]]]
   // CHECK-SCF-IF:  vector.transfer_write %{{.*}}, %{{.*}}[%[[C0]], %[[RID]], %[[C0]]] {in_bounds = [true, true, true]} : vector<1x2x128xf32>, memref<1x64x128xf32, 3>
   // CHECK-SCF-IF:  gpu.barrier
 

mlir/test/IR/invalid-affinemap.mlir

 
 // -----
 #hello_world = affine_map<(i, j) [s0] -> ((s0 + i, j)> // expected-error {{expected ')'}}
 
 // -----
 #hello_world = affine_map<(i, j) [s0] -> (((s0 + (i + j) + 5), j)> // expected-error {{expected ')'}}
 
 // -----
- 
 // expected-error @+1 {{expected '(' in affine map range}}
 #hello_world = affine_map<(i, j) [s0] -> i + s0, j)>
 
 // -----
 #hello_world = affine_map<(i, j) [s0] -> (x)> // expected-error {{use of undeclared identifier}}
 
 // -----
 #hello_world = affine_map<(i, j, i) [s0] -> (i)> // expected-error {{redefinition of identifier 'i'}}

mlir/test/IR/invalid-locations.mlir

^bb:
   return loc(fused<true [unknown]) // expected-error {{expected '>' after fused location metadata}}
 }
 
 // -----
 
 func.func @location_fused_missing_metadata() {
 ^bb:
   // expected-error@+1 {{expected attribute value}}
-  return loc(fused<) 
+  return loc(fused<)
 }
 
 // -----
 
 func.func @location_fused_missing_l_square() {
 ^bb:
   return loc(fused<true>unknown]) // expected-error {{expected '[' in fused location}}
 }

mlir/test/IR/invalid.mlir

 "t"(){""}
 
 // -----
 
 // This makes sure we emit an error at the end of the correct line, the : is
 // expected at the end of foo, not on the return line.
 func.func @error_at_end_of_line() {
   // expected-error@+1 {{expected ':' followed by operation type}}
-  %0 = "foo"() 
+  %0 = "foo"()
   return
 }
 
 // -----
 
 // This makes sure we emit an error at the end of the correct line, the : is
 // expected at the end of foo, not on the return line.
 func.func @error_at_end_of_line() {
-  %0 = "foo"() 
+  %0 = "foo"()
   // expected-error@-1 {{expected ':' followed by operation type}}
 
   // This is a comment and so is the thing above.
   return
 }
 
 // -----
 

mlir/test/IR/print-value-users.mlir

 // RUN: mlir-opt -allow-unregistered-dialect -mlir-print-value-users -split-input-file %s | FileCheck %s
 
 module {
     // CHECK: %[[ARG0:.+]]: i32, %[[ARG1:.+]]: i32, %[[ARG2:.+]]: i32
     func.func @foo(%arg0: i32, %arg1: i32, %arg3: i32) -> i32 {
         // CHECK-NEXT: // %[[ARG0]] is used by %[[ARG0U1:.+]], %[[ARG0U2:.+]], %[[ARG0U3:.+]]
         // CHECK-NEXT: // %[[ARG1]] is used by %[[ARG1U1:.+]], %[[ARG1U2:.+]]
         // CHECK-NEXT: // %[[ARG2]] is unused
         // CHECK-NEXT: test.noop
         // CHECK-NOT: // unused
         "test.noop"() : () -> ()
         // When no result is produced, an id should be printed.
         // CHECK-NEXT: // id: %[[ARG0U3]]
         "test.no_result"(%arg0) {} : (i32) -> ()
         // Check for unused result.
-        // CHECK-NEXT: %[[ARG0U2]] = 
+        // CHECK-NEXT: %[[ARG0U2]] =
         // CHECK-SAME: // unused
         %1 = "test.unused_result"(%arg0, %arg1) {} : (i32, i32) -> i32
         // Check that both users are printed.
-        // CHECK-NEXT: %[[ARG0U1]] = 
+        // CHECK-NEXT: %[[ARG0U1]] =
         // CHECK-SAME: // users: %[[A:.+]]#0, %[[A]]#1
         %2 = "test.one_result"(%arg0, %arg1) {} : (i32, i32) -> i32
         // For multiple results, users should be grouped per result.
-        // CHECK-NEXT: %[[A]]:2 = 
+        // CHECK-NEXT: %[[A]]:2 =
         // CHECK-SAME: // users: (%[[B:.+]], %[[C:.+]]), (%[[B]], %[[D:.+]])
         %3:2 = "test.many_results"(%2) {} : (i32) -> (i32, i32)
         // Two results are produced, but there is only one user.
         // CHECK-NEXT: // users:
         %7:2 = "test.many_results"() : () -> (i32, i32)
         // CHECK-NEXT: %[[C]] =
         // Result is used twice in next operation but it produces only one result.
         // CHECK-SAME: // user:

mlir/test/IR/test-clone.mlir

-// RUN: mlir-opt -allow-unregistered-dialect %s -pass-pipeline="builtin.module(func.func(test-clone))" -split-input-file 
+// RUN: mlir-opt -allow-unregistered-dialect %s -pass-pipeline="builtin.module(func.func(test-clone))" -split-input-file
 
 module {
   func.func @fixpoint(%arg1 : i32) -> i32 {
     %r = "test.use"(%arg1) ({
        "test.yield"(%arg1) : (i32) -> ()
     }) : (i32) -> i32
     return %r : i32
   }

mlir/test/IR/test-take-body.mlir

 // RUN: mlir-opt -allow-unregistered-dialect %s --test-take-body -split-input-file
 
 func.func @foo() {
   %0 = "test.foo"() : () -> i32
   cf.br ^header
-  
 ^header:
   cf.br ^body
 
 ^body:
   "test.use"(%0) : (i32) -> ()
   cf.br ^header
 }
 

mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_binary.mlir

func.func @dump_mat_4x4_i8(%A: tensor<4x4xi8, #DCSR>) {
 
     %c = sparse_tensor.convert %A : tensor<4x4xi8, #DCSR> to tensor<4x4xi8>
     %v = vector.transfer_read %c[%c0, %c0], %du: tensor<4x4xi8>, vector<4x4xi8>
     vector.print %v : vector<4x4xi8>
 
     %1 = sparse_tensor.values %A : tensor<4x4xi8, #DCSR> to memref<?xi8>
     %2 = vector.transfer_read %1[%c0], %du: memref<?xi8>, vector<16xi8>
     vector.print %2 : vector<16xi8>
-  
     return
   }
 
   // Driver method to call and verify kernels.
   func.func @entry() {
     %c0 = arith.constant 0 : index
 
     // Setup sparse vectors.

mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_codegen_foreach.mlir

func.func @foreach_print_dense(%arg0: tensor<2x2xf64>) {
     sparse_tensor.foreach in %arg0 : tensor<2x2xf64> do {
     ^bb0(%1: index, %2: index, %v: f64) :
       vector.print %1: index
       vector.print %2: index
       vector.print %v: f64
    }
    return
   }
-  
   //
   // Main driver.
   //
   func.func @entry() {
     //
     // Initialize a 3-dim dense tensor.
     //
     %src = arith.constant dense<
        [[  1.0,  2.0],
         [  5.0,  6.0]]
     > : tensor<2x2xf64>
-    
     %src3d = arith.constant sparse<
-       [[1, 2, 3], [4, 5, 6]], [1.0, 2.0] 
+       [[1, 2, 3], [4, 5, 6]], [1.0, 2.0]
     > : tensor<7x8x9xf64>
-    
     //
     // Convert dense tensor directly to various sparse tensors.
     //
     %s1 = sparse_tensor.convert %src : tensor<2x2xf64> to tensor<2x2xf64, #Row>
     %s2 = sparse_tensor.convert %src : tensor<2x2xf64> to tensor<2x2xf64, #CSR>
     %s3 = sparse_tensor.convert %src : tensor<2x2xf64> to tensor<2x2xf64, #DCSC>
     %s4 = sparse_tensor.convert %src : tensor<2x2xf64> to tensor<2x2xf64, #SortedCOO>
     %s5 = sparse_tensor.convert %src : tensor<2x2xf64> to tensor<2x2xf64, #SortedCOOPerm>
func.func @entry() {
     // CHECK-NEXT: 0
     // CHECK-NEXT: 1
     // CHECK-NEXT: 2
     // CHECK-NEXT: 1
     // CHECK-NEXT: 0
     // CHECK-NEXT: 5
     // CHECK-NEXT: 1
     // CHECK-NEXT: 1
-    // CHECK-NEXT: 6    
+    // CHECK-NEXT: 6
     call @foreach_print_dense(%src) : (tensor<2x2xf64>) -> ()
     // CHECK-NEXT: 0
     // CHECK-NEXT: 0
     // CHECK-NEXT: 1
     // CHECK-NEXT: 0
     // CHECK-NEXT: 1
     // CHECK-NEXT: 2
     // CHECK-NEXT: 1
func.func @entry() {
     // CHECK-NEXT: 2
     // CHECK-NEXT: 3
     // CHECK-NEXT: 1
     // CHECK-NEXT: 4
     // CHECK-NEXT: 5
     // CHECK-NEXT: 6
     // CHECK-NEXT: 2
     call @foreach_print_3d(%s6): (tensor<7x8x9xf64, #CCCPerm>) -> ()
-    
     bufferization.dealloc_tensor %s1 : tensor<2x2xf64, #Row>
     bufferization.dealloc_tensor %s2 : tensor<2x2xf64, #CSR>
     bufferization.dealloc_tensor %s3 : tensor<2x2xf64, #DCSC>
     bufferization.dealloc_tensor %s4 : tensor<2x2xf64, #SortedCOO>
     bufferization.dealloc_tensor %s5 : tensor<2x2xf64, #SortedCOOPerm>
     bufferization.dealloc_tensor %s6 : tensor<7x8x9xf64, #CCCPerm>
 
     return
   }
 }

mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conv_1d_nwc_wcf.mlir

func.func @entry() {
   %v2 = vector.transfer_read %2[%c0, %c0, %c0], %zero
       : tensor<?x?x?xf32>, vector<3x6x1xf32>
   vector.print %v2 : vector<3x6x1xf32>
 
   // Free the resources
   bufferization.dealloc_tensor %in1D_nwc : tensor<?x?x?xf32>
   bufferization.dealloc_tensor %filter1D_nwc : tensor<?x?x?xf32>
   bufferization.dealloc_tensor %out1D_nwc : tensor<?x?x?xf32>
-  
   bufferization.dealloc_tensor %in1D_nwc_CDC : tensor<?x?x?xf32, #CDC>
   bufferization.dealloc_tensor %filter1D_nwc_CDC : tensor<?x?x?xf32, #CDC>
   bufferization.dealloc_tensor %in1D_nwc_CCC : tensor<?x?x?xf32, #CCC>
   bufferization.dealloc_tensor %filter1D_nwc_CCC : tensor<?x?x?xf32, #CCC>
 
   bufferization.dealloc_tensor %CCC_ret : tensor<?x?x?xf32, #CCC>
   bufferization.dealloc_tensor %CDC_ret : tensor<?x?x?xf32, #CDC>
-  
   return
 }

mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conv_2d.mlir

func.func @conv2d(%input:  tensor<8x8xi32>,
     %0 = linalg.conv_2d
       ins  (%input, %filter: tensor<8x8xi32>, tensor<3x3xi32, #DCSR>)
       outs (%output: tensor<6x6xi32>) -> tensor<6x6xi32>
     return %0 : tensor<6x6xi32>
   }
 
   func.func @conv2d_sparse_out(%input:  tensor<8x8xi32>,
                %filter: tensor<3x3xi32, #DCSR>) -> tensor<6x6xi32, #DCSR> {
-    %s = bufferization.alloc_tensor() : tensor<6x6xi32, #DCSR>           
+    %s = bufferization.alloc_tensor() : tensor<6x6xi32, #DCSR>
     %0 = linalg.conv_2d
       ins  (%input, %filter: tensor<8x8xi32>, tensor<3x3xi32, #DCSR>)
       outs (%s: tensor<6x6xi32, #DCSR>) -> tensor<6x6xi32, #DCSR>
     return %0 : tensor<6x6xi32, #DCSR>
   }
 
   func.func @conv2d_all_sparse_DCSR(%input:  tensor<8x8xi32, #DCSR>,
                %filter: tensor<3x3xi32, #DCSR>) -> tensor<6x6xi32, #DCSR> {
-    %s = bufferization.alloc_tensor() : tensor<6x6xi32, #DCSR>           
+    %s = bufferization.alloc_tensor() : tensor<6x6xi32, #DCSR>
     %0 = linalg.conv_2d
       ins  (%input, %filter: tensor<8x8xi32, #DCSR>, tensor<3x3xi32, #DCSR>)
       outs (%s: tensor<6x6xi32, #DCSR>) -> tensor<6x6xi32, #DCSR>
     return %0 : tensor<6x6xi32, #DCSR>
   }
 
   func.func @conv2d_all_sparse_CSR(%input:  tensor<8x8xi32, #CSR>,
                %filter: tensor<3x3xi32, #CSR>) -> tensor<6x6xi32, #CSR> {
-    %s = bufferization.alloc_tensor() : tensor<6x6xi32, #CSR>           
+    %s = bufferization.alloc_tensor() : tensor<6x6xi32, #CSR>
     %0 = linalg.conv_2d
       ins  (%input, %filter: tensor<8x8xi32, #CSR>, tensor<3x3xi32, #CSR>)
       outs (%s: tensor<6x6xi32, #CSR>) -> tensor<6x6xi32, #CSR>
     return %0 : tensor<6x6xi32, #CSR>
   }
-  
   func.func @conv2d_all_sparse_CSC(%input:  tensor<8x8xi32, #CSC>,
                %filter: tensor<3x3xi32, #CSC>) -> tensor<6x6xi32, #CSC> {
-    %s = bufferization.alloc_tensor() : tensor<6x6xi32, #CSC>           
+    %s = bufferization.alloc_tensor() : tensor<6x6xi32, #CSC>
     %0 = linalg.conv_2d
       ins  (%input, %filter: tensor<8x8xi32, #CSC>, tensor<3x3xi32, #CSC>)
       outs (%s: tensor<6x6xi32, #CSC>) -> tensor<6x6xi32, #CSC>
     return %0 : tensor<6x6xi32, #CSC>
   }
 
   func.func @entry() {
     %c0 = arith.constant 0 : index
%input = arith.constant dense<[
       [  1,  3,  3,  4,  3,  0,  7,  8 ]
     ]> : tensor<8x8xi32>
     %sparse_input_DCSR = sparse_tensor.convert %input
       : tensor<8x8xi32> to tensor<8x8xi32, #DCSR>
     %sparse_input_CSR = sparse_tensor.convert %input
       : tensor<8x8xi32> to tensor<8x8xi32, #CSR>
     %sparse_input_CSC = sparse_tensor.convert %input
       : tensor<8x8xi32> to tensor<8x8xi32, #CSC>
-      
     // Call the kernel.
     %output = arith.constant dense<0> : tensor<6x6xi32>
     %0 = call @conv2d(%input, %sparse_filter_DCSR, %output)
        : (tensor<8x8xi32>,
           tensor<3x3xi32, #DCSR>, tensor<6x6xi32>) -> tensor<6x6xi32>
     %1 = call @conv2d_sparse_out(%input, %sparse_filter_DCSR)
        : (tensor<8x8xi32>,
           tensor<3x3xi32, #DCSR>) -> tensor<6x6xi32, #DCSR>
     %2 = call @conv2d_all_sparse_DCSR(%sparse_input_DCSR, %sparse_filter_DCSR)
        : (tensor<8x8xi32, #DCSR>,
           tensor<3x3xi32, #DCSR>) -> tensor<6x6xi32, #DCSR>
     %3 = call @conv2d_all_sparse_CSR(%sparse_input_CSR, %sparse_filter_CSR)
        : (tensor<8x8xi32, #CSR>,
           tensor<3x3xi32, #CSR>) -> tensor<6x6xi32, #CSR>
     %4 = call @conv2d_all_sparse_CSC(%sparse_input_CSC, %sparse_filter_CSC)
        : (tensor<8x8xi32, #CSC>,
           tensor<3x3xi32, #CSC>) -> tensor<6x6xi32, #CSC>
-          
- 
     // Verify the output.
     //
     // CHECK:    ( ( 0, 0, -1, -6, -1, 6 ),
     // CHECK-SAME: ( -1, 0, 1, 0, 1, 0 ),
     // CHECK-SAME: ( 0, -1, 1, 0, 0, 0 ),
     // CHECK-SAME: ( -1, 0, 0, 0, 0, 0 ),
     // CHECK-SAME: ( 0, 0, 3, 6, -3, -6 ),
     // CHECK-SAME: ( 2, -1, 3, 0, -3, 0 ) )
func.func @entry() {
     // CHECK-SAME: ( 0, 0, 3, 6, -3, -6 ),
     // CHECK-SAME: ( 2, -1, 3, 0, -3, 0 ) )
     //
     %sparse_ret = sparse_tensor.convert %1
       : tensor<6x6xi32, #DCSR> to tensor<6x6xi32>
     %v1 = vector.transfer_read %sparse_ret[%c0, %c0], %i0
       : tensor<6x6xi32>, vector<6x6xi32>
     vector.print %v1 : vector<6x6xi32>
-    
     //
     // Should be the same as dense output
     // CHECK:    ( ( 0, 0, -1, -6, -1, 6 ),
     // CHECK-SAME: ( -1, 0, 1, 0, 1, 0 ),
     // CHECK-SAME: ( 0, -1, 1, 0, 0, 0 ),
     // CHECK-SAME: ( -1, 0, 0, 0, 0, 0 ),
     // CHECK-SAME: ( 0, 0, 3, 6, -3, -6 ),
     // CHECK-SAME: ( 2, -1, 3, 0, -3, 0 ) )
     //
     %all_sparse_DCSR = sparse_tensor.convert %2
       : tensor<6x6xi32, #DCSR> to tensor<6x6xi32>
     %v2 = vector.transfer_read %all_sparse_DCSR[%c0, %c0], %i0
       : tensor<6x6xi32>, vector<6x6xi32>
     vector.print %v2 : vector<6x6xi32>
-    
     //
     // Should be the same as dense output
     // CHECK:    ( ( 0, 0, -1, -6, -1, 6 ),
     // CHECK-SAME: ( -1, 0, 1, 0, 1, 0 ),
     // CHECK-SAME: ( 0, -1, 1, 0, 0, 0 ),
     // CHECK-SAME: ( -1, 0, 0, 0, 0, 0 ),
     // CHECK-SAME: ( 0, 0, 3, 6, -3, -6 ),
     // CHECK-SAME: ( 2, -1, 3, 0, -3, 0 ) )
     //
     %all_sparse_CSR = sparse_tensor.convert %3
       : tensor<6x6xi32, #CSR> to tensor<6x6xi32>
     %v3 = vector.transfer_read %all_sparse_CSR[%c0, %c0], %i0
       : tensor<6x6xi32>, vector<6x6xi32>
     vector.print %v3 : vector<6x6xi32>
-    
     //
     // Should be the same as dense output
     // CHECK:    ( ( 0, 0, -1, -6, -1, 6 ),
     // CHECK-SAME: ( -1, 0, 1, 0, 1, 0 ),
     // CHECK-SAME: ( 0, -1, 1, 0, 0, 0 ),
     // CHECK-SAME: ( -1, 0, 0, 0, 0, 0 ),
     // CHECK-SAME: ( 0, 0, 3, 6, -3, -6 ),
     // CHECK-SAME: ( 2, -1, 3, 0, -3, 0 ) )
     //
     %all_sparse_CSC = sparse_tensor.convert %4
       : tensor<6x6xi32, #CSC> to tensor<6x6xi32>
     %v4 = vector.transfer_read %all_sparse_CSC[%c0, %c0], %i0
       : tensor<6x6xi32>, vector<6x6xi32>
     vector.print %v4 : vector<6x6xi32>
-    
     // Release the resources.
     bufferization.dealloc_tensor %sparse_filter_DCSR : tensor<3x3xi32, #DCSR>
     bufferization.dealloc_tensor %sparse_filter_CSR : tensor<3x3xi32, #CSR>
     bufferization.dealloc_tensor %sparse_filter_CSC : tensor<3x3xi32, #CSC>
-    
     bufferization.dealloc_tensor %sparse_input_DCSR : tensor<8x8xi32, #DCSR>
     bufferization.dealloc_tensor %sparse_input_CSR : tensor<8x8xi32, #CSR>
     bufferization.dealloc_tensor %sparse_input_CSC : tensor<8x8xi32, #CSC>
 
     bufferization.dealloc_tensor %1 : tensor<6x6xi32, #DCSR>
     bufferization.dealloc_tensor %2 : tensor<6x6xi32, #DCSR>
     bufferization.dealloc_tensor %3 : tensor<6x6xi32, #CSR>
     bufferization.dealloc_tensor %4 : tensor<6x6xi32, #CSC>
     return
   }
 }

mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conv_2d_nhwc_hwcf.mlir

func.func @entry() {
   %in2D_nhwc_CDCD = sparse_tensor.convert %in2D_nhwc
     : tensor<?x?x?x?xf32> to tensor<?x?x?x?xf32, #CDCD>
   %filter2D_nhwc_CDCD = sparse_tensor.convert %filter2D_nhwc
     : tensor<?x?x?x?xf32> to tensor<?x?x?x?xf32, #CDCD>
 
   %dense_ret = call @conv_2d_nhwc_hwcf(%in2D_nhwc, %filter2D_nhwc, %out2D_nhwc) : (tensor<?x?x?x?xf32>, tensor<?x?x?x?xf32>, tensor<?x?x?x?xf32>) -> (tensor<?x?x?x?xf32>)
   %CCCC_ret = call @conv_2d_nhwc_hwcf_CCCC(%in2D_nhwc_CCCC, %filter2D_nhwc_CCCC) : (tensor<?x?x?x?xf32, #CCCC>, tensor<?x?x?x?xf32, #CCCC>) -> (tensor<?x?x?x?xf32, #CCCC>)
   %CDCD_ret = call @conv_2d_nhwc_hwcf_CDCD(%in2D_nhwc_CDCD, %filter2D_nhwc_CDCD) : (tensor<?x?x?x?xf32, #CDCD>, tensor<?x?x?x?xf32, #CDCD>) -> (tensor<?x?x?x?xf32, #CDCD>)
-  
   // CHECK:     ( ( ( ( 108 ), ( 124 ), ( 124 ), ( 124 ), ( 108 ), ( 108 ) ),
   // CHECK-SAME:    ( ( 108 ), ( 108 ), ( 108 ), ( 108 ), ( 108 ), ( 108 ) ),
   // CHECK-SAME:    ( ( 108 ), ( 108 ), ( 108 ), ( 108 ), ( 108 ), ( 108 ) ),
   // CHECK-SAME:    ( ( 108 ), ( 108 ), ( 108 ), ( 108 ), ( 108 ), ( 108 ) ),
   // CHECK-SAME:    ( ( 108 ), ( 108 ), ( 108 ), ( 108 ), ( 108 ), ( 108 ) ),
   // CHECK-SAME:    ( ( 108 ), ( 108 ), ( 108 ), ( 108 ), ( 108 ), ( 108 ) ) ),
   // CHECK-SAME:  ( ( ( 108 ), ( 108 ), ( 108 ), ( 108 ), ( 108 ), ( 108 ) ),
   // CHECK-SAME:    ( ( 108 ), ( 108 ), ( 108 ), ( 108 ), ( 108 ), ( 108 ) ),
func.func @entry() {
   %v2 = vector.transfer_read %2[%c0, %c0, %c0, %c0], %zero
       : tensor<?x?x?x?xf32>, vector<3x6x6x1xf32>
   vector.print %v2 : vector<3x6x6x1xf32>
 
   // Free the resources
   bufferization.dealloc_tensor %in2D_nhwc : tensor<?x?x?x?xf32>
   bufferization.dealloc_tensor %filter2D_nhwc : tensor<?x?x?x?xf32>
   bufferization.dealloc_tensor %out2D_nhwc : tensor<?x?x?x?xf32>
-  
   bufferization.dealloc_tensor %in2D_nhwc_CDCD : tensor<?x?x?x?xf32, #CDCD>
   bufferization.dealloc_tensor %filter2D_nhwc_CDCD : tensor<?x?x?x?xf32, #CDCD>
   bufferization.dealloc_tensor %in2D_nhwc_CCCC : tensor<?x?x?x?xf32, #CCCC>
   bufferization.dealloc_tensor %filter2D_nhwc_CCCC : tensor<?x?x?x?xf32, #CCCC>
 
   bufferization.dealloc_tensor %CCCC_ret : tensor<?x?x?x?xf32, #CCCC>
   bufferization.dealloc_tensor %CDCD_ret : tensor<?x?x?x?xf32, #CDCD>
-  
   return
 }

mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conv_3d.mlir

func.func @entry() {
   // CHECK-SAME:    ( 108, 108, 108, 108, 108, 108 ),
   // CHECK-SAME:    ( 108, 108, 108, 108, 108, 108 ),
   // CHECK-SAME:    ( 108, 108, 108, 108, 108, 108 ) ) )
   %2 = sparse_tensor.convert %CCC_ret
     : tensor<?x?x?xf32, #CCC> to tensor<?x?x?xf32>
   %v2 = vector.transfer_read %2[%c0, %c0, %c0], %zero
       : tensor<?x?x?xf32>, vector<6x6x6xf32>
   vector.print %v2 : vector<6x6x6xf32>
-  
   // Free the resources
   bufferization.dealloc_tensor %in3D : tensor<?x?x?xf32>
   bufferization.dealloc_tensor %filter3D : tensor<?x?x?xf32>
   bufferization.dealloc_tensor %out3D : tensor<?x?x?xf32>
-  
   bufferization.dealloc_tensor %in3D_CDC : tensor<?x?x?xf32, #CDC>
   bufferization.dealloc_tensor %filter3D_CDC : tensor<?x?x?xf32, #CDC>
   bufferization.dealloc_tensor %in3D_CCC : tensor<?x?x?xf32, #CCC>
   bufferization.dealloc_tensor %filter3D_CCC : tensor<?x?x?xf32, #CCC>
 
   bufferization.dealloc_tensor %CCC_ret : tensor<?x?x?xf32, #CCC>
   bufferization.dealloc_tensor %CDC_ret : tensor<?x?x?xf32, #CDC>
 
   return
 }

mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conv_3d_ndhwc_dhwcf.mlir

func.func @entry() {
   %c0 = arith.constant 0 : index
   %c1 = arith.constant 1 : index
   %c3 = arith.constant 3 : index
   %c6 = arith.constant 6 : index
   %c8 = arith.constant 8 : index
   %f10 = arith.constant 10.00000e+00 : f32
   %val = arith.constant 2.00000e+00 : f32
   %zero = arith.constant 0.00000e+00 : f32
-  
   %in3D_tmp = call @alloc_5d_filled_f32(%c1, %c8, %c8, %c8, %c1, %val) : (index, index, index, index, index, f32) -> (tensor<?x?x?x?x?xf32>)
   %in3D_ndhwc = tensor.insert %f10 into %in3D_tmp[%c0, %c0, %c0, %c3, %c0] : tensor<?x?x?x?x?xf32>
-  
   %filter3D_ndhwc = call @alloc_5d_filled_f32(%c3, %c3, %c3, %c1, %c1, %val) : (index, index, index, index, index, f32) -> (tensor<?x?x?x?x?xf32>)
   %out3D_ndhwc = call @alloc_5d_filled_f32(%c1, %c6, %c6, %c6, %c1, %zero) : (index, index, index, index, index, f32) -> (tensor<?x?x?x?x?xf32>)
 
   %in3D_ndhwc_CCCCC = sparse_tensor.convert %in3D_ndhwc
     : tensor<?x?x?x?x?xf32> to tensor<?x?x?x?x?xf32, #CCCCC>
   %filter3D_ndhwc_CCCCC = sparse_tensor.convert %filter3D_ndhwc
     : tensor<?x?x?x?x?xf32> to tensor<?x?x?x?x?xf32, #CCCCC>
 
   %in3D_ndhwc_CDCDC = sparse_tensor.convert %in3D_ndhwc
     : tensor<?x?x?x?x?xf32> to tensor<?x?x?x?x?xf32, #CDCDC>
   %filter3D_ndhwc_CDCDC = sparse_tensor.convert %filter3D_ndhwc
     : tensor<?x?x?x?x?xf32> to tensor<?x?x?x?x?xf32, #CDCDC>
-    
   //      CHECK:( ( ( ( ( 108 ), ( 124 ), ( 124 ), ( 124 ), ( 108 ), ( 108 ) ),
   // CHECK-SAME:      ( ( 108 ), ( 108 ), ( 108 ), ( 108 ), ( 108 ), ( 108 ) ),
   // CHECK-SAME:      ( ( 108 ), ( 108 ), ( 108 ), ( 108 ), ( 108 ), ( 108 ) ),
   // CHECK-SAME:      ( ( 108 ), ( 108 ), ( 108 ), ( 108 ), ( 108 ), ( 108 ) ),
   // CHECK-SAME:      ( ( 108 ), ( 108 ), ( 108 ), ( 108 ), ( 108 ), ( 108 ) ),
   // CHECK-SAME:      ( ( 108 ), ( 108 ), ( 108 ), ( 108 ), ( 108 ), ( 108 ) ) ),
   // CHECK-SAME:    ( ( ( 108 ), ( 108 ), ( 108 ), ( 108 ), ( 108 ), ( 108 ) ),
   // CHECK-SAME:      ( ( 108 ), ( 108 ), ( 108 ), ( 108 ), ( 108 ), ( 108 ) ),
func.func @entry() {
   // CHECK-SAME:      ( ( 108 ), ( 108 ), ( 108 ), ( 108 ), ( 108 ), ( 108 ) ) ),
   // CHECK-SAME:    ( ( ( 108 ), ( 108 ), ( 108 ), ( 108 ), ( 108 ), ( 108 ) ),
   // CHECK-SAME:      ( ( 108 ), ( 108 ), ( 108 ), ( 108 ), ( 108 ), ( 108 ) ),
   // CHECK-SAME:      ( ( 108 ), ( 108 ), ( 108 ), ( 108 ), ( 108 ), ( 108 ) ),
   // CHECK-SAME:      ( ( 108 ), ( 108 ), ( 108 ), ( 108 ), ( 108 ), ( 108 ) ),
   // CHECK-SAME:      ( ( 108 ), ( 108 ), ( 108 ), ( 108 ), ( 108 ), ( 108 ) ),
   // CHECK-SAME:      ( ( 108 ), ( 108 ), ( 108 ), ( 108 ), ( 108 ), ( 108 ) ) ) ) )
   %1 = sparse_tensor.convert %CCCCC_ret
-    : tensor<?x?x?x?x?xf32, #CCCCC> to tensor<?x?x?x?x?xf32>         
+    : tensor<?x?x?x?x?xf32, #CCCCC> to tensor<?x?x?x?x?xf32>
   %v1 = vector.transfer_read %1[%c0, %c0, %c0, %c0, %c0], %zero
       : tensor<?x?x?x?x?xf32>, vector<1x6x6x6x1xf32>
   vector.print %v1 : vector<1x6x6x6x1xf32>
 
   %CDCDC_ret = call @conv_3d_ndhwc_dhwcf_CDCDC(%in3D_ndhwc_CDCDC, %filter3D_ndhwc_CDCDC)
       : (tensor<?x?x?x?x?xf32, #CDCDC>,
          tensor<?x?x?x?x?xf32, #CDCDC>) -> (tensor<?x?x?x?x?xf32, #CDCDC>)
 
func.func @entry() {
   // CHECK-SAME:      ( ( 108 ), ( 108 ), ( 108 ), ( 108 ), ( 108 ), ( 108 ) ),
   // CHECK-SAME:      ( ( 108 ), ( 108 ), ( 108 ), ( 108 ), ( 108 ), ( 108 ) ),
   // CHECK-SAME:      ( ( 108 ), ( 108 ), ( 108 ), ( 108 ), ( 108 ), ( 108 ) ) ) ) )
   %2 = sparse_tensor.convert %CDCDC_ret
     : tensor<?x?x?x?x?xf32, #CDCDC> to tensor<?x?x?x?x?xf32>
   %v2 = vector.transfer_read %dense_ret[%c0, %c0, %c0, %c0, %c0], %zero
       : tensor<?x?x?x?x?xf32>, vector<1x6x6x6x1xf32>
   vector.print %v2 : vector<1x6x6x6x1xf32>
-  
   // Free the resources
   bufferization.dealloc_tensor %in3D_ndhwc : tensor<?x?x?x?x?xf32>
   bufferization.dealloc_tensor %filter3D_ndhwc : tensor<?x?x?x?x?xf32>
   bufferization.dealloc_tensor %out3D_ndhwc : tensor<?x?x?x?x?xf32>
-  
   bufferization.dealloc_tensor %in3D_ndhwc_CDCDC : tensor<?x?x?x?x?xf32, #CDCDC>
   bufferization.dealloc_tensor %filter3D_ndhwc_CDCDC : tensor<?x?x?x?x?xf32, #CDCDC>
   bufferization.dealloc_tensor %in3D_ndhwc_CCCCC : tensor<?x?x?x?x?xf32, #CCCCC>
   bufferization.dealloc_tensor %filter3D_ndhwc_CCCCC : tensor<?x?x?x?x?xf32, #CCCCC>
 
   bufferization.dealloc_tensor %CCCCC_ret : tensor<?x?x?x?x?xf32, #CCCCC>
   bufferization.dealloc_tensor %CDCDC_ret : tensor<?x?x?x?x?xf32, #CDCDC>
 
   return
 }

mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_filter_conv2d.mlir

func.func @conv2d(%input:  tensor<8x8xi32>,
     %0 = linalg.conv_2d
       ins  (%input, %filter: tensor<8x8xi32>, tensor<3x3xi32, #DCSR>)
       outs (%output: tensor<6x6xi32>) -> tensor<6x6xi32>
     return %0 : tensor<6x6xi32>
   }
 
   func.func @conv2d_sparse_out(%input:  tensor<8x8xi32>,
                %filter: tensor<3x3xi32, #DCSR>) -> tensor<6x6xi32, #DCSR> {
-    %s = bufferization.alloc_tensor() : tensor<6x6xi32, #DCSR>           
+    %s = bufferization.alloc_tensor() : tensor<6x6xi32, #DCSR>
     %0 = linalg.conv_2d
       ins  (%input, %filter: tensor<8x8xi32>, tensor<3x3xi32, #DCSR>)
       outs (%s: tensor<6x6xi32, #DCSR>) -> tensor<6x6xi32, #DCSR>
     return %0 : tensor<6x6xi32, #DCSR>
   }
 
   func.func @entry() {
     %c0 = arith.constant 0 : index
func.func @entry() {
     // Call the kernel.
     %output = arith.constant dense<0> : tensor<6x6xi32>
     %0 = call @conv2d(%input, %sparse_filter, %output)
        : (tensor<8x8xi32>,
           tensor<3x3xi32, #DCSR>, tensor<6x6xi32>) -> tensor<6x6xi32>
     %1 = call @conv2d_sparse_out(%input, %sparse_filter)
        : (tensor<8x8xi32>,
           tensor<3x3xi32, #DCSR>) -> tensor<6x6xi32, #DCSR>
- 
     // Verify the output.
     //
     // CHECK:    ( ( 0, 0, -1, -6, -1, 6 ),
     // CHECK-SAME: ( -1, 0, 1, 0, 1, 0 ),
     // CHECK-SAME: ( 0, -1, 1, 0, 0, 0 ),
     // CHECK-SAME: ( -1, 0, 0, 0, 0, 0 ),
     // CHECK-SAME: ( 0, 0, 3, 6, -3, -6 ),
     // CHECK-SAME: ( 2, -1, 3, 0, -3, 0 ) )

mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_reshape.mlir

func.func @entry() {
     %df = arith.constant -1.0 : f64
 
     // Setup test vectors and matrices..
     %v = arith.constant dense <[ 1.0, 2.0, 3.0,  4.0,  5.0,  6.0,
                                  7.0, 8.0, 9.0, 10.0, 11.0, 12.0]> : tensor<12xf64>
     %m = arith.constant dense <[ [ 1.1,  1.2,  1.3,  1.4 ],
                                  [ 2.1,  2.2,  2.3,  2.4 ],
                                  [ 3.1,  3.2,  3.3,  3.4 ]]> : tensor<3x4xf64>
-    %n = arith.constant dense <[ 
+    %n = arith.constant dense <[
       [ [[1.0,  2.0],  [3.0,  4.0],  [5.0,  6.0],  [7.0,  8.0],  [9.0, 10.0]],
         [[11.0, 12.0], [13.0, 14.0], [15.0, 16.0], [17.0, 18.0], [19.0, 20.0]],
         [[21.0, 22.0], [23.0, 24.0], [25.0, 26.0], [27.0, 28.0], [29.0, 30.0]] ],
       [ [[31.0, 32.0], [33.0, 34.0], [35.0, 36.0], [37.0, 38.0], [39.0, 40.0]],
         [[41.0, 42.0], [43.0, 44.0], [45.0, 26.0], [47.0, 48.0], [49.0, 50.0]],
         [[51.0, 52.0], [53.0, 54.0], [55.0, 56.0], [57.0, 58.0], [59.0, 60.0]] ] ]> : tensor<2x3x5x2xf64>
     %sv = sparse_tensor.convert %v : tensor<12xf64> to tensor<12xf64, #SparseVector>
     %sm = sparse_tensor.convert %m : tensor<3x4xf64> to tensor<3x4xf64, #SparseMatrix>

mlir/test/Integration/Dialect/Vector/CPU/test-0-d-vectors.mlir

func.func @create_mask_0d(%zero : index, %one : index) {
   %one_mask = vector.create_mask %one : vector<i1>
   // CHECK: ( 1 )
   vector.print %one_mask : vector<i1>
 
   return
 }
 
 func.func @reduce_add(%arg0: vector<f32>) {
-  %0 = vector.reduction <add>, %arg0 : vector<f32> into f32    
+  %0 = vector.reduction <add>, %arg0 : vector<f32> into f32
   vector.print %0 : f32
   // CHECK: 5
   return
 }
 
 func.func @fma_0d(%four: vector<f32>) {
   %0 = vector.fma %four, %four, %four : vector<f32>
   // 4 * 4 + 4 = 20

mlir/test/Integration/Dialect/Vector/CPU/test-scan.mlir

func.func @entry() {
   vector.print %a#1 : vector<2xf32>
   vector.print %b#0 : vector<3x2xf32>
   vector.print %b#1 : vector<3xf32>
   vector.print %c#0 : vector<3x2xf32>
   vector.print %c#1 : vector<2xf32>
   vector.print %d#0 : vector<3x2xf32>
   vector.print %d#1 : vector<3xf32>
 
-  return 
+  return
 }

mlir/test/Interfaces/TilingInterface/tile-and-fuse-using-interface.mlir

%gemm = linalg.matmul
       outs(%fill : tensor<?x?xf32>) -> tensor<?x?xf32>
   %generic = linalg.generic {
       __internal_linalg_transform__ = "fusion",
       indexing_maps = [affine_map<(d0, d1) -> (d0, d1)>, affine_map<(d0, d1) -> (d1)>, affine_map<(d0, d1) -> (d0, d1)>],
       iterator_types = ["parallel", "parallel"]}
       ins(%gemm, %arg2 : tensor<?x?xf32>, tensor<?xf32>) outs(%init : tensor<?x?xf32>) {
     ^bb0(%b0 : f32, %b1 : f32, %b2 : f32):
       %add = arith.addf %b0, %b1 : f32
-      linalg.yield %add : f32 
+      linalg.yield %add : f32
   } -> tensor<?x?xf32>
-  return %generic : tensor<?x?xf32> 
+  return %generic : tensor<?x?xf32>
 }
 //      CHECK: func.func @gemm_generic_fusion(
 // CHECK-SAME:     %[[ARG0:[a-zA-Z0-9]+]]: tensor<?x?xf32>
 // CHECK-SAME:     %[[ARG1:[a-zA-Z0-9]+]]: tensor<?x?xf32>,
 // CHECK-SAME:     %[[ARG2:[a-zA-Z0-9]+]]: tensor<?xf32>)
 //      CHECK:   %[[INIT:.+]] = tensor.empty
 //      CHECK:   scf.for %[[IV0:[a-zA-Z0-9]+]] =
 // CHECK-SAME:       iter_args(%[[ITERARG0:.+]] = %[[INIT]])
%gemm = linalg.matmul
       outs(%fill : tensor<?x?xf32>) -> tensor<?x?xf32>
   %init1 = tensor.empty(%d1, %d0) : tensor<?x?xf32>
   %transpose = linalg.generic {
       __internal_linalg_transform__ = "fusion",
       indexing_maps = [affine_map<(d0, d1) -> (d0, d1)>, affine_map<(d0, d1) -> (d1, d0)>],
       iterator_types = ["parallel", "parallel"]}
       ins(%gemm : tensor<?x?xf32>) outs(%init1 : tensor<?x?xf32>) {
     ^bb0(%b0 : f32, %b1 : f32):
-      linalg.yield %b0 : f32 
+      linalg.yield %b0 : f32
   } -> tensor<?x?xf32>
   return %transpose : tensor<?x?xf32>
 }
 //      CHECK: func.func @gemm_transpose_fusion(
 // CHECK-SAME:     %[[ARG0:[a-zA-Z0-9]+]]: tensor<?x?xf32>
 // CHECK-SAME:     %[[ARG1:[a-zA-Z0-9]+]]: tensor<?x?xf32>)
 //  CHECK-DAG:   %[[C0:.+]] = arith.constant 0 : index
 //  CHECK-DAG:   %[[C1:.+]] = arith.constant 1 : index

mlir/test/Rewrite/pdl-bytecode.mlir

^end:
     pdl_interp.finalize
   }
 
   module @rewriters {
     pdl_interp.func @success(%root: !pdl.operation) {
       %rootOperand = pdl_interp.get_operand 0 of %root
       %rootOperands = pdl_interp.get_operands of %root : !pdl.range<value>
       %operandRange = pdl_interp.create_range %rootOperand, %rootOperands : !pdl.value, !pdl.range<value>
-      
       %operandType = pdl_interp.get_value_type of %rootOperand : !pdl.type
       %operandTypes = pdl_interp.get_value_type of %rootOperands : !pdl.range<type>
       %typeRange = pdl_interp.create_range %operandType, %operandTypes : !pdl.type, !pdl.range<type>
 
       %op = pdl_interp.create_operation "test.success"(%operandRange : !pdl.range<value>) -> (%typeRange : !pdl.range<type>)
       pdl_interp.erase %root
       pdl_interp.finalize
     }

mlir/test/Target/Cpp/for.mlir

 
 func.func @test_for_yield() {
   %start = arith.constant 0 : index
   %stop = arith.constant 10 : index
   %step = arith.constant 1 : index
 
   %s0 = arith.constant 0 : i32
   %p0 = arith.constant 1.0 : f32
-  
   %result:2 = scf.for %iter = %start to %stop step %step iter_args(%si = %s0, %pi = %p0) -> (i32, f32) {
     %sn = emitc.call "add"(%si, %iter) : (i32, index) -> i32
     %pn = emitc.call "mul"(%pi, %iter) : (f32, index) -> f32
     scf.yield %sn, %pn : i32, f32
   }
 
   return
 }

mlir/test/Target/LLVMIR/nvvmir.mlir

 }
 
 // CHECK:     !nvvm.annotations =
 // CHECK-NOT: {ptr @nvvm_special_regs, !"kernel", i32 1}
 // CHECK:     {ptr @kernel_func, !"kernel", i32 1}
 // CHECK:     {ptr @kernel_func, !"maxnreg", i32 16}
 // -----
 
-llvm.func @kernel_func() attributes {nvvm.kernel, nvvm.maxntid = [1,23,32], 
+llvm.func @kernel_func() attributes {nvvm.kernel, nvvm.maxntid = [1,23,32],
                                      nvvm.minctasm = 16, nvvm.maxnreg = 32} {
   llvm.return
 }
 
 // CHECK:     !nvvm.annotations =
 // CHECK-NOT: {ptr @nvvm_special_regs, !"kernel", i32 1}
 // CHECK:     {ptr @kernel_func, !"kernel", i32 1}
 // CHECK:     {ptr @kernel_func, !"maxnreg", i32 32}
 // CHECK:     {ptr @kernel_func, !"maxntidx", i32 1}
 // CHECK:     {ptr @kernel_func, !"maxntidy", i32 23}
 // CHECK:     {ptr @kernel_func, !"maxntidz", i32 32}
 // CHECK:     {ptr @kernel_func, !"minctasm", i32 16}
 
 // -----
-// expected-error @below {{'"nvvm.minctasm"' attribute must be integer constant}}  
-llvm.func @kernel_func() attributes {nvvm.kernel, 
+// expected-error @below {{'"nvvm.minctasm"' attribute must be integer constant}}
+llvm.func @kernel_func() attributes {nvvm.kernel,
 nvvm.minctasm = "foo"} {
   llvm.return
 }
 
 
 // -----
-// expected-error @below {{'"nvvm.maxnreg"' attribute must be integer constant}}  
-llvm.func @kernel_func() attributes {nvvm.kernel, 
+// expected-error @below {{'"nvvm.maxnreg"' attribute must be integer constant}}
+llvm.func @kernel_func() attributes {nvvm.kernel,
 nvvm.maxnreg = "boo"} {
   llvm.return
 }
 // -----
-// expected-error @below {{'"nvvm.reqntid"' attribute must be integer array with maximum 3 index}}  
+// expected-error @below {{'"nvvm.reqntid"' attribute must be integer array with maximum 3 index}}
 llvm.func @kernel_func() attributes {nvvm.kernel, nvvm.reqntid = [3,4,5,6]} {
   llvm.return
 }
 
 // -----
-// expected-error @below {{'"nvvm.maxntid"' attribute must be integer array with maximum 3 index}}  
+// expected-error @below {{'"nvvm.maxntid"' attribute must be integer array with maximum 3 index}}
 llvm.func @kernel_func() attributes {nvvm.kernel, nvvm.maxntid = [3,4,5,6]} {
   llvm.return
 }
 

mlir/test/Target/LLVMIR/openmp-llvm.mlir

llvm.func @omp_taskgroup(%x: i32, %y: i32, %zaddr: !llvm.ptr<i32>) {
   omp.taskgroup {
     llvm.call @foo() : () -> ()
     omp.terminator
   }
   llvm.return
 }
 
 // CHECK-LABEL: define void @omp_taskgroup(
-// CHECK-SAME:                             i32 %[[x:.+]], i32 %[[y:.+]], ptr %[[zaddr:.+]]) 
+// CHECK-SAME:                             i32 %[[x:.+]], i32 %[[y:.+]], ptr %[[zaddr:.+]])
 // CHECK:         br label %[[entry:[^,]+]]
 // CHECK:       [[entry]]:
 // CHECK:         %[[omp_global_thread_num:.+]] = call i32 @__kmpc_global_thread_num(ptr @{{.+}})
 // CHECK:         call void @__kmpc_taskgroup(ptr @{{.+}}, i32 %[[omp_global_thread_num]])
 // CHECK:         br label %[[omp_taskgroup_region:[^,]+]]
 // CHECK:       [[omp_taskgroup_region]]:
 // CHECK:         call void @foo()
 // CHECK:         br label %[[omp_region_cont:[^,]+]]
llvm.func @omp_taskgroup_task(%x: i32, %y: i32, %zaddr: !llvm.ptr<i32>) {
   ^bb1:
     llvm.call @foo() : () -> ()
     omp.terminator
   }
   llvm.return
 }
 
 // CHECK-LABEL: define void @omp_taskgroup_task(
-// CHECK-SAME:                                  i32 %[[x:.+]], i32 %[[y:.+]], ptr %[[zaddr:.+]]) 
+// CHECK-SAME:                                  i32 %[[x:.+]], i32 %[[y:.+]], ptr %[[zaddr:.+]])
 // CHECK:         %[[structArg:.+]] = alloca { i32, i32, ptr }, align 8
 // CHECK:         br label %[[entry:[^,]+]]
 // CHECK:       [[entry]]:                                            ; preds = %3
 // CHECK:         %[[omp_global_thread_num:.+]] = call i32 @__kmpc_global_thread_num(ptr @{{.+}})
 // CHECK:         call void @__kmpc_taskgroup(ptr @{{.+}}, i32 %[[omp_global_thread_num]])
 // CHECK:         br label %[[omp_taskgroup_region:[^,]+]]
 // CHECK:       [[omp_taskgroup_region1:.+]]:
 // CHECK:         call void @foo()

mlir/test/Target/LLVMIR/openmp-nested.mlir

 // RUN: mlir-translate -mlir-to-llvmir -split-input-file %s | FileCheck %s
- 
 module {
   llvm.func @printf(!llvm.ptr<i8>, ...) -> i32
   llvm.mlir.global internal constant @str0("WG size of kernel = %d X %d\0A\00")
 
   llvm.func @main(%arg0: i32, %arg1: !llvm.ptr<ptr<i8>>) -> i32 {
     omp.parallel   {
       %0 = llvm.mlir.constant(1 : index) : i64
       %1 = llvm.mlir.constant(10 : index) : i64

mlir/test/Target/LLVMIR/openmp-reduction.mlir

^bb2(%arg2: !llvm.ptr<f32>, %arg3: !llvm.ptr<f32>):
   omp.yield
 }
 
 // CHECK-LABEL: @simple_reduction
 llvm.func @simple_reduction(%lb : i64, %ub : i64, %step : i64) {
   %c1 = llvm.mlir.constant(1 : i32) : i32
   %0 = llvm.alloca %c1 x i32 : (i32) -> !llvm.ptr<f32>
   omp.parallel {
-    omp.wsloop reduction(@add_f32 -> %0 : !llvm.ptr<f32>) 
+    omp.wsloop reduction(@add_f32 -> %0 : !llvm.ptr<f32>)
     for (%iv) : i64 = (%lb) to (%ub) step (%step) {
       %1 = llvm.mlir.constant(2.0 : f32) : f32
       omp.reduction %1, %0 : !llvm.ptr<f32>
       omp.yield
     }
     omp.terminator
   }
   llvm.return

mlir/test/Target/SPIRV/ocl-ops.mlir

spirv.func @float_insts(%arg0 : f32) "None" {
     spirv.Return
   }
 
   spirv.func @integer_insts(%arg0 : i32) "None" {
     // CHECK: {{%.*}} = spirv.CL.s_abs {{%.*}} : i32
     %0 = spirv.CL.s_abs %arg0 : i32
     spirv.Return
   }
-  
   spirv.func @vector_size16(%arg0 : vector<16xf32>) "None" {
     // CHECK: {{%.*}} = spirv.CL.fabs {{%.*}} : vector<16xf32>
     %0 = spirv.CL.fabs %arg0 : vector<16xf32>
     spirv.Return
   }
 
   spirv.func @fma(%arg0 : f32, %arg1 : f32, %arg2 : f32) "None" {
     // CHECK: spirv.CL.fma {{%[^,]*}}, {{%[^,]*}}, {{%[^,]*}} : f32

mlir/test/Transforms/cse.mlir

test.graph_region {
     // CHECK-NEXT: arith.constant 1
     %1 = arith.constant 1 : i32
     %2 = arith.constant 1 : i32
 
     // CHECK-NEXT: "foo.yield"(%{{.*}}) : (i32) -> ()
     "foo.yield"(%0) : (i32) -> ()
   }
   return
-} 
+}
 
 /// This test is checking that CSE is removing duplicated read op that follow
 /// other.
 // CHECK-LABEL: @remove_direct_duplicated_read_op
 func.func @remove_direct_duplicated_read_op() -> i32 {
   // CHECK-NEXT: %[[READ_VALUE:.*]] = "test.op_with_memread"() : () -> i32
   %0 = "test.op_with_memread"() : () -> (i32)
   %1 = "test.op_with_memread"() : () -> (i32)

mlir/test/Transforms/loop-fusion-3.mlir

 // RUN: mlir-opt -allow-unregistered-dialect %s -affine-loop-fusion -split-input-file | FileCheck %s
 // RUN: mlir-opt -allow-unregistered-dialect %s -affine-loop-fusion="fusion-maximal" -split-input-file | FileCheck %s --check-prefix=MAXIMAL
 
-// Part I of fusion tests in  mlir/test/Transforms/loop-fusion.mlir. 
+// Part I of fusion tests in  mlir/test/Transforms/loop-fusion.mlir.
 // Part II of fusion tests in mlir/test/Transforms/loop-fusion-2.mlir
 // Part IV of fusion tests in mlir/test/Transforms/loop-fusion-4.mlir
 
 // -----
 
 // Test case from github bug 777.
 // CHECK-LABEL: func @mul_add_0
 func.func @mul_add_0(%arg0: memref<3x4xf32>, %arg1: memref<4x3xf32>, %arg2: memref<3x3xf32>, %arg3: memref<3x3xf32>) {

mlir/test/Transforms/loop-invariant-code-motion.mlir

affine.for %arg0 = 0 to 10 {
     %v0 = affine.load %m1[%arg0] : memref<10xf32>
     %v1 = affine.load %m2[%arg0] : memref<10xf32>
     %v2 = arith.addf %v0, %v1 : f32
     affine.store %v2, %m1[%arg0] : memref<10xf32>
   }
 
   // CHECK: memref.alloc() : memref<10xf32>
   // CHECK-NEXT: memref.alloc() : memref<10xf32>
-  // CHECK-NEXT: affine.for 
+  // CHECK-NEXT: affine.for
   // CHECK-NEXT: affine.load
   // CHECK-NEXT: affine.load
   // CHECK-NEXT: arith.addf
   // CHECK-NEXT: affine.store
 
   return
 }
 

 // -----
 
 func.func private @make_val() -> (index)
 
 // CHECK-LABEL: func @nested_uses_inside
 func.func @nested_uses_inside(%lb: index, %ub: index, %step: index) {
   %true = arith.constant true
 
-  // Check that ops that contain nested uses to values not defiend outside 
+  // Check that ops that contain nested uses to values not defiend outside
   // remain in the loop.
   // CHECK-NEXT: arith.constant
   // CHECK-NEXT: scf.for
   // CHECK-NEXT:   call @
   // CHECK-NEXT:   call @
   // CHECK-NEXT:   scf.if
   // CHECK-NEXT:     scf.yield
   // CHECK-NEXT:   else
// CHECK: scf.for
     %val = arith.ceildivsi %num, %c5 : i32
   }
 
   return
 }
 
 // -----
 
-func.func @speculate_static_pack_and_unpack(%source: tensor<128x256xf32>, 
+func.func @speculate_static_pack_and_unpack(%source: tensor<128x256xf32>,
   %dest: tensor<4x16x32x16xf32>, %lb: index, %ub: index, %step: index) {
 
   // CHECK: tensor.pack
-  // CHECK-NEXT: scf.for  
+  // CHECK-NEXT: scf.for
   scf.for %i = %lb to %ub step %step {
-    %packed = tensor.pack %source 
-      inner_dims_pos = [0, 1] 
+    %packed = tensor.pack %source
+      inner_dims_pos = [0, 1]
       inner_tiles = [32, 16] into %dest : tensor<128x256xf32> -> tensor<4x16x32x16xf32>
   }
-  
   // CHECK: tensor.unpack
-  // CHECK-NEXT: scf.for 
+  // CHECK-NEXT: scf.for
   scf.for %i = %lb to %ub step %step {
     %unpacked = tensor.unpack %dest
-      inner_dims_pos = [0, 1] 
+      inner_dims_pos = [0, 1]
       inner_tiles = [32, 16] into %source : tensor<4x16x32x16xf32> -> tensor<128x256xf32>
   }
-  return 
+  return
 }
 
 // -----
 
 func.func @speculate_dynamic_pack_and_unpack(%source: tensor<?x?xf32>,
   %dest: tensor<?x?x?x?xf32>, %lb: index, %ub: index, %step: index,
   %tile_m: index, %tile_n: index, %pad: f32) {
 
   // CHECK: scf.for
   // CHECK-NEXT: tensor.pack
   scf.for %i = %lb to %ub step %step {
     %packed = tensor.pack %source
       inner_dims_pos = [0, 1]
       inner_tiles = [%tile_n, %tile_m] into %dest : tensor<?x?xf32> -> tensor<?x?x?x?xf32>
   }
 
   // CHECK: scf.for
   // CHECK-NEXT: tensor.unpack
   scf.for %i = %lb to %ub step %step {
     %unpacked = tensor.unpack %dest
-      inner_dims_pos = [0, 1] 
+      inner_dims_pos = [0, 1]
       inner_tiles = [%tile_n, %tile_m] into %source : tensor<?x?x?x?xf32> -> tensor<?x?xf32>
   }
 
   // CHECK: tensor.pack
   // CHECK-NEXT: scf.for
   scf.for %i = %lb to %ub step %step {
     %packed = tensor.pack %source padding_value(%pad : f32)
       inner_dims_pos = [0, 1]
       inner_tiles = [%tile_n, %tile_m] into %dest : tensor<?x?xf32> -> tensor<?x?x?x?xf32>
   }
   return
 }

mlir/test/lib/Dialect/Transform/TestTransformDialectExtension.td

def TestTransformTestDialectHandleType
   let description = [{Handle pointing to an op from the Test dialect.}];
   let mnemonic = "test_dialect_op";
   let assemblyFormat = "";
 }
 
 def TestProduceParamOrForwardOperandOp
   : Op<Transform_Dialect, "test_produce_param_or_forward_operand",
        [DeclareOpInterfaceMethods<TransformOpInterface>]> {
-  let arguments = (ins 
+  let arguments = (ins
      Arg<Optional<PDL_Operation>, "", [TransformMappingRead]>:$operand,
      OptionalAttr<I64Attr>:$parameter);
-  let results = (outs 
+  let results = (outs
      Res<PDL_Operation, "",
          [TransformMappingAlloc, TransformMappingWrite]>:$res);
   let assemblyFormat = "(`from` $operand^)? ($parameter^)? attr-dict";
   let cppNamespace = "::mlir::test";
   let hasVerifier = 1;
 }
 
 def TestConsumeOperand : Op<Transform_Dialect, "test_consume_operand",
      [DeclareOpInterfaceMethods<TransformOpInterface>]> {
   let arguments = (ins
     Arg<PDL_Operation, "",
         [TransformMappingRead, TransformMappingFree]>:$operand,
     Arg<Optional<PDL_Operation>, "",
         [TransformMappingRead, TransformMappingFree]>:$second_operand);
   let assemblyFormat = "$operand (`,` $second_operand^)? attr-dict";
   let cppNamespace = "::mlir::test";
 }
 
 def TestConsumeOperandIfMatchesParamOrFail
   : Op<Transform_Dialect, "test_consume_operand_if_matches_param_or_fail",
        [DeclareOpInterfaceMethods<TransformOpInterface>]> {
-  let arguments = (ins 
+  let arguments = (ins
     Arg<PDL_Operation, "",
         [TransformMappingRead, TransformMappingFree]>:$operand,
     I64Attr:$parameter);
   let assemblyFormat = "$operand `[` $parameter `]` attr-dict";
   let cppNamespace = "::mlir::test";
 }
 
 def TestPrintRemarkAtOperandOp
   : Op<Transform_Dialect, "test_print_remark_at_operand",
        [DeclareOpInterfaceMethods<TransformOpInterface>]> {
-  let arguments = (ins 
+  let arguments = (ins
     Arg<TransformTypeInterface, "",
         [TransformMappingRead, PayloadIRRead]>:$operand,
     StrAttr:$message);
   let assemblyFormat =
     "$operand `,` $message attr-dict `:` type($operand)";
   let cppNamespace = "::mlir::test";
 }
 
def TestEmitRemarkAndEraseOperandOp
   let arguments = (ins PDL_Operation:$target, StrAttr:$remark,
                    UnitAttr:$fail_after_erase);
   let assemblyFormat = "$target `,` $remark attr-dict";
   let cppNamespace = "::mlir::test";
 }
 
 def TestWrongNumberOfResultsOp
   : Op<Transform_Dialect, "test_wrong_number_of_results",
-    [FunctionalStyleTransformOpTrait, MemoryEffectsOpInterface, 
+    [FunctionalStyleTransformOpTrait, MemoryEffectsOpInterface,
      TransformEachOpTrait, TransformOpInterface]> {
   let arguments = (ins PDL_Operation:$target);
   let results = (outs PDL_Operation:$a,
                       PDL_Operation:$b,
                       PDL_Operation:$c);
   let assemblyFormat = "$target attr-dict";
   let cppNamespace = "::mlir::test";
   let extraClassDeclaration = [{
     ::mlir::DiagnosedSilenceableFailure applyToOne(
-        ::mlir::Operation * target, 
-        ::llvm::SmallVectorImpl<::mlir::Operation *> &results, 
+        ::mlir::Operation * target,
+        ::llvm::SmallVectorImpl<::mlir::Operation *> &results,
         ::mlir::transform::TransformState &state);
   }];
 }
 
 def TestWrongNumberOfMultiResultsOp
   : Op<Transform_Dialect, "test_wrong_number_of_multi_results",
-    [FunctionalStyleTransformOpTrait, MemoryEffectsOpInterface, 
+    [FunctionalStyleTransformOpTrait, MemoryEffectsOpInterface,
      TransformEachOpTrait, TransformOpInterface]> {
   let arguments = (ins PDL_Operation:$target);
   let results = (outs PDL_Operation:$result);
   let assemblyFormat = "$target attr-dict";
   let cppNamespace = "::mlir::test";
   let extraClassDeclaration = [{
     ::mlir::DiagnosedSilenceableFailure applyToOne(
-        ::mlir::Operation * target, 
-        ::llvm::SmallVectorImpl<::mlir::Operation *> &results, 
+        ::mlir::Operation * target,
+        ::llvm::SmallVectorImpl<::mlir::Operation *> &results,
         ::mlir::transform::TransformState &state);
   }];
 }
 
 def TestCorrectNumberOfMultiResultsOp
   : Op<Transform_Dialect, "test_correct_number_of_multi_results",
-    [FunctionalStyleTransformOpTrait, MemoryEffectsOpInterface, 
+    [FunctionalStyleTransformOpTrait, MemoryEffectsOpInterface,
      TransformEachOpTrait, TransformOpInterface]> {
   let arguments = (ins PDL_Operation:$target);
   let results = (outs PDL_Operation:$result1,
                       PDL_Operation:$result2);
   let assemblyFormat = "$target attr-dict";
   let cppNamespace = "::mlir::test";
   let extraClassDeclaration = [{
     ::mlir::DiagnosedSilenceableFailure applyToOne(
-        ::mlir::Operation * target, 
-        ::llvm::SmallVectorImpl<::mlir::Operation *> &results, 
+        ::mlir::Operation * target,
+        ::llvm::SmallVectorImpl<::mlir::Operation *> &results,
         ::mlir::transform::TransformState &state);
   }];
 }
 
 def TestMixedNullAndNonNullResultsOp
   : Op<Transform_Dialect, "test_mixed_null_and_non_null_results",
-    [FunctionalStyleTransformOpTrait, MemoryEffectsOpInterface, 
+    [FunctionalStyleTransformOpTrait, MemoryEffectsOpInterface,
      TransformEachOpTrait, TransformOpInterface]> {
   let arguments = (ins PDL_Operation:$target);
   let results = (outs PDL_Operation:$null,
                       PDL_Operation:$non_null);
   let assemblyFormat = "$target attr-dict";
   let cppNamespace = "::mlir::test";
   let extraClassDeclaration = [{
     ::mlir::DiagnosedSilenceableFailure applyToOne(
-        ::mlir::Operation * target, 
-        ::llvm::SmallVectorImpl<::mlir::Operation *> &results, 
+        ::mlir::Operation * target,
+        ::llvm::SmallVectorImpl<::mlir::Operation *> &results,
         ::mlir::transform::TransformState &state);
   }];
 }
 
 def TestMixedSuccessAndSilenceableOp
   : Op<Transform_Dialect, "test_mixed_sucess_and_silenceable",
-    [FunctionalStyleTransformOpTrait, MemoryEffectsOpInterface, 
+    [FunctionalStyleTransformOpTrait, MemoryEffectsOpInterface,
      TransformEachOpTrait, TransformOpInterface]> {
   let arguments = (ins PDL_Operation:$target);
   let results = (outs);
   let assemblyFormat = "$target attr-dict";
   let cppNamespace = "::mlir::test";
   let extraClassDeclaration = [{
     ::mlir::DiagnosedSilenceableFailure applyToOne(
-        ::mlir::Operation * target, 
-        ::llvm::SmallVectorImpl<::mlir::Operation *> &results, 
+        ::mlir::Operation * target,
+        ::llvm::SmallVectorImpl<::mlir::Operation *> &results,
         ::mlir::transform::TransformState &state);
   }];
 }
 
 def TestPrintNumberOfAssociatedPayloadIROps
   : Op<Transform_Dialect, "test_print_number_of_associated_payload_ir_ops",
        [DeclareOpInterfaceMethods<TransformOpInterface>,
         DeclareOpInterfaceMethods<MemoryEffectsOpInterface>]> {

mlir/test/mlir-cpu-runner/math-polynomial-approx.mlir

 // RUN:   mlir-opt %s -pass-pipeline="builtin.module(func.func(test-math-polynomial-approximation,convert-arith-to-llvm),convert-vector-to-llvm,func.func(convert-math-to-llvm),convert-func-to-llvm,reconcile-unrealized-casts)" \
 // RUN: | mlir-cpu-runner                                                      \
 // RUN:     -e main -entry-point-result=void -O0                               \
 // RUN:     -shared-libs=%mlir_lib_dir/libmlir_c_runner_utils%shlibext  \
 // RUN:     -shared-libs=%mlir_lib_dir/libmlir_runner_utils%shlibext    \
 // RUN: | FileCheck %s
 
 // -------------------------------------------------------------------------- //
 // Tanh.
 // -------------------------------------------------------------------------- //
 
-func.func @tanh_f32(%a : f32) { 
+func.func @tanh_f32(%a : f32) {
   %r = math.tanh %a : f32
   vector.print %r : f32
   return
 }
 
-func.func @tanh_4xf32(%a : vector<4xf32>) { 
+func.func @tanh_4xf32(%a : vector<4xf32>) {
   %r = math.tanh %a : vector<4xf32>
   vector.print %r : vector<4xf32>
   return
 }
 
-func.func @tanh_8xf32(%a : vector<8xf32>) { 
+func.func @tanh_8xf32(%a : vector<8xf32>) {
   %r = math.tanh %a : vector<8xf32>
   vector.print %r : vector<8xf32>
   return
 }
 
-func.func @tanh() { 
+func.func @tanh() {
   // CHECK: 0.848284
   %f0 = arith.constant 1.25 : f32
   call @tanh_f32(%f0) : (f32) -> ()
 
   // CHECK: 0.244919, 0.635149, 0.761594, 0.848284
   %v1 = arith.constant dense<[0.25, 0.75, 1.0, 1.25]> : vector<4xf32>
   call @tanh_4xf32(%v1) : (vector<4xf32>) -> ()
 
   // CHECK: 0.099668, 0.197375, 0.291313, 0.379949, 0.462117, 0.53705, 0.604368, 0.664037
   %v2 = arith.constant dense<[0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8]> : vector<8xf32>
   call @tanh_8xf32(%v2) : (vector<8xf32>) -> ()
 
   // CHECK: nan
   %nan = arith.constant 0x7fc00000 : f32
   call @tanh_f32(%nan) : (f32) -> ()
 
  return
 }
 
 // -------------------------------------------------------------------------- //
 // Log.
 // -------------------------------------------------------------------------- //
 
-func.func @log_f32(%a : f32) { 
+func.func @log_f32(%a : f32) {
   %r = math.log %a : f32
   vector.print %r : f32
   return
 }
 
-func.func @log_4xf32(%a : vector<4xf32>) { 
+func.func @log_4xf32(%a : vector<4xf32>) {
   %r = math.log %a : vector<4xf32>
   vector.print %r : vector<4xf32>
   return
 }
 
-func.func @log_8xf32(%a : vector<8xf32>) { 
+func.func @log_8xf32(%a : vector<8xf32>) {
   %r = math.log %a : vector<8xf32>
   vector.print %r : vector<8xf32>
   return
 }
 
-func.func @log() { 
+func.func @log() {
   // CHECK: 2.64704
   %f1 = arith.constant 14.112233 : f32
   call @log_f32(%f1) : (f32) -> ()
 
   // CHECK: -1.38629, -0.287682, 0, 0.223144
   %v1 = arith.constant dense<[0.25, 0.75, 1.0, 1.25]> : vector<4xf32>
   call @log_4xf32(%v1) : (vector<4xf32>) -> ()
 
func.func @log() {
 
   // CHECK: -inf, nan, inf, 0.693147
   %special_vec = arith.constant dense<[0.0, -1.0, 0x7f800000, 2.0]> : vector<4xf32>
   call @log_4xf32(%special_vec) : (vector<4xf32>) -> ()
 
   return
 }
 
-func.func @log2_f32(%a : f32) { 
+func.func @log2_f32(%a : f32) {
   %r = math.log2 %a : f32
   vector.print %r : f32
   return
 }
 
-func.func @log2_4xf32(%a : vector<4xf32>) { 
+func.func @log2_4xf32(%a : vector<4xf32>) {
   %r = math.log2 %a : vector<4xf32>
   vector.print %r : vector<4xf32>
   return
 }
 
-func.func @log2_8xf32(%a : vector<8xf32>) { 
+func.func @log2_8xf32(%a : vector<8xf32>) {
   %r = math.log2 %a : vector<8xf32>
   vector.print %r : vector<8xf32>
   return
 }
 
 func.func @log2() {
   // CHECK: 3.81887
   %f0 = arith.constant 14.112233 : f32
func.func @log2() {
 
   // CHECK: -inf, nan, inf, 1.58496
   %special_vec = arith.constant dense<[0.0, -1.0, 0x7f800000, 3.0]> : vector<4xf32>
   call @log2_4xf32(%special_vec) : (vector<4xf32>) -> ()
 
   return
 }
 
-func.func @log1p_f32(%a : f32) { 
+func.func @log1p_f32(%a : f32) {
   %r = math.log1p %a : f32
   vector.print %r : f32
   return
 }
 
-func.func @log1p_4xf32(%a : vector<4xf32>) { 
+func.func @log1p_4xf32(%a : vector<4xf32>) {
   %r = math.log1p %a : vector<4xf32>
   vector.print %r : vector<4xf32>
   return
 }
 
-func.func @log1p_8xf32(%a : vector<8xf32>) { 
+func.func @log1p_8xf32(%a : vector<8xf32>) {
   %r = math.log1p %a : vector<8xf32>
   vector.print %r : vector<8xf32>
   return
 }
 
 func.func @log1p() {
   // CHECK: 0.00995033
   %f0 = arith.constant 0.01 : f32
func.func @log1p() {
   call @log1p_4xf32(%special_vec) : (vector<4xf32>) -> ()
 
   return
 }
 
 // -------------------------------------------------------------------------- //
 // Erf.
 // -------------------------------------------------------------------------- //
-func.func @erf_f32(%a : f32) { 
+func.func @erf_f32(%a : f32) {
   %r = math.erf %a : f32
   vector.print %r : f32
   return
 }
 
-func.func @erf_4xf32(%a : vector<4xf32>) { 
+func.func @erf_4xf32(%a : vector<4xf32>) {
   %r = math.erf %a : vector<4xf32>
   vector.print %r : vector<4xf32>
   return
 }
 
 func.func @erf() {
   // CHECK: -0.000274406
   %val1 = arith.constant -2.431864e-4 : f32
func.func @erf() {
   call @erf_f32(%nan) : (f32) -> ()
 
   return
 }
 
 // -------------------------------------------------------------------------- //
 // Exp.
 // -------------------------------------------------------------------------- //
-func.func @exp_f32(%a : f32) { 
+func.func @exp_f32(%a : f32) {
   %r = math.exp %a : f32
   vector.print %r : f32
   return
 }
 
-func.func @exp_4xf32(%a : vector<4xf32>) { 
+func.func @exp_4xf32(%a : vector<4xf32>) {
   %r = math.exp %a : vector<4xf32>
   vector.print %r : vector<4xf32>
   return
 }
 
 func.func @exp() {
   // CHECK: 2.71828
   %f0 = arith.constant 1.0 : f32
   call @exp_f32(%f0) : (f32) -> ()
 
   // CHECK: 0.778802, 2.117, 2.71828, 3.85742
   %v1 = arith.constant dense<[-0.25, 0.75, 1.0, 1.35]> : vector<4xf32>
   call @exp_4xf32(%v1) : (vector<4xf32>) -> ()
 
   // CHECK: 1
   %zero = arith.constant 0.0 : f32
   call @exp_f32(%zero) : (f32) -> ()
 
-  // CHECK: 1.17549e-38, 1.38879e-11, 7.20049e+10, inf 
+  // CHECK: 1.17549e-38, 1.38879e-11, 7.20049e+10, inf
   %special_vec = arith.constant dense<[-89.0, -25.0, 25.0, 89.0]> : vector<4xf32>
   call @exp_4xf32(%special_vec) : (vector<4xf32>) -> ()
 
   // CHECK: inf
   %inf = arith.constant 0x7f800000 : f32
   call @exp_f32(%inf) : (f32) -> ()
 
   // CHECK: 0
   %negative_inf = arith.constant 0xff800000 : f32
   call @exp_f32(%negative_inf) : (f32) -> ()
 
   // CHECK: nan
   %nan = arith.constant 0x7fc00000 : f32
   call @exp_f32(%nan) : (f32) -> ()
 
   return
 }
 
-func.func @expm1_f32(%a : f32) { 
+func.func @expm1_f32(%a : f32) {
   %r = math.expm1 %a : f32
   vector.print %r : f32
   return
 }
 
-func.func @expm1_3xf32(%a : vector<3xf32>) { 
+func.func @expm1_3xf32(%a : vector<3xf32>) {
   %r = math.expm1 %a : vector<3xf32>
   vector.print %r : vector<3xf32>
   return
 }
 
-func.func @expm1_4xf32(%a : vector<4xf32>) { 
+func.func @expm1_4xf32(%a : vector<4xf32>) {
   %r = math.expm1 %a : vector<4xf32>
   vector.print %r : vector<4xf32>
   return
 }
 
-func.func @expm1_8xf32(%a : vector<8xf32>) { 
+func.func @expm1_8xf32(%a : vector<8xf32>) {
   %r = math.expm1 %a : vector<8xf32>
   vector.print %r : vector<8xf32>
   return
 }
 
 func.func @expm1() {
   // CHECK: 1e-10
   %f0 = arith.constant 1.0e-10 : f32
func.func @expm1() {
   %nan = arith.constant 0x7fc00000 : f32
   call @expm1_f32(%nan) : (f32) -> ()
 
   return
 }
 // -------------------------------------------------------------------------- //
 // Sin.
 // -------------------------------------------------------------------------- //
-func.func @sin_f32(%a : f32) { 
+func.func @sin_f32(%a : f32) {
   %r = math.sin %a : f32
   vector.print %r : f32
   return
 }
 
-func.func @sin_3xf32(%a : vector<3xf32>) { 
+func.func @sin_3xf32(%a : vector<3xf32>) {
   %r = math.sin %a : vector<3xf32>
   vector.print %r : vector<3xf32>
   return
 }
 
 func.func @sin() {
   // CHECK: 0
   %zero = arith.constant 0.0 : f32
func.func @sin() {
   call @sin_3xf32(%vec_x) : (vector<3xf32>) -> ()
 
   return
 }
 
 // -------------------------------------------------------------------------- //
 // cos.
 // -------------------------------------------------------------------------- //
-func.func @cos_f32(%a : f32) { 
+func.func @cos_f32(%a : f32) {
   %r = math.cos %a : f32
   vector.print %r : f32
   return
 }
 
-func.func @cos_3xf32(%a : vector<3xf32>) { 
+func.func @cos_3xf32(%a : vector<3xf32>) {
   %r = math.cos %a : vector<3xf32>
   vector.print %r : vector<3xf32>
   return
 }
 
 func.func @cos() {
   // CHECK: 1
   %zero = arith.constant 0.0 : f32
func.func @cos() {
   call @cos_3xf32(%vec_x) : (vector<3xf32>) -> ()
 
   return
 }
 
 // -------------------------------------------------------------------------- //
 // Atan.
 // -------------------------------------------------------------------------- //
-func.func @atan_f32(%a : f32) { 
+func.func @atan_f32(%a : f32) {
   %r = math.atan %a : f32
   vector.print %r : f32
   return
 }
 
 func.func @atan() {
   // CHECK: -0.785184
   %0 = arith.constant -1.0 : f32
func.func @atan() {
 
   return
 }
 
 
 // -------------------------------------------------------------------------- //
 // Atan2.
 // -------------------------------------------------------------------------- //
-func.func @atan2_f32(%a : f32, %b : f32) { 
+func.func @atan2_f32(%a : f32, %b : f32) {
   %r = math.atan2 %a, %b : f32
   vector.print %r : f32
   return
 }
 
 func.func @atan2() {
   %zero = arith.constant 0.0 : f32
   %one = arith.constant 1.0 : f32

mlir/test/mlir-tblgen/typedefs.td

 // DEF-SAME: ::mlir::Type &value) {
 // DEF: .Case(::test::CompoundAType::getMnemonic()
 // DEF-NEXT:   value = ::test::CompoundAType::parse(parser);
 // DEF-NEXT:   return ::mlir::success(!!value);
 // DEF-NEXT: })
 // DEF-NEXT: .Case(::test::IndexType::getMnemonic()
 // DEF-NEXT:   value = ::test::IndexType::parse(parser);
 // DEF-NEXT:   return ::mlir::success(!!value);
-// DEF: .Default([&](llvm::StringRef keyword, 
+// DEF: .Default([&](llvm::StringRef keyword,
 // DEF-NEXT:   *mnemonic = keyword;
-// DEF-NEXT:   return llvm::None; 
+// DEF-NEXT:   return llvm::None;
 
 def Test_Dialect: Dialect {
 // DECL-NOT: TestDialect
   let name = "TestDialect";
   let cppNamespace = "::test";
 }
 
 class TestType<string name> : TypeDef<Test_Dialect, name> { }