This is an archive of the discontinued LLVM Phabricator instance.

Differential D138810

[RISCV] Support vector crypto extension C intrinsics
ClosedPublic

Authored by 4vtomat on Nov 28 2022, 6:31 AM.

Details

Reviewers
michaelmaitland
asb
ego
craig.topper
kito-cheng
Commits
rG2a05a5215f69: [RISCV] Support vector crypto extension C intrinsics
Summary

This patch implements vector crypto C intrinsics regarding to https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/234.

Depends on D141672, D138809

Diff Detail

Event Timeline

4vtomat created this revision.Nov 28 2022, 6:31 AM
Herald added a project: Restricted Project. · View Herald TranscriptNov 28 2022, 6:32 AM
Herald added subscribers: sunshaoce, VincentWu, vkmr and 27 others. · View Herald Transcript
4vtomat requested review of this revision.Nov 28 2022, 6:32 AM
Herald added a project: Restricted Project. · View Herald TranscriptNov 28 2022, 6:32 AM
Herald added subscribers: cfe-commits, • pcwang-thead, eopXD, MaskRay. · View Herald Transcript
Harbormaster completed remote builds in B199747: Diff 478220.Nov 28 2022, 6:32 AM
4vtomat added a subscriber: craig.topper.Nov 28 2022, 6:34 AM
4vtomat edited the summary of this revision. (Show Details)Nov 28 2022, 6:41 AM
asb added a comment.Nov 30 2022, 2:45 AM

Thanks for sharing these patches. I appreciate you're probably not expecting in-depth reviews at this point, but if you could update the patch description to link to the current spec for these intrinsics it would be a lot easier for anyone who is able to give some early feedback.

4vtomat updated this revision to Diff 479144.Nov 30 2022, 7:45 PM

Fixed the comment from Craig Topper and Philip Reames

Harbormaster completed remote builds in B200411: Diff 479144.Nov 30 2022, 7:45 PM
4vtomat updated this revision to Diff 508539.Mar 27 2023, 2:09 AM

Updated to spec version 20230206.

Herald added subscribers: jobnoorman, luke. · View Herald TranscriptMar 27 2023, 2:09 AM
Harbormaster completed remote builds in B221924: Diff 508539.Mar 27 2023, 7:51 PM
4vtomat updated this revision to Diff 517113.Apr 26 2023, 3:23 AM

Update to version 0.5.1.

asb added a comment.Apr 26 2023, 7:34 AM

I just wanted to check on whether this is ready to review? Also, to what degree are these intrinsics standardised and where is the relevant specification for them? Thanks!

4vtomat added a comment.Jun 12 2023, 7:40 PM

Sorry for late reply, this is the relevant spec for C intrinsics: https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/234
I will update the patch according to this! Thanks!

evandro removed a subscriber: evandro.Jun 14 2023, 8:04 AM
michaelmaitland added a reviewer: michaelmaitland.Jun 14 2023, 9:23 AM
4vtomat updated this revision to Diff 535696.Jun 29 2023, 2:47 AM

Ready for review

Herald added a subscriber: wangpc. · View Herald TranscriptJun 29 2023, 2:48 AM
4vtomat added reviewers: asb, ego, craig.topper, kito-cheng.Jun 29 2023, 2:51 AM
4vtomat edited the summary of this revision. (Show Details)
4vtomat added a parent revision: D141672: [RISCV] Support vector crypto extension ISA string and assembly.
Harbormaster completed remote builds in B242018: Diff 535696.Jun 29 2023, 3:35 AM
craig.topper added inline comments.Jul 5 2023, 3:59 PM
clang/include/clang/Basic/riscv_vector.td
2386

What does P in this name mean? Is this because they use OP_P as their opcode? If so I don't think that should be part of how we name intrinsics.

2387

Zvkb doesn't exist anymore

2431

I think I'd prefer to see the Zvbb instructions use their own class and not try to make RVVOutBuiltinSetP handle them and instructions that set HasVS.

2457

I think the Ue needs a K since its required to be a constant? Also need to update SemaChecking to verify the valid range.

I'm not sure whether we should use Ue or 'z' for constants.

2458

vaeskf2 needs K to mark the scalar as a constant. Should maybe use z instead of Ue. Need to update SemaChecking.cpp

2468

I think the Ue needs a K since its required to be a constant? Also need to update SemaChecking to verify the valid range.

I'm not sure whether we should use Ue or 'z' for constants.

2472

vsm3c needs K to mark the scalar as a constant. Should maybe use z instead of Ue. Need to update SemaChecking.cpp

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaeskf1.c
13

uimm is not used

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm3c.c
13

uimm isn't used

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vror.c
13

The intrinsic spec does not define rotates for signed types

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm4k.c
13

uimm is unused

14

Need to update SemaChecking.cpp to check the valid range for the immediate.

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsll.c
13

Shift amounts should always be unsigned

22

Scalar shift amount should be size_t to match other shifts. This was raised on the intrinsic PR

michaelmaitland added a comment.Jul 9 2023, 1:15 PM

Can you please add a description for this patch?

michaelmaitland mentioned this in D138809: [RISCV] Support vector crypto extension LLVM IR.Jul 9 2023, 1:55 PM
michaelmaitland added inline comments.Jul 9 2023, 2:05 PM
clang/include/clang/Basic/riscv_vector.td
2389

Why do we check HasVS when assigning suffix vv? I would have expected we use HasVV. In addition, why do we need to check !eq(NAME, "vsm4r") instead of setting the HasVV for that instruction?

2408

Why not set HasVS=1 and HasVV=0 for vaesz instead of checking !if(!eq(NAME, "vgmul"),...?

Also, do you mean to be discussing vaesz in the comment but use vgmul below?

4vtomat edited the summary of this revision. (Show Details)Jul 10 2023, 6:09 AM
4vtomat updated this revision to Diff 539402.Jul 11 2023, 11:33 PM
4vtomat marked 12 inline comments as done.

Resolved Craig's and Michael's comments.

4vtomat marked 2 inline comments as done.Jul 12 2023, 12:59 AM
4vtomat added inline comments.
clang/include/clang/Basic/riscv_vector.td
2386

Sure, I will rename by appending Zvk suffix for clarifying it's meaning~

2389

We check HasVS when assigning suffix vv because when the instruction has both VV and VS version, it uses double v as suffix, but if it just has VS version, it will use single v as suffix, that's why we check if it also has VS version in HasVV statement.
As per spec, the instruction name is vsm4r.v(single v), so it's an exception for HasVV case.

2408

The reason we set these condition to check vaesz and vgmul is because they are exceptions.
They don't need suffix in their overloaded name since they only have one version.
HasVS=1 and HasVV=0 is not enough to determine this situation.

2431

It's a good idea, it will be much clearer and reduce the code size, thanks!

2457

I'm not sure what's the difference between e and z, but seems both of them works fine.
However K is needed.

Harbormaster completed remote builds in B244682: Diff 539402.Jul 12 2023, 2:23 AM
eopXD added inline comments.Jul 17 2023, 11:12 AM
clang/lib/Sema/SemaChecking.cpp
4576 ↗(On Diff #539402)

Valid range of vaeskf1, vaeskf2 seems to be 0 to 15. [0]
Valid range of vsm4k seems to be 0 to 7 [1].

[0] https://github.com/riscv/riscv-crypto/blob/master/doc/vector/insns/vaeskf1.adoc
[1] https://github.com/riscv/riscv-crypto/blob/master/doc/vector/insns/vsm4k.adoc

craig.topper added inline comments.Jul 17 2023, 6:11 PM
clang/lib/Sema/SemaChecking.cpp
4576 ↗(On Diff #539402)

I think the field in the instruction is 5 bits, but vaeskf1 and vaeskf2 ignore bit 4. The true valid range is 1-10. The other values are aliased to one of the valid values. Should the intrinsic interface expose all 32 possible values or just 1-10?

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsll.c
13

It doesn't make sense for op2 to be signed. It's a shift amount, its always a positive number

23

scalar shift amounts should be size_t

craig.topper added inline comments.Jul 17 2023, 6:15 PM
clang/include/clang/Basic/riscv_vector.td
2413

Can we split this into two classes and get rid of IsVV?

craig.topper added inline comments.Jul 17 2023, 6:16 PM
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsll.c
13

The spec doesn't define signed versions of these instrinsics from what I can see.

craig.topper added inline comments.Jul 17 2023, 6:18 PM
clang/lib/Sema/SemaChecking.cpp
4576 ↗(On Diff #539402)

1-10 is the valid range for vaeskf1. vaeskf2 is 2-14.

craig.topper added inline comments.Jul 18 2023, 5:15 PM
clang/lib/Sema/SemaChecking.cpp
4576 ↗(On Diff #539402)

Let's leave it 0-31 for now and maybe start a conversation on crypto or intrinsic github.

4vtomat updated this revision to Diff 544624.Jul 26 2023, 11:58 PM
4vtomat marked 5 inline comments as done.

After discusstion in https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/234,
we will have multiple lmuls for scalar type operands.
Currently the test cases for those instructions are only presented in vaesdf,
all other instructions test cases will be copied from rvv-intrinsic-doc once
they're ready.
Also added test case for sema checking for checking valid lmul.

Harbormaster completed remote builds in B248449: Diff 544624.Jul 27 2023, 12:25 AM
craig.topper added inline comments.Aug 2 2023, 10:53 AM
clang/lib/Sema/SemaChecking.cpp
4496 ↗(On Diff #544624)

InValid -> Invalid

4499 ↗(On Diff #544624)

Can this be a plain array or a std::array instead of SmallVector since the size is fixed.

4693 ↗(On Diff #544624)

Are there tu versions of these builtins?

clang/test/Sema/zvk-invalid.c
19 ↗(On Diff #544624)

Test a _vs intrinsic since the vs operand has a different type than the result?

4vtomat updated this revision to Diff 546671.Aug 2 2023, 7:31 PM
4vtomat marked 3 inline comments as done.

This update does a few things:

  1. Update Craig's comments.
  2. Make LMUL=8 valid(https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/234#discussion_r1282568330).
  3. Rebase.
clang/include/clang/Basic/riscv_vector.td
2413

Sure, good idea~

clang/lib/Sema/SemaChecking.cpp
4693 ↗(On Diff #544624)

Yes, there are, thanks for reminding!

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsll.c
13

You are right, maybe it should only be signed version!

clang/test/Sema/zvk-invalid.c
19 ↗(On Diff #544624)

Sure~

4vtomat updated this revision to Diff 546677.Aug 2 2023, 8:17 PM

Update missing comment.

4vtomat marked an inline comment as done.Aug 2 2023, 8:18 PM
Harbormaster completed remote builds in B249938: Diff 546677.Aug 2 2023, 9:15 PM
4vtomat updated this revision to Diff 546746.Aug 3 2023, 1:46 AM

This update does a few things:

  1. Update test cases based on rvv-intrinsic-doc.
  2. Add checks for "zvknh[a|b]" instructions.
  3. Rename and restructure the function from CheckInvalidEGW to CheckInvalidVLENandLMUL.
craig.topper accepted this revision.Aug 8 2023, 4:24 PM

LGTM

This revision is now accepted and ready to land.Aug 8 2023, 4:24 PM
This revision was landed with ongoing or failed builds.Aug 8 2023, 5:10 PM
Closed by commit rG2a05a5215f69: [RISCV] Support vector crypto extension C intrinsics (authored by 4vtomat). · Explain Why
This revision was automatically updated to reflect the committed changes.
4vtomat added a commit: rG2a05a5215f69: [RISCV] Support vector crypto extension C intrinsics.
dyung added a subscriber: dyung.Aug 8 2023, 6:37 PM

The test you added clang/test/Sema/zvk-invalid.c is failing on bots, for example https://lab.llvm.org/buildbot/#/builders/139/builds/47055.

Is the test missing a REQUIRES: riscv-registered-target line by any chance?

4vtomat added a comment.Aug 8 2023, 6:41 PM
In D138810#4571579, @dyung wrote:

The test you added clang/test/Sema/zvk-invalid.c is failing on bots, for example https://lab.llvm.org/buildbot/#/builders/139/builds/47055.

Is the test missing a REQUIRES: riscv-registered-target line by any chance?

Yeah, you are right, I will have a patch to fix it, thanks!

rui.zhang added a subscriber: rui.zhang.Aug 9 2023, 4:25 PM

Large Diff

This large diff affects 113 files. Files without inline comments have been collapsed. Expand All Files

Revision Contents

PathSize
clang/
include/
clang/
Basic/
95 lines
test/
CodeGen/
RISCV/
rvv-intrinsics-autogenerated/
non-policy/
non-overloaded/
96 lines
96 lines
96 lines
96 lines
51 lines
51 lines
51 lines
1590 lines
402 lines
402 lines
150 lines
150 lines
402 lines
402 lines
402 lines
51 lines
51 lines
402 lines
1590 lines
1590 lines
87 lines
87 lines
87 lines
51 lines
51 lines
51 lines
96 lines
1085 lines
overloaded/
96 lines
96 lines
96 lines
96 lines
51 lines
51 lines
51 lines
1590 lines
402 lines
402 lines
150 lines
150 lines
402 lines
402 lines
402 lines
51 lines
51 lines
402 lines
1590 lines
1590 lines
87 lines
87 lines
87 lines
51 lines
51 lines
51 lines
96 lines
1085 lines
policy/
non-overloaded/
96 lines
96 lines
96 lines
96 lines
51 lines
51 lines
51 lines
3174 lines
798 lines
798 lines
294 lines
294 lines
798 lines
798 lines
798 lines
51 lines
51 lines
798 lines
3174 lines
3174 lines
87 lines
87 lines
87 lines
51 lines
51 lines
51 lines
96 lines
2165 lines
overloaded/
96 lines
96 lines
96 lines
96 lines
51 lines
51 lines
51 lines
3174 lines
798 lines
798 lines
294 lines
294 lines
798 lines
798 lines
798 lines
51 lines
51 lines
798 lines
3174 lines
3174 lines
87 lines
87 lines
87 lines
51 lines
51 lines
51 lines
96 lines
2165 lines

Diff 517113

clang/include/clang/Basic/riscv_vector.td

Show First 20 Lines • Show All 319 Lines • ▼ Show 20 Linesmulticlass RVVUnsignedBinBuiltinSet
: RVVOutOp1BuiltinSet<NAME, "csil", : RVVOutOp1BuiltinSet<NAME, "csil",
[["vv", "Uv", "UvUvUv"], [["vv", "Uv", "UvUvUv"],
["vx", "Uv", "UvUvUe"]]>; ["vx", "Uv", "UvUvUe"]]>;
multiclass RVVIntBinBuiltinSet multiclass RVVIntBinBuiltinSet
: RVVSignedBinBuiltinSet, : RVVSignedBinBuiltinSet,
RVVUnsignedBinBuiltinSet; RVVUnsignedBinBuiltinSet;
multiclass RVVInt64BinBuiltinSet
: RVVOutOp1BuiltinSet<NAME, "l",
[["vv", "v", "vvv"],
["vx", "v", "vve"]]>,
RVVOutOp1BuiltinSet<NAME, "l",
[["vv", "Uv", "UvUvUv"],
["vx", "Uv", "UvUvUe"]]>;
multiclass RVVSlideOneBuiltinSet multiclass RVVSlideOneBuiltinSet
: RVVOutOp1BuiltinSet<NAME, "csil", : RVVOutOp1BuiltinSet<NAME, "csil",
[["vx", "v", "vve"], [["vx", "v", "vve"],
["vx", "Uv", "UvUve"]]>; ["vx", "Uv", "UvUve"]]>;
multiclass RVVSignedShiftBuiltinSet multiclass RVVSignedShiftBuiltinSet
: RVVOutOp1BuiltinSet<NAME, "csil", : RVVOutOp1BuiltinSet<NAME, "csil",
[["vv", "v", "vvUv"], [["vv", "v", "vvUv"],
▲ Show 20 Lines • Show All 2,033 Lines • ▼ Show 20 Lines let Name = "vset_v", Log2LMUL = [0, 1, 2], MaskedPolicyScheme = NonePolicy,
} }
}] in { }] in {
foreach dst_lmul = ["(LFixedLog2LMUL:1)", "(LFixedLog2LMUL:2)", "(LFixedLog2LMUL:3)"] in { foreach dst_lmul = ["(LFixedLog2LMUL:1)", "(LFixedLog2LMUL:2)", "(LFixedLog2LMUL:3)"] in {
def : RVVBuiltin<"v" # dst_lmul # "v", dst_lmul # "v" # dst_lmul # "vKzv", "csilxfd">; def : RVVBuiltin<"v" # dst_lmul # "v", dst_lmul # "v" # dst_lmul # "vKzv", "csilxfd">;
def : RVVBuiltin<"Uv" # dst_lmul # "Uv", dst_lmul # "Uv" # dst_lmul #"UvKzUv", "csil">; def : RVVBuiltin<"Uv" # dst_lmul # "Uv", dst_lmul # "Uv" # dst_lmul #"UvKzUv", "csil">;
} }
} }
} }
multiclass RVVOutBuiltinSetP<bit HasVV = 1, bit HasVS = 1, bit HasSigned = 0,
craig.topperUnsubmitted
Done
ReplyInline Actions

What does P in this name mean? Is this because they use OP_P as their opcode? If so I don't think that should be part of how we name intrinsics.

craig.topper: What does `P` in this name mean? Is this because they use OP_P as their opcode? If so I don't…
4vtomatAuthorUnsubmitted
Done
ReplyInline Actions

Sure, I will rename by appending Zvk suffix for clarifying it's meaning~

4vtomat: Sure, I will rename by appending Zvk suffix for clarifying it's meaning~
string type_range = "i", bit IsZvkb = 0> {
craig.topperUnsubmitted
Done
ReplyInline Actions

Zvkb doesn't exist anymore

craig.topper: Zvkb doesn't exist anymore
if HasVV then {
defvar suffix = !if(!or(HasVS, !eq(NAME, "vsm4r")), "vv", "v");
michaelmaitlandUnsubmitted
Done
ReplyInline Actions

Why do we check HasVS when assigning suffix vv? I would have expected we use HasVV. In addition, why do we need to check !eq(NAME, "vsm4r") instead of setting the HasVV for that instruction?

michaelmaitland: Why do we check `HasVS` when assigning suffix `vv`? I would have expected we use `HasVV`. In…
4vtomatAuthorUnsubmitted
Done
ReplyInline Actions

We check HasVS when assigning suffix vv because when the instruction has both VV and VS version, it uses double v as suffix, but if it just has VS version, it will use single v as suffix, that's why we check if it also has VS version in HasVV statement.
As per spec, the instruction name is vsm4r.v(single v), so it's an exception for HasVV case.

4vtomat: We check `HasVS` when assigning suffix `vv` because when the instruction has both `VV` and `VS`…
// We don't need suffix in Zvkb extension since it's consider as normal
// arithmetic operation such as vadd. So we apply the same rule to this
// extension and re-use the APIs that are already defined.
defvar name = NAME # !if(IsZvkb, "", "_" # suffix);
let OverloadedName = name in
defm "" : RVVOutBuiltinSet<name, type_range,
!listconcat(!if(HasSigned,
[[suffix, "v", !if(!eq(type_range, "i"),
"vvv", "vv")]],
[]),
[[suffix, "Uv", !if(!eq(type_range, "i"),
"UvUvUv", "UvUv")]])>;
}
if HasVS then {
// vaesz only has 'vs' and does not have ambiguous prototypes like other
// zvkned instructions (e.g. vaesdf), so we don't need to encode the operand
// mnemonics into its intrinsic function name.
defvar name = NAME # !if(!or(IsZvkb, !eq(NAME, "vaesz")), "", "_vs");
michaelmaitlandUnsubmitted
Done
ReplyInline Actions

Why not set HasVS=1 and HasVV=0 for vaesz instead of checking !if(!eq(NAME, "vgmul"),...?

Also, do you mean to be discussing vaesz in the comment but use vgmul below?

michaelmaitland: Why not set `HasVS=1` and `HasVV=0` for `vaesz` instead of checking `!if(!eq(NAME, "vgmul"),...
4vtomatAuthorUnsubmitted
Done
ReplyInline Actions

The reason we set these condition to check vaesz and vgmul is because they are exceptions.
They don't need suffix in their overloaded name since they only have one version.
HasVS=1 and HasVV=0 is not enough to determine this situation.

4vtomat: The reason we set these condition to check `vaesz` and `vgmul` is because they are exceptions.
let OverloadedName = name in
defm "" : RVVOutOp1BuiltinSet<NAME # "_vs", type_range,
!listconcat(!if(HasSigned,
[["vs", "v", "vvSv"]],
[]),
craig.topperUnsubmitted
Done
ReplyInline Actions

Can we split this into two classes and get rid of IsVV?

craig.topper: Can we split this into two classes and get rid of IsVV?
4vtomatAuthorUnsubmitted
Done
ReplyInline Actions

Sure, good idea~

4vtomat: Sure, good idea~
[["vs", "Uv", "UvUvUSv"]])>;
}
}
multiclass RVVOutOp1BuiltinSetP<bit IsVV = 1, string type_range = "i"> {
defvar suffix = !if(IsVV, "vv", "vi");
defvar prototype = !if(IsVV, "UvUvUvUv", "UvUvUvUe");
defm "" : RVVBuiltinSet<NAME, type_range, [[suffix, "Uv", prototype]], [-1, 2]>;
}
let UnMaskedPolicyScheme = HasPassthruOperand in {
// zvbb
defm vandn : RVVIntBinBuiltinSet;
defm vbrev : RVVOutBuiltinSetP<1, 0, 1, "csil", 1>;
defm vbrev8 : RVVOutBuiltinSetP<1, 0, 1, "csil", 1>;
defm vrev8 : RVVOutBuiltinSetP<1, 0, 1, "csil", 1>;
defm vclz : RVVOutBuiltinSetP<1, 0, 1, "csil", 1>;
defm vctz : RVVOutBuiltinSetP<1, 0, 1, "csil", 1>;
craig.topperUnsubmitted
Done
ReplyInline Actions

I think I'd prefer to see the Zvbb instructions use their own class and not try to make RVVOutBuiltinSetP handle them and instructions that set HasVS.

craig.topper: I think I'd prefer to see the Zvbb instructions use their own class and not try to make…
4vtomatAuthorUnsubmitted
Done
ReplyInline Actions

It's a good idea, it will be much clearer and reduce the code size, thanks!

4vtomat: It's a good idea, it will be much clearer and reduce the code size, thanks!
defm vcpopv : RVVOutBuiltinSetP<1, 0, 1, "csil", 1>;
defm vrol : RVVIntBinBuiltinSet;
defm vror : RVVIntBinBuiltinSet;
defm vwsll : RVVUnsignedWidenBinBuiltinSet, RVVSignedWidenBinBuiltinSet;
// zvbc
defm vclmul : RVVInt64BinBuiltinSet;
defm vclmulh : RVVInt64BinBuiltinSet;
}
let UnMaskedPolicyScheme = HasPolicyOperand, HasMasked = false in {
// zvkg
defm vghsh : RVVOutOp1BuiltinSetP;
defm vgmul : RVVOutOp1BuiltinSetP;
// zvkned
defm vaesdf : RVVOutBuiltinSetP;
defm vaesdm : RVVOutBuiltinSetP;
defm vaesef : RVVOutBuiltinSetP;
defm vaesem : RVVOutBuiltinSetP;
let UnMaskedPolicyScheme = HasPassthruOperand in
defm vaeskf1 : RVVOutOp1BuiltinSet<"vaeskf1", "i", [["vi", "Uv", "UvUvUe"]]>;
defm vaeskf2 : RVVOutOp1BuiltinSetP<0>;
defm vaesz : RVVOutBuiltinSetP<0>;
// zvknha or zvknhb
craig.topperUnsubmitted
Done
ReplyInline Actions

I think the Ue needs a K since its required to be a constant? Also need to update SemaChecking to verify the valid range.

I'm not sure whether we should use Ue or 'z' for constants.

craig.topper: I think the `Ue` needs a `K` since its required to be a constant? Also need to update…
4vtomatAuthorUnsubmitted
Done
ReplyInline Actions

I'm not sure what's the difference between e and z, but seems both of them works fine.
However K is needed.

4vtomat: I'm not sure what's the difference between `e` and `z`, but seems both of them works fine.
defm vsha2ch : RVVOutOp1BuiltinSetP<1, "il">;
craig.topperUnsubmitted
Done
ReplyInline Actions

vaeskf2 needs K to mark the scalar as a constant. Should maybe use z instead of Ue. Need to update SemaChecking.cpp

craig.topper: vaeskf2 needs `K` to mark the scalar as a constant. Should maybe use `z` instead of `Ue`. Need…
defm vsha2cl : RVVOutOp1BuiltinSetP<1, "il">;
defm vsha2ms : RVVOutOp1BuiltinSetP<1, "il">;
// zvksed
let UnMaskedPolicyScheme = HasPassthruOperand in
defm vsm4k : RVVOutOp1BuiltinSet<"vsm4k", "i", [["vi", "Uv", "UvUvUe"]]>;
defm vsm4r : RVVOutBuiltinSetP;
// zvksh
defm vsm3c : RVVOutOp1BuiltinSetP<0>;
craig.topperUnsubmitted
Done
ReplyInline Actions

I think the Ue needs a K since its required to be a constant? Also need to update SemaChecking to verify the valid range.

I'm not sure whether we should use Ue or 'z' for constants.

craig.topper: I think the `Ue` needs a `K` since its required to be a constant? Also need to update…
let UnMaskedPolicyScheme = HasPassthruOperand in
defm vsm3me : RVVOutOp1BuiltinSet<"vsm3me", "i", [["vv", "Uv", "UvUvUv"]]>;
}
craig.topperUnsubmitted
Done
ReplyInline Actions

vsm3c needs K to mark the scalar as a constant. Should maybe use z instead of Ue. Need to update SemaChecking.cpp

craig.topper: vsm3c needs `K` to mark the scalar as a constant. Should maybe use `z` instead of `Ue`. Need to…

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdf.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdm.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesef.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesem.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaeskf1.c

  • This file was added.
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck %s
#include <riscv_vector.h>
// CHECK-LABEL: @test_vaeskf1_vi_u32mf2(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vaeskf1.nxv1i32.i32.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> [[VS2:%.*]], i32 0, i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
vuint32mf2_t test_vaeskf1_vi_u32mf2(vuint32mf2_t vs2, size_t uimm, size_t vl) {
return __riscv_vaeskf1_vi_u32mf2(vs2, 0, vl);
craig.topperUnsubmitted
Done
ReplyInline Actions

uimm is not used

craig.topper: `uimm` is not used
}
// CHECK-LABEL: @test_vaeskf1_vi_u32m1(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vaeskf1.nxv2i32.i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> [[VS2:%.*]], i32 0, i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
vuint32m1_t test_vaeskf1_vi_u32m1(vuint32m1_t vs2, size_t uimm, size_t vl) {
return __riscv_vaeskf1_vi_u32m1(vs2, 0, vl);
}
// CHECK-LABEL: @test_vaeskf1_vi_u32m2(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vaeskf1.nxv4i32.i32.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> [[VS2:%.*]], i32 0, i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
vuint32m2_t test_vaeskf1_vi_u32m2(vuint32m2_t vs2, size_t uimm, size_t vl) {
return __riscv_vaeskf1_vi_u32m2(vs2, 0, vl);
}
// CHECK-LABEL: @test_vaeskf1_vi_u32m4(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vaeskf1.nxv8i32.i32.i64(<vscale x 8 x i32> poison, <vscale x 8 x i32> [[VS2:%.*]], i32 0, i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
vuint32m4_t test_vaeskf1_vi_u32m4(vuint32m4_t vs2, size_t uimm, size_t vl) {
return __riscv_vaeskf1_vi_u32m4(vs2, 0, vl);
}
// CHECK-LABEL: @test_vaeskf1_vi_u32m8(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vaeskf1.nxv16i32.i32.i64(<vscale x 16 x i32> poison, <vscale x 16 x i32> [[VS2:%.*]], i32 0, i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
vuint32m8_t test_vaeskf1_vi_u32m8(vuint32m8_t vs2, size_t uimm, size_t vl) {
return __riscv_vaeskf1_vi_u32m8(vs2, 0, vl);
}

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaeskf2.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesz.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vandn.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vbrev.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vbrev8.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclmul.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclmulh.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclz.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpopv.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vctz.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vghsh.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vgmul.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrev8.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrol.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vror.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2ch.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2cl.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2ms.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm3c.c

  • This file was added.
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck %s
#include <riscv_vector.h>
// CHECK-LABEL: @test_vsm3c_vi_u32mf2(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vsm3c.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 0, i64 [[VL:%.*]], i64 3)
// CHECK-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
vuint32mf2_t test_vsm3c_vi_u32mf2(vuint32mf2_t vd, vuint32mf2_t vs2, size_t uimm, size_t vl) {
return __riscv_vsm3c_vi_u32mf2(vd, vs2, 0, vl);
craig.topperUnsubmitted
Done
ReplyInline Actions

uimm isn't used

craig.topper: `uimm` isn't used
}
// CHECK-LABEL: @test_vsm3c_vi_u32m1(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vsm3c.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 0, i64 [[VL:%.*]], i64 3)
// CHECK-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
vuint32m1_t test_vsm3c_vi_u32m1(vuint32m1_t vd, vuint32m1_t vs2, size_t uimm, size_t vl) {
return __riscv_vsm3c_vi_u32m1(vd, vs2, 0, vl);
}
// CHECK-LABEL: @test_vsm3c_vi_u32m2(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vsm3c.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 0, i64 [[VL:%.*]], i64 3)
// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
vuint32m2_t test_vsm3c_vi_u32m2(vuint32m2_t vd, vuint32m2_t vs2, size_t uimm, size_t vl) {
return __riscv_vsm3c_vi_u32m2(vd, vs2, 0, vl);
}
// CHECK-LABEL: @test_vsm3c_vi_u32m4(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vsm3c.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 0, i64 [[VL:%.*]], i64 3)
// CHECK-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
vuint32m4_t test_vsm3c_vi_u32m4(vuint32m4_t vd, vuint32m4_t vs2, size_t uimm, size_t vl) {
return __riscv_vsm3c_vi_u32m4(vd, vs2, 0, vl);
}
// CHECK-LABEL: @test_vsm3c_vi_u32m8(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vsm3c.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 0, i64 [[VL:%.*]], i64 3)
// CHECK-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
vuint32m8_t test_vsm3c_vi_u32m8(vuint32m8_t vd, vuint32m8_t vs2, size_t uimm, size_t vl) {
return __riscv_vsm3c_vi_u32m8(vd, vs2, 0, vl);
}

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm3me.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm4k.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm4r.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsll.c

  • This file was added.
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck %s
#include <riscv_vector.h>
// CHECK-LABEL: @test_vwsll_vv_i16mf4(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 1 x i16> [[TMP0]]
//
vint16mf4_t test_vwsll_vv_i16mf4(vint8mf8_t op1, vint8mf8_t op2, size_t vl) {
return __riscv_vwsll_vv_i16mf4(op1, op2, vl);
craig.topperUnsubmitted
Done
ReplyInline Actions

It doesn't make sense for op2 to be signed. It's a shift amount, its always a positive number

craig.topper: It doesn't make sense for op2 to be signed. It's a shift amount, its always a positive number
craig.topperUnsubmitted
Done
ReplyInline Actions

The spec doesn't define signed versions of these instrinsics from what I can see.

craig.topper: The spec doesn't define signed versions of these instrinsics from what I can see.
4vtomatAuthorUnsubmitted
Done
ReplyInline Actions

You are right, maybe it should only be signed version!

4vtomat: You are right, maybe it should only be signed version!
}
// CHECK-LABEL: @test_vwsll_vx_i16mf4(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 1 x i16> [[TMP0]]
//
vint16mf4_t test_vwsll_vx_i16mf4(vint8mf8_t op1, int8_t op2, size_t vl) {
return __riscv_vwsll_vx_i16mf4(op1, op2, vl);
}
craig.topperUnsubmitted
Done
ReplyInline Actions

scalar shift amounts should be size_t

craig.topper: scalar shift amounts should be size_t
// CHECK-LABEL: @test_vwsll_vv_i16mf2(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
vint16mf2_t test_vwsll_vv_i16mf2(vint8mf4_t op1, vint8mf4_t op2, size_t vl) {
return __riscv_vwsll_vv_i16mf2(op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i16mf2(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
vint16mf2_t test_vwsll_vx_i16mf2(vint8mf4_t op1, int8_t op2, size_t vl) {
return __riscv_vwsll_vx_i16mf2(op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i16m1(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
vint16m1_t test_vwsll_vv_i16m1(vint8mf2_t op1, vint8mf2_t op2, size_t vl) {
return __riscv_vwsll_vv_i16m1(op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i16m1(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
vint16m1_t test_vwsll_vx_i16m1(vint8mf2_t op1, int8_t op2, size_t vl) {
return __riscv_vwsll_vx_i16m1(op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i16m2(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
vint16m2_t test_vwsll_vv_i16m2(vint8m1_t op1, vint8m1_t op2, size_t vl) {
return __riscv_vwsll_vv_i16m2(op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i16m2(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
vint16m2_t test_vwsll_vx_i16m2(vint8m1_t op1, int8_t op2, size_t vl) {
return __riscv_vwsll_vx_i16m2(op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i16m4(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwsll.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
vint16m4_t test_vwsll_vv_i16m4(vint8m2_t op1, vint8m2_t op2, size_t vl) {
return __riscv_vwsll_vv_i16m4(op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i16m4(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwsll.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
vint16m4_t test_vwsll_vx_i16m4(vint8m2_t op1, int8_t op2, size_t vl) {
return __riscv_vwsll_vx_i16m4(op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i16m8(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwsll.nxv32i16.nxv32i8.nxv32i8.i64(<vscale x 32 x i16> poison, <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
vint16m8_t test_vwsll_vv_i16m8(vint8m4_t op1, vint8m4_t op2, size_t vl) {
return __riscv_vwsll_vv_i16m8(op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i16m8(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwsll.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16> poison, <vscale x 32 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
vint16m8_t test_vwsll_vx_i16m8(vint8m4_t op1, int8_t op2, size_t vl) {
return __riscv_vwsll_vx_i16m8(op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i32mf2(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwsll.nxv1i32.nxv1i16.nxv1i16.i64(<vscale x 1 x i32> poison, <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
vint32mf2_t test_vwsll_vv_i32mf2(vint16mf4_t op1, vint16mf4_t op2, size_t vl) {
return __riscv_vwsll_vv_i32mf2(op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i32mf2(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwsll.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32> poison, <vscale x 1 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
vint32mf2_t test_vwsll_vx_i32mf2(vint16mf4_t op1, int16_t op2, size_t vl) {
return __riscv_vwsll_vx_i32mf2(op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i32m1(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwsll.nxv2i32.nxv2i16.nxv2i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
vint32m1_t test_vwsll_vv_i32m1(vint16mf2_t op1, vint16mf2_t op2, size_t vl) {
return __riscv_vwsll_vv_i32m1(op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i32m1(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwsll.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
vint32m1_t test_vwsll_vx_i32m1(vint16mf2_t op1, int16_t op2, size_t vl) {
return __riscv_vwsll_vx_i32m1(op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i32m2(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwsll.nxv4i32.nxv4i16.nxv4i16.i64(<vscale x 4 x i32> poison, <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
vint32m2_t test_vwsll_vv_i32m2(vint16m1_t op1, vint16m1_t op2, size_t vl) {
return __riscv_vwsll_vv_i32m2(op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i32m2(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwsll.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32> poison, <vscale x 4 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
vint32m2_t test_vwsll_vx_i32m2(vint16m1_t op1, int16_t op2, size_t vl) {
return __riscv_vwsll_vx_i32m2(op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i32m4(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwsll.nxv8i32.nxv8i16.nxv8i16.i64(<vscale x 8 x i32> poison, <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
vint32m4_t test_vwsll_vv_i32m4(vint16m2_t op1, vint16m2_t op2, size_t vl) {
return __riscv_vwsll_vv_i32m4(op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i32m4(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwsll.nxv8i32.nxv8i16.i16.i64(<vscale x 8 x i32> poison, <vscale x 8 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
vint32m4_t test_vwsll_vx_i32m4(vint16m2_t op1, int16_t op2, size_t vl) {
return __riscv_vwsll_vx_i32m4(op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i32m8(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwsll.nxv16i32.nxv16i16.nxv16i16.i64(<vscale x 16 x i32> poison, <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
vint32m8_t test_vwsll_vv_i32m8(vint16m4_t op1, vint16m4_t op2, size_t vl) {
return __riscv_vwsll_vv_i32m8(op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i32m8(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwsll.nxv16i32.nxv16i16.i16.i64(<vscale x 16 x i32> poison, <vscale x 16 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
vint32m8_t test_vwsll_vx_i32m8(vint16m4_t op1, int16_t op2, size_t vl) {
return __riscv_vwsll_vx_i32m8(op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i64m1(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwsll.nxv1i64.nxv1i32.nxv1i32.i64(<vscale x 1 x i64> poison, <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 1 x i64> [[TMP0]]
//
vint64m1_t test_vwsll_vv_i64m1(vint32mf2_t op1, vint32mf2_t op2, size_t vl) {
return __riscv_vwsll_vv_i64m1(op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i64m1(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwsll.nxv1i64.nxv1i32.i32.i64(<vscale x 1 x i64> poison, <vscale x 1 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 1 x i64> [[TMP0]]
//
vint64m1_t test_vwsll_vx_i64m1(vint32mf2_t op1, int32_t op2, size_t vl) {
return __riscv_vwsll_vx_i64m1(op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i64m2(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwsll.nxv2i64.nxv2i32.nxv2i32.i64(<vscale x 2 x i64> poison, <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
vint64m2_t test_vwsll_vv_i64m2(vint32m1_t op1, vint32m1_t op2, size_t vl) {
return __riscv_vwsll_vv_i64m2(op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i64m2(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwsll.nxv2i64.nxv2i32.i32.i64(<vscale x 2 x i64> poison, <vscale x 2 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
vint64m2_t test_vwsll_vx_i64m2(vint32m1_t op1, int32_t op2, size_t vl) {
return __riscv_vwsll_vx_i64m2(op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i64m4(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwsll.nxv4i64.nxv4i32.nxv4i32.i64(<vscale x 4 x i64> poison, <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
vint64m4_t test_vwsll_vv_i64m4(vint32m2_t op1, vint32m2_t op2, size_t vl) {
return __riscv_vwsll_vv_i64m4(op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i64m4(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwsll.nxv4i64.nxv4i32.i32.i64(<vscale x 4 x i64> poison, <vscale x 4 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
vint64m4_t test_vwsll_vx_i64m4(vint32m2_t op1, int32_t op2, size_t vl) {
return __riscv_vwsll_vx_i64m4(op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i64m8(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwsll.nxv8i64.nxv8i32.nxv8i32.i64(<vscale x 8 x i64> poison, <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
vint64m8_t test_vwsll_vv_i64m8(vint32m4_t op1, vint32m4_t op2, size_t vl) {
return __riscv_vwsll_vv_i64m8(op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i64m8(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwsll.nxv8i64.nxv8i32.i32.i64(<vscale x 8 x i64> poison, <vscale x 8 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
vint64m8_t test_vwsll_vx_i64m8(vint32m4_t op1, int32_t op2, size_t vl) {
return __riscv_vwsll_vx_i64m8(op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i16mf4_m(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwsll.mask.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
// CHECK-NEXT: ret <vscale x 1 x i16> [[TMP0]]
//
vint16mf4_t test_vwsll_vv_i16mf4_m(vbool64_t mask, vint8mf8_t op1, vint8mf8_t op2, size_t vl) {
return __riscv_vwsll_vv_i16mf4_m(mask, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i16mf4_m(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwsll.mask.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
// CHECK-NEXT: ret <vscale x 1 x i16> [[TMP0]]
//
vint16mf4_t test_vwsll_vx_i16mf4_m(vbool64_t mask, vint8mf8_t op1, int8_t op2, size_t vl) {
return __riscv_vwsll_vx_i16mf4_m(mask, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i16mf2_m(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwsll.mask.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
// CHECK-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
vint16mf2_t test_vwsll_vv_i16mf2_m(vbool32_t mask, vint8mf4_t op1, vint8mf4_t op2, size_t vl) {
return __riscv_vwsll_vv_i16mf2_m(mask, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i16mf2_m(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwsll.mask.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
// CHECK-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
vint16mf2_t test_vwsll_vx_i16mf2_m(vbool32_t mask, vint8mf4_t op1, int8_t op2, size_t vl) {
return __riscv_vwsll_vx_i16mf2_m(mask, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i16m1_m(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwsll.mask.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
// CHECK-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
vint16m1_t test_vwsll_vv_i16m1_m(vbool16_t mask, vint8mf2_t op1, vint8mf2_t op2, size_t vl) {
return __riscv_vwsll_vv_i16m1_m(mask, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i16m1_m(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwsll.mask.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
// CHECK-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
vint16m1_t test_vwsll_vx_i16m1_m(vbool16_t mask, vint8mf2_t op1, int8_t op2, size_t vl) {
return __riscv_vwsll_vx_i16m1_m(mask, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i16m2_m(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwsll.mask.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
vint16m2_t test_vwsll_vv_i16m2_m(vbool8_t mask, vint8m1_t op1, vint8m1_t op2, size_t vl) {
return __riscv_vwsll_vv_i16m2_m(mask, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i16m2_m(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwsll.mask.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
vint16m2_t test_vwsll_vx_i16m2_m(vbool8_t mask, vint8m1_t op1, int8_t op2, size_t vl) {
return __riscv_vwsll_vx_i16m2_m(mask, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i16m4_m(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwsll.mask.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
// CHECK-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
vint16m4_t test_vwsll_vv_i16m4_m(vbool4_t mask, vint8m2_t op1, vint8m2_t op2, size_t vl) {
return __riscv_vwsll_vv_i16m4_m(mask, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i16m4_m(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwsll.mask.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
// CHECK-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
vint16m4_t test_vwsll_vx_i16m4_m(vbool4_t mask, vint8m2_t op1, int8_t op2, size_t vl) {
return __riscv_vwsll_vx_i16m4_m(mask, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i16m8_m(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwsll.mask.nxv32i16.nxv32i8.nxv32i8.i64(<vscale x 32 x i16> poison, <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
// CHECK-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
vint16m8_t test_vwsll_vv_i16m8_m(vbool2_t mask, vint8m4_t op1, vint8m4_t op2, size_t vl) {
return __riscv_vwsll_vv_i16m8_m(mask, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i16m8_m(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwsll.mask.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16> poison, <vscale x 32 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
// CHECK-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
vint16m8_t test_vwsll_vx_i16m8_m(vbool2_t mask, vint8m4_t op1, int8_t op2, size_t vl) {
return __riscv_vwsll_vx_i16m8_m(mask, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i32mf2_m(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwsll.mask.nxv1i32.nxv1i16.nxv1i16.i64(<vscale x 1 x i32> poison, <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
// CHECK-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
vint32mf2_t test_vwsll_vv_i32mf2_m(vbool64_t mask, vint16mf4_t op1, vint16mf4_t op2, size_t vl) {
return __riscv_vwsll_vv_i32mf2_m(mask, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i32mf2_m(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwsll.mask.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32> poison, <vscale x 1 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
// CHECK-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
vint32mf2_t test_vwsll_vx_i32mf2_m(vbool64_t mask, vint16mf4_t op1, int16_t op2, size_t vl) {
return __riscv_vwsll_vx_i32mf2_m(mask, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i32m1_m(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwsll.mask.nxv2i32.nxv2i16.nxv2i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
// CHECK-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
vint32m1_t test_vwsll_vv_i32m1_m(vbool32_t mask, vint16mf2_t op1, vint16mf2_t op2, size_t vl) {
return __riscv_vwsll_vv_i32m1_m(mask, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i32m1_m(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwsll.mask.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
// CHECK-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
vint32m1_t test_vwsll_vx_i32m1_m(vbool32_t mask, vint16mf2_t op1, int16_t op2, size_t vl) {
return __riscv_vwsll_vx_i32m1_m(mask, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i32m2_m(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwsll.mask.nxv4i32.nxv4i16.nxv4i16.i64(<vscale x 4 x i32> poison, <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
vint32m2_t test_vwsll_vv_i32m2_m(vbool16_t mask, vint16m1_t op1, vint16m1_t op2, size_t vl) {
return __riscv_vwsll_vv_i32m2_m(mask, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i32m2_m(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwsll.mask.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32> poison, <vscale x 4 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
vint32m2_t test_vwsll_vx_i32m2_m(vbool16_t mask, vint16m1_t op1, int16_t op2, size_t vl) {
return __riscv_vwsll_vx_i32m2_m(mask, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i32m4_m(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwsll.mask.nxv8i32.nxv8i16.nxv8i16.i64(<vscale x 8 x i32> poison, <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
// CHECK-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
vint32m4_t test_vwsll_vv_i32m4_m(vbool8_t mask, vint16m2_t op1, vint16m2_t op2, size_t vl) {
return __riscv_vwsll_vv_i32m4_m(mask, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i32m4_m(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwsll.mask.nxv8i32.nxv8i16.i16.i64(<vscale x 8 x i32> poison, <vscale x 8 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
// CHECK-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
vint32m4_t test_vwsll_vx_i32m4_m(vbool8_t mask, vint16m2_t op1, int16_t op2, size_t vl) {
return __riscv_vwsll_vx_i32m4_m(mask, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i32m8_m(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwsll.mask.nxv16i32.nxv16i16.nxv16i16.i64(<vscale x 16 x i32> poison, <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
// CHECK-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
vint32m8_t test_vwsll_vv_i32m8_m(vbool4_t mask, vint16m4_t op1, vint16m4_t op2, size_t vl) {
return __riscv_vwsll_vv_i32m8_m(mask, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i32m8_m(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwsll.mask.nxv16i32.nxv16i16.i16.i64(<vscale x 16 x i32> poison, <vscale x 16 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
// CHECK-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
vint32m8_t test_vwsll_vx_i32m8_m(vbool4_t mask, vint16m4_t op1, int16_t op2, size_t vl) {
return __riscv_vwsll_vx_i32m8_m(mask, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i64m1_m(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwsll.mask.nxv1i64.nxv1i32.nxv1i32.i64(<vscale x 1 x i64> poison, <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
// CHECK-NEXT: ret <vscale x 1 x i64> [[TMP0]]
//
vint64m1_t test_vwsll_vv_i64m1_m(vbool64_t mask, vint32mf2_t op1, vint32mf2_t op2, size_t vl) {
return __riscv_vwsll_vv_i64m1_m(mask, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i64m1_m(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwsll.mask.nxv1i64.nxv1i32.i32.i64(<vscale x 1 x i64> poison, <vscale x 1 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
// CHECK-NEXT: ret <vscale x 1 x i64> [[TMP0]]
//
vint64m1_t test_vwsll_vx_i64m1_m(vbool64_t mask, vint32mf2_t op1, int32_t op2, size_t vl) {
return __riscv_vwsll_vx_i64m1_m(mask, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i64m2_m(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwsll.mask.nxv2i64.nxv2i32.nxv2i32.i64(<vscale x 2 x i64> poison, <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
vint64m2_t test_vwsll_vv_i64m2_m(vbool32_t mask, vint32m1_t op1, vint32m1_t op2, size_t vl) {
return __riscv_vwsll_vv_i64m2_m(mask, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i64m2_m(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwsll.mask.nxv2i64.nxv2i32.i32.i64(<vscale x 2 x i64> poison, <vscale x 2 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
vint64m2_t test_vwsll_vx_i64m2_m(vbool32_t mask, vint32m1_t op1, int32_t op2, size_t vl) {
return __riscv_vwsll_vx_i64m2_m(mask, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i64m4_m(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwsll.mask.nxv4i64.nxv4i32.nxv4i32.i64(<vscale x 4 x i64> poison, <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
// CHECK-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
vint64m4_t test_vwsll_vv_i64m4_m(vbool16_t mask, vint32m2_t op1, vint32m2_t op2, size_t vl) {
return __riscv_vwsll_vv_i64m4_m(mask, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i64m4_m(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwsll.mask.nxv4i64.nxv4i32.i32.i64(<vscale x 4 x i64> poison, <vscale x 4 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
// CHECK-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
vint64m4_t test_vwsll_vx_i64m4_m(vbool16_t mask, vint32m2_t op1, int32_t op2, size_t vl) {
return __riscv_vwsll_vx_i64m4_m(mask, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i64m8_m(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwsll.mask.nxv8i64.nxv8i32.nxv8i32.i64(<vscale x 8 x i64> poison, <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
// CHECK-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
vint64m8_t test_vwsll_vv_i64m8_m(vbool8_t mask, vint32m4_t op1, vint32m4_t op2, size_t vl) {
return __riscv_vwsll_vv_i64m8_m(mask, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i64m8_m(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwsll.mask.nxv8i64.nxv8i32.i32.i64(<vscale x 8 x i64> poison, <vscale x 8 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
// CHECK-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
vint64m8_t test_vwsll_vx_i64m8_m(vbool8_t mask, vint32m4_t op1, int32_t op2, size_t vl) {
return __riscv_vwsll_vx_i64m8_m(mask, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u16mf4(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 1 x i16> [[TMP0]]
//
vuint16mf4_t test_vwsll_vv_u16mf4(vuint8mf8_t op1, vuint8mf8_t op2, size_t vl) {
return __riscv_vwsll_vv_u16mf4(op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u16mf4(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 1 x i16> [[TMP0]]
//
vuint16mf4_t test_vwsll_vx_u16mf4(vuint8mf8_t op1, uint8_t op2, size_t vl) {
return __riscv_vwsll_vx_u16mf4(op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u16mf2(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
vuint16mf2_t test_vwsll_vv_u16mf2(vuint8mf4_t op1, vuint8mf4_t op2, size_t vl) {
return __riscv_vwsll_vv_u16mf2(op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u16mf2(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
vuint16mf2_t test_vwsll_vx_u16mf2(vuint8mf4_t op1, uint8_t op2, size_t vl) {
return __riscv_vwsll_vx_u16mf2(op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u16m1(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
vuint16m1_t test_vwsll_vv_u16m1(vuint8mf2_t op1, vuint8mf2_t op2, size_t vl) {
return __riscv_vwsll_vv_u16m1(op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u16m1(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
vuint16m1_t test_vwsll_vx_u16m1(vuint8mf2_t op1, uint8_t op2, size_t vl) {
return __riscv_vwsll_vx_u16m1(op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u16m2(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
vuint16m2_t test_vwsll_vv_u16m2(vuint8m1_t op1, vuint8m1_t op2, size_t vl) {
return __riscv_vwsll_vv_u16m2(op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u16m2(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
vuint16m2_t test_vwsll_vx_u16m2(vuint8m1_t op1, uint8_t op2, size_t vl) {
return __riscv_vwsll_vx_u16m2(op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u16m4(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwsll.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
vuint16m4_t test_vwsll_vv_u16m4(vuint8m2_t op1, vuint8m2_t op2, size_t vl) {
return __riscv_vwsll_vv_u16m4(op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u16m4(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwsll.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
vuint16m4_t test_vwsll_vx_u16m4(vuint8m2_t op1, uint8_t op2, size_t vl) {
return __riscv_vwsll_vx_u16m4(op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u16m8(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwsll.nxv32i16.nxv32i8.nxv32i8.i64(<vscale x 32 x i16> poison, <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
vuint16m8_t test_vwsll_vv_u16m8(vuint8m4_t op1, vuint8m4_t op2, size_t vl) {
return __riscv_vwsll_vv_u16m8(op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u16m8(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwsll.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16> poison, <vscale x 32 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
vuint16m8_t test_vwsll_vx_u16m8(vuint8m4_t op1, uint8_t op2, size_t vl) {
return __riscv_vwsll_vx_u16m8(op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u32mf2(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwsll.nxv1i32.nxv1i16.nxv1i16.i64(<vscale x 1 x i32> poison, <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
vuint32mf2_t test_vwsll_vv_u32mf2(vuint16mf4_t op1, vuint16mf4_t op2, size_t vl) {
return __riscv_vwsll_vv_u32mf2(op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u32mf2(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwsll.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32> poison, <vscale x 1 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
vuint32mf2_t test_vwsll_vx_u32mf2(vuint16mf4_t op1, uint16_t op2, size_t vl) {
return __riscv_vwsll_vx_u32mf2(op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u32m1(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwsll.nxv2i32.nxv2i16.nxv2i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
vuint32m1_t test_vwsll_vv_u32m1(vuint16mf2_t op1, vuint16mf2_t op2, size_t vl) {
return __riscv_vwsll_vv_u32m1(op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u32m1(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwsll.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
vuint32m1_t test_vwsll_vx_u32m1(vuint16mf2_t op1, uint16_t op2, size_t vl) {
return __riscv_vwsll_vx_u32m1(op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u32m2(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwsll.nxv4i32.nxv4i16.nxv4i16.i64(<vscale x 4 x i32> poison, <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
vuint32m2_t test_vwsll_vv_u32m2(vuint16m1_t op1, vuint16m1_t op2, size_t vl) {
return __riscv_vwsll_vv_u32m2(op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u32m2(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwsll.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32> poison, <vscale x 4 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
vuint32m2_t test_vwsll_vx_u32m2(vuint16m1_t op1, uint16_t op2, size_t vl) {
return __riscv_vwsll_vx_u32m2(op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u32m4(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwsll.nxv8i32.nxv8i16.nxv8i16.i64(<vscale x 8 x i32> poison, <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
vuint32m4_t test_vwsll_vv_u32m4(vuint16m2_t op1, vuint16m2_t op2, size_t vl) {
return __riscv_vwsll_vv_u32m4(op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u32m4(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwsll.nxv8i32.nxv8i16.i16.i64(<vscale x 8 x i32> poison, <vscale x 8 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
vuint32m4_t test_vwsll_vx_u32m4(vuint16m2_t op1, uint16_t op2, size_t vl) {
return __riscv_vwsll_vx_u32m4(op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u32m8(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwsll.nxv16i32.nxv16i16.nxv16i16.i64(<vscale x 16 x i32> poison, <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
vuint32m8_t test_vwsll_vv_u32m8(vuint16m4_t op1, vuint16m4_t op2, size_t vl) {
return __riscv_vwsll_vv_u32m8(op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u32m8(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwsll.nxv16i32.nxv16i16.i16.i64(<vscale x 16 x i32> poison, <vscale x 16 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
vuint32m8_t test_vwsll_vx_u32m8(vuint16m4_t op1, uint16_t op2, size_t vl) {
return __riscv_vwsll_vx_u32m8(op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u64m1(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwsll.nxv1i64.nxv1i32.nxv1i32.i64(<vscale x 1 x i64> poison, <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 1 x i64> [[TMP0]]
//
vuint64m1_t test_vwsll_vv_u64m1(vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) {
return __riscv_vwsll_vv_u64m1(op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u64m1(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwsll.nxv1i64.nxv1i32.i32.i64(<vscale x 1 x i64> poison, <vscale x 1 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 1 x i64> [[TMP0]]
//
vuint64m1_t test_vwsll_vx_u64m1(vuint32mf2_t op1, uint32_t op2, size_t vl) {
return __riscv_vwsll_vx_u64m1(op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u64m2(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwsll.nxv2i64.nxv2i32.nxv2i32.i64(<vscale x 2 x i64> poison, <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
vuint64m2_t test_vwsll_vv_u64m2(vuint32m1_t op1, vuint32m1_t op2, size_t vl) {
return __riscv_vwsll_vv_u64m2(op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u64m2(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwsll.nxv2i64.nxv2i32.i32.i64(<vscale x 2 x i64> poison, <vscale x 2 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
vuint64m2_t test_vwsll_vx_u64m2(vuint32m1_t op1, uint32_t op2, size_t vl) {
return __riscv_vwsll_vx_u64m2(op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u64m4(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwsll.nxv4i64.nxv4i32.nxv4i32.i64(<vscale x 4 x i64> poison, <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
vuint64m4_t test_vwsll_vv_u64m4(vuint32m2_t op1, vuint32m2_t op2, size_t vl) {
return __riscv_vwsll_vv_u64m4(op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u64m4(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwsll.nxv4i64.nxv4i32.i32.i64(<vscale x 4 x i64> poison, <vscale x 4 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
vuint64m4_t test_vwsll_vx_u64m4(vuint32m2_t op1, uint32_t op2, size_t vl) {
return __riscv_vwsll_vx_u64m4(op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u64m8(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwsll.nxv8i64.nxv8i32.nxv8i32.i64(<vscale x 8 x i64> poison, <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
vuint64m8_t test_vwsll_vv_u64m8(vuint32m4_t op1, vuint32m4_t op2, size_t vl) {
return __riscv_vwsll_vv_u64m8(op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u64m8(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwsll.nxv8i64.nxv8i32.i32.i64(<vscale x 8 x i64> poison, <vscale x 8 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
vuint64m8_t test_vwsll_vx_u64m8(vuint32m4_t op1, uint32_t op2, size_t vl) {
return __riscv_vwsll_vx_u64m8(op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u16mf4_m(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwsll.mask.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
// CHECK-NEXT: ret <vscale x 1 x i16> [[TMP0]]
//
vuint16mf4_t test_vwsll_vv_u16mf4_m(vbool64_t mask, vuint8mf8_t op1, vuint8mf8_t op2, size_t vl) {
return __riscv_vwsll_vv_u16mf4_m(mask, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u16mf4_m(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwsll.mask.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
// CHECK-NEXT: ret <vscale x 1 x i16> [[TMP0]]
//
vuint16mf4_t test_vwsll_vx_u16mf4_m(vbool64_t mask, vuint8mf8_t op1, uint8_t op2, size_t vl) {
return __riscv_vwsll_vx_u16mf4_m(mask, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u16mf2_m(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwsll.mask.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
// CHECK-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
vuint16mf2_t test_vwsll_vv_u16mf2_m(vbool32_t mask, vuint8mf4_t op1, vuint8mf4_t op2, size_t vl) {
return __riscv_vwsll_vv_u16mf2_m(mask, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u16mf2_m(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwsll.mask.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
// CHECK-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
vuint16mf2_t test_vwsll_vx_u16mf2_m(vbool32_t mask, vuint8mf4_t op1, uint8_t op2, size_t vl) {
return __riscv_vwsll_vx_u16mf2_m(mask, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u16m1_m(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwsll.mask.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
// CHECK-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
vuint16m1_t test_vwsll_vv_u16m1_m(vbool16_t mask, vuint8mf2_t op1, vuint8mf2_t op2, size_t vl) {
return __riscv_vwsll_vv_u16m1_m(mask, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u16m1_m(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwsll.mask.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
// CHECK-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
vuint16m1_t test_vwsll_vx_u16m1_m(vbool16_t mask, vuint8mf2_t op1, uint8_t op2, size_t vl) {
return __riscv_vwsll_vx_u16m1_m(mask, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u16m2_m(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwsll.mask.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
vuint16m2_t test_vwsll_vv_u16m2_m(vbool8_t mask, vuint8m1_t op1, vuint8m1_t op2, size_t vl) {
return __riscv_vwsll_vv_u16m2_m(mask, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u16m2_m(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwsll.mask.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
vuint16m2_t test_vwsll_vx_u16m2_m(vbool8_t mask, vuint8m1_t op1, uint8_t op2, size_t vl) {
return __riscv_vwsll_vx_u16m2_m(mask, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u16m4_m(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwsll.mask.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
// CHECK-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
vuint16m4_t test_vwsll_vv_u16m4_m(vbool4_t mask, vuint8m2_t op1, vuint8m2_t op2, size_t vl) {
return __riscv_vwsll_vv_u16m4_m(mask, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u16m4_m(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwsll.mask.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
// CHECK-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
vuint16m4_t test_vwsll_vx_u16m4_m(vbool4_t mask, vuint8m2_t op1, uint8_t op2, size_t vl) {
return __riscv_vwsll_vx_u16m4_m(mask, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u16m8_m(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwsll.mask.nxv32i16.nxv32i8.nxv32i8.i64(<vscale x 32 x i16> poison, <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
// CHECK-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
vuint16m8_t test_vwsll_vv_u16m8_m(vbool2_t mask, vuint8m4_t op1, vuint8m4_t op2, size_t vl) {
return __riscv_vwsll_vv_u16m8_m(mask, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u16m8_m(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwsll.mask.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16> poison, <vscale x 32 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
// CHECK-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
vuint16m8_t test_vwsll_vx_u16m8_m(vbool2_t mask, vuint8m4_t op1, uint8_t op2, size_t vl) {
return __riscv_vwsll_vx_u16m8_m(mask, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u32mf2_m(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwsll.mask.nxv1i32.nxv1i16.nxv1i16.i64(<vscale x 1 x i32> poison, <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
// CHECK-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
vuint32mf2_t test_vwsll_vv_u32mf2_m(vbool64_t mask, vuint16mf4_t op1, vuint16mf4_t op2, size_t vl) {
return __riscv_vwsll_vv_u32mf2_m(mask, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u32mf2_m(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwsll.mask.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32> poison, <vscale x 1 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
// CHECK-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
vuint32mf2_t test_vwsll_vx_u32mf2_m(vbool64_t mask, vuint16mf4_t op1, uint16_t op2, size_t vl) {
return __riscv_vwsll_vx_u32mf2_m(mask, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u32m1_m(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwsll.mask.nxv2i32.nxv2i16.nxv2i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
// CHECK-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
vuint32m1_t test_vwsll_vv_u32m1_m(vbool32_t mask, vuint16mf2_t op1, vuint16mf2_t op2, size_t vl) {
return __riscv_vwsll_vv_u32m1_m(mask, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u32m1_m(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwsll.mask.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
// CHECK-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
vuint32m1_t test_vwsll_vx_u32m1_m(vbool32_t mask, vuint16mf2_t op1, uint16_t op2, size_t vl) {
return __riscv_vwsll_vx_u32m1_m(mask, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u32m2_m(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwsll.mask.nxv4i32.nxv4i16.nxv4i16.i64(<vscale x 4 x i32> poison, <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
vuint32m2_t test_vwsll_vv_u32m2_m(vbool16_t mask, vuint16m1_t op1, vuint16m1_t op2, size_t vl) {
return __riscv_vwsll_vv_u32m2_m(mask, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u32m2_m(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwsll.mask.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32> poison, <vscale x 4 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
vuint32m2_t test_vwsll_vx_u32m2_m(vbool16_t mask, vuint16m1_t op1, uint16_t op2, size_t vl) {
return __riscv_vwsll_vx_u32m2_m(mask, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u32m4_m(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwsll.mask.nxv8i32.nxv8i16.nxv8i16.i64(<vscale x 8 x i32> poison, <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
// CHECK-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
vuint32m4_t test_vwsll_vv_u32m4_m(vbool8_t mask, vuint16m2_t op1, vuint16m2_t op2, size_t vl) {
return __riscv_vwsll_vv_u32m4_m(mask, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u32m4_m(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwsll.mask.nxv8i32.nxv8i16.i16.i64(<vscale x 8 x i32> poison, <vscale x 8 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
// CHECK-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
vuint32m4_t test_vwsll_vx_u32m4_m(vbool8_t mask, vuint16m2_t op1, uint16_t op2, size_t vl) {
return __riscv_vwsll_vx_u32m4_m(mask, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u32m8_m(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwsll.mask.nxv16i32.nxv16i16.nxv16i16.i64(<vscale x 16 x i32> poison, <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
// CHECK-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
vuint32m8_t test_vwsll_vv_u32m8_m(vbool4_t mask, vuint16m4_t op1, vuint16m4_t op2, size_t vl) {
return __riscv_vwsll_vv_u32m8_m(mask, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u32m8_m(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwsll.mask.nxv16i32.nxv16i16.i16.i64(<vscale x 16 x i32> poison, <vscale x 16 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
// CHECK-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
vuint32m8_t test_vwsll_vx_u32m8_m(vbool4_t mask, vuint16m4_t op1, uint16_t op2, size_t vl) {
return __riscv_vwsll_vx_u32m8_m(mask, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u64m1_m(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwsll.mask.nxv1i64.nxv1i32.nxv1i32.i64(<vscale x 1 x i64> poison, <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
// CHECK-NEXT: ret <vscale x 1 x i64> [[TMP0]]
//
vuint64m1_t test_vwsll_vv_u64m1_m(vbool64_t mask, vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) {
return __riscv_vwsll_vv_u64m1_m(mask, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u64m1_m(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwsll.mask.nxv1i64.nxv1i32.i32.i64(<vscale x 1 x i64> poison, <vscale x 1 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
// CHECK-NEXT: ret <vscale x 1 x i64> [[TMP0]]
//
vuint64m1_t test_vwsll_vx_u64m1_m(vbool64_t mask, vuint32mf2_t op1, uint32_t op2, size_t vl) {
return __riscv_vwsll_vx_u64m1_m(mask, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u64m2_m(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwsll.mask.nxv2i64.nxv2i32.nxv2i32.i64(<vscale x 2 x i64> poison, <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
vuint64m2_t test_vwsll_vv_u64m2_m(vbool32_t mask, vuint32m1_t op1, vuint32m1_t op2, size_t vl) {
return __riscv_vwsll_vv_u64m2_m(mask, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u64m2_m(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwsll.mask.nxv2i64.nxv2i32.i32.i64(<vscale x 2 x i64> poison, <vscale x 2 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
vuint64m2_t test_vwsll_vx_u64m2_m(vbool32_t mask, vuint32m1_t op1, uint32_t op2, size_t vl) {
return __riscv_vwsll_vx_u64m2_m(mask, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u64m4_m(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwsll.mask.nxv4i64.nxv4i32.nxv4i32.i64(<vscale x 4 x i64> poison, <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
// CHECK-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
vuint64m4_t test_vwsll_vv_u64m4_m(vbool16_t mask, vuint32m2_t op1, vuint32m2_t op2, size_t vl) {
return __riscv_vwsll_vv_u64m4_m(mask, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u64m4_m(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwsll.mask.nxv4i64.nxv4i32.i32.i64(<vscale x 4 x i64> poison, <vscale x 4 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
// CHECK-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
vuint64m4_t test_vwsll_vx_u64m4_m(vbool16_t mask, vuint32m2_t op1, uint32_t op2, size_t vl) {
return __riscv_vwsll_vx_u64m4_m(mask, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u64m8_m(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwsll.mask.nxv8i64.nxv8i32.nxv8i32.i64(<vscale x 8 x i64> poison, <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
// CHECK-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
vuint64m8_t test_vwsll_vv_u64m8_m(vbool8_t mask, vuint32m4_t op1, vuint32m4_t op2, size_t vl) {
return __riscv_vwsll_vv_u64m8_m(mask, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u64m8_m(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwsll.mask.nxv8i64.nxv8i32.i32.i64(<vscale x 8 x i64> poison, <vscale x 8 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
// CHECK-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
vuint64m8_t test_vwsll_vx_u64m8_m(vbool8_t mask, vuint32m4_t op1, uint32_t op2, size_t vl) {
return __riscv_vwsll_vx_u64m8_m(mask, op1, op2, vl);
}

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdf.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdm.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesef.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesem.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaeskf1.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaeskf2.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesz.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vandn.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vbrev.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vbrev8.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclmul.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclmulh.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclz.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpopv.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vctz.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vghsh.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vgmul.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrev8.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrol.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vror.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsha2ch.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsha2cl.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsha2ms.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm3c.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm3me.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm4k.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm4r.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsll.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesdf.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesdm.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesef.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesem.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaeskf1.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaeskf2.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesz.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vandn.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vbrev.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vbrev8.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vclmul.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vclmulh.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vclz.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcpopv.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vctz.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vghsh.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vgmul.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrev8.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrol.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vror.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsha2ch.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsha2cl.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsha2ms.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm3c.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm3me.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm4k.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm4r.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsll.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesdf.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesdm.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesef.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesem.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaeskf1.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaeskf2.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesz.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vandn.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vbrev.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vbrev8.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vclmul.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vclmulh.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vclz.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcpopv.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vctz.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vghsh.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vgmul.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrev8.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrol.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vror.c

  • This file was added.
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck %s
#include <riscv_vector.h>
// CHECK-LABEL: @test_vror_vv_i8mf8_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[VS2:%.*]], <vscale x 1 x i8> [[VS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 1 x i8> [[TMP0]]
//
vint8mf8_t test_vror_vv_i8mf8_tu(vint8mf8_t maskedoff, vint8mf8_t vs2, vint8mf8_t vs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, vs1, vl);
craig.topperUnsubmitted
Done
ReplyInline Actions

The intrinsic spec does not define rotates for signed types

craig.topper: The intrinsic spec does not define rotates for signed types
}
// CHECK-LABEL: @test_vror_vx_i8mf8_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 1 x i8> [[TMP0]]
//
vint8mf8_t test_vror_vx_i8mf8_tu(vint8mf8_t maskedoff, vint8mf8_t vs2, int8_t rs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i8mf4_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[VS2:%.*]], <vscale x 2 x i8> [[VS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 2 x i8> [[TMP0]]
//
vint8mf4_t test_vror_vv_i8mf4_tu(vint8mf4_t maskedoff, vint8mf4_t vs2, vint8mf4_t vs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i8mf4_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.i8.i64(<vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 2 x i8> [[TMP0]]
//
vint8mf4_t test_vror_vx_i8mf4_tu(vint8mf4_t maskedoff, vint8mf4_t vs2, int8_t rs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i8mf2_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 4 x i8> [[TMP0]]
//
vint8mf2_t test_vror_vv_i8mf2_tu(vint8mf2_t maskedoff, vint8mf2_t vs2, vint8mf2_t vs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i8mf2_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.i8.i64(<vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 4 x i8> [[TMP0]]
//
vint8mf2_t test_vror_vx_i8mf2_tu(vint8mf2_t maskedoff, vint8mf2_t vs2, int8_t rs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i8m1_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 8 x i8> [[TMP0]]
//
vint8m1_t test_vror_vv_i8m1_tu(vint8m1_t maskedoff, vint8m1_t vs2, vint8m1_t vs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i8m1_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.i8.i64(<vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 8 x i8> [[TMP0]]
//
vint8m1_t test_vror_vx_i8m1_tu(vint8m1_t maskedoff, vint8m1_t vs2, int8_t rs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i8m2_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vror.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]
//
vint8m2_t test_vror_vv_i8m2_tu(vint8m2_t maskedoff, vint8m2_t vs2, vint8m2_t vs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i8m2_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vror.nxv16i8.i8.i64(<vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]
//
vint8m2_t test_vror_vx_i8m2_tu(vint8m2_t maskedoff, vint8m2_t vs2, int8_t rs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i8m4_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vror.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 32 x i8> [[TMP0]]
//
vint8m4_t test_vror_vv_i8m4_tu(vint8m4_t maskedoff, vint8m4_t vs2, vint8m4_t vs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i8m4_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vror.nxv32i8.i8.i64(<vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 32 x i8> [[TMP0]]
//
vint8m4_t test_vror_vx_i8m4_tu(vint8m4_t maskedoff, vint8m4_t vs2, int8_t rs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i8m8_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vror.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 64 x i8> [[TMP0]]
//
vint8m8_t test_vror_vv_i8m8_tu(vint8m8_t maskedoff, vint8m8_t vs2, vint8m8_t vs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i8m8_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vror.nxv64i8.i8.i64(<vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 64 x i8> [[TMP0]]
//
vint8m8_t test_vror_vx_i8m8_tu(vint8m8_t maskedoff, vint8m8_t vs2, int8_t rs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i16mf4_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vror.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[VS2:%.*]], <vscale x 1 x i16> [[VS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 1 x i16> [[TMP0]]
//
vint16mf4_t test_vror_vv_i16mf4_tu(vint16mf4_t maskedoff, vint16mf4_t vs2, vint16mf4_t vs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i16mf4_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vror.nxv1i16.i16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 1 x i16> [[TMP0]]
//
vint16mf4_t test_vror_vx_i16mf4_tu(vint16mf4_t maskedoff, vint16mf4_t vs2, int16_t rs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i16mf2_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vror.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[VS2:%.*]], <vscale x 2 x i16> [[VS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
vint16mf2_t test_vror_vv_i16mf2_tu(vint16mf2_t maskedoff, vint16mf2_t vs2, vint16mf2_t vs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i16mf2_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vror.nxv2i16.i16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
vint16mf2_t test_vror_vx_i16mf2_tu(vint16mf2_t maskedoff, vint16mf2_t vs2, int16_t rs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i16m1_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vror.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[VS2:%.*]], <vscale x 4 x i16> [[VS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
vint16m1_t test_vror_vv_i16m1_tu(vint16m1_t maskedoff, vint16m1_t vs2, vint16m1_t vs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i16m1_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vror.nxv4i16.i16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
vint16m1_t test_vror_vx_i16m1_tu(vint16m1_t maskedoff, vint16m1_t vs2, int16_t rs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i16m2_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vror.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[VS2:%.*]], <vscale x 8 x i16> [[VS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
vint16m2_t test_vror_vv_i16m2_tu(vint16m2_t maskedoff, vint16m2_t vs2, vint16m2_t vs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i16m2_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vror.nxv8i16.i16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
vint16m2_t test_vror_vx_i16m2_tu(vint16m2_t maskedoff, vint16m2_t vs2, int16_t rs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i16m4_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vror.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[VS2:%.*]], <vscale x 16 x i16> [[VS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
vint16m4_t test_vror_vv_i16m4_tu(vint16m4_t maskedoff, vint16m4_t vs2, vint16m4_t vs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i16m4_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vror.nxv16i16.i16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
vint16m4_t test_vror_vx_i16m4_tu(vint16m4_t maskedoff, vint16m4_t vs2, int16_t rs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i16m8_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vror.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[VS2:%.*]], <vscale x 32 x i16> [[VS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
vint16m8_t test_vror_vv_i16m8_tu(vint16m8_t maskedoff, vint16m8_t vs2, vint16m8_t vs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i16m8_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vror.nxv32i16.i16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
vint16m8_t test_vror_vx_i16m8_tu(vint16m8_t maskedoff, vint16m8_t vs2, int16_t rs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i32mf2_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vror.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
vint32mf2_t test_vror_vv_i32mf2_tu(vint32mf2_t maskedoff, vint32mf2_t vs2, vint32mf2_t vs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i32mf2_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vror.nxv1i32.i32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
vint32mf2_t test_vror_vx_i32mf2_tu(vint32mf2_t maskedoff, vint32mf2_t vs2, int32_t rs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i32m1_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vror.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
vint32m1_t test_vror_vv_i32m1_tu(vint32m1_t maskedoff, vint32m1_t vs2, vint32m1_t vs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i32m1_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vror.nxv2i32.i32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
vint32m1_t test_vror_vx_i32m1_tu(vint32m1_t maskedoff, vint32m1_t vs2, int32_t rs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i32m2_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vror.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
vint32m2_t test_vror_vv_i32m2_tu(vint32m2_t maskedoff, vint32m2_t vs2, vint32m2_t vs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i32m2_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vror.nxv4i32.i32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
vint32m2_t test_vror_vx_i32m2_tu(vint32m2_t maskedoff, vint32m2_t vs2, int32_t rs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i32m4_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vror.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
vint32m4_t test_vror_vv_i32m4_tu(vint32m4_t maskedoff, vint32m4_t vs2, vint32m4_t vs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i32m4_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vror.nxv8i32.i32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
vint32m4_t test_vror_vx_i32m4_tu(vint32m4_t maskedoff, vint32m4_t vs2, int32_t rs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i32m8_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vror.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[VS2:%.*]], <vscale x 16 x i32> [[VS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
vint32m8_t test_vror_vv_i32m8_tu(vint32m8_t maskedoff, vint32m8_t vs2, vint32m8_t vs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i32m8_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vror.nxv16i32.i32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
vint32m8_t test_vror_vx_i32m8_tu(vint32m8_t maskedoff, vint32m8_t vs2, int32_t rs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i64m1_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vror.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 1 x i64> [[TMP0]]
//
vint64m1_t test_vror_vv_i64m1_tu(vint64m1_t maskedoff, vint64m1_t vs2, vint64m1_t vs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i64m1_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vror.nxv1i64.i64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 1 x i64> [[TMP0]]
//
vint64m1_t test_vror_vx_i64m1_tu(vint64m1_t maskedoff, vint64m1_t vs2, int64_t rs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i64m2_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vror.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
vint64m2_t test_vror_vv_i64m2_tu(vint64m2_t maskedoff, vint64m2_t vs2, vint64m2_t vs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i64m2_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vror.nxv2i64.i64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
vint64m2_t test_vror_vx_i64m2_tu(vint64m2_t maskedoff, vint64m2_t vs2, int64_t rs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i64m4_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vror.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
vint64m4_t test_vror_vv_i64m4_tu(vint64m4_t maskedoff, vint64m4_t vs2, vint64m4_t vs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i64m4_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vror.nxv4i64.i64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
vint64m4_t test_vror_vx_i64m4_tu(vint64m4_t maskedoff, vint64m4_t vs2, int64_t rs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i64m8_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vror.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[VS2:%.*]], <vscale x 8 x i64> [[VS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
vint64m8_t test_vror_vv_i64m8_tu(vint64m8_t maskedoff, vint64m8_t vs2, vint64m8_t vs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i64m8_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vror.nxv8i64.i64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
vint64m8_t test_vror_vx_i64m8_tu(vint64m8_t maskedoff, vint64m8_t vs2, int64_t rs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u8mf8_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[VS2:%.*]], <vscale x 1 x i8> [[VS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 1 x i8> [[TMP0]]
//
vuint8mf8_t test_vror_vv_u8mf8_tu(vuint8mf8_t maskedoff, vuint8mf8_t vs2, vuint8mf8_t vs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u8mf8_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 1 x i8> [[TMP0]]
//
vuint8mf8_t test_vror_vx_u8mf8_tu(vuint8mf8_t maskedoff, vuint8mf8_t vs2, uint8_t rs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u8mf4_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[VS2:%.*]], <vscale x 2 x i8> [[VS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 2 x i8> [[TMP0]]
//
vuint8mf4_t test_vror_vv_u8mf4_tu(vuint8mf4_t maskedoff, vuint8mf4_t vs2, vuint8mf4_t vs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u8mf4_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.i8.i64(<vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 2 x i8> [[TMP0]]
//
vuint8mf4_t test_vror_vx_u8mf4_tu(vuint8mf4_t maskedoff, vuint8mf4_t vs2, uint8_t rs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u8mf2_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 4 x i8> [[TMP0]]
//
vuint8mf2_t test_vror_vv_u8mf2_tu(vuint8mf2_t maskedoff, vuint8mf2_t vs2, vuint8mf2_t vs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u8mf2_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.i8.i64(<vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 4 x i8> [[TMP0]]
//
vuint8mf2_t test_vror_vx_u8mf2_tu(vuint8mf2_t maskedoff, vuint8mf2_t vs2, uint8_t rs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u8m1_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 8 x i8> [[TMP0]]
//
vuint8m1_t test_vror_vv_u8m1_tu(vuint8m1_t maskedoff, vuint8m1_t vs2, vuint8m1_t vs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u8m1_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.i8.i64(<vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 8 x i8> [[TMP0]]
//
vuint8m1_t test_vror_vx_u8m1_tu(vuint8m1_t maskedoff, vuint8m1_t vs2, uint8_t rs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u8m2_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vror.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]
//
vuint8m2_t test_vror_vv_u8m2_tu(vuint8m2_t maskedoff, vuint8m2_t vs2, vuint8m2_t vs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u8m2_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vror.nxv16i8.i8.i64(<vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]
//
vuint8m2_t test_vror_vx_u8m2_tu(vuint8m2_t maskedoff, vuint8m2_t vs2, uint8_t rs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u8m4_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vror.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 32 x i8> [[TMP0]]
//
vuint8m4_t test_vror_vv_u8m4_tu(vuint8m4_t maskedoff, vuint8m4_t vs2, vuint8m4_t vs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u8m4_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vror.nxv32i8.i8.i64(<vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 32 x i8> [[TMP0]]
//
vuint8m4_t test_vror_vx_u8m4_tu(vuint8m4_t maskedoff, vuint8m4_t vs2, uint8_t rs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u8m8_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vror.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 64 x i8> [[TMP0]]
//
vuint8m8_t test_vror_vv_u8m8_tu(vuint8m8_t maskedoff, vuint8m8_t vs2, vuint8m8_t vs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u8m8_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vror.nxv64i8.i8.i64(<vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 64 x i8> [[TMP0]]
//
vuint8m8_t test_vror_vx_u8m8_tu(vuint8m8_t maskedoff, vuint8m8_t vs2, uint8_t rs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u16mf4_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vror.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[VS2:%.*]], <vscale x 1 x i16> [[VS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 1 x i16> [[TMP0]]
//
vuint16mf4_t test_vror_vv_u16mf4_tu(vuint16mf4_t maskedoff, vuint16mf4_t vs2, vuint16mf4_t vs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u16mf4_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vror.nxv1i16.i16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 1 x i16> [[TMP0]]
//
vuint16mf4_t test_vror_vx_u16mf4_tu(vuint16mf4_t maskedoff, vuint16mf4_t vs2, uint16_t rs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u16mf2_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vror.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[VS2:%.*]], <vscale x 2 x i16> [[VS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
vuint16mf2_t test_vror_vv_u16mf2_tu(vuint16mf2_t maskedoff, vuint16mf2_t vs2, vuint16mf2_t vs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u16mf2_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vror.nxv2i16.i16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
vuint16mf2_t test_vror_vx_u16mf2_tu(vuint16mf2_t maskedoff, vuint16mf2_t vs2, uint16_t rs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u16m1_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vror.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[VS2:%.*]], <vscale x 4 x i16> [[VS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
vuint16m1_t test_vror_vv_u16m1_tu(vuint16m1_t maskedoff, vuint16m1_t vs2, vuint16m1_t vs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u16m1_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vror.nxv4i16.i16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
vuint16m1_t test_vror_vx_u16m1_tu(vuint16m1_t maskedoff, vuint16m1_t vs2, uint16_t rs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u16m2_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vror.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[VS2:%.*]], <vscale x 8 x i16> [[VS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
vuint16m2_t test_vror_vv_u16m2_tu(vuint16m2_t maskedoff, vuint16m2_t vs2, vuint16m2_t vs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u16m2_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vror.nxv8i16.i16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
vuint16m2_t test_vror_vx_u16m2_tu(vuint16m2_t maskedoff, vuint16m2_t vs2, uint16_t rs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u16m4_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vror.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[VS2:%.*]], <vscale x 16 x i16> [[VS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
vuint16m4_t test_vror_vv_u16m4_tu(vuint16m4_t maskedoff, vuint16m4_t vs2, vuint16m4_t vs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u16m4_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vror.nxv16i16.i16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
vuint16m4_t test_vror_vx_u16m4_tu(vuint16m4_t maskedoff, vuint16m4_t vs2, uint16_t rs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u16m8_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vror.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[VS2:%.*]], <vscale x 32 x i16> [[VS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
vuint16m8_t test_vror_vv_u16m8_tu(vuint16m8_t maskedoff, vuint16m8_t vs2, vuint16m8_t vs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u16m8_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vror.nxv32i16.i16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
vuint16m8_t test_vror_vx_u16m8_tu(vuint16m8_t maskedoff, vuint16m8_t vs2, uint16_t rs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u32mf2_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vror.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
vuint32mf2_t test_vror_vv_u32mf2_tu(vuint32mf2_t maskedoff, vuint32mf2_t vs2, vuint32mf2_t vs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u32mf2_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vror.nxv1i32.i32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
vuint32mf2_t test_vror_vx_u32mf2_tu(vuint32mf2_t maskedoff, vuint32mf2_t vs2, uint32_t rs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u32m1_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vror.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
vuint32m1_t test_vror_vv_u32m1_tu(vuint32m1_t maskedoff, vuint32m1_t vs2, vuint32m1_t vs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u32m1_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vror.nxv2i32.i32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
vuint32m1_t test_vror_vx_u32m1_tu(vuint32m1_t maskedoff, vuint32m1_t vs2, uint32_t rs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u32m2_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vror.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
vuint32m2_t test_vror_vv_u32m2_tu(vuint32m2_t maskedoff, vuint32m2_t vs2, vuint32m2_t vs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u32m2_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vror.nxv4i32.i32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
vuint32m2_t test_vror_vx_u32m2_tu(vuint32m2_t maskedoff, vuint32m2_t vs2, uint32_t rs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u32m4_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vror.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
vuint32m4_t test_vror_vv_u32m4_tu(vuint32m4_t maskedoff, vuint32m4_t vs2, vuint32m4_t vs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u32m4_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vror.nxv8i32.i32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
vuint32m4_t test_vror_vx_u32m4_tu(vuint32m4_t maskedoff, vuint32m4_t vs2, uint32_t rs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u32m8_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vror.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[VS2:%.*]], <vscale x 16 x i32> [[VS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
vuint32m8_t test_vror_vv_u32m8_tu(vuint32m8_t maskedoff, vuint32m8_t vs2, vuint32m8_t vs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u32m8_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vror.nxv16i32.i32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
vuint32m8_t test_vror_vx_u32m8_tu(vuint32m8_t maskedoff, vuint32m8_t vs2, uint32_t rs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u64m1_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vror.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 1 x i64> [[TMP0]]
//
vuint64m1_t test_vror_vv_u64m1_tu(vuint64m1_t maskedoff, vuint64m1_t vs2, vuint64m1_t vs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u64m1_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vror.nxv1i64.i64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 1 x i64> [[TMP0]]
//
vuint64m1_t test_vror_vx_u64m1_tu(vuint64m1_t maskedoff, vuint64m1_t vs2, uint64_t rs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u64m2_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vror.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
vuint64m2_t test_vror_vv_u64m2_tu(vuint64m2_t maskedoff, vuint64m2_t vs2, vuint64m2_t vs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u64m2_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vror.nxv2i64.i64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
vuint64m2_t test_vror_vx_u64m2_tu(vuint64m2_t maskedoff, vuint64m2_t vs2, uint64_t rs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u64m4_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vror.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
vuint64m4_t test_vror_vv_u64m4_tu(vuint64m4_t maskedoff, vuint64m4_t vs2, vuint64m4_t vs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u64m4_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vror.nxv4i64.i64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
vuint64m4_t test_vror_vx_u64m4_tu(vuint64m4_t maskedoff, vuint64m4_t vs2, uint64_t rs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u64m8_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vror.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[VS2:%.*]], <vscale x 8 x i64> [[VS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
vuint64m8_t test_vror_vv_u64m8_tu(vuint64m8_t maskedoff, vuint64m8_t vs2, vuint64m8_t vs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u64m8_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vror.nxv8i64.i64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
vuint64m8_t test_vror_vx_u64m8_tu(vuint64m8_t maskedoff, vuint64m8_t vs2, uint64_t rs1, size_t vl) {
return __riscv_vror_tu(maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i8mf8_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vror.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[VS2:%.*]], <vscale x 1 x i8> [[VS1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 1 x i8> [[TMP0]]
//
vint8mf8_t test_vror_vv_i8mf8_tum(vbool64_t mask, vint8mf8_t maskedoff, vint8mf8_t vs2, vint8mf8_t vs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i8mf8_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vror.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 1 x i8> [[TMP0]]
//
vint8mf8_t test_vror_vx_i8mf8_tum(vbool64_t mask, vint8mf8_t maskedoff, vint8mf8_t vs2, int8_t rs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i8mf4_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vror.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[VS2:%.*]], <vscale x 2 x i8> [[VS1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 2 x i8> [[TMP0]]
//
vint8mf4_t test_vror_vv_i8mf4_tum(vbool32_t mask, vint8mf4_t maskedoff, vint8mf4_t vs2, vint8mf4_t vs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i8mf4_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vror.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 2 x i8> [[TMP0]]
//
vint8mf4_t test_vror_vx_i8mf4_tum(vbool32_t mask, vint8mf4_t maskedoff, vint8mf4_t vs2, int8_t rs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i8mf2_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vror.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 4 x i8> [[TMP0]]
//
vint8mf2_t test_vror_vv_i8mf2_tum(vbool16_t mask, vint8mf2_t maskedoff, vint8mf2_t vs2, vint8mf2_t vs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i8mf2_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vror.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 4 x i8> [[TMP0]]
//
vint8mf2_t test_vror_vx_i8mf2_tum(vbool16_t mask, vint8mf2_t maskedoff, vint8mf2_t vs2, int8_t rs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i8m1_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vror.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 8 x i8> [[TMP0]]
//
vint8m1_t test_vror_vv_i8m1_tum(vbool8_t mask, vint8m1_t maskedoff, vint8m1_t vs2, vint8m1_t vs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i8m1_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vror.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 8 x i8> [[TMP0]]
//
vint8m1_t test_vror_vx_i8m1_tum(vbool8_t mask, vint8m1_t maskedoff, vint8m1_t vs2, int8_t rs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i8m2_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vror.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]
//
vint8m2_t test_vror_vv_i8m2_tum(vbool4_t mask, vint8m2_t maskedoff, vint8m2_t vs2, vint8m2_t vs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i8m2_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vror.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]
//
vint8m2_t test_vror_vx_i8m2_tum(vbool4_t mask, vint8m2_t maskedoff, vint8m2_t vs2, int8_t rs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i8m4_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vror.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 32 x i8> [[TMP0]]
//
vint8m4_t test_vror_vv_i8m4_tum(vbool2_t mask, vint8m4_t maskedoff, vint8m4_t vs2, vint8m4_t vs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i8m4_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vror.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 32 x i8> [[TMP0]]
//
vint8m4_t test_vror_vx_i8m4_tum(vbool2_t mask, vint8m4_t maskedoff, vint8m4_t vs2, int8_t rs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i8m8_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vror.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 64 x i8> [[TMP0]]
//
vint8m8_t test_vror_vv_i8m8_tum(vbool1_t mask, vint8m8_t maskedoff, vint8m8_t vs2, vint8m8_t vs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i8m8_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vror.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 64 x i8> [[TMP0]]
//
vint8m8_t test_vror_vx_i8m8_tum(vbool1_t mask, vint8m8_t maskedoff, vint8m8_t vs2, int8_t rs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i16mf4_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vror.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[VS2:%.*]], <vscale x 1 x i16> [[VS1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 1 x i16> [[TMP0]]
//
vint16mf4_t test_vror_vv_i16mf4_tum(vbool64_t mask, vint16mf4_t maskedoff, vint16mf4_t vs2, vint16mf4_t vs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i16mf4_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vror.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 1 x i16> [[TMP0]]
//
vint16mf4_t test_vror_vx_i16mf4_tum(vbool64_t mask, vint16mf4_t maskedoff, vint16mf4_t vs2, int16_t rs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i16mf2_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vror.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[VS2:%.*]], <vscale x 2 x i16> [[VS1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
vint16mf2_t test_vror_vv_i16mf2_tum(vbool32_t mask, vint16mf2_t maskedoff, vint16mf2_t vs2, vint16mf2_t vs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i16mf2_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vror.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
vint16mf2_t test_vror_vx_i16mf2_tum(vbool32_t mask, vint16mf2_t maskedoff, vint16mf2_t vs2, int16_t rs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i16m1_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vror.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[VS2:%.*]], <vscale x 4 x i16> [[VS1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
vint16m1_t test_vror_vv_i16m1_tum(vbool16_t mask, vint16m1_t maskedoff, vint16m1_t vs2, vint16m1_t vs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i16m1_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vror.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
vint16m1_t test_vror_vx_i16m1_tum(vbool16_t mask, vint16m1_t maskedoff, vint16m1_t vs2, int16_t rs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i16m2_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vror.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[VS2:%.*]], <vscale x 8 x i16> [[VS1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
vint16m2_t test_vror_vv_i16m2_tum(vbool8_t mask, vint16m2_t maskedoff, vint16m2_t vs2, vint16m2_t vs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i16m2_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vror.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
vint16m2_t test_vror_vx_i16m2_tum(vbool8_t mask, vint16m2_t maskedoff, vint16m2_t vs2, int16_t rs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i16m4_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vror.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[VS2:%.*]], <vscale x 16 x i16> [[VS1:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
vint16m4_t test_vror_vv_i16m4_tum(vbool4_t mask, vint16m4_t maskedoff, vint16m4_t vs2, vint16m4_t vs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i16m4_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vror.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
vint16m4_t test_vror_vx_i16m4_tum(vbool4_t mask, vint16m4_t maskedoff, vint16m4_t vs2, int16_t rs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i16m8_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vror.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[VS2:%.*]], <vscale x 32 x i16> [[VS1:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
vint16m8_t test_vror_vv_i16m8_tum(vbool2_t mask, vint16m8_t maskedoff, vint16m8_t vs2, vint16m8_t vs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i16m8_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vror.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
vint16m8_t test_vror_vx_i16m8_tum(vbool2_t mask, vint16m8_t maskedoff, vint16m8_t vs2, int16_t rs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i32mf2_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vror.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
vint32mf2_t test_vror_vv_i32mf2_tum(vbool64_t mask, vint32mf2_t maskedoff, vint32mf2_t vs2, vint32mf2_t vs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i32mf2_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vror.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
vint32mf2_t test_vror_vx_i32mf2_tum(vbool64_t mask, vint32mf2_t maskedoff, vint32mf2_t vs2, int32_t rs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i32m1_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vror.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
vint32m1_t test_vror_vv_i32m1_tum(vbool32_t mask, vint32m1_t maskedoff, vint32m1_t vs2, vint32m1_t vs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i32m1_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vror.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
vint32m1_t test_vror_vx_i32m1_tum(vbool32_t mask, vint32m1_t maskedoff, vint32m1_t vs2, int32_t rs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i32m2_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vror.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
vint32m2_t test_vror_vv_i32m2_tum(vbool16_t mask, vint32m2_t maskedoff, vint32m2_t vs2, vint32m2_t vs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i32m2_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vror.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
vint32m2_t test_vror_vx_i32m2_tum(vbool16_t mask, vint32m2_t maskedoff, vint32m2_t vs2, int32_t rs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i32m4_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vror.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
vint32m4_t test_vror_vv_i32m4_tum(vbool8_t mask, vint32m4_t maskedoff, vint32m4_t vs2, vint32m4_t vs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i32m4_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vror.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
vint32m4_t test_vror_vx_i32m4_tum(vbool8_t mask, vint32m4_t maskedoff, vint32m4_t vs2, int32_t rs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i32m8_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vror.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[VS2:%.*]], <vscale x 16 x i32> [[VS1:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
vint32m8_t test_vror_vv_i32m8_tum(vbool4_t mask, vint32m8_t maskedoff, vint32m8_t vs2, vint32m8_t vs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i32m8_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vror.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
vint32m8_t test_vror_vx_i32m8_tum(vbool4_t mask, vint32m8_t maskedoff, vint32m8_t vs2, int32_t rs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i64m1_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vror.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 1 x i64> [[TMP0]]
//
vint64m1_t test_vror_vv_i64m1_tum(vbool64_t mask, vint64m1_t maskedoff, vint64m1_t vs2, vint64m1_t vs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i64m1_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vror.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 1 x i64> [[TMP0]]
//
vint64m1_t test_vror_vx_i64m1_tum(vbool64_t mask, vint64m1_t maskedoff, vint64m1_t vs2, int64_t rs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i64m2_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vror.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
vint64m2_t test_vror_vv_i64m2_tum(vbool32_t mask, vint64m2_t maskedoff, vint64m2_t vs2, vint64m2_t vs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i64m2_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vror.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
vint64m2_t test_vror_vx_i64m2_tum(vbool32_t mask, vint64m2_t maskedoff, vint64m2_t vs2, int64_t rs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i64m4_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vror.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
vint64m4_t test_vror_vv_i64m4_tum(vbool16_t mask, vint64m4_t maskedoff, vint64m4_t vs2, vint64m4_t vs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i64m4_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vror.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
vint64m4_t test_vror_vx_i64m4_tum(vbool16_t mask, vint64m4_t maskedoff, vint64m4_t vs2, int64_t rs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i64m8_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vror.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[VS2:%.*]], <vscale x 8 x i64> [[VS1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
vint64m8_t test_vror_vv_i64m8_tum(vbool8_t mask, vint64m8_t maskedoff, vint64m8_t vs2, vint64m8_t vs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i64m8_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vror.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
vint64m8_t test_vror_vx_i64m8_tum(vbool8_t mask, vint64m8_t maskedoff, vint64m8_t vs2, int64_t rs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u8mf8_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vror.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[VS2:%.*]], <vscale x 1 x i8> [[VS1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 1 x i8> [[TMP0]]
//
vuint8mf8_t test_vror_vv_u8mf8_tum(vbool64_t mask, vuint8mf8_t maskedoff, vuint8mf8_t vs2, vuint8mf8_t vs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u8mf8_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vror.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 1 x i8> [[TMP0]]
//
vuint8mf8_t test_vror_vx_u8mf8_tum(vbool64_t mask, vuint8mf8_t maskedoff, vuint8mf8_t vs2, uint8_t rs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u8mf4_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vror.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[VS2:%.*]], <vscale x 2 x i8> [[VS1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 2 x i8> [[TMP0]]
//
vuint8mf4_t test_vror_vv_u8mf4_tum(vbool32_t mask, vuint8mf4_t maskedoff, vuint8mf4_t vs2, vuint8mf4_t vs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u8mf4_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vror.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 2 x i8> [[TMP0]]
//
vuint8mf4_t test_vror_vx_u8mf4_tum(vbool32_t mask, vuint8mf4_t maskedoff, vuint8mf4_t vs2, uint8_t rs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u8mf2_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vror.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 4 x i8> [[TMP0]]
//
vuint8mf2_t test_vror_vv_u8mf2_tum(vbool16_t mask, vuint8mf2_t maskedoff, vuint8mf2_t vs2, vuint8mf2_t vs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u8mf2_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vror.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 4 x i8> [[TMP0]]
//
vuint8mf2_t test_vror_vx_u8mf2_tum(vbool16_t mask, vuint8mf2_t maskedoff, vuint8mf2_t vs2, uint8_t rs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u8m1_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vror.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 8 x i8> [[TMP0]]
//
vuint8m1_t test_vror_vv_u8m1_tum(vbool8_t mask, vuint8m1_t maskedoff, vuint8m1_t vs2, vuint8m1_t vs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u8m1_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vror.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 8 x i8> [[TMP0]]
//
vuint8m1_t test_vror_vx_u8m1_tum(vbool8_t mask, vuint8m1_t maskedoff, vuint8m1_t vs2, uint8_t rs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u8m2_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vror.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]
//
vuint8m2_t test_vror_vv_u8m2_tum(vbool4_t mask, vuint8m2_t maskedoff, vuint8m2_t vs2, vuint8m2_t vs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u8m2_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vror.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]
//
vuint8m2_t test_vror_vx_u8m2_tum(vbool4_t mask, vuint8m2_t maskedoff, vuint8m2_t vs2, uint8_t rs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u8m4_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vror.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 32 x i8> [[TMP0]]
//
vuint8m4_t test_vror_vv_u8m4_tum(vbool2_t mask, vuint8m4_t maskedoff, vuint8m4_t vs2, vuint8m4_t vs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u8m4_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vror.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 32 x i8> [[TMP0]]
//
vuint8m4_t test_vror_vx_u8m4_tum(vbool2_t mask, vuint8m4_t maskedoff, vuint8m4_t vs2, uint8_t rs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u8m8_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vror.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 64 x i8> [[TMP0]]
//
vuint8m8_t test_vror_vv_u8m8_tum(vbool1_t mask, vuint8m8_t maskedoff, vuint8m8_t vs2, vuint8m8_t vs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u8m8_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vror.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 64 x i8> [[TMP0]]
//
vuint8m8_t test_vror_vx_u8m8_tum(vbool1_t mask, vuint8m8_t maskedoff, vuint8m8_t vs2, uint8_t rs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u16mf4_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vror.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[VS2:%.*]], <vscale x 1 x i16> [[VS1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 1 x i16> [[TMP0]]
//
vuint16mf4_t test_vror_vv_u16mf4_tum(vbool64_t mask, vuint16mf4_t maskedoff, vuint16mf4_t vs2, vuint16mf4_t vs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u16mf4_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vror.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 1 x i16> [[TMP0]]
//
vuint16mf4_t test_vror_vx_u16mf4_tum(vbool64_t mask, vuint16mf4_t maskedoff, vuint16mf4_t vs2, uint16_t rs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u16mf2_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vror.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[VS2:%.*]], <vscale x 2 x i16> [[VS1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
vuint16mf2_t test_vror_vv_u16mf2_tum(vbool32_t mask, vuint16mf2_t maskedoff, vuint16mf2_t vs2, vuint16mf2_t vs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u16mf2_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vror.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
vuint16mf2_t test_vror_vx_u16mf2_tum(vbool32_t mask, vuint16mf2_t maskedoff, vuint16mf2_t vs2, uint16_t rs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u16m1_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vror.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[VS2:%.*]], <vscale x 4 x i16> [[VS1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
vuint16m1_t test_vror_vv_u16m1_tum(vbool16_t mask, vuint16m1_t maskedoff, vuint16m1_t vs2, vuint16m1_t vs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u16m1_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vror.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
vuint16m1_t test_vror_vx_u16m1_tum(vbool16_t mask, vuint16m1_t maskedoff, vuint16m1_t vs2, uint16_t rs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u16m2_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vror.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[VS2:%.*]], <vscale x 8 x i16> [[VS1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
vuint16m2_t test_vror_vv_u16m2_tum(vbool8_t mask, vuint16m2_t maskedoff, vuint16m2_t vs2, vuint16m2_t vs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u16m2_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vror.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
vuint16m2_t test_vror_vx_u16m2_tum(vbool8_t mask, vuint16m2_t maskedoff, vuint16m2_t vs2, uint16_t rs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u16m4_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vror.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[VS2:%.*]], <vscale x 16 x i16> [[VS1:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
vuint16m4_t test_vror_vv_u16m4_tum(vbool4_t mask, vuint16m4_t maskedoff, vuint16m4_t vs2, vuint16m4_t vs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u16m4_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vror.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
vuint16m4_t test_vror_vx_u16m4_tum(vbool4_t mask, vuint16m4_t maskedoff, vuint16m4_t vs2, uint16_t rs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u16m8_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vror.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[VS2:%.*]], <vscale x 32 x i16> [[VS1:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
vuint16m8_t test_vror_vv_u16m8_tum(vbool2_t mask, vuint16m8_t maskedoff, vuint16m8_t vs2, vuint16m8_t vs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u16m8_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vror.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
vuint16m8_t test_vror_vx_u16m8_tum(vbool2_t mask, vuint16m8_t maskedoff, vuint16m8_t vs2, uint16_t rs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u32mf2_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vror.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
vuint32mf2_t test_vror_vv_u32mf2_tum(vbool64_t mask, vuint32mf2_t maskedoff, vuint32mf2_t vs2, vuint32mf2_t vs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u32mf2_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vror.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
vuint32mf2_t test_vror_vx_u32mf2_tum(vbool64_t mask, vuint32mf2_t maskedoff, vuint32mf2_t vs2, uint32_t rs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u32m1_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vror.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
vuint32m1_t test_vror_vv_u32m1_tum(vbool32_t mask, vuint32m1_t maskedoff, vuint32m1_t vs2, vuint32m1_t vs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u32m1_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vror.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
vuint32m1_t test_vror_vx_u32m1_tum(vbool32_t mask, vuint32m1_t maskedoff, vuint32m1_t vs2, uint32_t rs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u32m2_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vror.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
vuint32m2_t test_vror_vv_u32m2_tum(vbool16_t mask, vuint32m2_t maskedoff, vuint32m2_t vs2, vuint32m2_t vs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u32m2_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vror.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
vuint32m2_t test_vror_vx_u32m2_tum(vbool16_t mask, vuint32m2_t maskedoff, vuint32m2_t vs2, uint32_t rs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u32m4_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vror.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
vuint32m4_t test_vror_vv_u32m4_tum(vbool8_t mask, vuint32m4_t maskedoff, vuint32m4_t vs2, vuint32m4_t vs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u32m4_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vror.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
vuint32m4_t test_vror_vx_u32m4_tum(vbool8_t mask, vuint32m4_t maskedoff, vuint32m4_t vs2, uint32_t rs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u32m8_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vror.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[VS2:%.*]], <vscale x 16 x i32> [[VS1:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
vuint32m8_t test_vror_vv_u32m8_tum(vbool4_t mask, vuint32m8_t maskedoff, vuint32m8_t vs2, vuint32m8_t vs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u32m8_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vror.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
vuint32m8_t test_vror_vx_u32m8_tum(vbool4_t mask, vuint32m8_t maskedoff, vuint32m8_t vs2, uint32_t rs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u64m1_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vror.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 1 x i64> [[TMP0]]
//
vuint64m1_t test_vror_vv_u64m1_tum(vbool64_t mask, vuint64m1_t maskedoff, vuint64m1_t vs2, vuint64m1_t vs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u64m1_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vror.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 1 x i64> [[TMP0]]
//
vuint64m1_t test_vror_vx_u64m1_tum(vbool64_t mask, vuint64m1_t maskedoff, vuint64m1_t vs2, uint64_t rs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u64m2_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vror.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
vuint64m2_t test_vror_vv_u64m2_tum(vbool32_t mask, vuint64m2_t maskedoff, vuint64m2_t vs2, vuint64m2_t vs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u64m2_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vror.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
vuint64m2_t test_vror_vx_u64m2_tum(vbool32_t mask, vuint64m2_t maskedoff, vuint64m2_t vs2, uint64_t rs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u64m4_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vror.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
vuint64m4_t test_vror_vv_u64m4_tum(vbool16_t mask, vuint64m4_t maskedoff, vuint64m4_t vs2, vuint64m4_t vs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u64m4_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vror.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
vuint64m4_t test_vror_vx_u64m4_tum(vbool16_t mask, vuint64m4_t maskedoff, vuint64m4_t vs2, uint64_t rs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u64m8_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vror.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[VS2:%.*]], <vscale x 8 x i64> [[VS1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
vuint64m8_t test_vror_vv_u64m8_tum(vbool8_t mask, vuint64m8_t maskedoff, vuint64m8_t vs2, vuint64m8_t vs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u64m8_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vror.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
vuint64m8_t test_vror_vx_u64m8_tum(vbool8_t mask, vuint64m8_t maskedoff, vuint64m8_t vs2, uint64_t rs1, size_t vl) {
return __riscv_vror_tum(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i8mf8_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vror.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[VS2:%.*]], <vscale x 1 x i8> [[VS1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 1 x i8> [[TMP0]]
//
vint8mf8_t test_vror_vv_i8mf8_tumu(vbool64_t mask, vint8mf8_t maskedoff, vint8mf8_t vs2, vint8mf8_t vs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i8mf8_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vror.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 1 x i8> [[TMP0]]
//
vint8mf8_t test_vror_vx_i8mf8_tumu(vbool64_t mask, vint8mf8_t maskedoff, vint8mf8_t vs2, int8_t rs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i8mf4_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vror.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[VS2:%.*]], <vscale x 2 x i8> [[VS1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i8> [[TMP0]]
//
vint8mf4_t test_vror_vv_i8mf4_tumu(vbool32_t mask, vint8mf4_t maskedoff, vint8mf4_t vs2, vint8mf4_t vs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i8mf4_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vror.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i8> [[TMP0]]
//
vint8mf4_t test_vror_vx_i8mf4_tumu(vbool32_t mask, vint8mf4_t maskedoff, vint8mf4_t vs2, int8_t rs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i8mf2_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vror.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i8> [[TMP0]]
//
vint8mf2_t test_vror_vv_i8mf2_tumu(vbool16_t mask, vint8mf2_t maskedoff, vint8mf2_t vs2, vint8mf2_t vs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i8mf2_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vror.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i8> [[TMP0]]
//
vint8mf2_t test_vror_vx_i8mf2_tumu(vbool16_t mask, vint8mf2_t maskedoff, vint8mf2_t vs2, int8_t rs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i8m1_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vror.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i8> [[TMP0]]
//
vint8m1_t test_vror_vv_i8m1_tumu(vbool8_t mask, vint8m1_t maskedoff, vint8m1_t vs2, vint8m1_t vs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i8m1_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vror.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i8> [[TMP0]]
//
vint8m1_t test_vror_vx_i8m1_tumu(vbool8_t mask, vint8m1_t maskedoff, vint8m1_t vs2, int8_t rs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i8m2_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vror.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]
//
vint8m2_t test_vror_vv_i8m2_tumu(vbool4_t mask, vint8m2_t maskedoff, vint8m2_t vs2, vint8m2_t vs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i8m2_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vror.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]
//
vint8m2_t test_vror_vx_i8m2_tumu(vbool4_t mask, vint8m2_t maskedoff, vint8m2_t vs2, int8_t rs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i8m4_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vror.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 32 x i8> [[TMP0]]
//
vint8m4_t test_vror_vv_i8m4_tumu(vbool2_t mask, vint8m4_t maskedoff, vint8m4_t vs2, vint8m4_t vs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i8m4_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vror.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 32 x i8> [[TMP0]]
//
vint8m4_t test_vror_vx_i8m4_tumu(vbool2_t mask, vint8m4_t maskedoff, vint8m4_t vs2, int8_t rs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i8m8_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vror.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 64 x i8> [[TMP0]]
//
vint8m8_t test_vror_vv_i8m8_tumu(vbool1_t mask, vint8m8_t maskedoff, vint8m8_t vs2, vint8m8_t vs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i8m8_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vror.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 64 x i8> [[TMP0]]
//
vint8m8_t test_vror_vx_i8m8_tumu(vbool1_t mask, vint8m8_t maskedoff, vint8m8_t vs2, int8_t rs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i16mf4_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vror.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[VS2:%.*]], <vscale x 1 x i16> [[VS1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 1 x i16> [[TMP0]]
//
vint16mf4_t test_vror_vv_i16mf4_tumu(vbool64_t mask, vint16mf4_t maskedoff, vint16mf4_t vs2, vint16mf4_t vs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i16mf4_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vror.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 1 x i16> [[TMP0]]
//
vint16mf4_t test_vror_vx_i16mf4_tumu(vbool64_t mask, vint16mf4_t maskedoff, vint16mf4_t vs2, int16_t rs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i16mf2_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vror.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[VS2:%.*]], <vscale x 2 x i16> [[VS1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
vint16mf2_t test_vror_vv_i16mf2_tumu(vbool32_t mask, vint16mf2_t maskedoff, vint16mf2_t vs2, vint16mf2_t vs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i16mf2_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vror.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
vint16mf2_t test_vror_vx_i16mf2_tumu(vbool32_t mask, vint16mf2_t maskedoff, vint16mf2_t vs2, int16_t rs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i16m1_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vror.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[VS2:%.*]], <vscale x 4 x i16> [[VS1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
vint16m1_t test_vror_vv_i16m1_tumu(vbool16_t mask, vint16m1_t maskedoff, vint16m1_t vs2, vint16m1_t vs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i16m1_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vror.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
vint16m1_t test_vror_vx_i16m1_tumu(vbool16_t mask, vint16m1_t maskedoff, vint16m1_t vs2, int16_t rs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i16m2_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vror.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[VS2:%.*]], <vscale x 8 x i16> [[VS1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
vint16m2_t test_vror_vv_i16m2_tumu(vbool8_t mask, vint16m2_t maskedoff, vint16m2_t vs2, vint16m2_t vs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i16m2_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vror.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
vint16m2_t test_vror_vx_i16m2_tumu(vbool8_t mask, vint16m2_t maskedoff, vint16m2_t vs2, int16_t rs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i16m4_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vror.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[VS2:%.*]], <vscale x 16 x i16> [[VS1:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
vint16m4_t test_vror_vv_i16m4_tumu(vbool4_t mask, vint16m4_t maskedoff, vint16m4_t vs2, vint16m4_t vs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i16m4_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vror.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
vint16m4_t test_vror_vx_i16m4_tumu(vbool4_t mask, vint16m4_t maskedoff, vint16m4_t vs2, int16_t rs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i16m8_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vror.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[VS2:%.*]], <vscale x 32 x i16> [[VS1:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
vint16m8_t test_vror_vv_i16m8_tumu(vbool2_t mask, vint16m8_t maskedoff, vint16m8_t vs2, vint16m8_t vs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i16m8_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vror.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
vint16m8_t test_vror_vx_i16m8_tumu(vbool2_t mask, vint16m8_t maskedoff, vint16m8_t vs2, int16_t rs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i32mf2_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vror.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
vint32mf2_t test_vror_vv_i32mf2_tumu(vbool64_t mask, vint32mf2_t maskedoff, vint32mf2_t vs2, vint32mf2_t vs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i32mf2_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vror.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
vint32mf2_t test_vror_vx_i32mf2_tumu(vbool64_t mask, vint32mf2_t maskedoff, vint32mf2_t vs2, int32_t rs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i32m1_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vror.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
vint32m1_t test_vror_vv_i32m1_tumu(vbool32_t mask, vint32m1_t maskedoff, vint32m1_t vs2, vint32m1_t vs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i32m1_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vror.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
vint32m1_t test_vror_vx_i32m1_tumu(vbool32_t mask, vint32m1_t maskedoff, vint32m1_t vs2, int32_t rs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i32m2_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vror.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
vint32m2_t test_vror_vv_i32m2_tumu(vbool16_t mask, vint32m2_t maskedoff, vint32m2_t vs2, vint32m2_t vs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i32m2_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vror.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
vint32m2_t test_vror_vx_i32m2_tumu(vbool16_t mask, vint32m2_t maskedoff, vint32m2_t vs2, int32_t rs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i32m4_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vror.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
vint32m4_t test_vror_vv_i32m4_tumu(vbool8_t mask, vint32m4_t maskedoff, vint32m4_t vs2, vint32m4_t vs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i32m4_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vror.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
vint32m4_t test_vror_vx_i32m4_tumu(vbool8_t mask, vint32m4_t maskedoff, vint32m4_t vs2, int32_t rs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i32m8_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vror.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[VS2:%.*]], <vscale x 16 x i32> [[VS1:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
vint32m8_t test_vror_vv_i32m8_tumu(vbool4_t mask, vint32m8_t maskedoff, vint32m8_t vs2, vint32m8_t vs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i32m8_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vror.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
vint32m8_t test_vror_vx_i32m8_tumu(vbool4_t mask, vint32m8_t maskedoff, vint32m8_t vs2, int32_t rs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i64m1_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vror.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 1 x i64> [[TMP0]]
//
vint64m1_t test_vror_vv_i64m1_tumu(vbool64_t mask, vint64m1_t maskedoff, vint64m1_t vs2, vint64m1_t vs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i64m1_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vror.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 1 x i64> [[TMP0]]
//
vint64m1_t test_vror_vx_i64m1_tumu(vbool64_t mask, vint64m1_t maskedoff, vint64m1_t vs2, int64_t rs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i64m2_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vror.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
vint64m2_t test_vror_vv_i64m2_tumu(vbool32_t mask, vint64m2_t maskedoff, vint64m2_t vs2, vint64m2_t vs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i64m2_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vror.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
vint64m2_t test_vror_vx_i64m2_tumu(vbool32_t mask, vint64m2_t maskedoff, vint64m2_t vs2, int64_t rs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i64m4_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vror.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
vint64m4_t test_vror_vv_i64m4_tumu(vbool16_t mask, vint64m4_t maskedoff, vint64m4_t vs2, vint64m4_t vs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i64m4_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vror.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
vint64m4_t test_vror_vx_i64m4_tumu(vbool16_t mask, vint64m4_t maskedoff, vint64m4_t vs2, int64_t rs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i64m8_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vror.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[VS2:%.*]], <vscale x 8 x i64> [[VS1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
vint64m8_t test_vror_vv_i64m8_tumu(vbool8_t mask, vint64m8_t maskedoff, vint64m8_t vs2, vint64m8_t vs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i64m8_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vror.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
vint64m8_t test_vror_vx_i64m8_tumu(vbool8_t mask, vint64m8_t maskedoff, vint64m8_t vs2, int64_t rs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u8mf8_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vror.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[VS2:%.*]], <vscale x 1 x i8> [[VS1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 1 x i8> [[TMP0]]
//
vuint8mf8_t test_vror_vv_u8mf8_tumu(vbool64_t mask, vuint8mf8_t maskedoff, vuint8mf8_t vs2, vuint8mf8_t vs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u8mf8_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vror.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 1 x i8> [[TMP0]]
//
vuint8mf8_t test_vror_vx_u8mf8_tumu(vbool64_t mask, vuint8mf8_t maskedoff, vuint8mf8_t vs2, uint8_t rs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u8mf4_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vror.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[VS2:%.*]], <vscale x 2 x i8> [[VS1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i8> [[TMP0]]
//
vuint8mf4_t test_vror_vv_u8mf4_tumu(vbool32_t mask, vuint8mf4_t maskedoff, vuint8mf4_t vs2, vuint8mf4_t vs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u8mf4_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vror.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i8> [[TMP0]]
//
vuint8mf4_t test_vror_vx_u8mf4_tumu(vbool32_t mask, vuint8mf4_t maskedoff, vuint8mf4_t vs2, uint8_t rs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u8mf2_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vror.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i8> [[TMP0]]
//
vuint8mf2_t test_vror_vv_u8mf2_tumu(vbool16_t mask, vuint8mf2_t maskedoff, vuint8mf2_t vs2, vuint8mf2_t vs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u8mf2_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vror.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i8> [[TMP0]]
//
vuint8mf2_t test_vror_vx_u8mf2_tumu(vbool16_t mask, vuint8mf2_t maskedoff, vuint8mf2_t vs2, uint8_t rs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u8m1_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vror.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i8> [[TMP0]]
//
vuint8m1_t test_vror_vv_u8m1_tumu(vbool8_t mask, vuint8m1_t maskedoff, vuint8m1_t vs2, vuint8m1_t vs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u8m1_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vror.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i8> [[TMP0]]
//
vuint8m1_t test_vror_vx_u8m1_tumu(vbool8_t mask, vuint8m1_t maskedoff, vuint8m1_t vs2, uint8_t rs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u8m2_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vror.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]
//
vuint8m2_t test_vror_vv_u8m2_tumu(vbool4_t mask, vuint8m2_t maskedoff, vuint8m2_t vs2, vuint8m2_t vs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u8m2_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vror.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]
//
vuint8m2_t test_vror_vx_u8m2_tumu(vbool4_t mask, vuint8m2_t maskedoff, vuint8m2_t vs2, uint8_t rs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u8m4_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vror.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 32 x i8> [[TMP0]]
//
vuint8m4_t test_vror_vv_u8m4_tumu(vbool2_t mask, vuint8m4_t maskedoff, vuint8m4_t vs2, vuint8m4_t vs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u8m4_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vror.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 32 x i8> [[TMP0]]
//
vuint8m4_t test_vror_vx_u8m4_tumu(vbool2_t mask, vuint8m4_t maskedoff, vuint8m4_t vs2, uint8_t rs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u8m8_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vror.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 64 x i8> [[TMP0]]
//
vuint8m8_t test_vror_vv_u8m8_tumu(vbool1_t mask, vuint8m8_t maskedoff, vuint8m8_t vs2, vuint8m8_t vs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u8m8_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vror.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 64 x i8> [[TMP0]]
//
vuint8m8_t test_vror_vx_u8m8_tumu(vbool1_t mask, vuint8m8_t maskedoff, vuint8m8_t vs2, uint8_t rs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u16mf4_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vror.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[VS2:%.*]], <vscale x 1 x i16> [[VS1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 1 x i16> [[TMP0]]
//
vuint16mf4_t test_vror_vv_u16mf4_tumu(vbool64_t mask, vuint16mf4_t maskedoff, vuint16mf4_t vs2, vuint16mf4_t vs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u16mf4_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vror.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 1 x i16> [[TMP0]]
//
vuint16mf4_t test_vror_vx_u16mf4_tumu(vbool64_t mask, vuint16mf4_t maskedoff, vuint16mf4_t vs2, uint16_t rs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u16mf2_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vror.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[VS2:%.*]], <vscale x 2 x i16> [[VS1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
vuint16mf2_t test_vror_vv_u16mf2_tumu(vbool32_t mask, vuint16mf2_t maskedoff, vuint16mf2_t vs2, vuint16mf2_t vs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u16mf2_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vror.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
vuint16mf2_t test_vror_vx_u16mf2_tumu(vbool32_t mask, vuint16mf2_t maskedoff, vuint16mf2_t vs2, uint16_t rs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u16m1_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vror.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[VS2:%.*]], <vscale x 4 x i16> [[VS1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
vuint16m1_t test_vror_vv_u16m1_tumu(vbool16_t mask, vuint16m1_t maskedoff, vuint16m1_t vs2, vuint16m1_t vs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u16m1_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vror.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
vuint16m1_t test_vror_vx_u16m1_tumu(vbool16_t mask, vuint16m1_t maskedoff, vuint16m1_t vs2, uint16_t rs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u16m2_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vror.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[VS2:%.*]], <vscale x 8 x i16> [[VS1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
vuint16m2_t test_vror_vv_u16m2_tumu(vbool8_t mask, vuint16m2_t maskedoff, vuint16m2_t vs2, vuint16m2_t vs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u16m2_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vror.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
vuint16m2_t test_vror_vx_u16m2_tumu(vbool8_t mask, vuint16m2_t maskedoff, vuint16m2_t vs2, uint16_t rs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u16m4_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vror.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[VS2:%.*]], <vscale x 16 x i16> [[VS1:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
vuint16m4_t test_vror_vv_u16m4_tumu(vbool4_t mask, vuint16m4_t maskedoff, vuint16m4_t vs2, vuint16m4_t vs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u16m4_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vror.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
vuint16m4_t test_vror_vx_u16m4_tumu(vbool4_t mask, vuint16m4_t maskedoff, vuint16m4_t vs2, uint16_t rs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u16m8_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vror.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[VS2:%.*]], <vscale x 32 x i16> [[VS1:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
vuint16m8_t test_vror_vv_u16m8_tumu(vbool2_t mask, vuint16m8_t maskedoff, vuint16m8_t vs2, vuint16m8_t vs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u16m8_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vror.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
vuint16m8_t test_vror_vx_u16m8_tumu(vbool2_t mask, vuint16m8_t maskedoff, vuint16m8_t vs2, uint16_t rs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u32mf2_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vror.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
vuint32mf2_t test_vror_vv_u32mf2_tumu(vbool64_t mask, vuint32mf2_t maskedoff, vuint32mf2_t vs2, vuint32mf2_t vs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u32mf2_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vror.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
vuint32mf2_t test_vror_vx_u32mf2_tumu(vbool64_t mask, vuint32mf2_t maskedoff, vuint32mf2_t vs2, uint32_t rs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u32m1_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vror.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
vuint32m1_t test_vror_vv_u32m1_tumu(vbool32_t mask, vuint32m1_t maskedoff, vuint32m1_t vs2, vuint32m1_t vs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u32m1_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vror.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
vuint32m1_t test_vror_vx_u32m1_tumu(vbool32_t mask, vuint32m1_t maskedoff, vuint32m1_t vs2, uint32_t rs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u32m2_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vror.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
vuint32m2_t test_vror_vv_u32m2_tumu(vbool16_t mask, vuint32m2_t maskedoff, vuint32m2_t vs2, vuint32m2_t vs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u32m2_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vror.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
vuint32m2_t test_vror_vx_u32m2_tumu(vbool16_t mask, vuint32m2_t maskedoff, vuint32m2_t vs2, uint32_t rs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u32m4_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vror.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
vuint32m4_t test_vror_vv_u32m4_tumu(vbool8_t mask, vuint32m4_t maskedoff, vuint32m4_t vs2, vuint32m4_t vs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u32m4_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vror.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
vuint32m4_t test_vror_vx_u32m4_tumu(vbool8_t mask, vuint32m4_t maskedoff, vuint32m4_t vs2, uint32_t rs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u32m8_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vror.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[VS2:%.*]], <vscale x 16 x i32> [[VS1:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
vuint32m8_t test_vror_vv_u32m8_tumu(vbool4_t mask, vuint32m8_t maskedoff, vuint32m8_t vs2, vuint32m8_t vs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u32m8_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vror.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
vuint32m8_t test_vror_vx_u32m8_tumu(vbool4_t mask, vuint32m8_t maskedoff, vuint32m8_t vs2, uint32_t rs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u64m1_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vror.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 1 x i64> [[TMP0]]
//
vuint64m1_t test_vror_vv_u64m1_tumu(vbool64_t mask, vuint64m1_t maskedoff, vuint64m1_t vs2, vuint64m1_t vs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u64m1_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vror.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 1 x i64> [[TMP0]]
//
vuint64m1_t test_vror_vx_u64m1_tumu(vbool64_t mask, vuint64m1_t maskedoff, vuint64m1_t vs2, uint64_t rs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u64m2_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vror.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
vuint64m2_t test_vror_vv_u64m2_tumu(vbool32_t mask, vuint64m2_t maskedoff, vuint64m2_t vs2, vuint64m2_t vs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u64m2_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vror.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
vuint64m2_t test_vror_vx_u64m2_tumu(vbool32_t mask, vuint64m2_t maskedoff, vuint64m2_t vs2, uint64_t rs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u64m4_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vror.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
vuint64m4_t test_vror_vv_u64m4_tumu(vbool16_t mask, vuint64m4_t maskedoff, vuint64m4_t vs2, vuint64m4_t vs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u64m4_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vror.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
vuint64m4_t test_vror_vx_u64m4_tumu(vbool16_t mask, vuint64m4_t maskedoff, vuint64m4_t vs2, uint64_t rs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u64m8_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vror.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[VS2:%.*]], <vscale x 8 x i64> [[VS1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
vuint64m8_t test_vror_vv_u64m8_tumu(vbool8_t mask, vuint64m8_t maskedoff, vuint64m8_t vs2, vuint64m8_t vs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u64m8_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vror.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
vuint64m8_t test_vror_vx_u64m8_tumu(vbool8_t mask, vuint64m8_t maskedoff, vuint64m8_t vs2, uint64_t rs1, size_t vl) {
return __riscv_vror_tumu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i8mf8_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vror.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[VS2:%.*]], <vscale x 1 x i8> [[VS1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 1 x i8> [[TMP0]]
//
vint8mf8_t test_vror_vv_i8mf8_mu(vbool64_t mask, vint8mf8_t maskedoff, vint8mf8_t vs2, vint8mf8_t vs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i8mf8_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vror.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 1 x i8> [[TMP0]]
//
vint8mf8_t test_vror_vx_i8mf8_mu(vbool64_t mask, vint8mf8_t maskedoff, vint8mf8_t vs2, int8_t rs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i8mf4_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vror.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[VS2:%.*]], <vscale x 2 x i8> [[VS1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 2 x i8> [[TMP0]]
//
vint8mf4_t test_vror_vv_i8mf4_mu(vbool32_t mask, vint8mf4_t maskedoff, vint8mf4_t vs2, vint8mf4_t vs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i8mf4_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vror.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 2 x i8> [[TMP0]]
//
vint8mf4_t test_vror_vx_i8mf4_mu(vbool32_t mask, vint8mf4_t maskedoff, vint8mf4_t vs2, int8_t rs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i8mf2_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vror.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 4 x i8> [[TMP0]]
//
vint8mf2_t test_vror_vv_i8mf2_mu(vbool16_t mask, vint8mf2_t maskedoff, vint8mf2_t vs2, vint8mf2_t vs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i8mf2_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vror.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 4 x i8> [[TMP0]]
//
vint8mf2_t test_vror_vx_i8mf2_mu(vbool16_t mask, vint8mf2_t maskedoff, vint8mf2_t vs2, int8_t rs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i8m1_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vror.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 8 x i8> [[TMP0]]
//
vint8m1_t test_vror_vv_i8m1_mu(vbool8_t mask, vint8m1_t maskedoff, vint8m1_t vs2, vint8m1_t vs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i8m1_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vror.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 8 x i8> [[TMP0]]
//
vint8m1_t test_vror_vx_i8m1_mu(vbool8_t mask, vint8m1_t maskedoff, vint8m1_t vs2, int8_t rs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i8m2_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vror.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]
//
vint8m2_t test_vror_vv_i8m2_mu(vbool4_t mask, vint8m2_t maskedoff, vint8m2_t vs2, vint8m2_t vs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i8m2_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vror.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]
//
vint8m2_t test_vror_vx_i8m2_mu(vbool4_t mask, vint8m2_t maskedoff, vint8m2_t vs2, int8_t rs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i8m4_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vror.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 32 x i8> [[TMP0]]
//
vint8m4_t test_vror_vv_i8m4_mu(vbool2_t mask, vint8m4_t maskedoff, vint8m4_t vs2, vint8m4_t vs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i8m4_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vror.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 32 x i8> [[TMP0]]
//
vint8m4_t test_vror_vx_i8m4_mu(vbool2_t mask, vint8m4_t maskedoff, vint8m4_t vs2, int8_t rs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i8m8_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vror.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 64 x i8> [[TMP0]]
//
vint8m8_t test_vror_vv_i8m8_mu(vbool1_t mask, vint8m8_t maskedoff, vint8m8_t vs2, vint8m8_t vs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i8m8_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vror.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 64 x i8> [[TMP0]]
//
vint8m8_t test_vror_vx_i8m8_mu(vbool1_t mask, vint8m8_t maskedoff, vint8m8_t vs2, int8_t rs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i16mf4_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vror.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[VS2:%.*]], <vscale x 1 x i16> [[VS1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 1 x i16> [[TMP0]]
//
vint16mf4_t test_vror_vv_i16mf4_mu(vbool64_t mask, vint16mf4_t maskedoff, vint16mf4_t vs2, vint16mf4_t vs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i16mf4_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vror.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 1 x i16> [[TMP0]]
//
vint16mf4_t test_vror_vx_i16mf4_mu(vbool64_t mask, vint16mf4_t maskedoff, vint16mf4_t vs2, int16_t rs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i16mf2_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vror.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[VS2:%.*]], <vscale x 2 x i16> [[VS1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
vint16mf2_t test_vror_vv_i16mf2_mu(vbool32_t mask, vint16mf2_t maskedoff, vint16mf2_t vs2, vint16mf2_t vs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i16mf2_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vror.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
vint16mf2_t test_vror_vx_i16mf2_mu(vbool32_t mask, vint16mf2_t maskedoff, vint16mf2_t vs2, int16_t rs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i16m1_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vror.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[VS2:%.*]], <vscale x 4 x i16> [[VS1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
vint16m1_t test_vror_vv_i16m1_mu(vbool16_t mask, vint16m1_t maskedoff, vint16m1_t vs2, vint16m1_t vs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i16m1_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vror.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
vint16m1_t test_vror_vx_i16m1_mu(vbool16_t mask, vint16m1_t maskedoff, vint16m1_t vs2, int16_t rs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i16m2_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vror.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[VS2:%.*]], <vscale x 8 x i16> [[VS1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
vint16m2_t test_vror_vv_i16m2_mu(vbool8_t mask, vint16m2_t maskedoff, vint16m2_t vs2, vint16m2_t vs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i16m2_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vror.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
vint16m2_t test_vror_vx_i16m2_mu(vbool8_t mask, vint16m2_t maskedoff, vint16m2_t vs2, int16_t rs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i16m4_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vror.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[VS2:%.*]], <vscale x 16 x i16> [[VS1:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
vint16m4_t test_vror_vv_i16m4_mu(vbool4_t mask, vint16m4_t maskedoff, vint16m4_t vs2, vint16m4_t vs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i16m4_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vror.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
vint16m4_t test_vror_vx_i16m4_mu(vbool4_t mask, vint16m4_t maskedoff, vint16m4_t vs2, int16_t rs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i16m8_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vror.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[VS2:%.*]], <vscale x 32 x i16> [[VS1:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
vint16m8_t test_vror_vv_i16m8_mu(vbool2_t mask, vint16m8_t maskedoff, vint16m8_t vs2, vint16m8_t vs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i16m8_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vror.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
vint16m8_t test_vror_vx_i16m8_mu(vbool2_t mask, vint16m8_t maskedoff, vint16m8_t vs2, int16_t rs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i32mf2_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vror.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
vint32mf2_t test_vror_vv_i32mf2_mu(vbool64_t mask, vint32mf2_t maskedoff, vint32mf2_t vs2, vint32mf2_t vs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i32mf2_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vror.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
vint32mf2_t test_vror_vx_i32mf2_mu(vbool64_t mask, vint32mf2_t maskedoff, vint32mf2_t vs2, int32_t rs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i32m1_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vror.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
vint32m1_t test_vror_vv_i32m1_mu(vbool32_t mask, vint32m1_t maskedoff, vint32m1_t vs2, vint32m1_t vs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i32m1_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vror.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
vint32m1_t test_vror_vx_i32m1_mu(vbool32_t mask, vint32m1_t maskedoff, vint32m1_t vs2, int32_t rs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i32m2_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vror.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
vint32m2_t test_vror_vv_i32m2_mu(vbool16_t mask, vint32m2_t maskedoff, vint32m2_t vs2, vint32m2_t vs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i32m2_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vror.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
vint32m2_t test_vror_vx_i32m2_mu(vbool16_t mask, vint32m2_t maskedoff, vint32m2_t vs2, int32_t rs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i32m4_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vror.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
vint32m4_t test_vror_vv_i32m4_mu(vbool8_t mask, vint32m4_t maskedoff, vint32m4_t vs2, vint32m4_t vs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i32m4_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vror.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
vint32m4_t test_vror_vx_i32m4_mu(vbool8_t mask, vint32m4_t maskedoff, vint32m4_t vs2, int32_t rs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i32m8_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vror.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[VS2:%.*]], <vscale x 16 x i32> [[VS1:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
vint32m8_t test_vror_vv_i32m8_mu(vbool4_t mask, vint32m8_t maskedoff, vint32m8_t vs2, vint32m8_t vs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i32m8_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vror.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
vint32m8_t test_vror_vx_i32m8_mu(vbool4_t mask, vint32m8_t maskedoff, vint32m8_t vs2, int32_t rs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i64m1_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vror.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 1 x i64> [[TMP0]]
//
vint64m1_t test_vror_vv_i64m1_mu(vbool64_t mask, vint64m1_t maskedoff, vint64m1_t vs2, vint64m1_t vs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i64m1_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vror.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 1 x i64> [[TMP0]]
//
vint64m1_t test_vror_vx_i64m1_mu(vbool64_t mask, vint64m1_t maskedoff, vint64m1_t vs2, int64_t rs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i64m2_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vror.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
vint64m2_t test_vror_vv_i64m2_mu(vbool32_t mask, vint64m2_t maskedoff, vint64m2_t vs2, vint64m2_t vs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i64m2_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vror.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
vint64m2_t test_vror_vx_i64m2_mu(vbool32_t mask, vint64m2_t maskedoff, vint64m2_t vs2, int64_t rs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i64m4_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vror.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
vint64m4_t test_vror_vv_i64m4_mu(vbool16_t mask, vint64m4_t maskedoff, vint64m4_t vs2, vint64m4_t vs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i64m4_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vror.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
vint64m4_t test_vror_vx_i64m4_mu(vbool16_t mask, vint64m4_t maskedoff, vint64m4_t vs2, int64_t rs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_i64m8_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vror.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[VS2:%.*]], <vscale x 8 x i64> [[VS1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
vint64m8_t test_vror_vv_i64m8_mu(vbool8_t mask, vint64m8_t maskedoff, vint64m8_t vs2, vint64m8_t vs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_i64m8_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vror.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
vint64m8_t test_vror_vx_i64m8_mu(vbool8_t mask, vint64m8_t maskedoff, vint64m8_t vs2, int64_t rs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u8mf8_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vror.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[VS2:%.*]], <vscale x 1 x i8> [[VS1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 1 x i8> [[TMP0]]
//
vuint8mf8_t test_vror_vv_u8mf8_mu(vbool64_t mask, vuint8mf8_t maskedoff, vuint8mf8_t vs2, vuint8mf8_t vs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u8mf8_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vror.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 1 x i8> [[TMP0]]
//
vuint8mf8_t test_vror_vx_u8mf8_mu(vbool64_t mask, vuint8mf8_t maskedoff, vuint8mf8_t vs2, uint8_t rs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u8mf4_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vror.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[VS2:%.*]], <vscale x 2 x i8> [[VS1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 2 x i8> [[TMP0]]
//
vuint8mf4_t test_vror_vv_u8mf4_mu(vbool32_t mask, vuint8mf4_t maskedoff, vuint8mf4_t vs2, vuint8mf4_t vs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u8mf4_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vror.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 2 x i8> [[TMP0]]
//
vuint8mf4_t test_vror_vx_u8mf4_mu(vbool32_t mask, vuint8mf4_t maskedoff, vuint8mf4_t vs2, uint8_t rs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u8mf2_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vror.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 4 x i8> [[TMP0]]
//
vuint8mf2_t test_vror_vv_u8mf2_mu(vbool16_t mask, vuint8mf2_t maskedoff, vuint8mf2_t vs2, vuint8mf2_t vs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u8mf2_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vror.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 4 x i8> [[TMP0]]
//
vuint8mf2_t test_vror_vx_u8mf2_mu(vbool16_t mask, vuint8mf2_t maskedoff, vuint8mf2_t vs2, uint8_t rs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u8m1_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vror.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 8 x i8> [[TMP0]]
//
vuint8m1_t test_vror_vv_u8m1_mu(vbool8_t mask, vuint8m1_t maskedoff, vuint8m1_t vs2, vuint8m1_t vs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u8m1_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vror.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 8 x i8> [[TMP0]]
//
vuint8m1_t test_vror_vx_u8m1_mu(vbool8_t mask, vuint8m1_t maskedoff, vuint8m1_t vs2, uint8_t rs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u8m2_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vror.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]
//
vuint8m2_t test_vror_vv_u8m2_mu(vbool4_t mask, vuint8m2_t maskedoff, vuint8m2_t vs2, vuint8m2_t vs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u8m2_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vror.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]
//
vuint8m2_t test_vror_vx_u8m2_mu(vbool4_t mask, vuint8m2_t maskedoff, vuint8m2_t vs2, uint8_t rs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u8m4_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vror.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 32 x i8> [[TMP0]]
//
vuint8m4_t test_vror_vv_u8m4_mu(vbool2_t mask, vuint8m4_t maskedoff, vuint8m4_t vs2, vuint8m4_t vs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u8m4_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vror.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 32 x i8> [[TMP0]]
//
vuint8m4_t test_vror_vx_u8m4_mu(vbool2_t mask, vuint8m4_t maskedoff, vuint8m4_t vs2, uint8_t rs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u8m8_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vror.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 64 x i8> [[TMP0]]
//
vuint8m8_t test_vror_vv_u8m8_mu(vbool1_t mask, vuint8m8_t maskedoff, vuint8m8_t vs2, vuint8m8_t vs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u8m8_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vror.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 64 x i8> [[TMP0]]
//
vuint8m8_t test_vror_vx_u8m8_mu(vbool1_t mask, vuint8m8_t maskedoff, vuint8m8_t vs2, uint8_t rs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u16mf4_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vror.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[VS2:%.*]], <vscale x 1 x i16> [[VS1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 1 x i16> [[TMP0]]
//
vuint16mf4_t test_vror_vv_u16mf4_mu(vbool64_t mask, vuint16mf4_t maskedoff, vuint16mf4_t vs2, vuint16mf4_t vs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u16mf4_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vror.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 1 x i16> [[TMP0]]
//
vuint16mf4_t test_vror_vx_u16mf4_mu(vbool64_t mask, vuint16mf4_t maskedoff, vuint16mf4_t vs2, uint16_t rs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u16mf2_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vror.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[VS2:%.*]], <vscale x 2 x i16> [[VS1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
vuint16mf2_t test_vror_vv_u16mf2_mu(vbool32_t mask, vuint16mf2_t maskedoff, vuint16mf2_t vs2, vuint16mf2_t vs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u16mf2_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vror.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
vuint16mf2_t test_vror_vx_u16mf2_mu(vbool32_t mask, vuint16mf2_t maskedoff, vuint16mf2_t vs2, uint16_t rs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u16m1_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vror.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[VS2:%.*]], <vscale x 4 x i16> [[VS1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
vuint16m1_t test_vror_vv_u16m1_mu(vbool16_t mask, vuint16m1_t maskedoff, vuint16m1_t vs2, vuint16m1_t vs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u16m1_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vror.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
vuint16m1_t test_vror_vx_u16m1_mu(vbool16_t mask, vuint16m1_t maskedoff, vuint16m1_t vs2, uint16_t rs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u16m2_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vror.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[VS2:%.*]], <vscale x 8 x i16> [[VS1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
vuint16m2_t test_vror_vv_u16m2_mu(vbool8_t mask, vuint16m2_t maskedoff, vuint16m2_t vs2, vuint16m2_t vs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u16m2_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vror.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
vuint16m2_t test_vror_vx_u16m2_mu(vbool8_t mask, vuint16m2_t maskedoff, vuint16m2_t vs2, uint16_t rs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u16m4_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vror.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[VS2:%.*]], <vscale x 16 x i16> [[VS1:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
vuint16m4_t test_vror_vv_u16m4_mu(vbool4_t mask, vuint16m4_t maskedoff, vuint16m4_t vs2, vuint16m4_t vs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u16m4_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vror.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
vuint16m4_t test_vror_vx_u16m4_mu(vbool4_t mask, vuint16m4_t maskedoff, vuint16m4_t vs2, uint16_t rs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u16m8_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vror.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[VS2:%.*]], <vscale x 32 x i16> [[VS1:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
vuint16m8_t test_vror_vv_u16m8_mu(vbool2_t mask, vuint16m8_t maskedoff, vuint16m8_t vs2, vuint16m8_t vs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u16m8_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vror.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
vuint16m8_t test_vror_vx_u16m8_mu(vbool2_t mask, vuint16m8_t maskedoff, vuint16m8_t vs2, uint16_t rs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u32mf2_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vror.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
vuint32mf2_t test_vror_vv_u32mf2_mu(vbool64_t mask, vuint32mf2_t maskedoff, vuint32mf2_t vs2, vuint32mf2_t vs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u32mf2_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vror.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
vuint32mf2_t test_vror_vx_u32mf2_mu(vbool64_t mask, vuint32mf2_t maskedoff, vuint32mf2_t vs2, uint32_t rs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u32m1_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vror.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
vuint32m1_t test_vror_vv_u32m1_mu(vbool32_t mask, vuint32m1_t maskedoff, vuint32m1_t vs2, vuint32m1_t vs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u32m1_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vror.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
vuint32m1_t test_vror_vx_u32m1_mu(vbool32_t mask, vuint32m1_t maskedoff, vuint32m1_t vs2, uint32_t rs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u32m2_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vror.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
vuint32m2_t test_vror_vv_u32m2_mu(vbool16_t mask, vuint32m2_t maskedoff, vuint32m2_t vs2, vuint32m2_t vs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u32m2_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vror.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
vuint32m2_t test_vror_vx_u32m2_mu(vbool16_t mask, vuint32m2_t maskedoff, vuint32m2_t vs2, uint32_t rs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u32m4_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vror.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
vuint32m4_t test_vror_vv_u32m4_mu(vbool8_t mask, vuint32m4_t maskedoff, vuint32m4_t vs2, vuint32m4_t vs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u32m4_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vror.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
vuint32m4_t test_vror_vx_u32m4_mu(vbool8_t mask, vuint32m4_t maskedoff, vuint32m4_t vs2, uint32_t rs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u32m8_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vror.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[VS2:%.*]], <vscale x 16 x i32> [[VS1:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
vuint32m8_t test_vror_vv_u32m8_mu(vbool4_t mask, vuint32m8_t maskedoff, vuint32m8_t vs2, vuint32m8_t vs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u32m8_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vror.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
vuint32m8_t test_vror_vx_u32m8_mu(vbool4_t mask, vuint32m8_t maskedoff, vuint32m8_t vs2, uint32_t rs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u64m1_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vror.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 1 x i64> [[TMP0]]
//
vuint64m1_t test_vror_vv_u64m1_mu(vbool64_t mask, vuint64m1_t maskedoff, vuint64m1_t vs2, vuint64m1_t vs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u64m1_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vror.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 1 x i64> [[TMP0]]
//
vuint64m1_t test_vror_vx_u64m1_mu(vbool64_t mask, vuint64m1_t maskedoff, vuint64m1_t vs2, uint64_t rs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u64m2_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vror.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
vuint64m2_t test_vror_vv_u64m2_mu(vbool32_t mask, vuint64m2_t maskedoff, vuint64m2_t vs2, vuint64m2_t vs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u64m2_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vror.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
vuint64m2_t test_vror_vx_u64m2_mu(vbool32_t mask, vuint64m2_t maskedoff, vuint64m2_t vs2, uint64_t rs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u64m4_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vror.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
vuint64m4_t test_vror_vv_u64m4_mu(vbool16_t mask, vuint64m4_t maskedoff, vuint64m4_t vs2, vuint64m4_t vs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u64m4_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vror.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
vuint64m4_t test_vror_vx_u64m4_mu(vbool16_t mask, vuint64m4_t maskedoff, vuint64m4_t vs2, uint64_t rs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, rs1, vl);
}
// CHECK-LABEL: @test_vror_vv_u64m8_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vror.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[VS2:%.*]], <vscale x 8 x i64> [[VS1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
vuint64m8_t test_vror_vv_u64m8_mu(vbool8_t mask, vuint64m8_t maskedoff, vuint64m8_t vs2, vuint64m8_t vs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, vs1, vl);
}
// CHECK-LABEL: @test_vror_vx_u64m8_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vror.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
vuint64m8_t test_vror_vx_u64m8_mu(vbool8_t mask, vuint64m8_t maskedoff, vuint64m8_t vs2, uint64_t rs1, size_t vl) {
return __riscv_vror_mu(mask, maskedoff, vs2, rs1, vl);
}

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsha2ch.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsha2cl.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsha2ms.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm3c.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm3me.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm4k.c

  • This file was added.
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck %s
#include <riscv_vector.h>
// CHECK-LABEL: @test_vsm4k_vi_u32mf2_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vsm4k.nxv1i32.i32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 0, i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
vuint32mf2_t test_vsm4k_vi_u32mf2_tu(vuint32mf2_t maskedoff, vuint32mf2_t vs2, size_t uimm, size_t vl) {
return __riscv_vsm4k_tu(maskedoff, vs2, 0, vl);
craig.topperUnsubmitted
Done
ReplyInline Actions

uimm is unused

craig.topper: `uimm` is unused
}
craig.topperUnsubmitted
Done
ReplyInline Actions

Need to update SemaChecking.cpp to check the valid range for the immediate.

craig.topper: Need to update SemaChecking.cpp to check the valid range for the immediate.
// CHECK-LABEL: @test_vsm4k_vi_u32m1_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vsm4k.nxv2i32.i32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 0, i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
vuint32m1_t test_vsm4k_vi_u32m1_tu(vuint32m1_t maskedoff, vuint32m1_t vs2, size_t uimm, size_t vl) {
return __riscv_vsm4k_tu(maskedoff, vs2, 0, vl);
}
// CHECK-LABEL: @test_vsm4k_vi_u32m2_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vsm4k.nxv4i32.i32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 0, i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
vuint32m2_t test_vsm4k_vi_u32m2_tu(vuint32m2_t maskedoff, vuint32m2_t vs2, size_t uimm, size_t vl) {
return __riscv_vsm4k_tu(maskedoff, vs2, 0, vl);
}
// CHECK-LABEL: @test_vsm4k_vi_u32m4_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vsm4k.nxv8i32.i32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 0, i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
vuint32m4_t test_vsm4k_vi_u32m4_tu(vuint32m4_t maskedoff, vuint32m4_t vs2, size_t uimm, size_t vl) {
return __riscv_vsm4k_tu(maskedoff, vs2, 0, vl);
}
// CHECK-LABEL: @test_vsm4k_vi_u32m8_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vsm4k.nxv16i32.i32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 0, i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
vuint32m8_t test_vsm4k_vi_u32m8_tu(vuint32m8_t maskedoff, vuint32m8_t vs2, size_t uimm, size_t vl) {
return __riscv_vsm4k_tu(maskedoff, vs2, 0, vl);
}

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm4r.c

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsll.c

  • This file was added.
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck %s
#include <riscv_vector.h>
// CHECK-LABEL: @test_vwsll_vv_i16mf4_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 1 x i16> [[TMP0]]
//
vint16mf4_t test_vwsll_vv_i16mf4_tu(vint16mf4_t maskedoff, vint8mf8_t op1, vint8mf8_t op2, size_t vl) {
return __riscv_vwsll_vv_tu(maskedoff, op1, op2, vl);
craig.topperUnsubmitted
Not Done
ReplyInline Actions

Shift amounts should always be unsigned

craig.topper: Shift amounts should always be unsigned
}
// CHECK-LABEL: @test_vwsll_vx_i16mf4_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 1 x i16> [[TMP0]]
//
vint16mf4_t test_vwsll_vx_i16mf4_tu(vint16mf4_t maskedoff, vint8mf8_t op1, int8_t op2, size_t vl) {
return __riscv_vwsll_vx_tu(maskedoff, op1, op2, vl);
craig.topperUnsubmitted
Done
ReplyInline Actions

Scalar shift amount should be size_t to match other shifts. This was raised on the intrinsic PR

craig.topper: Scalar shift amount should be size_t to match other shifts. This was raised on the intrinsic PR
}
// CHECK-LABEL: @test_vwsll_vv_i16mf2_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
vint16mf2_t test_vwsll_vv_i16mf2_tu(vint16mf2_t maskedoff, vint8mf4_t op1, vint8mf4_t op2, size_t vl) {
return __riscv_vwsll_vv_tu(maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i16mf2_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
vint16mf2_t test_vwsll_vx_i16mf2_tu(vint16mf2_t maskedoff, vint8mf4_t op1, int8_t op2, size_t vl) {
return __riscv_vwsll_vx_tu(maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i16m1_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
vint16m1_t test_vwsll_vv_i16m1_tu(vint16m1_t maskedoff, vint8mf2_t op1, vint8mf2_t op2, size_t vl) {
return __riscv_vwsll_vv_tu(maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i16m1_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
vint16m1_t test_vwsll_vx_i16m1_tu(vint16m1_t maskedoff, vint8mf2_t op1, int8_t op2, size_t vl) {
return __riscv_vwsll_vx_tu(maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i16m2_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
vint16m2_t test_vwsll_vv_i16m2_tu(vint16m2_t maskedoff, vint8m1_t op1, vint8m1_t op2, size_t vl) {
return __riscv_vwsll_vv_tu(maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i16m2_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
vint16m2_t test_vwsll_vx_i16m2_tu(vint16m2_t maskedoff, vint8m1_t op1, int8_t op2, size_t vl) {
return __riscv_vwsll_vx_tu(maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i16m4_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwsll.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
vint16m4_t test_vwsll_vv_i16m4_tu(vint16m4_t maskedoff, vint8m2_t op1, vint8m2_t op2, size_t vl) {
return __riscv_vwsll_vv_tu(maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i16m4_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwsll.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
vint16m4_t test_vwsll_vx_i16m4_tu(vint16m4_t maskedoff, vint8m2_t op1, int8_t op2, size_t vl) {
return __riscv_vwsll_vx_tu(maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i16m8_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwsll.nxv32i16.nxv32i8.nxv32i8.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
vint16m8_t test_vwsll_vv_i16m8_tu(vint16m8_t maskedoff, vint8m4_t op1, vint8m4_t op2, size_t vl) {
return __riscv_vwsll_vv_tu(maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i16m8_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwsll.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
vint16m8_t test_vwsll_vx_i16m8_tu(vint16m8_t maskedoff, vint8m4_t op1, int8_t op2, size_t vl) {
return __riscv_vwsll_vx_tu(maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i32mf2_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwsll.nxv1i32.nxv1i16.nxv1i16.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
vint32mf2_t test_vwsll_vv_i32mf2_tu(vint32mf2_t maskedoff, vint16mf4_t op1, vint16mf4_t op2, size_t vl) {
return __riscv_vwsll_vv_tu(maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i32mf2_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwsll.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
vint32mf2_t test_vwsll_vx_i32mf2_tu(vint32mf2_t maskedoff, vint16mf4_t op1, int16_t op2, size_t vl) {
return __riscv_vwsll_vx_tu(maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i32m1_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwsll.nxv2i32.nxv2i16.nxv2i16.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
vint32m1_t test_vwsll_vv_i32m1_tu(vint32m1_t maskedoff, vint16mf2_t op1, vint16mf2_t op2, size_t vl) {
return __riscv_vwsll_vv_tu(maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i32m1_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwsll.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
vint32m1_t test_vwsll_vx_i32m1_tu(vint32m1_t maskedoff, vint16mf2_t op1, int16_t op2, size_t vl) {
return __riscv_vwsll_vx_tu(maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i32m2_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwsll.nxv4i32.nxv4i16.nxv4i16.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
vint32m2_t test_vwsll_vv_i32m2_tu(vint32m2_t maskedoff, vint16m1_t op1, vint16m1_t op2, size_t vl) {
return __riscv_vwsll_vv_tu(maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i32m2_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwsll.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
vint32m2_t test_vwsll_vx_i32m2_tu(vint32m2_t maskedoff, vint16m1_t op1, int16_t op2, size_t vl) {
return __riscv_vwsll_vx_tu(maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i32m4_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwsll.nxv8i32.nxv8i16.nxv8i16.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
vint32m4_t test_vwsll_vv_i32m4_tu(vint32m4_t maskedoff, vint16m2_t op1, vint16m2_t op2, size_t vl) {
return __riscv_vwsll_vv_tu(maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i32m4_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwsll.nxv8i32.nxv8i16.i16.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
vint32m4_t test_vwsll_vx_i32m4_tu(vint32m4_t maskedoff, vint16m2_t op1, int16_t op2, size_t vl) {
return __riscv_vwsll_vx_tu(maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i32m8_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwsll.nxv16i32.nxv16i16.nxv16i16.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
vint32m8_t test_vwsll_vv_i32m8_tu(vint32m8_t maskedoff, vint16m4_t op1, vint16m4_t op2, size_t vl) {
return __riscv_vwsll_vv_tu(maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i32m8_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwsll.nxv16i32.nxv16i16.i16.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
vint32m8_t test_vwsll_vx_i32m8_tu(vint32m8_t maskedoff, vint16m4_t op1, int16_t op2, size_t vl) {
return __riscv_vwsll_vx_tu(maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i64m1_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwsll.nxv1i64.nxv1i32.nxv1i32.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 1 x i64> [[TMP0]]
//
vint64m1_t test_vwsll_vv_i64m1_tu(vint64m1_t maskedoff, vint32mf2_t op1, vint32mf2_t op2, size_t vl) {
return __riscv_vwsll_vv_tu(maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i64m1_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwsll.nxv1i64.nxv1i32.i32.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 1 x i64> [[TMP0]]
//
vint64m1_t test_vwsll_vx_i64m1_tu(vint64m1_t maskedoff, vint32mf2_t op1, int32_t op2, size_t vl) {
return __riscv_vwsll_vx_tu(maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i64m2_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwsll.nxv2i64.nxv2i32.nxv2i32.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
vint64m2_t test_vwsll_vv_i64m2_tu(vint64m2_t maskedoff, vint32m1_t op1, vint32m1_t op2, size_t vl) {
return __riscv_vwsll_vv_tu(maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i64m2_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwsll.nxv2i64.nxv2i32.i32.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
vint64m2_t test_vwsll_vx_i64m2_tu(vint64m2_t maskedoff, vint32m1_t op1, int32_t op2, size_t vl) {
return __riscv_vwsll_vx_tu(maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i64m4_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwsll.nxv4i64.nxv4i32.nxv4i32.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
vint64m4_t test_vwsll_vv_i64m4_tu(vint64m4_t maskedoff, vint32m2_t op1, vint32m2_t op2, size_t vl) {
return __riscv_vwsll_vv_tu(maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i64m4_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwsll.nxv4i64.nxv4i32.i32.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
vint64m4_t test_vwsll_vx_i64m4_tu(vint64m4_t maskedoff, vint32m2_t op1, int32_t op2, size_t vl) {
return __riscv_vwsll_vx_tu(maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i64m8_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwsll.nxv8i64.nxv8i32.nxv8i32.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
vint64m8_t test_vwsll_vv_i64m8_tu(vint64m8_t maskedoff, vint32m4_t op1, vint32m4_t op2, size_t vl) {
return __riscv_vwsll_vv_tu(maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i64m8_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwsll.nxv8i64.nxv8i32.i32.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
vint64m8_t test_vwsll_vx_i64m8_tu(vint64m8_t maskedoff, vint32m4_t op1, int32_t op2, size_t vl) {
return __riscv_vwsll_vx_tu(maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i16mf4_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwsll.mask.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 1 x i16> [[TMP0]]
//
vint16mf4_t test_vwsll_vv_i16mf4_tum(vbool64_t mask, vint16mf4_t maskedoff, vint8mf8_t op1, vint8mf8_t op2, size_t vl) {
return __riscv_vwsll_vv_tum(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i16mf4_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwsll.mask.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 1 x i16> [[TMP0]]
//
vint16mf4_t test_vwsll_vx_i16mf4_tum(vbool64_t mask, vint16mf4_t maskedoff, vint8mf8_t op1, int8_t op2, size_t vl) {
return __riscv_vwsll_vx_tum(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i16mf2_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwsll.mask.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
vint16mf2_t test_vwsll_vv_i16mf2_tum(vbool32_t mask, vint16mf2_t maskedoff, vint8mf4_t op1, vint8mf4_t op2, size_t vl) {
return __riscv_vwsll_vv_tum(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i16mf2_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwsll.mask.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
vint16mf2_t test_vwsll_vx_i16mf2_tum(vbool32_t mask, vint16mf2_t maskedoff, vint8mf4_t op1, int8_t op2, size_t vl) {
return __riscv_vwsll_vx_tum(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i16m1_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwsll.mask.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
vint16m1_t test_vwsll_vv_i16m1_tum(vbool16_t mask, vint16m1_t maskedoff, vint8mf2_t op1, vint8mf2_t op2, size_t vl) {
return __riscv_vwsll_vv_tum(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i16m1_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwsll.mask.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
vint16m1_t test_vwsll_vx_i16m1_tum(vbool16_t mask, vint16m1_t maskedoff, vint8mf2_t op1, int8_t op2, size_t vl) {
return __riscv_vwsll_vx_tum(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i16m2_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwsll.mask.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
vint16m2_t test_vwsll_vv_i16m2_tum(vbool8_t mask, vint16m2_t maskedoff, vint8m1_t op1, vint8m1_t op2, size_t vl) {
return __riscv_vwsll_vv_tum(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i16m2_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwsll.mask.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
vint16m2_t test_vwsll_vx_i16m2_tum(vbool8_t mask, vint16m2_t maskedoff, vint8m1_t op1, int8_t op2, size_t vl) {
return __riscv_vwsll_vx_tum(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i16m4_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwsll.mask.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
vint16m4_t test_vwsll_vv_i16m4_tum(vbool4_t mask, vint16m4_t maskedoff, vint8m2_t op1, vint8m2_t op2, size_t vl) {
return __riscv_vwsll_vv_tum(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i16m4_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwsll.mask.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
vint16m4_t test_vwsll_vx_i16m4_tum(vbool4_t mask, vint16m4_t maskedoff, vint8m2_t op1, int8_t op2, size_t vl) {
return __riscv_vwsll_vx_tum(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i16m8_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwsll.mask.nxv32i16.nxv32i8.nxv32i8.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
vint16m8_t test_vwsll_vv_i16m8_tum(vbool2_t mask, vint16m8_t maskedoff, vint8m4_t op1, vint8m4_t op2, size_t vl) {
return __riscv_vwsll_vv_tum(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i16m8_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwsll.mask.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
vint16m8_t test_vwsll_vx_i16m8_tum(vbool2_t mask, vint16m8_t maskedoff, vint8m4_t op1, int8_t op2, size_t vl) {
return __riscv_vwsll_vx_tum(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i32mf2_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwsll.mask.nxv1i32.nxv1i16.nxv1i16.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
vint32mf2_t test_vwsll_vv_i32mf2_tum(vbool64_t mask, vint32mf2_t maskedoff, vint16mf4_t op1, vint16mf4_t op2, size_t vl) {
return __riscv_vwsll_vv_tum(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i32mf2_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwsll.mask.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
vint32mf2_t test_vwsll_vx_i32mf2_tum(vbool64_t mask, vint32mf2_t maskedoff, vint16mf4_t op1, int16_t op2, size_t vl) {
return __riscv_vwsll_vx_tum(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i32m1_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwsll.mask.nxv2i32.nxv2i16.nxv2i16.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
vint32m1_t test_vwsll_vv_i32m1_tum(vbool32_t mask, vint32m1_t maskedoff, vint16mf2_t op1, vint16mf2_t op2, size_t vl) {
return __riscv_vwsll_vv_tum(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i32m1_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwsll.mask.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
vint32m1_t test_vwsll_vx_i32m1_tum(vbool32_t mask, vint32m1_t maskedoff, vint16mf2_t op1, int16_t op2, size_t vl) {
return __riscv_vwsll_vx_tum(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i32m2_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwsll.mask.nxv4i32.nxv4i16.nxv4i16.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
vint32m2_t test_vwsll_vv_i32m2_tum(vbool16_t mask, vint32m2_t maskedoff, vint16m1_t op1, vint16m1_t op2, size_t vl) {
return __riscv_vwsll_vv_tum(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i32m2_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwsll.mask.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
vint32m2_t test_vwsll_vx_i32m2_tum(vbool16_t mask, vint32m2_t maskedoff, vint16m1_t op1, int16_t op2, size_t vl) {
return __riscv_vwsll_vx_tum(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i32m4_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwsll.mask.nxv8i32.nxv8i16.nxv8i16.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
vint32m4_t test_vwsll_vv_i32m4_tum(vbool8_t mask, vint32m4_t maskedoff, vint16m2_t op1, vint16m2_t op2, size_t vl) {
return __riscv_vwsll_vv_tum(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i32m4_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwsll.mask.nxv8i32.nxv8i16.i16.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
vint32m4_t test_vwsll_vx_i32m4_tum(vbool8_t mask, vint32m4_t maskedoff, vint16m2_t op1, int16_t op2, size_t vl) {
return __riscv_vwsll_vx_tum(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i32m8_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwsll.mask.nxv16i32.nxv16i16.nxv16i16.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
vint32m8_t test_vwsll_vv_i32m8_tum(vbool4_t mask, vint32m8_t maskedoff, vint16m4_t op1, vint16m4_t op2, size_t vl) {
return __riscv_vwsll_vv_tum(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i32m8_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwsll.mask.nxv16i32.nxv16i16.i16.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
vint32m8_t test_vwsll_vx_i32m8_tum(vbool4_t mask, vint32m8_t maskedoff, vint16m4_t op1, int16_t op2, size_t vl) {
return __riscv_vwsll_vx_tum(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i64m1_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwsll.mask.nxv1i64.nxv1i32.nxv1i32.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 1 x i64> [[TMP0]]
//
vint64m1_t test_vwsll_vv_i64m1_tum(vbool64_t mask, vint64m1_t maskedoff, vint32mf2_t op1, vint32mf2_t op2, size_t vl) {
return __riscv_vwsll_vv_tum(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i64m1_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwsll.mask.nxv1i64.nxv1i32.i32.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 1 x i64> [[TMP0]]
//
vint64m1_t test_vwsll_vx_i64m1_tum(vbool64_t mask, vint64m1_t maskedoff, vint32mf2_t op1, int32_t op2, size_t vl) {
return __riscv_vwsll_vx_tum(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i64m2_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwsll.mask.nxv2i64.nxv2i32.nxv2i32.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
vint64m2_t test_vwsll_vv_i64m2_tum(vbool32_t mask, vint64m2_t maskedoff, vint32m1_t op1, vint32m1_t op2, size_t vl) {
return __riscv_vwsll_vv_tum(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i64m2_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwsll.mask.nxv2i64.nxv2i32.i32.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
vint64m2_t test_vwsll_vx_i64m2_tum(vbool32_t mask, vint64m2_t maskedoff, vint32m1_t op1, int32_t op2, size_t vl) {
return __riscv_vwsll_vx_tum(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i64m4_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwsll.mask.nxv4i64.nxv4i32.nxv4i32.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
vint64m4_t test_vwsll_vv_i64m4_tum(vbool16_t mask, vint64m4_t maskedoff, vint32m2_t op1, vint32m2_t op2, size_t vl) {
return __riscv_vwsll_vv_tum(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i64m4_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwsll.mask.nxv4i64.nxv4i32.i32.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
vint64m4_t test_vwsll_vx_i64m4_tum(vbool16_t mask, vint64m4_t maskedoff, vint32m2_t op1, int32_t op2, size_t vl) {
return __riscv_vwsll_vx_tum(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i64m8_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwsll.mask.nxv8i64.nxv8i32.nxv8i32.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
vint64m8_t test_vwsll_vv_i64m8_tum(vbool8_t mask, vint64m8_t maskedoff, vint32m4_t op1, vint32m4_t op2, size_t vl) {
return __riscv_vwsll_vv_tum(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i64m8_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwsll.mask.nxv8i64.nxv8i32.i32.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
vint64m8_t test_vwsll_vx_i64m8_tum(vbool8_t mask, vint64m8_t maskedoff, vint32m4_t op1, int32_t op2, size_t vl) {
return __riscv_vwsll_vx_tum(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i16mf4_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwsll.mask.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 1 x i16> [[TMP0]]
//
vint16mf4_t test_vwsll_vv_i16mf4_tumu(vbool64_t mask, vint16mf4_t maskedoff, vint8mf8_t op1, vint8mf8_t op2, size_t vl) {
return __riscv_vwsll_vv_tumu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i16mf4_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwsll.mask.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 1 x i16> [[TMP0]]
//
vint16mf4_t test_vwsll_vx_i16mf4_tumu(vbool64_t mask, vint16mf4_t maskedoff, vint8mf8_t op1, int8_t op2, size_t vl) {
return __riscv_vwsll_vx_tumu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i16mf2_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwsll.mask.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
vint16mf2_t test_vwsll_vv_i16mf2_tumu(vbool32_t mask, vint16mf2_t maskedoff, vint8mf4_t op1, vint8mf4_t op2, size_t vl) {
return __riscv_vwsll_vv_tumu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i16mf2_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwsll.mask.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
vint16mf2_t test_vwsll_vx_i16mf2_tumu(vbool32_t mask, vint16mf2_t maskedoff, vint8mf4_t op1, int8_t op2, size_t vl) {
return __riscv_vwsll_vx_tumu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i16m1_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwsll.mask.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
vint16m1_t test_vwsll_vv_i16m1_tumu(vbool16_t mask, vint16m1_t maskedoff, vint8mf2_t op1, vint8mf2_t op2, size_t vl) {
return __riscv_vwsll_vv_tumu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i16m1_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwsll.mask.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
vint16m1_t test_vwsll_vx_i16m1_tumu(vbool16_t mask, vint16m1_t maskedoff, vint8mf2_t op1, int8_t op2, size_t vl) {
return __riscv_vwsll_vx_tumu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i16m2_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwsll.mask.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
vint16m2_t test_vwsll_vv_i16m2_tumu(vbool8_t mask, vint16m2_t maskedoff, vint8m1_t op1, vint8m1_t op2, size_t vl) {
return __riscv_vwsll_vv_tumu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i16m2_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwsll.mask.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
vint16m2_t test_vwsll_vx_i16m2_tumu(vbool8_t mask, vint16m2_t maskedoff, vint8m1_t op1, int8_t op2, size_t vl) {
return __riscv_vwsll_vx_tumu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i16m4_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwsll.mask.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
vint16m4_t test_vwsll_vv_i16m4_tumu(vbool4_t mask, vint16m4_t maskedoff, vint8m2_t op1, vint8m2_t op2, size_t vl) {
return __riscv_vwsll_vv_tumu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i16m4_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwsll.mask.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
vint16m4_t test_vwsll_vx_i16m4_tumu(vbool4_t mask, vint16m4_t maskedoff, vint8m2_t op1, int8_t op2, size_t vl) {
return __riscv_vwsll_vx_tumu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i16m8_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwsll.mask.nxv32i16.nxv32i8.nxv32i8.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
vint16m8_t test_vwsll_vv_i16m8_tumu(vbool2_t mask, vint16m8_t maskedoff, vint8m4_t op1, vint8m4_t op2, size_t vl) {
return __riscv_vwsll_vv_tumu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i16m8_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwsll.mask.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
vint16m8_t test_vwsll_vx_i16m8_tumu(vbool2_t mask, vint16m8_t maskedoff, vint8m4_t op1, int8_t op2, size_t vl) {
return __riscv_vwsll_vx_tumu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i32mf2_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwsll.mask.nxv1i32.nxv1i16.nxv1i16.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
vint32mf2_t test_vwsll_vv_i32mf2_tumu(vbool64_t mask, vint32mf2_t maskedoff, vint16mf4_t op1, vint16mf4_t op2, size_t vl) {
return __riscv_vwsll_vv_tumu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i32mf2_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwsll.mask.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
vint32mf2_t test_vwsll_vx_i32mf2_tumu(vbool64_t mask, vint32mf2_t maskedoff, vint16mf4_t op1, int16_t op2, size_t vl) {
return __riscv_vwsll_vx_tumu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i32m1_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwsll.mask.nxv2i32.nxv2i16.nxv2i16.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
vint32m1_t test_vwsll_vv_i32m1_tumu(vbool32_t mask, vint32m1_t maskedoff, vint16mf2_t op1, vint16mf2_t op2, size_t vl) {
return __riscv_vwsll_vv_tumu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i32m1_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwsll.mask.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
vint32m1_t test_vwsll_vx_i32m1_tumu(vbool32_t mask, vint32m1_t maskedoff, vint16mf2_t op1, int16_t op2, size_t vl) {
return __riscv_vwsll_vx_tumu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i32m2_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwsll.mask.nxv4i32.nxv4i16.nxv4i16.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
vint32m2_t test_vwsll_vv_i32m2_tumu(vbool16_t mask, vint32m2_t maskedoff, vint16m1_t op1, vint16m1_t op2, size_t vl) {
return __riscv_vwsll_vv_tumu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i32m2_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwsll.mask.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
vint32m2_t test_vwsll_vx_i32m2_tumu(vbool16_t mask, vint32m2_t maskedoff, vint16m1_t op1, int16_t op2, size_t vl) {
return __riscv_vwsll_vx_tumu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i32m4_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwsll.mask.nxv8i32.nxv8i16.nxv8i16.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
vint32m4_t test_vwsll_vv_i32m4_tumu(vbool8_t mask, vint32m4_t maskedoff, vint16m2_t op1, vint16m2_t op2, size_t vl) {
return __riscv_vwsll_vv_tumu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i32m4_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwsll.mask.nxv8i32.nxv8i16.i16.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
vint32m4_t test_vwsll_vx_i32m4_tumu(vbool8_t mask, vint32m4_t maskedoff, vint16m2_t op1, int16_t op2, size_t vl) {
return __riscv_vwsll_vx_tumu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i32m8_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwsll.mask.nxv16i32.nxv16i16.nxv16i16.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
vint32m8_t test_vwsll_vv_i32m8_tumu(vbool4_t mask, vint32m8_t maskedoff, vint16m4_t op1, vint16m4_t op2, size_t vl) {
return __riscv_vwsll_vv_tumu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i32m8_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwsll.mask.nxv16i32.nxv16i16.i16.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
vint32m8_t test_vwsll_vx_i32m8_tumu(vbool4_t mask, vint32m8_t maskedoff, vint16m4_t op1, int16_t op2, size_t vl) {
return __riscv_vwsll_vx_tumu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i64m1_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwsll.mask.nxv1i64.nxv1i32.nxv1i32.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 1 x i64> [[TMP0]]
//
vint64m1_t test_vwsll_vv_i64m1_tumu(vbool64_t mask, vint64m1_t maskedoff, vint32mf2_t op1, vint32mf2_t op2, size_t vl) {
return __riscv_vwsll_vv_tumu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i64m1_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwsll.mask.nxv1i64.nxv1i32.i32.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 1 x i64> [[TMP0]]
//
vint64m1_t test_vwsll_vx_i64m1_tumu(vbool64_t mask, vint64m1_t maskedoff, vint32mf2_t op1, int32_t op2, size_t vl) {
return __riscv_vwsll_vx_tumu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i64m2_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwsll.mask.nxv2i64.nxv2i32.nxv2i32.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
vint64m2_t test_vwsll_vv_i64m2_tumu(vbool32_t mask, vint64m2_t maskedoff, vint32m1_t op1, vint32m1_t op2, size_t vl) {
return __riscv_vwsll_vv_tumu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i64m2_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwsll.mask.nxv2i64.nxv2i32.i32.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
vint64m2_t test_vwsll_vx_i64m2_tumu(vbool32_t mask, vint64m2_t maskedoff, vint32m1_t op1, int32_t op2, size_t vl) {
return __riscv_vwsll_vx_tumu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i64m4_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwsll.mask.nxv4i64.nxv4i32.nxv4i32.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
vint64m4_t test_vwsll_vv_i64m4_tumu(vbool16_t mask, vint64m4_t maskedoff, vint32m2_t op1, vint32m2_t op2, size_t vl) {
return __riscv_vwsll_vv_tumu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i64m4_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwsll.mask.nxv4i64.nxv4i32.i32.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
vint64m4_t test_vwsll_vx_i64m4_tumu(vbool16_t mask, vint64m4_t maskedoff, vint32m2_t op1, int32_t op2, size_t vl) {
return __riscv_vwsll_vx_tumu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i64m8_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwsll.mask.nxv8i64.nxv8i32.nxv8i32.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
vint64m8_t test_vwsll_vv_i64m8_tumu(vbool8_t mask, vint64m8_t maskedoff, vint32m4_t op1, vint32m4_t op2, size_t vl) {
return __riscv_vwsll_vv_tumu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i64m8_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwsll.mask.nxv8i64.nxv8i32.i32.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
vint64m8_t test_vwsll_vx_i64m8_tumu(vbool8_t mask, vint64m8_t maskedoff, vint32m4_t op1, int32_t op2, size_t vl) {
return __riscv_vwsll_vx_tumu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i16mf4_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwsll.mask.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 1 x i16> [[TMP0]]
//
vint16mf4_t test_vwsll_vv_i16mf4_mu(vbool64_t mask, vint16mf4_t maskedoff, vint8mf8_t op1, vint8mf8_t op2, size_t vl) {
return __riscv_vwsll_vv_mu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i16mf4_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwsll.mask.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 1 x i16> [[TMP0]]
//
vint16mf4_t test_vwsll_vx_i16mf4_mu(vbool64_t mask, vint16mf4_t maskedoff, vint8mf8_t op1, int8_t op2, size_t vl) {
return __riscv_vwsll_vx_mu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i16mf2_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwsll.mask.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
vint16mf2_t test_vwsll_vv_i16mf2_mu(vbool32_t mask, vint16mf2_t maskedoff, vint8mf4_t op1, vint8mf4_t op2, size_t vl) {
return __riscv_vwsll_vv_mu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i16mf2_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwsll.mask.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
vint16mf2_t test_vwsll_vx_i16mf2_mu(vbool32_t mask, vint16mf2_t maskedoff, vint8mf4_t op1, int8_t op2, size_t vl) {
return __riscv_vwsll_vx_mu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i16m1_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwsll.mask.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
vint16m1_t test_vwsll_vv_i16m1_mu(vbool16_t mask, vint16m1_t maskedoff, vint8mf2_t op1, vint8mf2_t op2, size_t vl) {
return __riscv_vwsll_vv_mu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i16m1_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwsll.mask.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
vint16m1_t test_vwsll_vx_i16m1_mu(vbool16_t mask, vint16m1_t maskedoff, vint8mf2_t op1, int8_t op2, size_t vl) {
return __riscv_vwsll_vx_mu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i16m2_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwsll.mask.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
vint16m2_t test_vwsll_vv_i16m2_mu(vbool8_t mask, vint16m2_t maskedoff, vint8m1_t op1, vint8m1_t op2, size_t vl) {
return __riscv_vwsll_vv_mu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i16m2_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwsll.mask.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
vint16m2_t test_vwsll_vx_i16m2_mu(vbool8_t mask, vint16m2_t maskedoff, vint8m1_t op1, int8_t op2, size_t vl) {
return __riscv_vwsll_vx_mu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i16m4_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwsll.mask.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
vint16m4_t test_vwsll_vv_i16m4_mu(vbool4_t mask, vint16m4_t maskedoff, vint8m2_t op1, vint8m2_t op2, size_t vl) {
return __riscv_vwsll_vv_mu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i16m4_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwsll.mask.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
vint16m4_t test_vwsll_vx_i16m4_mu(vbool4_t mask, vint16m4_t maskedoff, vint8m2_t op1, int8_t op2, size_t vl) {
return __riscv_vwsll_vx_mu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i16m8_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwsll.mask.nxv32i16.nxv32i8.nxv32i8.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
vint16m8_t test_vwsll_vv_i16m8_mu(vbool2_t mask, vint16m8_t maskedoff, vint8m4_t op1, vint8m4_t op2, size_t vl) {
return __riscv_vwsll_vv_mu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i16m8_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwsll.mask.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
vint16m8_t test_vwsll_vx_i16m8_mu(vbool2_t mask, vint16m8_t maskedoff, vint8m4_t op1, int8_t op2, size_t vl) {
return __riscv_vwsll_vx_mu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i32mf2_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwsll.mask.nxv1i32.nxv1i16.nxv1i16.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
vint32mf2_t test_vwsll_vv_i32mf2_mu(vbool64_t mask, vint32mf2_t maskedoff, vint16mf4_t op1, vint16mf4_t op2, size_t vl) {
return __riscv_vwsll_vv_mu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i32mf2_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwsll.mask.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
vint32mf2_t test_vwsll_vx_i32mf2_mu(vbool64_t mask, vint32mf2_t maskedoff, vint16mf4_t op1, int16_t op2, size_t vl) {
return __riscv_vwsll_vx_mu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i32m1_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwsll.mask.nxv2i32.nxv2i16.nxv2i16.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
vint32m1_t test_vwsll_vv_i32m1_mu(vbool32_t mask, vint32m1_t maskedoff, vint16mf2_t op1, vint16mf2_t op2, size_t vl) {
return __riscv_vwsll_vv_mu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i32m1_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwsll.mask.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
vint32m1_t test_vwsll_vx_i32m1_mu(vbool32_t mask, vint32m1_t maskedoff, vint16mf2_t op1, int16_t op2, size_t vl) {
return __riscv_vwsll_vx_mu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i32m2_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwsll.mask.nxv4i32.nxv4i16.nxv4i16.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
vint32m2_t test_vwsll_vv_i32m2_mu(vbool16_t mask, vint32m2_t maskedoff, vint16m1_t op1, vint16m1_t op2, size_t vl) {
return __riscv_vwsll_vv_mu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i32m2_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwsll.mask.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
vint32m2_t test_vwsll_vx_i32m2_mu(vbool16_t mask, vint32m2_t maskedoff, vint16m1_t op1, int16_t op2, size_t vl) {
return __riscv_vwsll_vx_mu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i32m4_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwsll.mask.nxv8i32.nxv8i16.nxv8i16.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
vint32m4_t test_vwsll_vv_i32m4_mu(vbool8_t mask, vint32m4_t maskedoff, vint16m2_t op1, vint16m2_t op2, size_t vl) {
return __riscv_vwsll_vv_mu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i32m4_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwsll.mask.nxv8i32.nxv8i16.i16.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
vint32m4_t test_vwsll_vx_i32m4_mu(vbool8_t mask, vint32m4_t maskedoff, vint16m2_t op1, int16_t op2, size_t vl) {
return __riscv_vwsll_vx_mu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i32m8_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwsll.mask.nxv16i32.nxv16i16.nxv16i16.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
vint32m8_t test_vwsll_vv_i32m8_mu(vbool4_t mask, vint32m8_t maskedoff, vint16m4_t op1, vint16m4_t op2, size_t vl) {
return __riscv_vwsll_vv_mu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i32m8_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwsll.mask.nxv16i32.nxv16i16.i16.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
vint32m8_t test_vwsll_vx_i32m8_mu(vbool4_t mask, vint32m8_t maskedoff, vint16m4_t op1, int16_t op2, size_t vl) {
return __riscv_vwsll_vx_mu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i64m1_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwsll.mask.nxv1i64.nxv1i32.nxv1i32.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 1 x i64> [[TMP0]]
//
vint64m1_t test_vwsll_vv_i64m1_mu(vbool64_t mask, vint64m1_t maskedoff, vint32mf2_t op1, vint32mf2_t op2, size_t vl) {
return __riscv_vwsll_vv_mu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i64m1_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwsll.mask.nxv1i64.nxv1i32.i32.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 1 x i64> [[TMP0]]
//
vint64m1_t test_vwsll_vx_i64m1_mu(vbool64_t mask, vint64m1_t maskedoff, vint32mf2_t op1, int32_t op2, size_t vl) {
return __riscv_vwsll_vx_mu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i64m2_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwsll.mask.nxv2i64.nxv2i32.nxv2i32.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
vint64m2_t test_vwsll_vv_i64m2_mu(vbool32_t mask, vint64m2_t maskedoff, vint32m1_t op1, vint32m1_t op2, size_t vl) {
return __riscv_vwsll_vv_mu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i64m2_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwsll.mask.nxv2i64.nxv2i32.i32.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
vint64m2_t test_vwsll_vx_i64m2_mu(vbool32_t mask, vint64m2_t maskedoff, vint32m1_t op1, int32_t op2, size_t vl) {
return __riscv_vwsll_vx_mu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i64m4_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwsll.mask.nxv4i64.nxv4i32.nxv4i32.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
vint64m4_t test_vwsll_vv_i64m4_mu(vbool16_t mask, vint64m4_t maskedoff, vint32m2_t op1, vint32m2_t op2, size_t vl) {
return __riscv_vwsll_vv_mu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i64m4_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwsll.mask.nxv4i64.nxv4i32.i32.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
vint64m4_t test_vwsll_vx_i64m4_mu(vbool16_t mask, vint64m4_t maskedoff, vint32m2_t op1, int32_t op2, size_t vl) {
return __riscv_vwsll_vx_mu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_i64m8_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwsll.mask.nxv8i64.nxv8i32.nxv8i32.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
vint64m8_t test_vwsll_vv_i64m8_mu(vbool8_t mask, vint64m8_t maskedoff, vint32m4_t op1, vint32m4_t op2, size_t vl) {
return __riscv_vwsll_vv_mu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_i64m8_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwsll.mask.nxv8i64.nxv8i32.i32.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
vint64m8_t test_vwsll_vx_i64m8_mu(vbool8_t mask, vint64m8_t maskedoff, vint32m4_t op1, int32_t op2, size_t vl) {
return __riscv_vwsll_vx_mu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u16mf4_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 1 x i16> [[TMP0]]
//
vuint16mf4_t test_vwsll_vv_u16mf4_tu(vuint16mf4_t maskedoff, vuint8mf8_t op1, vuint8mf8_t op2, size_t vl) {
return __riscv_vwsll_vv_tu(maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u16mf4_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 1 x i16> [[TMP0]]
//
vuint16mf4_t test_vwsll_vx_u16mf4_tu(vuint16mf4_t maskedoff, vuint8mf8_t op1, uint8_t op2, size_t vl) {
return __riscv_vwsll_vx_tu(maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u16mf2_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
vuint16mf2_t test_vwsll_vv_u16mf2_tu(vuint16mf2_t maskedoff, vuint8mf4_t op1, vuint8mf4_t op2, size_t vl) {
return __riscv_vwsll_vv_tu(maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u16mf2_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
vuint16mf2_t test_vwsll_vx_u16mf2_tu(vuint16mf2_t maskedoff, vuint8mf4_t op1, uint8_t op2, size_t vl) {
return __riscv_vwsll_vx_tu(maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u16m1_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
vuint16m1_t test_vwsll_vv_u16m1_tu(vuint16m1_t maskedoff, vuint8mf2_t op1, vuint8mf2_t op2, size_t vl) {
return __riscv_vwsll_vv_tu(maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u16m1_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
vuint16m1_t test_vwsll_vx_u16m1_tu(vuint16m1_t maskedoff, vuint8mf2_t op1, uint8_t op2, size_t vl) {
return __riscv_vwsll_vx_tu(maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u16m2_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
vuint16m2_t test_vwsll_vv_u16m2_tu(vuint16m2_t maskedoff, vuint8m1_t op1, vuint8m1_t op2, size_t vl) {
return __riscv_vwsll_vv_tu(maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u16m2_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
vuint16m2_t test_vwsll_vx_u16m2_tu(vuint16m2_t maskedoff, vuint8m1_t op1, uint8_t op2, size_t vl) {
return __riscv_vwsll_vx_tu(maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u16m4_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwsll.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
vuint16m4_t test_vwsll_vv_u16m4_tu(vuint16m4_t maskedoff, vuint8m2_t op1, vuint8m2_t op2, size_t vl) {
return __riscv_vwsll_vv_tu(maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u16m4_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwsll.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
vuint16m4_t test_vwsll_vx_u16m4_tu(vuint16m4_t maskedoff, vuint8m2_t op1, uint8_t op2, size_t vl) {
return __riscv_vwsll_vx_tu(maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u16m8_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwsll.nxv32i16.nxv32i8.nxv32i8.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
vuint16m8_t test_vwsll_vv_u16m8_tu(vuint16m8_t maskedoff, vuint8m4_t op1, vuint8m4_t op2, size_t vl) {
return __riscv_vwsll_vv_tu(maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u16m8_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwsll.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
vuint16m8_t test_vwsll_vx_u16m8_tu(vuint16m8_t maskedoff, vuint8m4_t op1, uint8_t op2, size_t vl) {
return __riscv_vwsll_vx_tu(maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u32mf2_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwsll.nxv1i32.nxv1i16.nxv1i16.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
vuint32mf2_t test_vwsll_vv_u32mf2_tu(vuint32mf2_t maskedoff, vuint16mf4_t op1, vuint16mf4_t op2, size_t vl) {
return __riscv_vwsll_vv_tu(maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u32mf2_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwsll.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
vuint32mf2_t test_vwsll_vx_u32mf2_tu(vuint32mf2_t maskedoff, vuint16mf4_t op1, uint16_t op2, size_t vl) {
return __riscv_vwsll_vx_tu(maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u32m1_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwsll.nxv2i32.nxv2i16.nxv2i16.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
vuint32m1_t test_vwsll_vv_u32m1_tu(vuint32m1_t maskedoff, vuint16mf2_t op1, vuint16mf2_t op2, size_t vl) {
return __riscv_vwsll_vv_tu(maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u32m1_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwsll.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
vuint32m1_t test_vwsll_vx_u32m1_tu(vuint32m1_t maskedoff, vuint16mf2_t op1, uint16_t op2, size_t vl) {
return __riscv_vwsll_vx_tu(maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u32m2_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwsll.nxv4i32.nxv4i16.nxv4i16.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
vuint32m2_t test_vwsll_vv_u32m2_tu(vuint32m2_t maskedoff, vuint16m1_t op1, vuint16m1_t op2, size_t vl) {
return __riscv_vwsll_vv_tu(maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u32m2_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwsll.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
vuint32m2_t test_vwsll_vx_u32m2_tu(vuint32m2_t maskedoff, vuint16m1_t op1, uint16_t op2, size_t vl) {
return __riscv_vwsll_vx_tu(maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u32m4_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwsll.nxv8i32.nxv8i16.nxv8i16.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
vuint32m4_t test_vwsll_vv_u32m4_tu(vuint32m4_t maskedoff, vuint16m2_t op1, vuint16m2_t op2, size_t vl) {
return __riscv_vwsll_vv_tu(maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u32m4_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwsll.nxv8i32.nxv8i16.i16.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
vuint32m4_t test_vwsll_vx_u32m4_tu(vuint32m4_t maskedoff, vuint16m2_t op1, uint16_t op2, size_t vl) {
return __riscv_vwsll_vx_tu(maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u32m8_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwsll.nxv16i32.nxv16i16.nxv16i16.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
vuint32m8_t test_vwsll_vv_u32m8_tu(vuint32m8_t maskedoff, vuint16m4_t op1, vuint16m4_t op2, size_t vl) {
return __riscv_vwsll_vv_tu(maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u32m8_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwsll.nxv16i32.nxv16i16.i16.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
vuint32m8_t test_vwsll_vx_u32m8_tu(vuint32m8_t maskedoff, vuint16m4_t op1, uint16_t op2, size_t vl) {
return __riscv_vwsll_vx_tu(maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u64m1_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwsll.nxv1i64.nxv1i32.nxv1i32.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 1 x i64> [[TMP0]]
//
vuint64m1_t test_vwsll_vv_u64m1_tu(vuint64m1_t maskedoff, vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) {
return __riscv_vwsll_vv_tu(maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u64m1_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwsll.nxv1i64.nxv1i32.i32.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 1 x i64> [[TMP0]]
//
vuint64m1_t test_vwsll_vx_u64m1_tu(vuint64m1_t maskedoff, vuint32mf2_t op1, uint32_t op2, size_t vl) {
return __riscv_vwsll_vx_tu(maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u64m2_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwsll.nxv2i64.nxv2i32.nxv2i32.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
vuint64m2_t test_vwsll_vv_u64m2_tu(vuint64m2_t maskedoff, vuint32m1_t op1, vuint32m1_t op2, size_t vl) {
return __riscv_vwsll_vv_tu(maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u64m2_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwsll.nxv2i64.nxv2i32.i32.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
vuint64m2_t test_vwsll_vx_u64m2_tu(vuint64m2_t maskedoff, vuint32m1_t op1, uint32_t op2, size_t vl) {
return __riscv_vwsll_vx_tu(maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u64m4_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwsll.nxv4i64.nxv4i32.nxv4i32.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
vuint64m4_t test_vwsll_vv_u64m4_tu(vuint64m4_t maskedoff, vuint32m2_t op1, vuint32m2_t op2, size_t vl) {
return __riscv_vwsll_vv_tu(maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u64m4_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwsll.nxv4i64.nxv4i32.i32.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
vuint64m4_t test_vwsll_vx_u64m4_tu(vuint64m4_t maskedoff, vuint32m2_t op1, uint32_t op2, size_t vl) {
return __riscv_vwsll_vx_tu(maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u64m8_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwsll.nxv8i64.nxv8i32.nxv8i32.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
vuint64m8_t test_vwsll_vv_u64m8_tu(vuint64m8_t maskedoff, vuint32m4_t op1, vuint32m4_t op2, size_t vl) {
return __riscv_vwsll_vv_tu(maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u64m8_tu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwsll.nxv8i64.nxv8i32.i32.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
vuint64m8_t test_vwsll_vx_u64m8_tu(vuint64m8_t maskedoff, vuint32m4_t op1, uint32_t op2, size_t vl) {
return __riscv_vwsll_vx_tu(maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u16mf4_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwsll.mask.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 1 x i16> [[TMP0]]
//
vuint16mf4_t test_vwsll_vv_u16mf4_tum(vbool64_t mask, vuint16mf4_t maskedoff, vuint8mf8_t op1, vuint8mf8_t op2, size_t vl) {
return __riscv_vwsll_vv_tum(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u16mf4_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwsll.mask.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 1 x i16> [[TMP0]]
//
vuint16mf4_t test_vwsll_vx_u16mf4_tum(vbool64_t mask, vuint16mf4_t maskedoff, vuint8mf8_t op1, uint8_t op2, size_t vl) {
return __riscv_vwsll_vx_tum(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u16mf2_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwsll.mask.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
vuint16mf2_t test_vwsll_vv_u16mf2_tum(vbool32_t mask, vuint16mf2_t maskedoff, vuint8mf4_t op1, vuint8mf4_t op2, size_t vl) {
return __riscv_vwsll_vv_tum(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u16mf2_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwsll.mask.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
vuint16mf2_t test_vwsll_vx_u16mf2_tum(vbool32_t mask, vuint16mf2_t maskedoff, vuint8mf4_t op1, uint8_t op2, size_t vl) {
return __riscv_vwsll_vx_tum(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u16m1_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwsll.mask.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
vuint16m1_t test_vwsll_vv_u16m1_tum(vbool16_t mask, vuint16m1_t maskedoff, vuint8mf2_t op1, vuint8mf2_t op2, size_t vl) {
return __riscv_vwsll_vv_tum(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u16m1_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwsll.mask.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
vuint16m1_t test_vwsll_vx_u16m1_tum(vbool16_t mask, vuint16m1_t maskedoff, vuint8mf2_t op1, uint8_t op2, size_t vl) {
return __riscv_vwsll_vx_tum(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u16m2_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwsll.mask.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
vuint16m2_t test_vwsll_vv_u16m2_tum(vbool8_t mask, vuint16m2_t maskedoff, vuint8m1_t op1, vuint8m1_t op2, size_t vl) {
return __riscv_vwsll_vv_tum(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u16m2_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwsll.mask.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
vuint16m2_t test_vwsll_vx_u16m2_tum(vbool8_t mask, vuint16m2_t maskedoff, vuint8m1_t op1, uint8_t op2, size_t vl) {
return __riscv_vwsll_vx_tum(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u16m4_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwsll.mask.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
vuint16m4_t test_vwsll_vv_u16m4_tum(vbool4_t mask, vuint16m4_t maskedoff, vuint8m2_t op1, vuint8m2_t op2, size_t vl) {
return __riscv_vwsll_vv_tum(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u16m4_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwsll.mask.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
vuint16m4_t test_vwsll_vx_u16m4_tum(vbool4_t mask, vuint16m4_t maskedoff, vuint8m2_t op1, uint8_t op2, size_t vl) {
return __riscv_vwsll_vx_tum(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u16m8_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwsll.mask.nxv32i16.nxv32i8.nxv32i8.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
vuint16m8_t test_vwsll_vv_u16m8_tum(vbool2_t mask, vuint16m8_t maskedoff, vuint8m4_t op1, vuint8m4_t op2, size_t vl) {
return __riscv_vwsll_vv_tum(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u16m8_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwsll.mask.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
vuint16m8_t test_vwsll_vx_u16m8_tum(vbool2_t mask, vuint16m8_t maskedoff, vuint8m4_t op1, uint8_t op2, size_t vl) {
return __riscv_vwsll_vx_tum(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u32mf2_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwsll.mask.nxv1i32.nxv1i16.nxv1i16.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
vuint32mf2_t test_vwsll_vv_u32mf2_tum(vbool64_t mask, vuint32mf2_t maskedoff, vuint16mf4_t op1, vuint16mf4_t op2, size_t vl) {
return __riscv_vwsll_vv_tum(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u32mf2_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwsll.mask.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
vuint32mf2_t test_vwsll_vx_u32mf2_tum(vbool64_t mask, vuint32mf2_t maskedoff, vuint16mf4_t op1, uint16_t op2, size_t vl) {
return __riscv_vwsll_vx_tum(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u32m1_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwsll.mask.nxv2i32.nxv2i16.nxv2i16.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
vuint32m1_t test_vwsll_vv_u32m1_tum(vbool32_t mask, vuint32m1_t maskedoff, vuint16mf2_t op1, vuint16mf2_t op2, size_t vl) {
return __riscv_vwsll_vv_tum(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u32m1_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwsll.mask.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
vuint32m1_t test_vwsll_vx_u32m1_tum(vbool32_t mask, vuint32m1_t maskedoff, vuint16mf2_t op1, uint16_t op2, size_t vl) {
return __riscv_vwsll_vx_tum(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u32m2_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwsll.mask.nxv4i32.nxv4i16.nxv4i16.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
vuint32m2_t test_vwsll_vv_u32m2_tum(vbool16_t mask, vuint32m2_t maskedoff, vuint16m1_t op1, vuint16m1_t op2, size_t vl) {
return __riscv_vwsll_vv_tum(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u32m2_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwsll.mask.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
vuint32m2_t test_vwsll_vx_u32m2_tum(vbool16_t mask, vuint32m2_t maskedoff, vuint16m1_t op1, uint16_t op2, size_t vl) {
return __riscv_vwsll_vx_tum(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u32m4_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwsll.mask.nxv8i32.nxv8i16.nxv8i16.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
vuint32m4_t test_vwsll_vv_u32m4_tum(vbool8_t mask, vuint32m4_t maskedoff, vuint16m2_t op1, vuint16m2_t op2, size_t vl) {
return __riscv_vwsll_vv_tum(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u32m4_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwsll.mask.nxv8i32.nxv8i16.i16.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
vuint32m4_t test_vwsll_vx_u32m4_tum(vbool8_t mask, vuint32m4_t maskedoff, vuint16m2_t op1, uint16_t op2, size_t vl) {
return __riscv_vwsll_vx_tum(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u32m8_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwsll.mask.nxv16i32.nxv16i16.nxv16i16.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
vuint32m8_t test_vwsll_vv_u32m8_tum(vbool4_t mask, vuint32m8_t maskedoff, vuint16m4_t op1, vuint16m4_t op2, size_t vl) {
return __riscv_vwsll_vv_tum(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u32m8_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwsll.mask.nxv16i32.nxv16i16.i16.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
vuint32m8_t test_vwsll_vx_u32m8_tum(vbool4_t mask, vuint32m8_t maskedoff, vuint16m4_t op1, uint16_t op2, size_t vl) {
return __riscv_vwsll_vx_tum(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u64m1_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwsll.mask.nxv1i64.nxv1i32.nxv1i32.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 1 x i64> [[TMP0]]
//
vuint64m1_t test_vwsll_vv_u64m1_tum(vbool64_t mask, vuint64m1_t maskedoff, vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) {
return __riscv_vwsll_vv_tum(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u64m1_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwsll.mask.nxv1i64.nxv1i32.i32.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 1 x i64> [[TMP0]]
//
vuint64m1_t test_vwsll_vx_u64m1_tum(vbool64_t mask, vuint64m1_t maskedoff, vuint32mf2_t op1, uint32_t op2, size_t vl) {
return __riscv_vwsll_vx_tum(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u64m2_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwsll.mask.nxv2i64.nxv2i32.nxv2i32.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
vuint64m2_t test_vwsll_vv_u64m2_tum(vbool32_t mask, vuint64m2_t maskedoff, vuint32m1_t op1, vuint32m1_t op2, size_t vl) {
return __riscv_vwsll_vv_tum(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u64m2_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwsll.mask.nxv2i64.nxv2i32.i32.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
vuint64m2_t test_vwsll_vx_u64m2_tum(vbool32_t mask, vuint64m2_t maskedoff, vuint32m1_t op1, uint32_t op2, size_t vl) {
return __riscv_vwsll_vx_tum(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u64m4_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwsll.mask.nxv4i64.nxv4i32.nxv4i32.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
vuint64m4_t test_vwsll_vv_u64m4_tum(vbool16_t mask, vuint64m4_t maskedoff, vuint32m2_t op1, vuint32m2_t op2, size_t vl) {
return __riscv_vwsll_vv_tum(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u64m4_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwsll.mask.nxv4i64.nxv4i32.i32.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
vuint64m4_t test_vwsll_vx_u64m4_tum(vbool16_t mask, vuint64m4_t maskedoff, vuint32m2_t op1, uint32_t op2, size_t vl) {
return __riscv_vwsll_vx_tum(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u64m8_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwsll.mask.nxv8i64.nxv8i32.nxv8i32.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
vuint64m8_t test_vwsll_vv_u64m8_tum(vbool8_t mask, vuint64m8_t maskedoff, vuint32m4_t op1, vuint32m4_t op2, size_t vl) {
return __riscv_vwsll_vv_tum(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u64m8_tum(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwsll.mask.nxv8i64.nxv8i32.i32.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
// CHECK-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
vuint64m8_t test_vwsll_vx_u64m8_tum(vbool8_t mask, vuint64m8_t maskedoff, vuint32m4_t op1, uint32_t op2, size_t vl) {
return __riscv_vwsll_vx_tum(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u16mf4_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwsll.mask.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 1 x i16> [[TMP0]]
//
vuint16mf4_t test_vwsll_vv_u16mf4_tumu(vbool64_t mask, vuint16mf4_t maskedoff, vuint8mf8_t op1, vuint8mf8_t op2, size_t vl) {
return __riscv_vwsll_vv_tumu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u16mf4_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwsll.mask.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 1 x i16> [[TMP0]]
//
vuint16mf4_t test_vwsll_vx_u16mf4_tumu(vbool64_t mask, vuint16mf4_t maskedoff, vuint8mf8_t op1, uint8_t op2, size_t vl) {
return __riscv_vwsll_vx_tumu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u16mf2_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwsll.mask.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
vuint16mf2_t test_vwsll_vv_u16mf2_tumu(vbool32_t mask, vuint16mf2_t maskedoff, vuint8mf4_t op1, vuint8mf4_t op2, size_t vl) {
return __riscv_vwsll_vv_tumu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u16mf2_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwsll.mask.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
vuint16mf2_t test_vwsll_vx_u16mf2_tumu(vbool32_t mask, vuint16mf2_t maskedoff, vuint8mf4_t op1, uint8_t op2, size_t vl) {
return __riscv_vwsll_vx_tumu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u16m1_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwsll.mask.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
vuint16m1_t test_vwsll_vv_u16m1_tumu(vbool16_t mask, vuint16m1_t maskedoff, vuint8mf2_t op1, vuint8mf2_t op2, size_t vl) {
return __riscv_vwsll_vv_tumu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u16m1_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwsll.mask.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
vuint16m1_t test_vwsll_vx_u16m1_tumu(vbool16_t mask, vuint16m1_t maskedoff, vuint8mf2_t op1, uint8_t op2, size_t vl) {
return __riscv_vwsll_vx_tumu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u16m2_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwsll.mask.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
vuint16m2_t test_vwsll_vv_u16m2_tumu(vbool8_t mask, vuint16m2_t maskedoff, vuint8m1_t op1, vuint8m1_t op2, size_t vl) {
return __riscv_vwsll_vv_tumu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u16m2_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwsll.mask.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
vuint16m2_t test_vwsll_vx_u16m2_tumu(vbool8_t mask, vuint16m2_t maskedoff, vuint8m1_t op1, uint8_t op2, size_t vl) {
return __riscv_vwsll_vx_tumu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u16m4_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwsll.mask.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
vuint16m4_t test_vwsll_vv_u16m4_tumu(vbool4_t mask, vuint16m4_t maskedoff, vuint8m2_t op1, vuint8m2_t op2, size_t vl) {
return __riscv_vwsll_vv_tumu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u16m4_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwsll.mask.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
vuint16m4_t test_vwsll_vx_u16m4_tumu(vbool4_t mask, vuint16m4_t maskedoff, vuint8m2_t op1, uint8_t op2, size_t vl) {
return __riscv_vwsll_vx_tumu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u16m8_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwsll.mask.nxv32i16.nxv32i8.nxv32i8.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
vuint16m8_t test_vwsll_vv_u16m8_tumu(vbool2_t mask, vuint16m8_t maskedoff, vuint8m4_t op1, vuint8m4_t op2, size_t vl) {
return __riscv_vwsll_vv_tumu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u16m8_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwsll.mask.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
vuint16m8_t test_vwsll_vx_u16m8_tumu(vbool2_t mask, vuint16m8_t maskedoff, vuint8m4_t op1, uint8_t op2, size_t vl) {
return __riscv_vwsll_vx_tumu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u32mf2_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwsll.mask.nxv1i32.nxv1i16.nxv1i16.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
vuint32mf2_t test_vwsll_vv_u32mf2_tumu(vbool64_t mask, vuint32mf2_t maskedoff, vuint16mf4_t op1, vuint16mf4_t op2, size_t vl) {
return __riscv_vwsll_vv_tumu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u32mf2_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwsll.mask.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
vuint32mf2_t test_vwsll_vx_u32mf2_tumu(vbool64_t mask, vuint32mf2_t maskedoff, vuint16mf4_t op1, uint16_t op2, size_t vl) {
return __riscv_vwsll_vx_tumu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u32m1_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwsll.mask.nxv2i32.nxv2i16.nxv2i16.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
vuint32m1_t test_vwsll_vv_u32m1_tumu(vbool32_t mask, vuint32m1_t maskedoff, vuint16mf2_t op1, vuint16mf2_t op2, size_t vl) {
return __riscv_vwsll_vv_tumu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u32m1_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwsll.mask.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
vuint32m1_t test_vwsll_vx_u32m1_tumu(vbool32_t mask, vuint32m1_t maskedoff, vuint16mf2_t op1, uint16_t op2, size_t vl) {
return __riscv_vwsll_vx_tumu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u32m2_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwsll.mask.nxv4i32.nxv4i16.nxv4i16.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
vuint32m2_t test_vwsll_vv_u32m2_tumu(vbool16_t mask, vuint32m2_t maskedoff, vuint16m1_t op1, vuint16m1_t op2, size_t vl) {
return __riscv_vwsll_vv_tumu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u32m2_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwsll.mask.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
vuint32m2_t test_vwsll_vx_u32m2_tumu(vbool16_t mask, vuint32m2_t maskedoff, vuint16m1_t op1, uint16_t op2, size_t vl) {
return __riscv_vwsll_vx_tumu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u32m4_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwsll.mask.nxv8i32.nxv8i16.nxv8i16.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
vuint32m4_t test_vwsll_vv_u32m4_tumu(vbool8_t mask, vuint32m4_t maskedoff, vuint16m2_t op1, vuint16m2_t op2, size_t vl) {
return __riscv_vwsll_vv_tumu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u32m4_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwsll.mask.nxv8i32.nxv8i16.i16.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
vuint32m4_t test_vwsll_vx_u32m4_tumu(vbool8_t mask, vuint32m4_t maskedoff, vuint16m2_t op1, uint16_t op2, size_t vl) {
return __riscv_vwsll_vx_tumu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u32m8_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwsll.mask.nxv16i32.nxv16i16.nxv16i16.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
vuint32m8_t test_vwsll_vv_u32m8_tumu(vbool4_t mask, vuint32m8_t maskedoff, vuint16m4_t op1, vuint16m4_t op2, size_t vl) {
return __riscv_vwsll_vv_tumu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u32m8_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwsll.mask.nxv16i32.nxv16i16.i16.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
vuint32m8_t test_vwsll_vx_u32m8_tumu(vbool4_t mask, vuint32m8_t maskedoff, vuint16m4_t op1, uint16_t op2, size_t vl) {
return __riscv_vwsll_vx_tumu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u64m1_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwsll.mask.nxv1i64.nxv1i32.nxv1i32.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 1 x i64> [[TMP0]]
//
vuint64m1_t test_vwsll_vv_u64m1_tumu(vbool64_t mask, vuint64m1_t maskedoff, vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) {
return __riscv_vwsll_vv_tumu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u64m1_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwsll.mask.nxv1i64.nxv1i32.i32.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 1 x i64> [[TMP0]]
//
vuint64m1_t test_vwsll_vx_u64m1_tumu(vbool64_t mask, vuint64m1_t maskedoff, vuint32mf2_t op1, uint32_t op2, size_t vl) {
return __riscv_vwsll_vx_tumu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u64m2_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwsll.mask.nxv2i64.nxv2i32.nxv2i32.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
vuint64m2_t test_vwsll_vv_u64m2_tumu(vbool32_t mask, vuint64m2_t maskedoff, vuint32m1_t op1, vuint32m1_t op2, size_t vl) {
return __riscv_vwsll_vv_tumu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u64m2_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwsll.mask.nxv2i64.nxv2i32.i32.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
vuint64m2_t test_vwsll_vx_u64m2_tumu(vbool32_t mask, vuint64m2_t maskedoff, vuint32m1_t op1, uint32_t op2, size_t vl) {
return __riscv_vwsll_vx_tumu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u64m4_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwsll.mask.nxv4i64.nxv4i32.nxv4i32.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
vuint64m4_t test_vwsll_vv_u64m4_tumu(vbool16_t mask, vuint64m4_t maskedoff, vuint32m2_t op1, vuint32m2_t op2, size_t vl) {
return __riscv_vwsll_vv_tumu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u64m4_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwsll.mask.nxv4i64.nxv4i32.i32.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
vuint64m4_t test_vwsll_vx_u64m4_tumu(vbool16_t mask, vuint64m4_t maskedoff, vuint32m2_t op1, uint32_t op2, size_t vl) {
return __riscv_vwsll_vx_tumu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u64m8_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwsll.mask.nxv8i64.nxv8i32.nxv8i32.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
vuint64m8_t test_vwsll_vv_u64m8_tumu(vbool8_t mask, vuint64m8_t maskedoff, vuint32m4_t op1, vuint32m4_t op2, size_t vl) {
return __riscv_vwsll_vv_tumu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u64m8_tumu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwsll.mask.nxv8i64.nxv8i32.i32.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
vuint64m8_t test_vwsll_vx_u64m8_tumu(vbool8_t mask, vuint64m8_t maskedoff, vuint32m4_t op1, uint32_t op2, size_t vl) {
return __riscv_vwsll_vx_tumu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u16mf4_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwsll.mask.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 1 x i16> [[TMP0]]
//
vuint16mf4_t test_vwsll_vv_u16mf4_mu(vbool64_t mask, vuint16mf4_t maskedoff, vuint8mf8_t op1, vuint8mf8_t op2, size_t vl) {
return __riscv_vwsll_vv_mu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u16mf4_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwsll.mask.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 1 x i16> [[TMP0]]
//
vuint16mf4_t test_vwsll_vx_u16mf4_mu(vbool64_t mask, vuint16mf4_t maskedoff, vuint8mf8_t op1, uint8_t op2, size_t vl) {
return __riscv_vwsll_vx_mu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u16mf2_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwsll.mask.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
vuint16mf2_t test_vwsll_vv_u16mf2_mu(vbool32_t mask, vuint16mf2_t maskedoff, vuint8mf4_t op1, vuint8mf4_t op2, size_t vl) {
return __riscv_vwsll_vv_mu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u16mf2_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwsll.mask.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
vuint16mf2_t test_vwsll_vx_u16mf2_mu(vbool32_t mask, vuint16mf2_t maskedoff, vuint8mf4_t op1, uint8_t op2, size_t vl) {
return __riscv_vwsll_vx_mu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u16m1_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwsll.mask.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
vuint16m1_t test_vwsll_vv_u16m1_mu(vbool16_t mask, vuint16m1_t maskedoff, vuint8mf2_t op1, vuint8mf2_t op2, size_t vl) {
return __riscv_vwsll_vv_mu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u16m1_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwsll.mask.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
vuint16m1_t test_vwsll_vx_u16m1_mu(vbool16_t mask, vuint16m1_t maskedoff, vuint8mf2_t op1, uint8_t op2, size_t vl) {
return __riscv_vwsll_vx_mu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u16m2_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwsll.mask.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
vuint16m2_t test_vwsll_vv_u16m2_mu(vbool8_t mask, vuint16m2_t maskedoff, vuint8m1_t op1, vuint8m1_t op2, size_t vl) {
return __riscv_vwsll_vv_mu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u16m2_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwsll.mask.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
vuint16m2_t test_vwsll_vx_u16m2_mu(vbool8_t mask, vuint16m2_t maskedoff, vuint8m1_t op1, uint8_t op2, size_t vl) {
return __riscv_vwsll_vx_mu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u16m4_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwsll.mask.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
vuint16m4_t test_vwsll_vv_u16m4_mu(vbool4_t mask, vuint16m4_t maskedoff, vuint8m2_t op1, vuint8m2_t op2, size_t vl) {
return __riscv_vwsll_vv_mu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u16m4_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwsll.mask.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
vuint16m4_t test_vwsll_vx_u16m4_mu(vbool4_t mask, vuint16m4_t maskedoff, vuint8m2_t op1, uint8_t op2, size_t vl) {
return __riscv_vwsll_vx_mu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u16m8_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwsll.mask.nxv32i16.nxv32i8.nxv32i8.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
vuint16m8_t test_vwsll_vv_u16m8_mu(vbool2_t mask, vuint16m8_t maskedoff, vuint8m4_t op1, vuint8m4_t op2, size_t vl) {
return __riscv_vwsll_vv_mu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u16m8_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwsll.mask.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
vuint16m8_t test_vwsll_vx_u16m8_mu(vbool2_t mask, vuint16m8_t maskedoff, vuint8m4_t op1, uint8_t op2, size_t vl) {
return __riscv_vwsll_vx_mu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u32mf2_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwsll.mask.nxv1i32.nxv1i16.nxv1i16.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
vuint32mf2_t test_vwsll_vv_u32mf2_mu(vbool64_t mask, vuint32mf2_t maskedoff, vuint16mf4_t op1, vuint16mf4_t op2, size_t vl) {
return __riscv_vwsll_vv_mu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u32mf2_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwsll.mask.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
vuint32mf2_t test_vwsll_vx_u32mf2_mu(vbool64_t mask, vuint32mf2_t maskedoff, vuint16mf4_t op1, uint16_t op2, size_t vl) {
return __riscv_vwsll_vx_mu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u32m1_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwsll.mask.nxv2i32.nxv2i16.nxv2i16.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
vuint32m1_t test_vwsll_vv_u32m1_mu(vbool32_t mask, vuint32m1_t maskedoff, vuint16mf2_t op1, vuint16mf2_t op2, size_t vl) {
return __riscv_vwsll_vv_mu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u32m1_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwsll.mask.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
vuint32m1_t test_vwsll_vx_u32m1_mu(vbool32_t mask, vuint32m1_t maskedoff, vuint16mf2_t op1, uint16_t op2, size_t vl) {
return __riscv_vwsll_vx_mu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u32m2_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwsll.mask.nxv4i32.nxv4i16.nxv4i16.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
vuint32m2_t test_vwsll_vv_u32m2_mu(vbool16_t mask, vuint32m2_t maskedoff, vuint16m1_t op1, vuint16m1_t op2, size_t vl) {
return __riscv_vwsll_vv_mu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u32m2_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwsll.mask.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
vuint32m2_t test_vwsll_vx_u32m2_mu(vbool16_t mask, vuint32m2_t maskedoff, vuint16m1_t op1, uint16_t op2, size_t vl) {
return __riscv_vwsll_vx_mu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u32m4_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwsll.mask.nxv8i32.nxv8i16.nxv8i16.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
vuint32m4_t test_vwsll_vv_u32m4_mu(vbool8_t mask, vuint32m4_t maskedoff, vuint16m2_t op1, vuint16m2_t op2, size_t vl) {
return __riscv_vwsll_vv_mu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u32m4_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwsll.mask.nxv8i32.nxv8i16.i16.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
vuint32m4_t test_vwsll_vx_u32m4_mu(vbool8_t mask, vuint32m4_t maskedoff, vuint16m2_t op1, uint16_t op2, size_t vl) {
return __riscv_vwsll_vx_mu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u32m8_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwsll.mask.nxv16i32.nxv16i16.nxv16i16.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
vuint32m8_t test_vwsll_vv_u32m8_mu(vbool4_t mask, vuint32m8_t maskedoff, vuint16m4_t op1, vuint16m4_t op2, size_t vl) {
return __riscv_vwsll_vv_mu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u32m8_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwsll.mask.nxv16i32.nxv16i16.i16.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
vuint32m8_t test_vwsll_vx_u32m8_mu(vbool4_t mask, vuint32m8_t maskedoff, vuint16m4_t op1, uint16_t op2, size_t vl) {
return __riscv_vwsll_vx_mu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u64m1_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwsll.mask.nxv1i64.nxv1i32.nxv1i32.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 1 x i64> [[TMP0]]
//
vuint64m1_t test_vwsll_vv_u64m1_mu(vbool64_t mask, vuint64m1_t maskedoff, vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) {
return __riscv_vwsll_vv_mu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u64m1_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwsll.mask.nxv1i64.nxv1i32.i32.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 1 x i64> [[TMP0]]
//
vuint64m1_t test_vwsll_vx_u64m1_mu(vbool64_t mask, vuint64m1_t maskedoff, vuint32mf2_t op1, uint32_t op2, size_t vl) {
return __riscv_vwsll_vx_mu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u64m2_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwsll.mask.nxv2i64.nxv2i32.nxv2i32.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
vuint64m2_t test_vwsll_vv_u64m2_mu(vbool32_t mask, vuint64m2_t maskedoff, vuint32m1_t op1, vuint32m1_t op2, size_t vl) {
return __riscv_vwsll_vv_mu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u64m2_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwsll.mask.nxv2i64.nxv2i32.i32.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
vuint64m2_t test_vwsll_vx_u64m2_mu(vbool32_t mask, vuint64m2_t maskedoff, vuint32m1_t op1, uint32_t op2, size_t vl) {
return __riscv_vwsll_vx_mu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u64m4_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwsll.mask.nxv4i64.nxv4i32.nxv4i32.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
vuint64m4_t test_vwsll_vv_u64m4_mu(vbool16_t mask, vuint64m4_t maskedoff, vuint32m2_t op1, vuint32m2_t op2, size_t vl) {
return __riscv_vwsll_vv_mu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u64m4_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwsll.mask.nxv4i64.nxv4i32.i32.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
vuint64m4_t test_vwsll_vx_u64m4_mu(vbool16_t mask, vuint64m4_t maskedoff, vuint32m2_t op1, uint32_t op2, size_t vl) {
return __riscv_vwsll_vx_mu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vv_u64m8_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwsll.mask.nxv8i64.nxv8i32.nxv8i32.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
vuint64m8_t test_vwsll_vv_u64m8_mu(vbool8_t mask, vuint64m8_t maskedoff, vuint32m4_t op1, vuint32m4_t op2, size_t vl) {
return __riscv_vwsll_vv_mu(mask, maskedoff, op1, op2, vl);
}
// CHECK-LABEL: @test_vwsll_vx_u64m8_mu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwsll.mask.nxv8i64.nxv8i32.i32.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
vuint64m8_t test_vwsll_vx_u64m8_mu(vbool8_t mask, vuint64m8_t maskedoff, vuint32m4_t op1, uint32_t op2, size_t vl) {
return __riscv_vwsll_vx_mu(mask, maskedoff, op1, op2, vl);
}