[AArch64][clang] implement 2022 General Data-Processing instructions

[stuij]

Summary

This patch implements the 2022 Architecture General Data-Processing Instructions

They include:

Common Short Sequence Compression (CSSC) instructions

• scalar comparison instructions SMAX, SMIN, UMAX, UMIN (32/64 bits) with or without immediate
• ABS (absolute), CNT (count non-zero bits), CTZ (count trailing zeroes)
• command-line options for CSSC

Associated with these instructions in the documentation is the Range Prefetch
Memory (RPRFM) instruction, which signals to the memory system that data memory
accesses from a specified range of addresses are likely to occur in the near
future. The instruction lies in hint space, and is made unconditional.

Specs for the individual instructions can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09/Base-Instructions/

contributors to this patch:

• Cullen Rhodes
• Son Tuan Vu
• Mark Murray
• Tomas Matheson
• Sam Elliott
• Ties Stuij

[lenary]

LGTM!

[lenary]

Oh, actually, I have a few nits. You can fix them on commit though.

llvm/lib/Target/AArch64/AArch64.td

497

Please use the full name in parens: FEAT_CSSC (we've done this upstream for most other architectural extensions).

llvm/test/MC/AArch64/armv9.4a-v94-dp.s

1 ↗

(On Diff #477133)

CSSC is actually a v8.9a feature, can you update this filename?

llvm/test/MC/Disassembler/AArch64/armv9.4a-v94-dp.txt

1 ↗

(On Diff #477133)

And this filename too?

[dmgreen]

llvm/include/llvm/Support/AArch64TargetParser.h

79

48!?

llvm/lib/Target/AArch64/AArch64.td

497

Can you add (FEAT_SCCS) to this (if that is the correct name).

llvm/lib/Target/AArch64/AArch64InstrFormats.td

11725

Can we make this WriteI, maybe. I think that would probably be the closest sched class.

[tschuett]

llvm/lib/Target/AArch64/AArch64InstrFormats.td

11698

FEAT_CSSC or FEAT_V94_DP?

[stuij]

addressed review comments

llvm/lib/Target/AArch64/AArch64InstrFormats.td

11725

I'm assuming you meant WriteLD.

[dmgreen]

llvm/lib/Target/AArch64/AArch64InstrFormats.td

11725

That would be a Load I believe. There are the min/max instructions? I think "simple ALU instruction" should be the closest match, which would be WriteI

[stuij]

addressed review comment

[stuij]

llvm/lib/Target/AArch64/AArch64InstrFormats.td

11725

ah right, sorry misread your comment.

[stuij]

renamed *v94-dp* to *cssc*

[stuij]

llvm/lib/Target/AArch64/AArch64InstrFormats.td

11698

Yes, should be FEAT_CSSC. Thanks!

[dmgreen]

Thanks. I haven't looked though all the details, but thanks for fixing the scheduling info.

clang/test/Driver/aarch64-cssc.c

+// Test that target feature cssc is implemented and available correctly
+// RUN: %clang -### -target aarch64-none-none-eabi                         %s 2>&1 | FileCheck %s --check-prefix=ABSENT_CSSC
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.8-a+cssc   %s 2>&1 | FileCheck %s
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.9-a        %s 2>&1 | FileCheck %s --check-prefix=ABSENT_CSSC
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.8-a+cssc   %s 2>&1 | FileCheck %s
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.9-a+nocssc %s 2>&1 | FileCheck %s --check-prefix=NO_CSSC
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9.3-a+cssc   %s 2>&1 | FileCheck %s
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9.4-a        %s 2>&1 | FileCheck %s --check-prefix=ABSENT_CSSC
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9.3-a+cssc   %s 2>&1 | FileCheck %s
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9.4-a+nocssc %s 2>&1 | FileCheck %s --check-prefix=NO_CSSC
+
+// CHECK: "-target-feature" "+cssc"
+// NO_CSSC: "-target-feature" "-cssc"
+// ABSENT_CSSC-NOT: "-target-feature" "+cssc"
+// ABSENT_CSSC-NOT: "-target-feature" "-cssc"

llvm/include/llvm/Support/AArch64TargetParser.h

enum ArchExtKind : uint64_t {
   AEK_SMEI16I64 =   1ULL << 39, // FEAT_SME_I16I64
   AEK_HBC =         1ULL << 40, // FEAT_HBC
   AEK_MOPS =        1ULL << 41, // FEAT_MOPS
   AEK_PERFMON =     1ULL << 42, // FEAT_PMUv3
   AEK_SME2 =        1ULL << 43, // FEAT_SME2
   AEK_SVE2p1 =      1ULL << 44, // FEAT_SVE2p1
   AEK_SME2p1 =      1ULL << 45, // FEAT_SME2p1
   AEK_B16B16 =      1ULL << 46, // FEAT_B16B16
-  AEK_SMEF16F16 =   1ULL << 47  // FEAT_SMEF16F16
+  AEK_SMEF16F16 =   1ULL << 47, // FEAT_SMEF16F16
+  AEK_CSSC =        1ULL << 48, // FEAT_CSSC
 };
 
 enum class ArchKind {
 #define AARCH64_ARCH(NAME, ID, ARCH_FEATURE, ARCH_BASE_EXT) ID,
 #include "AArch64TargetParser.def"
 };
 
 struct ArchNames {

llvm/include/llvm/Support/AArch64TargetParser.def

 AARCH64_ARCH_EXT_NAME("sme-f64f64",   AArch64::AEK_SMEF64F64,   "+sme-f64f64",   "-sme-f64f64")
 AARCH64_ARCH_EXT_NAME("sme-i16i64",   AArch64::AEK_SMEI16I64,   "+sme-i16i64",   "-sme-i16i64")
 AARCH64_ARCH_EXT_NAME("sme-f16f16",   AArch64::AEK_SMEF16F16,   "+sme-f16f16",   "-sme-f16f16")
 AARCH64_ARCH_EXT_NAME("sme2",         AArch64::AEK_SME2,        "+sme2",         "-sme2")
 AARCH64_ARCH_EXT_NAME("sme2p1",       AArch64::AEK_SME2p1,      "+sme2p1",       "-sme2p1")
 AARCH64_ARCH_EXT_NAME("hbc",          AArch64::AEK_HBC,         "+hbc",          "-hbc")
 AARCH64_ARCH_EXT_NAME("mops",         AArch64::AEK_MOPS,        "+mops",         "-mops")
 AARCH64_ARCH_EXT_NAME("pmuv3",        AArch64::AEK_PERFMON,     "+perfmon",      "-perfmon")
+AARCH64_ARCH_EXT_NAME("cssc",         AArch64::AEK_CSSC,        "+cssc",         "-cssc")
 #undef AARCH64_ARCH_EXT_NAME
 
 #ifndef AARCH64_CPU_NAME
 #define AARCH64_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT)
 #endif
 AARCH64_CPU_NAME("cortex-a34", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
                  (AArch64::AEK_CRC))
 AARCH64_CPU_NAME("cortex-a35", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,

llvm/lib/Target/AArch64/AArch64.td

def FeatureAppleA7SysReg  : SubtargetFeature<"apple-a7-sysreg", "HasAppleA7SysReg", "true",
   "Apple A7 (the CPU formerly known as Cyclone)">;
 
 def FeatureEL2VMSA : SubtargetFeature<"el2vmsa", "HasEL2VMSA", "true",
   "Enable Exception Level 2 Virtual Memory System Architecture">;
 
 def FeatureEL3 : SubtargetFeature<"el3", "HasEL3", "true",
   "Enable Exception Level 3">;
 
+def FeatureCSSC : SubtargetFeature<"cssc", "HasCSSC", "true",
+  "Enable Common Short Sequence Compression (CSSC) instructions (FEAT_CSSC)">;
+
 def FeatureFixCortexA53_835769 : SubtargetFeature<"fix-cortex-a53-835769",
   "FixCortexA53_835769", "true", "Mitigate Cortex-A53 Erratum 835769">;
 
 def FeatureNoBTIAtReturnTwice : SubtargetFeature<"no-bti-at-return-twice",
                                                  "NoBTIAtReturnTwice", "true",
                                                  "Don't place a BTI instruction "
                                                  "after a return-twice">;
 
def HasV8_7aOps : SubtargetFeature<
   [HasV8_6aOps, FeatureXS, FeatureWFxT, FeatureHCX]>;
 
 def HasV8_8aOps : SubtargetFeature<
   "v8.8a", "HasV8_8aOps", "true", "Support ARM v8.8a instructions",
   [HasV8_7aOps, FeatureHBC, FeatureMOPS]>;
 
 def HasV8_9aOps : SubtargetFeature<
   "v8.9a", "HasV8_9aOps", "true", "Support ARM v8.9a instructions",
-  [HasV8_8aOps]>;
+  [HasV8_8aOps, FeatureCSSC]>;
 
 def HasV9_0aOps : SubtargetFeature<
   "v9a", "HasV9_0aOps", "true", "Support ARM v9a instructions",
   [HasV8_5aOps, FeatureMEC, FeatureSVE2]>;
 
 def HasV9_1aOps : SubtargetFeature<
   "v9.1a", "HasV9_1aOps", "true", "Support ARM v9.1a instructions",
   [HasV8_6aOps, HasV9_0aOps]>;

llvm/lib/Target/AArch64/AArch64InstrFormats.td

 
 class SImmOperand<int width> : AsmOperandClass {
   let Name = "SImm" # width;
   let DiagnosticType = "InvalidMemoryIndexedSImm" # width;
   let RenderMethod = "addImmOperands";
   let PredicateMethod = "isSImm<" # width # ">";
 }
 
-
 class AsmImmRange<int Low, int High> : AsmOperandClass {
   let Name = "Imm" # Low # "_" # High;
   let DiagnosticType = "InvalidImm" # Low # "_" # High;
   let RenderMethod = "addImmOperands";
   let PredicateMethod = "isImmInRange<" # Low # "," # High # ">";
 }
 
 // Authenticated loads for v8.3 can have scaled 10-bit immediate offsets.

 }
 
 def SImm9Operand : SImmOperand<9>;
 def simm9 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= -256 && Imm < 256; }]> {
   let ParserMatchClass = SImm9Operand;
   let DecoderMethod = "DecodeSImm<9>";
 }
 
+// imm0_255 predicate - True if the immediate is in the range [0,255].
+def Imm0_255Operand : AsmImmRange<0,255>;
+
+def uimm8_32b : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
+  let ParserMatchClass = Imm0_255Operand;
+}
+def uimm8_64b : Operand<i64>, ImmLeaf<i64, [{ return Imm >= 0 && Imm < 256; }]> {
+  let ParserMatchClass = Imm0_255Operand;
+}
+
 def SImm8Operand : SImmOperand<8>;
-def simm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= -128 && Imm < 128; }]> {
+def simm8_32b : Operand<i32>, ImmLeaf<i32, [{ return Imm >= -128 && Imm < 128; }]> {
+  let ParserMatchClass = SImm8Operand;
+  let DecoderMethod = "DecodeSImm<8>";
+}
+def simm8_64b : Operand<i64>, ImmLeaf<i64, [{ return Imm >= -128 && Imm < 128; }]> {
   let ParserMatchClass = SImm8Operand;
   let DecoderMethod = "DecodeSImm<8>";
 }
 
 def SImm6Operand : SImmOperand<6>;
 def simm6_32b : Operand<i32>, ImmLeaf<i32, [{ return Imm >= -32 && Imm < 32; }]> {
   let ParserMatchClass = SImm6Operand;
   let DecoderMethod = "DecodeSImm<6>";
def timm32_0_65535 : Operand<i32>, TImmLeaf<i32, [{
   return ((uint32_t)Imm) < 65536;
 }]>;
 
 def timm64_0_65535 : Operand<i64>, TImmLeaf<i64, [{
   return ((uint64_t)Imm) < 65536;
 }]>;
 }
 
-// imm0_255 predicate - True if the immediate is in the range [0,255].
-def Imm0_255Operand : AsmImmRange<0,255>;
-
 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{
   return ((uint32_t)Imm) < 256;
 }]> {
   let ParserMatchClass = Imm0_255Operand;
   let PrintMethod = "printImm";
 }
 
 // imm0_127 predicate - True if the immediate is in the range [0,127]
class SystemLXtI<bit L, string asm>
   bits<3> op2;
   let Inst{20-19} = 0b01;
   let Inst{18-16} = op1;
   let Inst{15-12} = Cn;
   let Inst{11-8}  = Cm;
   let Inst{7-5}   = op2;
 }
 
+def RangePrefetchOperand : AsmOperandClass {
+  let Name = "RangePrefetch";
+  let ParserMethod = "tryParseRPRFMOperand";
+  let PredicateMethod = "isPrefetch";
+  let RenderMethod = "addPrefetchOperands";
+}
+
+def rprfop : Operand<i32>, TImmLeaf<i32, [{
+    return (((uint32_t)Imm) <= 63);
+  }]> {
+  let PrintMethod = "printRPRFMOperand";
+  let ParserMatchClass = RangePrefetchOperand;
+}
 
 // Branch (register) instructions:
 //
 //  case opc of
 //    0001 blr
 //    0000 br
 //    0101 dret
 //    0100 eret

 class CallImm<bit op, string asm, list<dag> pattern>
     : BImm<op, (ins am_bl_target:$addr), asm, pattern>;
 
 //---
 // Basic one-operand data processing instructions.
 //---
 
 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
-class BaseOneOperandData<bits<3> opc, RegisterClass regtype, string asm,
+class BaseOneOperandData<bit sf, bit S, bits<5> opc2, bits<6> opc,
+                         RegisterClass regtype, string asm,
                          SDPatternOperator node>
   : I<(outs regtype:$Rd), (ins regtype:$Rn), asm, "\t$Rd, $Rn", "",
       [(set regtype:$Rd, (node regtype:$Rn))]>,
     Sched<[WriteI, ReadI]> {
   bits<5> Rd;
   bits<5> Rn;
 
-  let Inst{30-13} = 0b101101011000000000;
-  let Inst{12-10} = opc;
+  let Inst{31} = sf;
+  let Inst{30} = 0b1;
+  let Inst{29} = S;
+  let Inst{28-21} = 0b11010110;
+  let Inst{20-16} = opc2;
+  let Inst{15-10} = opc;
   let Inst{9-5}   = Rn;
   let Inst{4-0}   = Rd;
 }
 
 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
-multiclass OneOperandData<bits<3> opc, string asm,
+multiclass OneOperandData<bits<6> opc, string asm,
                           SDPatternOperator node = null_frag> {
-  def Wr : BaseOneOperandData<opc, GPR32, asm, node> {
-    let Inst{31} = 0;
-  }
+  def Wr : BaseOneOperandData<0b0, 0b0, 0b00000, opc, GPR32, asm, node>;
 
-  def Xr : BaseOneOperandData<opc, GPR64, asm, node> {
-    let Inst{31} = 1;
-  }
+  def Xr : BaseOneOperandData<0b1, 0b0, 0b00000, opc, GPR64, asm, node>;
 }
 
-class OneWRegData<bits<3> opc, string asm, SDPatternOperator node>
-    : BaseOneOperandData<opc, GPR32, asm, node> {
-  let Inst{31} = 0;
-}
+class OneWRegData<bits<6> opc, string asm, SDPatternOperator node>
+    : BaseOneOperandData<0b0, 0b0, 0b00000, opc, GPR32, asm, node>;
 
-class OneXRegData<bits<3> opc, string asm, SDPatternOperator node>
-    : BaseOneOperandData<opc, GPR64, asm, node> {
-  let Inst{31} = 1;
-}
+class OneXRegData<bits<6> opc, string asm, SDPatternOperator node>
+    : BaseOneOperandData<0b1, 0b0, 0b00000, opc, GPR64, asm, node>;
 
 class SignAuthOneData<bits<3> opcode_prefix, bits<2> opcode, string asm,
                       SDPatternOperator op>
   : I<(outs GPR64:$dst), (ins GPR64:$Rd, GPR64sp:$Rn), asm, "\t$Rd, $Rn",
       "$dst = $Rd", [(set GPR64:$dst, (op GPR64:$Rd, opcode, GPR64sp:$Rn))]>,
     Sched<[WriteI, ReadI]> {
   bits<5> Rd;
   bits<5> Rn;
multiclass AddSubCarry<bit isSub, string asm, string asm_setflags,
   }
   def SXr : BaseAddSubCarrySetFlags<isSub, GPR64, asm_setflags,
                                     OpNode_setflags> {
     let Inst{31} = 1;
     let Inst{29} = 1;
   }
 }
 
-class BaseTwoOperand<bits<4> opc, RegisterClass regtype, string asm,
-                     SDPatternOperator OpNode,
+class BaseTwoOperandRegReg<bit sf, bit S, bits<6> opc, RegisterClass regtype,
+                           string asm, SDPatternOperator OpNode,
                            RegisterClass in1regtype = regtype,
                            RegisterClass in2regtype = regtype>
   : I<(outs regtype:$Rd), (ins in1regtype:$Rn, in2regtype:$Rm),
       asm, "\t$Rd, $Rn, $Rm", "",
       [(set regtype:$Rd, (OpNode in1regtype:$Rn, in2regtype:$Rm))]> {
   bits<5> Rd;
   bits<5> Rn;
   bits<5> Rm;
-  let Inst{30-21} = 0b0011010110;
+  let Inst{31}    = sf;
+  let Inst{30}    = 0b0;
+  let Inst{29}    = S;
+  let Inst{28-21} = 0b11010110;
   let Inst{20-16} = Rm;
-  let Inst{15-14} = 0b00;
-  let Inst{13-10} = opc;
+  let Inst{15-10} = opc;
   let Inst{9-5}   = Rn;
   let Inst{4-0}   = Rd;
 }
 
-class BaseDiv<bit isSigned, RegisterClass regtype, string asm,
+class BaseDiv<bit size, bit isSigned, RegisterClass regtype, string asm,
               SDPatternOperator OpNode>
-    : BaseTwoOperand<{0,0,1,?}, regtype, asm, OpNode> {
+    : BaseTwoOperandRegReg<size, 0b0, {0,0,0,0,1,?}, regtype, asm, OpNode> {
   let Inst{10}    = isSigned;
 }
 
 multiclass Div<bit isSigned, string asm, SDPatternOperator OpNode> {
-  def Wr : BaseDiv<isSigned, GPR32, asm, OpNode>,
-           Sched<[WriteID32, ReadID, ReadID]> {
-    let Inst{31} = 0;
-  }
-  def Xr : BaseDiv<isSigned, GPR64, asm, OpNode>,
-           Sched<[WriteID64, ReadID, ReadID]> {
-    let Inst{31} = 1;
-  }
+  def Wr : BaseDiv<0b0, isSigned, GPR32, asm, OpNode>,
+           Sched<[WriteID32, ReadID, ReadID]>;
+
+  def Xr : BaseDiv<0b1, isSigned, GPR64, asm, OpNode>,
+           Sched<[WriteID64, ReadID, ReadID]>;
 }
 
-class BaseShift<bits<2> shift_type, RegisterClass regtype, string asm,
+class BaseShift<bit size, bits<2> shift_type, RegisterClass regtype, string asm,
                 SDPatternOperator OpNode = null_frag>
-  : BaseTwoOperand<{1,0,?,?}, regtype, asm, OpNode>,
+  : BaseTwoOperandRegReg<size, 0b0, {0,0,1,0,?,?}, regtype, asm, OpNode>,
     Sched<[WriteIS, ReadI]> {
   let Inst{11-10} = shift_type;
 }
 
 multiclass Shift<bits<2> shift_type, string asm, SDNode OpNode> {
-  def Wr : BaseShift<shift_type, GPR32, asm> {
-    let Inst{31} = 0;
-  }
+  def Wr : BaseShift<0b0, shift_type, GPR32, asm>;
 
-  def Xr : BaseShift<shift_type, GPR64, asm, OpNode> {
-    let Inst{31} = 1;
-  }
+  def Xr : BaseShift<0b1, shift_type, GPR64, asm, OpNode>;
 
   def : Pat<(i32 (OpNode GPR32:$Rn, i64:$Rm)),
             (!cast<Instruction>(NAME # "Wr") GPR32:$Rn,
                                              (EXTRACT_SUBREG i64:$Rm, sub_32))>;
 
   def : Pat<(i32 (OpNode GPR32:$Rn, (i64 (zext GPR32:$Rm)))),
             (!cast<Instruction>(NAME # "Wr") GPR32:$Rn, GPR32:$Rm)>;
 
class AddSubG<bit isSub, string asm_inst, SDPatternOperator OpNode>
   let Inst{23-22} = 0b10;
   let Inst{21-16} = imm6;
   let Inst{15-14} = 0b00;
   let Inst{13-10} = imm4;
   let Unpredictable{15-14} = 0b11;
 }
 
 class SUBP<bit setsFlags, string asm_instr, SDPatternOperator OpNode>
-      : BaseTwoOperand<0b0000, GPR64, asm_instr, OpNode, GPR64sp, GPR64sp> {
-  let Inst{31} = 1;
-  let Inst{29} = setsFlags;
-}
+      : BaseTwoOperandRegReg<0b1, setsFlags, 0b000000, GPR64, asm_instr, OpNode,
+                             GPR64sp, GPR64sp>;
 
 //---
 // Extract
 //---
 def SDTA64EXTR : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
                                       SDTCisPtrTy<3>]>;
 def AArch64Extr : SDNode<"AArch64ISD::EXTR", SDTA64EXTR>;
 
class BasePrefetchRO<bits<2> sz, bit V, bits<2> opc, dag outs, dag ins,
   let Inst{21}    = 1;
   let Inst{20-16} = Rm;
   let Inst{15}    = extend{1}; // sign extend Rm?
   let Inst{14}    = 1;
   let Inst{12}    = extend{0}; // do shift?
   let Inst{11-10} = 0b10;
   let Inst{9-5}   = Rn;
   let Inst{4-0}   = Rt;
+  let DecoderMethod = "DecodePRFMRegInstruction";
+  // PRFM (reg) aliases with RPRFM added to the base A64 instruction set. When
+  // the decoder method returns Fail, the decoder should attempt to decode the
+  // instruction as RPRFM.
+  let hasCompleteDecoder = 0;
 }
 
 multiclass PrefetchRO<bits<2> sz, bit V, bits<2> opc, string asm> {
   def roW : BasePrefetchRO<sz, V, opc, (outs),
                 (ins prfop:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend),
                 asm, [(AArch64Prefetch timm:$Rt,
                                      (ro_Windexed64 GPR64sp:$Rn, GPR32:$Rm,
                                                     ro_Wextend64:$extend))]> {

 
 multiclass MOPSMemorySetTaggingInsns<bits<2> opcode, string asm> {
   def "" : MOPSMemorySetTagging<opcode, 0, 0, asm>;
   def T  : MOPSMemorySetTagging<opcode, 1, 0, asm # "t">;
   def N  : MOPSMemorySetTagging<opcode, 0, 1, asm # "n">;
   def TN : MOPSMemorySetTagging<opcode, 1, 1, asm # "tn">;
 }
 
+//---
+// 2022 Architecture Extensions: General Data Processing (FEAT_CSSC)
+//---
+
+class BaseTwoOperandRegImm<bit sf, bit Op, bit S, bits<4> opc,
+                           RegisterClass regtype, ImmLeaf immtype, string asm,
+                           SDPatternOperator OpNode>
+    : I<(outs regtype:$Rd), (ins regtype:$Rn, immtype:$imm),
+        asm, "\t$Rd, $Rn, $imm", "",
+        [(set regtype:$Rd, (OpNode regtype:$Rn, immtype:$imm))]> {
+  bits<5> Rd;
+  bits<5> Rn;
+  bits<8> imm;
+
+  let Inst{31}    = sf;
+  let Inst{30}    = Op;
+  let Inst{29}    = S;
+  let Inst{28-22} = 0b1000111;
+  let Inst{21-18} = opc;
+  let Inst{17-10} = imm;
+  let Inst{9-5}   = Rn;
+  let Inst{4-0}   = Rd;
+}
+
+class BaseComparisonOpReg<bit size, bit isUnsigned, bit isMin,
+                          RegisterClass regtype, string asm,
+                          SDPatternOperator OpNode>
+    : BaseTwoOperandRegReg<size, 0b0, {0,1,1,0,?,?}, regtype, asm, OpNode>,
+      Sched<[WriteI]> {
+  let Inst{11} = isMin;
+  let Inst{10} = isUnsigned;
+  let mayLoad  = 0;
+  let mayStore = 0;
+  let hasSideEffects = 0;
+}
+
+class BaseComparisonOpImm<bit size, bit isUnsigned, bit isMin,
+                          RegisterClass regtype, ImmLeaf immtype, string asm,
+                          SDPatternOperator OpNode>
+    : BaseTwoOperandRegImm<size, 0b0, 0b0, {0,0,?,?}, regtype, immtype, asm,
+                           OpNode>,
+      Sched<[]> {
+  let Inst{19} = isMin;
+  let Inst{18} = isUnsigned;
+  let mayLoad  = 0;
+  let mayStore = 0;
+  let hasSideEffects = 0;
+}
+
+multiclass ComparisonOp<bit isUnsigned, bit isMin, string asm,
+                        SDPatternOperator OpNode = null_frag> {
+  def Wrr : BaseComparisonOpReg<0b0, isUnsigned, isMin, GPR32, asm, OpNode>;
+
+  def Wri : BaseComparisonOpImm<0b0, isUnsigned, isMin, GPR32,
+                                !cond(isUnsigned : uimm8_32b,
+                                      !not(isUnsigned) : simm8_32b), asm, OpNode>;
+
+  def Xrr : BaseComparisonOpReg<0b1, isUnsigned, isMin, GPR64, asm, OpNode>;
+
+  def Xri : BaseComparisonOpImm<0b1, isUnsigned, isMin, GPR64,
+                                !cond(isUnsigned : uimm8_64b,
+                                      !not(isUnsigned) : simm8_64b), asm, OpNode>;
+}
+
 //----------------------------------------------------------------------------
 // Allow the size specifier tokens to be upper case, not just lower.
 def : TokenAlias<".4B", ".4b">;  // Add dot product
 def : TokenAlias<".8B", ".8b">;
 def : TokenAlias<".4H", ".4h">;
 def : TokenAlias<".2S", ".2s">;
 def : TokenAlias<".1D", ".1d">;
 def : TokenAlias<".16B", ".16b">;

llvm/lib/Target/AArch64/AArch64InstrInfo.td

 //=- AArch64InstrInfo.td - Describe the AArch64 Instructions -*- tablegen -*-=//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // AArch64 Instruction definitions.
 //
 //===----------------------------------------------------------------------===//
 
 //===----------------------------------------------------------------------===//
 // ARM Instruction Predicate Definitions.
 //
+def HasV8_0a         : Predicate<"Subtarget->hasV8_0aOps()">,
+                                 AssemblerPredicate<(all_of HasV8_0aOps), "armv8.0a">;
 def HasV8_1a         : Predicate<"Subtarget->hasV8_1aOps()">,
                                  AssemblerPredicateWithAll<(all_of HasV8_1aOps), "armv8.1a">;
 def HasV8_2a         : Predicate<"Subtarget->hasV8_2aOps()">,
                                  AssemblerPredicateWithAll<(all_of HasV8_2aOps), "armv8.2a">;
 def HasV8_3a         : Predicate<"Subtarget->hasV8_3aOps()">,
                                  AssemblerPredicateWithAll<(all_of HasV8_3aOps), "armv8.3a">;
 def HasV8_4a         : Predicate<"Subtarget->hasV8_4aOps()">,
                                  AssemblerPredicateWithAll<(all_of HasV8_4aOps), "armv8.4a">;

 def HasSHA2          : Predicate<"Subtarget->hasSHA2()">,
                                  AssemblerPredicateWithAll<(all_of FeatureSHA2), "sha2">;
 def HasAES           : Predicate<"Subtarget->hasAES()">,
                                  AssemblerPredicateWithAll<(all_of FeatureAES), "aes">;
 def HasDotProd       : Predicate<"Subtarget->hasDotProd()">,
                                  AssemblerPredicateWithAll<(all_of FeatureDotProd), "dotprod">;
 def HasCRC           : Predicate<"Subtarget->hasCRC()">,
                                  AssemblerPredicateWithAll<(all_of FeatureCRC), "crc">;
+def HasCSSC           : Predicate<"Subtarget->hasCSSC()">,
+                                 AssemblerPredicateWithAll<(all_of FeatureCSSC), "cssc">;
 def HasLSE           : Predicate<"Subtarget->hasLSE()">,
                                  AssemblerPredicateWithAll<(all_of FeatureLSE), "lse">;
 def HasNoLSE         : Predicate<"!Subtarget->hasLSE()">;
 def HasRAS           : Predicate<"Subtarget->hasRAS()">,
                                  AssemblerPredicateWithAll<(all_of FeatureRAS), "ras">;
 def HasRDM           : Predicate<"Subtarget->hasRDM()">,
                                  AssemblerPredicateWithAll<(all_of FeatureRDM), "rdm">;
 def HasPerfMon       : Predicate<"Subtarget->hasPerfMon()">;

 defm : STOPregister<"stsmax","LDSMAX">;// STSMAXx
 defm : STOPregister<"stsmin","LDSMIN">;// STSMINx
 defm : STOPregister<"stumax","LDUMAX">;// STUMAXx
 defm : STOPregister<"stumin","LDUMIN">;// STUMINx
 
 // v8.5 Memory Tagging Extension
 let Predicates = [HasMTE] in {
 
-def IRG   : BaseTwoOperand<0b0100, GPR64sp, "irg", int_aarch64_irg, GPR64sp, GPR64>,
-            Sched<[]>{
-  let Inst{31} = 1;
-}
-def GMI   : BaseTwoOperand<0b0101, GPR64, "gmi", int_aarch64_gmi, GPR64sp>, Sched<[]>{
-  let Inst{31} = 1;
+def IRG   : BaseTwoOperandRegReg<0b1, 0b0, 0b000100, GPR64sp, "irg",
+                                 int_aarch64_irg, GPR64sp, GPR64>, Sched<[]>;
+
+def GMI   : BaseTwoOperandRegReg<0b1, 0b0, 0b000101, GPR64, "gmi",
+                                 int_aarch64_gmi, GPR64sp>, Sched<[]> {
   let isNotDuplicable = 1;
 }
 def ADDG  : AddSubG<0, "addg", null_frag>;
 def SUBG  : AddSubG<1, "subg", null_frag>;
 
 def : InstAlias<"irg $dst, $src", (IRG GPR64sp:$dst, GPR64sp:$src, XZR), 1>;
 
 def SUBP : SUBP<0, "subp", int_aarch64_subp>, Sched<[]>;

 def : Pat<(not GPR32:$Wm), (ORNWrr WZR, GPR32:$Wm)>;
 def : Pat<(not GPR64:$Xm), (ORNXrr XZR, GPR64:$Xm)>;
 
 
 //===----------------------------------------------------------------------===//
 // One operand data processing instructions.
 //===----------------------------------------------------------------------===//
 
-defm CLS    : OneOperandData<0b101, "cls">;
-defm CLZ    : OneOperandData<0b100, "clz", ctlz>;
-defm RBIT   : OneOperandData<0b000, "rbit", bitreverse>;
+defm CLS    : OneOperandData<0b000101, "cls">;
+defm CLZ    : OneOperandData<0b000100, "clz", ctlz>;
+defm RBIT   : OneOperandData<0b000000, "rbit", bitreverse>;
 
-def  REV16Wr : OneWRegData<0b001, "rev16",
+def  REV16Wr : OneWRegData<0b000001, "rev16",
                                      UnOpFrag<(rotr (bswap node:$LHS), (i64 16))>>;
-def  REV16Xr : OneXRegData<0b001, "rev16", null_frag>;
+def  REV16Xr : OneXRegData<0b000001, "rev16", null_frag>;
 
 def : Pat<(cttz GPR32:$Rn),
           (CLZWr (RBITWr GPR32:$Rn))>;
 def : Pat<(cttz GPR64:$Rn),
           (CLZXr (RBITXr GPR64:$Rn))>;
 def : Pat<(ctlz (or (shl (xor (sra GPR32:$Rn, (i64 31)), GPR32:$Rn), (i64 1)),
                 (i32 1))),
           (CLSWr GPR32:$Rn)>;
 def : Pat<(ctlz (or (shl (xor (sra GPR64:$Rn, (i64 63)), GPR64:$Rn), (i64 1)),
                 (i64 1))),
           (CLSXr GPR64:$Rn)>;
 def : Pat<(int_aarch64_cls GPR32:$Rn), (CLSWr GPR32:$Rn)>;
 def : Pat<(int_aarch64_cls64 GPR64:$Rm), (EXTRACT_SUBREG (CLSXr GPR64:$Rm), sub_32)>;
 
 // Unlike the other one operand instructions, the instructions with the "rev"
 // mnemonic do *not* just different in the size bit, but actually use different
 // opcode bits for the different sizes.
-def REVWr   : OneWRegData<0b010, "rev", bswap>;
-def REVXr   : OneXRegData<0b011, "rev", bswap>;
-def REV32Xr : OneXRegData<0b010, "rev32",
+def REVWr   : OneWRegData<0b000010, "rev", bswap>;
+def REVXr   : OneXRegData<0b000011, "rev", bswap>;
+def REV32Xr : OneXRegData<0b000010, "rev32",
                                     UnOpFrag<(rotr (bswap node:$LHS), (i64 32))>>;
 
 def : InstAlias<"rev64 $Rd, $Rn", (REVXr GPR64:$Rd, GPR64:$Rn), 0>;
 
 // The bswap commutes with the rotr so we want a pattern for both possible
 // orders.
 def : Pat<(bswap (rotr GPR32:$Rn, (i64 16))), (REV16Wr GPR32:$Rn)>;
 def : Pat<(bswap (rotr GPR64:$Rn, (i64 32))), (REV32Xr GPR64:$Rn)>;
 

 def StoreSwiftAsyncContext
       : Pseudo<(outs), (ins GPR64:$ctx, GPR64sp:$base, simm9:$offset),
                []>, Sched<[]>;
 
 def AArch64AssertZExtBool : SDNode<"AArch64ISD::ASSERT_ZEXT_BOOL", SDT_assert>;
 def : Pat<(AArch64AssertZExtBool GPR32:$op),
           (i32 GPR32:$op)>;
 
+//===----------------------------===//
+// 2022 Architecture Extensions:
+//===----------------------------===//
+
+//===----------------------------------------------------------------------===//
+// General Data-Processing Instructions (FEAT_V94_DP)
+//===----------------------------------------------------------------------===//
+defm ABS : OneOperandData<0b001000, "abs">, Requires<[HasCSSC]>;
+defm CNT : OneOperandData<0b000111, "cnt">, Requires<[HasCSSC]>;
+defm CTZ : OneOperandData<0b000110, "ctz">, Requires<[HasCSSC]>;
+
+defm SMAX : ComparisonOp<0, 0, "smax">, Requires<[HasCSSC]>;
+defm SMIN : ComparisonOp<0, 1, "smin">, Requires<[HasCSSC]>;
+defm UMAX : ComparisonOp<1, 0, "umax">, Requires<[HasCSSC]>;
+defm UMIN : ComparisonOp<1, 1, "umin">, Requires<[HasCSSC]>;
+
+def RPRFM:
+    I<(outs), (ins rprfop:$Rt, GPR64:$Rm, GPR64sp:$Rn),
+      "rprfm", "\t$Rt, $Rm, [$Rn]", "", []>,
+    Sched<[]> {
+  bits<6> Rt;
+  bits<5> Rn;
+  bits<5> Rm;
+  let Inst{2-0} = Rt{2-0};
+  let Inst{4-3} = 0b11;
+  let Inst{9-5} = Rn;
+  let Inst{11-10} = 0b10;
+  let Inst{13-12} = Rt{4-3};
+  let Inst{14} = 0b1;
+  let Inst{15} = Rt{5};
+  let Inst{20-16} = Rm;
+  let Inst{31-21} = 0b11111000101;
+  let mayLoad = 0;
+  let mayStore = 0;
+  let hasSideEffects = 1;
+  // RPRFM overlaps with PRFM (reg), when the decoder method of PRFM returns
+  // Fail, the decoder should attempt to decode RPRFM. This requires setting
+  // the decoder namespace to "Fallback".
+  let DecoderNamespace = "Fallback";
+}
+
 include "AArch64InstrAtomics.td"
 include "AArch64SVEInstrInfo.td"
 include "AArch64SMEInstrInfo.td"
 include "AArch64InstrGISel.td"

llvm/lib/Target/AArch64/AArch64SystemOperands.td

 def : SVEPRFM<"pstl1strm", 0x09>;
 def : SVEPRFM<"pstl2keep", 0x0a>;
 def : SVEPRFM<"pstl2strm", 0x0b>;
 def : SVEPRFM<"pstl3keep", 0x0c>;
 def : SVEPRFM<"pstl3strm", 0x0d>;
 }
 
 //===----------------------------------------------------------------------===//
+// RPRFM (prefetch) instruction options.
+//===----------------------------------------------------------------------===//
+
+class RPRFM<string name, bits<1> type_encoding, bits<5> policy_encoding> : SearchableTable {
+  let SearchableFields = ["Name", "Encoding"];
+  let EnumValueField = "Encoding";
+
+  string Name = name;
+  bits<6> Encoding;
+  let Encoding{0} = type_encoding;
+  let Encoding{5-1} = policy_encoding;
+  code Requires = [{ {} }];
+}
+
+def : RPRFM<"pldkeep", 0b0, 0b00000>;
+def : RPRFM<"pstkeep", 0b1, 0b00000>;
+def : RPRFM<"pldstrm", 0b0, 0b00010>;
+def : RPRFM<"pststrm", 0b1, 0b00010>;
+
+//===----------------------------------------------------------------------===//
 // SVE Predicate patterns
 //===----------------------------------------------------------------------===//
 
 class SVEPREDPAT<string name, bits<5> encoding> : SearchableTable {
   let SearchableFields = ["Name", "Encoding"];
   let EnumValueField = "Encoding";
 
   string Name = name;

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

#include "AArch64GenAsmMatcher.inc"
   OperandMatchResultTy tryParseOptionalShiftExtend(OperandVector &Operands);
   OperandMatchResultTy tryParseBarrierOperand(OperandVector &Operands);
   OperandMatchResultTy tryParseBarriernXSOperand(OperandVector &Operands);
   OperandMatchResultTy tryParseMRSSystemRegister(OperandVector &Operands);
   OperandMatchResultTy tryParseSysReg(OperandVector &Operands);
   OperandMatchResultTy tryParseSysCROperand(OperandVector &Operands);
   template <bool IsSVEPrefetch = false>
   OperandMatchResultTy tryParsePrefetch(OperandVector &Operands);
+  OperandMatchResultTy tryParseRPRFMOperand(OperandVector &Operands);
   OperandMatchResultTy tryParsePSBHint(OperandVector &Operands);
   OperandMatchResultTy tryParseBTIHint(OperandVector &Operands);
   OperandMatchResultTy tryParseAdrpLabel(OperandVector &Operands);
   OperandMatchResultTy tryParseAdrLabel(OperandVector &Operands);
   template<bool AddFPZeroAsLiteral>
   OperandMatchResultTy tryParseFPImm(OperandVector &Operands);
   OperandMatchResultTy tryParseImmWithOptionalShift(OperandVector &Operands);
   OperandMatchResultTy tryParseGPR64sp0Operand(OperandVector &Operands);
AArch64AsmParser::tryParseSysCROperand(OperandVector &Operands) {
   }
 
   Lex(); // Eat identifier token.
   Operands.push_back(
       AArch64Operand::CreateSysCR(CRNum, S, getLoc(), getContext()));
   return MatchOperand_Success;
 }
 
+// Either an identifier for named values or a 6-bit immediate.
+OperandMatchResultTy
+AArch64AsmParser::tryParseRPRFMOperand(OperandVector &Operands) {
+  SMLoc S = getLoc();
+  const AsmToken &Tok = getTok();
+
+  unsigned MaxVal = 63;
+
+  // Immediate case, with optional leading hash:
+  if (parseOptionalToken(AsmToken::Hash) ||
+      Tok.is(AsmToken::Integer)) {
+    const MCExpr *ImmVal;
+    if (getParser().parseExpression(ImmVal))
+      return MatchOperand_ParseFail;
+
+    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
+    if (!MCE) {
+      TokError("immediate value expected for prefetch operand");
+      return MatchOperand_ParseFail;
+    }
+    unsigned prfop = MCE->getValue();
+    if (prfop > MaxVal) {
+      TokError("prefetch operand out of range, [0," + utostr(MaxVal) +
+               "] expected");
+      return MatchOperand_ParseFail;
+    }
+
+    auto RPRFM = AArch64RPRFM::lookupRPRFMByEncoding(MCE->getValue());
+    Operands.push_back(AArch64Operand::CreatePrefetch(
+        prfop, RPRFM ? RPRFM->Name : "", S, getContext()));
+    return MatchOperand_Success;
+  }
+
+  if (Tok.isNot(AsmToken::Identifier)) {
+    TokError("prefetch hint expected");
+    return MatchOperand_ParseFail;
+  }
+
+  auto RPRFM = AArch64RPRFM::lookupRPRFMByName(Tok.getString());
+  if (!RPRFM) {
+    TokError("prefetch hint expected");
+    return MatchOperand_ParseFail;
+  }
+
+  Operands.push_back(AArch64Operand::CreatePrefetch(
+      RPRFM->Encoding, Tok.getString(), S, getContext()));
+  Lex(); // Eat identifier token.
+  return MatchOperand_Success;
+}
+
 /// tryParsePrefetch - Try to parse a prefetch operand.
 template <bool IsSVEPrefetch>
 OperandMatchResultTy
 AArch64AsmParser::tryParsePrefetch(OperandVector &Operands) {
   SMLoc S = getLoc();
   const AsmToken &Tok = getTok();
 
   auto LookupByName = [](StringRef N) {

llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp

 static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address,
                                  const MCDisassembler *Decoder);
 static DecodeStatus DecodeCPYMemOpInstruction(MCInst &Inst, uint32_t insn,
                                               uint64_t Addr,
                                               const MCDisassembler *Decoder);
 static DecodeStatus DecodeSETMemOpInstruction(MCInst &Inst, uint32_t insn,
                                               uint64_t Addr,
                                               const MCDisassembler *Decoder);
+static DecodeStatus DecodePRFMRegInstruction(MCInst &Inst, uint32_t insn,
+                                             uint64_t Address,
+                                             const MCDisassembler *Decoder);
 
 #include "AArch64GenDisassemblerTables.inc"
 #include "AArch64GenInstrInfo.inc"
 
 #define Success MCDisassembler::Success
 #define Fail MCDisassembler::Fail
 #define SoftFail MCDisassembler::SoftFail
 
if (!DecodeGPR64commonRegisterClass(Inst, Rd, Addr, Decoder) ||
       !DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder) ||
       !DecodeGPR64commonRegisterClass(Inst, Rd, Addr, Decoder) ||
       !DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder) ||
       !DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder))
     return MCDisassembler::Fail;
 
   return MCDisassembler::Success;
 }
+
+static DecodeStatus DecodePRFMRegInstruction(MCInst &Inst, uint32_t insn,
+                                             uint64_t Addr,
+                                             const MCDisassembler *Decoder) {
+  // PRFM with Rt = '11xxx' should be decoded as RPRFM.
+  // Fail to decode and defer to fallback decoder table to decode RPRFM.
+  unsigned Mask = 0x18;
+  uint64_t Rt = fieldFromInstruction(insn, 0, 5);
+  if ((Rt & Mask) == Mask)
+    return Fail;
+
+  uint64_t Rn = fieldFromInstruction(insn, 5, 5);
+  uint64_t Shift = fieldFromInstruction(insn, 12, 1);
+  uint64_t Extend = fieldFromInstruction(insn, 15, 1);
+  uint64_t Rm = fieldFromInstruction(insn, 16, 5);
+
+  Inst.addOperand(MCOperand::createImm(Rt));
+  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
+
+  switch (Inst.getOpcode()) {
+  default:
+    return Fail;
+  case AArch64::PRFMroW:
+    DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
+    break;
+  case AArch64::PRFMroX:
+    DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
+    break;
+  }
+
+  DecodeMemExtend(Inst, (Extend << 1) | Shift, Addr, Decoder);
+
+  return Success;
+}

llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h

public:
   }
 
   static const char *getRegisterName(unsigned RegNo,
                                      unsigned AltIdx = AArch64::NoRegAltName);
 
 protected:
   bool printSysAlias(const MCInst *MI, const MCSubtargetInfo &STI,
                      raw_ostream &O);
+  bool printRangePrefetchAlias(const MCInst *MI, const MCSubtargetInfo &STI,
+                               raw_ostream &O, StringRef Annot);
   // Operand printers
   void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
                     raw_ostream &O);
   void printImm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
                 raw_ostream &O);
   void printImmHex(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
                    raw_ostream &O);
   template <int Size>
protected:
   template <int Scale, int Offset>
   void printImmRangeScale(const MCInst *MI, unsigned OpNum,
                           const MCSubtargetInfo &STI, raw_ostream &O);
 
   template <bool IsSVEPrefetch = false>
   void printPrefetchOp(const MCInst *MI, unsigned OpNum,
                        const MCSubtargetInfo &STI, raw_ostream &O);
 
+  void printRPRFMOperand(const MCInst *MI, unsigned OpNum,
+                         const MCSubtargetInfo &STI, raw_ostream &O);
+
   void printPSBHintOp(const MCInst *MI, unsigned OpNum,
                       const MCSubtargetInfo &STI, raw_ostream &O);
 
   void printBTIHintOp(const MCInst *MI, unsigned OpNum,
                       const MCSubtargetInfo &STI, raw_ostream &O);
 
   void printFPImmOperand(const MCInst *MI, unsigned OpNum,
                          const MCSubtargetInfo &STI, raw_ostream &O);

llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp

void AArch64InstPrinter::printInst(const MCInst *MI, uint64_t Address,
   unsigned Opcode = MI->getOpcode();
 
   if (Opcode == AArch64::SYSxt)
     if (printSysAlias(MI, STI, O)) {
       printAnnotation(O, Annot);
       return;
     }
 
+  // RPRFM overlaps PRFM (reg), so try to print it as RPRFM here.
+  if ((Opcode == AArch64::PRFMroX) || (Opcode == AArch64::PRFMroW)) {
+    if (printRangePrefetchAlias(MI, STI, O, Annot))
+      return;
+  }
+
   // SBFM/UBFM should print to a nicer aliased form if possible.
   if (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri ||
       Opcode == AArch64::UBFMXri || Opcode == AArch64::UBFMWri) {
     const MCOperand &Op0 = MI->getOperand(0);
     const MCOperand &Op1 = MI->getOperand(1);
     const MCOperand &Op2 = MI->getOperand(2);
     const MCOperand &Op3 = MI->getOperand(3);
 
if (const LdStNInstrDesc *LdStDesc = getLdStNInstrDesc(Opcode)) {
 
     printAnnotation(O, Annot);
     return;
   }
 
   AArch64InstPrinter::printInst(MI, Address, Annot, STI, O);
 }
 
+bool AArch64InstPrinter::printRangePrefetchAlias(const MCInst *MI,
+                                                 const MCSubtargetInfo &STI,
+                                                 raw_ostream &O,
+                                                 StringRef Annot) {
+  unsigned Opcode = MI->getOpcode();
+
+#ifndef NDEBUG
+  assert(((Opcode == AArch64::PRFMroX) || (Opcode == AArch64::PRFMroW)) &&
+         "Invalid opcode for RPRFM alias!");
+#endif
+
+  unsigned PRFOp = MI->getOperand(0).getImm();
+  unsigned Mask = 0x18; // 0b11000
+  if ((PRFOp & Mask) != Mask)
+    return false; // Rt != '11xxx', it's a PRFM instruction.
+
+  unsigned Rm = MI->getOperand(2).getReg();
+
+  // "Rm" must be a 64-bit GPR for RPRFM.
+  if (MRI.getRegClass(AArch64::GPR32RegClassID).contains(Rm))
+    Rm = MRI.getMatchingSuperReg(Rm, AArch64::sub_32,
+                                 &MRI.getRegClass(AArch64::GPR64RegClassID));
+
+  unsigned SignExtend = MI->getOperand(3).getImm(); // encoded in "option<2>".
+  unsigned Shift = MI->getOperand(4).getImm();      // encoded in "S".
+
+  assert((SignExtend <= 1) && "sign extend should be a single bit!");
+  assert((Shift <= 1) && "Shift should be a single bit!");
+
+  unsigned Option0 = (Opcode == AArch64::PRFMroX) ? 1 : 0;
+
+  // encoded in "option<2>:option<0>:S:Rt<2:0>".
+  unsigned RPRFOp =
+      (SignExtend << 5) | (Option0 << 4) | (Shift << 3) | (PRFOp & 0x7);
+
+  O << "\trprfm ";
+  if (auto RPRFM = AArch64RPRFM::lookupRPRFMByEncoding(RPRFOp))
+    O << RPRFM->Name << ", ";
+  else
+    O << "#" << formatImm(RPRFOp) << ", ";
+  O << getRegisterName(Rm);
+  O << ", [";
+  printOperand(MI, 1, STI, O); // "Rn".
+  O << "]";
+
+  printAnnotation(O, Annot);
+
+  return true;
+}
+
 bool AArch64InstPrinter::printSysAlias(const MCInst *MI,
                                        const MCSubtargetInfo &STI,
                                        raw_ostream &O) {
 #ifndef NDEBUG
   unsigned Opcode = MI->getOpcode();
   assert(Opcode == AArch64::SYSxt && "Invalid opcode for SYS alias!");
 #endif
 
void AArch64InstPrinter::printAMIndexedWB(const MCInst *MI, unsigned OpNum,
   } else {
     assert(MO1.isExpr() && "Unexpected operand type!");
     O << ", ";
     MO1.getExpr()->print(O, &MAI);
   }
   O << ']';
 }
 
+void AArch64InstPrinter::printRPRFMOperand(const MCInst *MI, unsigned OpNum,
+                                           const MCSubtargetInfo &STI,
+                                           raw_ostream &O) {
+  unsigned prfop = MI->getOperand(OpNum).getImm();
+  if (auto PRFM = AArch64RPRFM::lookupRPRFMByEncoding(prfop)) {
+    O << PRFM->Name;
+    return;
+  }
+
+  O << '#' << formatImm(prfop);
+}
+
 template <bool IsSVEPrefetch>
 void AArch64InstPrinter::printPrefetchOp(const MCInst *MI, unsigned OpNum,
                                          const MCSubtargetInfo &STI,
                                          raw_ostream &O) {
   unsigned prfop = MI->getOperand(OpNum).getImm();
   if (IsSVEPrefetch) {
     if (auto PRFM = AArch64SVEPRFM::lookupSVEPRFMByEncoding(prfop)) {
       O << PRFM->Name;

llvm/lib/Target/AArch64/SVEInstrFormats.td

: I<(outs zprty:$Zdn), (ins zprty:$_Zdn, immtype:$imm),
   let Inst{4-0} = Zdn;
 
   let Constraints = "$Zdn = $_Zdn";
   let DestructiveInstType = DestructiveOther;
   let ElementSize = ElementSizeNone;
 }
 
 multiclass sve_int_arith_imm1<bits<2> opc, string asm, SDPatternOperator op> {
-  def _B : sve_int_arith_imm<0b00, { 0b1010, opc }, asm, ZPR8, simm8>;
-  def _H : sve_int_arith_imm<0b01, { 0b1010, opc }, asm, ZPR16, simm8>;
-  def _S : sve_int_arith_imm<0b10, { 0b1010, opc }, asm, ZPR32, simm8>;
-  def _D : sve_int_arith_imm<0b11, { 0b1010, opc }, asm, ZPR64, simm8>;
+  def _B : sve_int_arith_imm<0b00, { 0b1010, opc }, asm, ZPR8, simm8_32b>;
+  def _H : sve_int_arith_imm<0b01, { 0b1010, opc }, asm, ZPR16, simm8_32b>;
+  def _S : sve_int_arith_imm<0b10, { 0b1010, opc }, asm, ZPR32, simm8_32b>;
+  def _D : sve_int_arith_imm<0b11, { 0b1010, opc }, asm, ZPR64, simm8_32b>;
 
   def : SVE_1_Op_Imm_Arith_All_Active<nxv16i8, nxv16i1, op, ZPR8, i32, SVEArithSImmPat32, !cast<Instruction>(NAME # _B)>;
   def : SVE_1_Op_Imm_Arith_All_Active<nxv8i16, nxv8i1,  op, ZPR16, i32, SVEArithSImmPat32, !cast<Instruction>(NAME # _H)>;
   def : SVE_1_Op_Imm_Arith_All_Active<nxv4i32, nxv4i1,  op, ZPR32, i32, SVEArithSImmPat32, !cast<Instruction>(NAME # _S)>;
   def : SVE_1_Op_Imm_Arith_All_Active<nxv2i64, nxv2i1,  op, ZPR64, i64, SVEArithSImmPat64, !cast<Instruction>(NAME # _D)>;
 }
 
 multiclass sve_int_arith_imm1_unsigned<bits<2> opc, string asm, SDPatternOperator op> {
   def _B : sve_int_arith_imm<0b00, { 0b1010, opc }, asm, ZPR8, imm0_255>;
   def _H : sve_int_arith_imm<0b01, { 0b1010, opc }, asm, ZPR16, imm0_255>;
   def _S : sve_int_arith_imm<0b10, { 0b1010, opc }, asm, ZPR32, imm0_255>;
   def _D : sve_int_arith_imm<0b11, { 0b1010, opc }, asm, ZPR64, imm0_255>;
 
   def : SVE_1_Op_Imm_Arith_All_Active<nxv16i8, nxv16i1, op, ZPR8, i32, SVEArithUImm8Pat, !cast<Instruction>(NAME # _B)>;
   def : SVE_1_Op_Imm_Arith_All_Active<nxv8i16, nxv8i1, op, ZPR16, i32, SVEArithUImm16Pat, !cast<Instruction>(NAME # _H)>;
   def : SVE_1_Op_Imm_Arith_All_Active<nxv4i32, nxv4i1, op, ZPR32, i32, SVEArithUImm32Pat, !cast<Instruction>(NAME # _S)>;
   def : SVE_1_Op_Imm_Arith_All_Active<nxv2i64, nxv2i1, op, ZPR64, i64, SVEArithUImm64Pat, !cast<Instruction>(NAME # _D)>;
 }
 
 multiclass sve_int_arith_imm2<string asm, SDPatternOperator op> {
-  def _B : sve_int_arith_imm<0b00, 0b110000, asm, ZPR8,  simm8>;
-  def _H : sve_int_arith_imm<0b01, 0b110000, asm, ZPR16, simm8>;
-  def _S : sve_int_arith_imm<0b10, 0b110000, asm, ZPR32, simm8>;
-  def _D : sve_int_arith_imm<0b11, 0b110000, asm, ZPR64, simm8>;
+  def _B : sve_int_arith_imm<0b00, 0b110000, asm, ZPR8,  simm8_32b>;
+  def _H : sve_int_arith_imm<0b01, 0b110000, asm, ZPR16, simm8_32b>;
+  def _S : sve_int_arith_imm<0b10, 0b110000, asm, ZPR32, simm8_32b>;
+  def _D : sve_int_arith_imm<0b11, 0b110000, asm, ZPR64, simm8_32b>;
 
   def : SVE_1_Op_Imm_Arith_All_Active<nxv16i8, nxv16i1, op, ZPR8, i32, SVEArithSImmPat32, !cast<Instruction>(NAME # _B)>;
   def : SVE_1_Op_Imm_Arith_All_Active<nxv8i16, nxv8i1, op, ZPR16, i32, SVEArithSImmPat32, !cast<Instruction>(NAME # _H)>;
   def : SVE_1_Op_Imm_Arith_All_Active<nxv4i32, nxv4i1, op, ZPR32, i32, SVEArithSImmPat32, !cast<Instruction>(NAME # _S)>;
   def : SVE_1_Op_Imm_Arith_All_Active<nxv2i64, nxv2i1, op, ZPR64, i64, SVEArithSImmPat64, !cast<Instruction>(NAME # _D)>;
 }
 
 //===----------------------------------------------------------------------===//

llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h

 namespace AArch64SVEPRFM {
   struct SVEPRFM : SysAlias {
     using SysAlias::SysAlias;
   };
 #define GET_SVEPRFM_DECL
 #include "AArch64GenSystemOperands.inc"
 }
 
+namespace AArch64RPRFM {
+struct RPRFM : SysAlias {
+  using SysAlias::SysAlias;
+};
+#define GET_RPRFM_DECL
+#include "AArch64GenSystemOperands.inc"
+} // namespace AArch64RPRFM
+
 namespace AArch64SVEPredPattern {
   struct SVEPREDPAT {
     const char *Name;
     uint16_t Encoding;
   };
 #define GET_SVEPREDPAT_DECL
 #include "AArch64GenSystemOperands.inc"
 }

llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp

 namespace llvm {
   namespace AArch64SVEPRFM {
 #define GET_SVEPRFM_IMPL
 #include "AArch64GenSystemOperands.inc"
   }
 }
 
 namespace llvm {
+  namespace AArch64RPRFM {
+#define GET_RPRFM_IMPL
+#include "AArch64GenSystemOperands.inc"
+  } // namespace AArch64RPRFM
+} // namespace llvm
+
+namespace llvm {
   namespace AArch64SVEPredPattern {
 #define GET_SVEPREDPAT_IMPL
 #include "AArch64GenSystemOperands.inc"
   }
 }
 
 namespace llvm {
 namespace AArch64SVEVecLenSpecifier {

llvm/test/MC/AArch64/CSSC/abs_32.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+v9.4a < %s \
+// RUN:        | llvm-objdump -d --mattr=+v9.4a - | FileCheck %s --check-prefix=CHECK-INST
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+v9.4a -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+abs     w0, w0
+// CHECK-INST: abs     w0, w0
+// CHECK-ENCODING: [0x00,0x20,0xc0,0x5a]
+// CHECK-ERROR: instruction requires: cssc
+
+abs     w21, w10
+// CHECK-INST: abs     w21, w10
+// CHECK-ENCODING: [0x55,0x21,0xc0,0x5a]
+// CHECK-ERROR: instruction requires: cssc
+
+abs     w23, w13
+// CHECK-INST: abs     w23, w13
+// CHECK-ENCODING: [0xb7,0x21,0xc0,0x5a]
+// CHECK-ERROR: instruction requires: cssc
+
+abs     wzr, wzr
+// CHECK-INST: abs     wzr, wzr
+// CHECK-ENCODING: [0xff,0x23,0xc0,0x5a]
+// CHECK-ERROR: instruction requires: cssc

llvm/test/MC/AArch64/CSSC/abs_64.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+v9.4a < %s \
+// RUN:        | llvm-objdump -d --mattr=+v9.4a - | FileCheck %s --check-prefix=CHECK-INST
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+v9.4a -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+abs     x0, x0
+// CHECK-INST: abs     x0, x0
+// CHECK-ENCODING: [0x00,0x20,0xc0,0xda]
+// CHECK-ERROR: instruction requires: cssc
+
+abs     x21, x10
+// CHECK-INST: abs     x21, x10
+// CHECK-ENCODING: [0x55,0x21,0xc0,0xda]
+// CHECK-ERROR: instruction requires: cssc
+
+abs     x23, x13
+// CHECK-INST: abs     x23, x13
+// CHECK-ENCODING: [0xb7,0x21,0xc0,0xda]
+// CHECK-ERROR: instruction requires: cssc
+
+abs     xzr, xzr
+// CHECK-INST: abs     xzr, xzr
+// CHECK-ENCODING: [0xff,0x23,0xc0,0xda]
+// CHECK-ERROR: instruction requires: cssc

llvm/test/MC/AArch64/CSSC/cnt_32.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+v9.4a < %s \
+// RUN:        | llvm-objdump -d --mattr=+v9.4a - | FileCheck %s --check-prefix=CHECK-INST
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+v9.4a -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+cnt     w0, w0
+// CHECK-INST: cnt     w0, w0
+// CHECK-ENCODING: [0x00,0x1c,0xc0,0x5a]
+// CHECK-ERROR: instruction requires: cssc
+
+cnt     w21, w10
+// CHECK-INST: cnt     w21, w10
+// CHECK-ENCODING: [0x55,0x1d,0xc0,0x5a]
+// CHECK-ERROR: instruction requires: cssc
+
+cnt     w23, w13
+// CHECK-INST: cnt     w23, w13
+// CHECK-ENCODING: [0xb7,0x1d,0xc0,0x5a]
+// CHECK-ERROR: instruction requires: cssc
+
+cnt     wzr, wzr
+// CHECK-INST: cnt     wzr, wzr
+// CHECK-ENCODING: [0xff,0x1f,0xc0,0x5a]
+// CHECK-ERROR: instruction requires: cssc

llvm/test/MC/AArch64/CSSC/cnt_64.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+v9.4a < %s \
+// RUN:        | llvm-objdump -d --mattr=+v9.4a - | FileCheck %s --check-prefix=CHECK-INST
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+v9.4a -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+cnt     x0, x0
+// CHECK-INST: cnt     x0, x0
+// CHECK-ENCODING: [0x00,0x1c,0xc0,0xda]
+// CHECK-ERROR: instruction requires: cssc
+
+cnt     x21, x10
+// CHECK-INST: cnt     x21, x10
+// CHECK-ENCODING: [0x55,0x1d,0xc0,0xda]
+// CHECK-ERROR: instruction requires: cssc
+
+cnt     x23, x13
+// CHECK-INST: cnt     x23, x13
+// CHECK-ENCODING: [0xb7,0x1d,0xc0,0xda]
+// CHECK-ERROR: instruction requires: cssc
+
+cnt     xzr, xzr
+// CHECK-INST: cnt     xzr, xzr
+// CHECK-ENCODING: [0xff,0x1f,0xc0,0xda]
+// CHECK-ERROR: instruction requires: cssc

llvm/test/MC/AArch64/CSSC/ctz_32.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+v9.4a < %s \
+// RUN:        | llvm-objdump -d --mattr=+v9.4a - | FileCheck %s --check-prefix=CHECK-INST
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+v9.4a -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+ctz     w0, w0
+// CHECK-INST: ctz     w0, w0
+// CHECK-ENCODING: [0x00,0x18,0xc0,0x5a]
+// CHECK-ERROR: instruction requires: cssc
+
+ctz     w21, w10
+// CHECK-INST: ctz     w21, w10
+// CHECK-ENCODING: [0x55,0x19,0xc0,0x5a]
+// CHECK-ERROR: instruction requires: cssc
+
+ctz     w23, w13
+// CHECK-INST: ctz     w23, w13
+// CHECK-ENCODING: [0xb7,0x19,0xc0,0x5a]
+// CHECK-ERROR: instruction requires: cssc
+
+ctz     wzr, wzr
+// CHECK-INST: ctz     wzr, wzr
+// CHECK-ENCODING: [0xff,0x1b,0xc0,0x5a]
+// CHECK-ERROR: instruction requires: cssc

llvm/test/MC/AArch64/CSSC/ctz_64.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+v9.4a < %s \
+// RUN:        | llvm-objdump -d --mattr=+v9.4a - | FileCheck %s --check-prefix=CHECK-INST
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+v9.4a -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+ctz     x0, x0
+// CHECK-INST: ctz     x0, x0
+// CHECK-ENCODING: [0x00,0x18,0xc0,0xda]
+// CHECK-ERROR: instruction requires: cssc
+
+ctz     x21, x10
+// CHECK-INST: ctz     x21, x10
+// CHECK-ENCODING: [0x55,0x19,0xc0,0xda]
+// CHECK-ERROR: instruction requires: cssc
+
+ctz     x23, x13
+// CHECK-INST: ctz     x23, x13
+// CHECK-ENCODING: [0xb7,0x19,0xc0,0xda]
+// CHECK-ERROR: instruction requires: cssc
+
+ctz     xzr, xzr
+// CHECK-INST: ctz     xzr, xzr
+// CHECK-ENCODING: [0xff,0x1b,0xc0,0xda]
+// CHECK-ERROR: instruction requires: cssc

llvm/test/MC/AArch64/CSSC/smax_32_imm.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding --print-imm-hex=false -mattr=+v9.4a < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+v9.4a < %s \
+// RUN:        | llvm-objdump -d --print-imm-hex=false --mattr=+v9.4a - \
+// RUN:        | FileCheck %s --check-prefix=CHECK-INST
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+v9.4a -disassemble -show-encoding \
+// RUN:           --print-imm-hex=false \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+smax    w0, w0, #0
+// CHECK-INST: smax    w0, w0, #0
+// CHECK-ENCODING: [0x00,0x00,0xc0,0x11]
+// CHECK-ERROR: instruction requires: cssc
+
+smax    w21, w10, #85
+// CHECK-INST: smax    w21, w10, #85
+// CHECK-ENCODING: [0x55,0x55,0xc1,0x11]
+// CHECK-ERROR: instruction requires: cssc
+
+smax    w23, w13, #59
+// CHECK-INST: smax    w23, w13, #59
+// CHECK-ENCODING: [0xb7,0xed,0xc0,0x11]
+// CHECK-ERROR: instruction requires: cssc
+
+smax    wzr, wzr, #-1
+// CHECK-INST: smax    wzr, wzr, #-1
+// CHECK-ENCODING: [0xff,0xff,0xc3,0x11]
+// CHECK-ERROR: instruction requires: cssc
+

llvm/test/MC/AArch64/CSSC/smax_32_reg.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+v9.4a < %s \
+// RUN:        | llvm-objdump -d --mattr=+v9.4a - | FileCheck %s --check-prefix=CHECK-INST
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+v9.4a -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+smax    w0, w0, w0
+// CHECK-INST: smax    w0, w0, w0
+// CHECK-ENCODING: [0x00,0x60,0xc0,0x1a]
+// CHECK-ERROR: instruction requires: cssc
+
+smax    w21, w10, w21
+// CHECK-INST: smax    w21, w10, w21
+// CHECK-ENCODING: [0x55,0x61,0xd5,0x1a]
+// CHECK-ERROR: instruction requires: cssc
+
+smax    w23, w13, w8
+// CHECK-INST: smax    w23, w13, w8
+// CHECK-ENCODING: [0xb7,0x61,0xc8,0x1a]
+// CHECK-ERROR: instruction requires: cssc
+
+smax    wzr, wzr, wzr
+// CHECK-INST: smax    wzr, wzr, wzr
+// CHECK-ENCODING: [0xff,0x63,0xdf,0x1a]
+// CHECK-ERROR: instruction requires: cssc

llvm/test/MC/AArch64/CSSC/smax_64_imm.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding --print-imm-hex=false -mattr=+v9.4a < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+v9.4a < %s \
+// RUN:        | llvm-objdump -d --print-imm-hex=false --mattr=+v9.4a - \
+// RUN:        | FileCheck %s --check-prefix=CHECK-INST
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+v9.4a -disassemble -show-encoding \
+// RUN:           --print-imm-hex=false \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+smax    x0, x0, #0
+// CHECK-INST: smax    x0, x0, #0
+// CHECK-ENCODING: [0x00,0x00,0xc0,0x91]
+// CHECK-ERROR: instruction requires: cssc
+// CHECK-UNKNOWN: 00 00 c0 91 <unknown>
+
+smax    x21, x10, #85
+// CHECK-INST: smax    x21, x10, #85
+// CHECK-ENCODING: [0x55,0x55,0xc1,0x91]
+// CHECK-ERROR: instruction requires: cssc
+// CHECK-UNKNOWN: 55 55 c1 91 <unknown>
+
+smax    x23, x13, #59
+// CHECK-INST: smax    x23, x13, #59
+// CHECK-ENCODING: [0xb7,0xed,0xc0,0x91]
+// CHECK-ERROR: instruction requires: cssc
+// CHECK-UNKNOWN: b7 ed c0 91 <unknown>
+
+smax    xzr, xzr, #-1
+// CHECK-INST: smax    xzr, xzr, #-1
+// CHECK-ENCODING: [0xff,0xff,0xc3,0x91]
+// CHECK-ERROR: instruction requires: cssc
+// CHECK-UNKNOWN: ff ff c3 91 <unknown>
+

llvm/test/MC/AArch64/CSSC/smax_64_reg.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+v9.4a < %s \
+// RUN:        | llvm-objdump -d --mattr=+v9.4a - | FileCheck %s --check-prefix=CHECK-INST
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+v9.4a -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+smax    x0, x0, x0
+// CHECK-INST: smax    x0, x0, x0
+// CHECK-ENCODING: [0x00,0x60,0xc0,0x9a]
+// CHECK-ERROR: instruction requires: cssc
+
+smax    x21, x10, x21
+// CHECK-INST: smax    x21, x10, x21
+// CHECK-ENCODING: [0x55,0x61,0xd5,0x9a]
+// CHECK-ERROR: instruction requires: cssc
+
+smax    x23, x13, x8
+// CHECK-INST: smax    x23, x13, x8
+// CHECK-ENCODING: [0xb7,0x61,0xc8,0x9a]
+// CHECK-ERROR: instruction requires: cssc
+
+smax    xzr, xzr, xzr
+// CHECK-INST: smax    xzr, xzr, xzr
+// CHECK-ENCODING: [0xff,0x63,0xdf,0x9a]
+// CHECK-ERROR: instruction requires: cssc

llvm/test/MC/AArch64/CSSC/smin_32_imm.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding --print-imm-hex=false -mattr=+v9.4a < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+v9.4a < %s \
+// RUN:        | llvm-objdump -d --print-imm-hex=false --mattr=+v9.4a - \
+// RUN:        | FileCheck %s --check-prefix=CHECK-INST
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+v9.4a -disassemble -show-encoding \
+// RUN:           --print-imm-hex=false \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+smin    w0, w0, #0
+// CHECK-INST: smin    w0, w0, #0
+// CHECK-ENCODING: [0x00,0x00,0xc8,0x11]
+// CHECK-ERROR: instruction requires: cssc
+
+smin    w21, w10, #85
+// CHECK-INST: smin    w21, w10, #85
+// CHECK-ENCODING: [0x55,0x55,0xc9,0x11]
+// CHECK-ERROR: instruction requires: cssc
+
+smin    w23, w13, #59
+// CHECK-INST: smin    w23, w13, #59
+// CHECK-ENCODING: [0xb7,0xed,0xc8,0x11]
+// CHECK-ERROR: instruction requires: cssc
+
+smin    wzr, wzr, #-1
+// CHECK-INST: smin    wzr, wzr, #-1
+// CHECK-ENCODING: [0xff,0xff,0xcb,0x11]
+// CHECK-ERROR: instruction requires: cssc

llvm/test/MC/AArch64/CSSC/smin_32_reg.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+v9.4a < %s \
+// RUN:        | llvm-objdump -d --mattr=+v9.4a - | FileCheck %s --check-prefix=CHECK-INST
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+v9.4a -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+smin    w0, w0, w0
+// CHECK-INST: smin    w0, w0, w0
+// CHECK-ENCODING: [0x00,0x68,0xc0,0x1a]
+// CHECK-ERROR: instruction requires: cssc
+
+smin    w21, w10, w21
+// CHECK-INST: smin    w21, w10, w21
+// CHECK-ENCODING: [0x55,0x69,0xd5,0x1a]
+// CHECK-ERROR: instruction requires: cssc
+
+smin    w23, w13, w8
+// CHECK-INST: smin    w23, w13, w8
+// CHECK-ENCODING: [0xb7,0x69,0xc8,0x1a]
+// CHECK-ERROR: instruction requires: cssc
+
+smin    wzr, wzr, wzr
+// CHECK-INST: smin    wzr, wzr, wzr
+// CHECK-ENCODING: [0xff,0x6b,0xdf,0x1a]
+// CHECK-ERROR: instruction requires: cssc

llvm/test/MC/AArch64/CSSC/smin_64_imm.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding --print-imm-hex=false -mattr=+v9.4a < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+v9.4a < %s \
+// RUN:        | llvm-objdump -d --print-imm-hex=false --mattr=+v9.4a - \
+// RUN:        | FileCheck %s --check-prefix=CHECK-INST
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+v9.4a -disassemble -show-encoding \
+// RUN:           --print-imm-hex=false \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+smin    x0, x0, #0
+// CHECK-INST: smin    x0, x0, #0
+// CHECK-ENCODING: [0x00,0x00,0xc8,0x91]
+// CHECK-ERROR: instruction requires: cssc
+
+smin    x21, x10, #85
+// CHECK-INST: smin    x21, x10, #85
+// CHECK-ENCODING: [0x55,0x55,0xc9,0x91]
+// CHECK-ERROR: instruction requires: cssc
+
+smin    x23, x13, #59
+// CHECK-INST: smin    x23, x13, #59
+// CHECK-ENCODING: [0xb7,0xed,0xc8,0x91]
+// CHECK-ERROR: instruction requires: cssc
+
+smin    xzr, xzr, #-1
+// CHECK-INST: smin    xzr, xzr, #-1
+// CHECK-ENCODING: [0xff,0xff,0xcb,0x91]
+// CHECK-ERROR: instruction requires: cssc

llvm/test/MC/AArch64/CSSC/smin_64_reg.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+v9.4a < %s \
+// RUN:        | llvm-objdump -d --mattr=+v9.4a - | FileCheck %s --check-prefix=CHECK-INST
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+v9.4a -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+smin    x0, x0, x0
+// CHECK-INST: smin    x0, x0, x0
+// CHECK-ENCODING: [0x00,0x68,0xc0,0x9a]
+// CHECK-ERROR: instruction requires: cssc
+
+smin    x21, x10, x21
+// CHECK-INST: smin    x21, x10, x21
+// CHECK-ENCODING: [0x55,0x69,0xd5,0x9a]
+// CHECK-ERROR: instruction requires: cssc
+
+smin    x23, x13, x8
+// CHECK-INST: smin    x23, x13, x8
+// CHECK-ENCODING: [0xb7,0x69,0xc8,0x9a]
+// CHECK-ERROR: instruction requires: cssc
+
+smin    xzr, xzr, xzr
+// CHECK-INST: smin    xzr, xzr, xzr
+// CHECK-ENCODING: [0xff,0x6b,0xdf,0x9a]
+// CHECK-ERROR: instruction requires: cssc

llvm/test/MC/AArch64/CSSC/umax_32_imm.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding --print-imm-hex=false -mattr=+v9.4a < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+v9.4a < %s \
+// RUN:        | llvm-objdump -d --print-imm-hex=false --mattr=+v9.4a - \
+// RUN:        | FileCheck %s --check-prefix=CHECK-INST
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+v9.4a -disassemble -show-encoding \
+// RUN:           --print-imm-hex=false \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+umax    w0, w0, #0
+// CHECK-INST: umax    w0, w0, #0
+// CHECK-ENCODING: [0x00,0x00,0xc4,0x11]
+// CHECK-ERROR: instruction requires: cssc
+
+umax    w21, w10, #85
+// CHECK-INST: umax    w21, w10, #85
+// CHECK-ENCODING: [0x55,0x55,0xc5,0x11]
+// CHECK-ERROR: instruction requires: cssc
+
+umax    w23, w13, #59
+// CHECK-INST: umax    w23, w13, #59
+// CHECK-ENCODING: [0xb7,0xed,0xc4,0x11]
+// CHECK-ERROR: instruction requires: cssc
+
+umax    wzr, wzr, #255
+// CHECK-INST: umax    wzr, wzr, #255
+// CHECK-ENCODING: [0xff,0xff,0xc7,0x11]
+// CHECK-ERROR: instruction requires: cssc

llvm/test/MC/AArch64/CSSC/umax_32_reg.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+v9.4a < %s \
+// RUN:        | llvm-objdump -d --mattr=+v9.4a - | FileCheck %s --check-prefix=CHECK-INST
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+v9.4a -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+umax    w0, w0, w0
+// CHECK-INST: umax    w0, w0, w0
+// CHECK-ENCODING: [0x00,0x64,0xc0,0x1a]
+// CHECK-ERROR: instruction requires: cssc
+
+umax    w21, w10, w21
+// CHECK-INST: umax    w21, w10, w21
+// CHECK-ENCODING: [0x55,0x65,0xd5,0x1a]
+// CHECK-ERROR: instruction requires: cssc
+
+umax    w23, w13, w8
+// CHECK-INST: umax    w23, w13, w8
+// CHECK-ENCODING: [0xb7,0x65,0xc8,0x1a]
+// CHECK-ERROR: instruction requires: cssc
+
+umax    wzr, wzr, wzr
+// CHECK-INST: umax    wzr, wzr, wzr
+// CHECK-ENCODING: [0xff,0x67,0xdf,0x1a]
+// CHECK-ERROR: instruction requires: cssc

llvm/test/MC/AArch64/CSSC/umax_64_imm.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding --print-imm-hex=false -mattr=+v9.4a < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+v9.4a < %s \
+// RUN:        | llvm-objdump -d --print-imm-hex=false --mattr=+v9.4a - \
+// RUN:        | FileCheck %s --check-prefix=CHECK-INST
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+v9.4a -disassemble -show-encoding \
+// RUN:           --print-imm-hex=false \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+umax    x0, x0, #0
+// CHECK-INST: umax    x0, x0, #0
+// CHECK-ENCODING: [0x00,0x00,0xc4,0x91]
+// CHECK-ERROR: instruction requires: cssc
+
+umax    x21, x10, #85
+// CHECK-INST: umax    x21, x10, #85
+// CHECK-ENCODING: [0x55,0x55,0xc5,0x91]
+// CHECK-ERROR: instruction requires: cssc
+
+umax    x23, x13, #59
+// CHECK-INST: umax    x23, x13, #59
+// CHECK-ENCODING: [0xb7,0xed,0xc4,0x91]
+// CHECK-ERROR: instruction requires: cssc
+
+umax    xzr, xzr, #255
+// CHECK-INST: umax    xzr, xzr, #255
+// CHECK-ENCODING: [0xff,0xff,0xc7,0x91]
+// CHECK-ERROR: instruction requires: cssc

llvm/test/MC/AArch64/CSSC/umax_64_reg.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+v9.4a < %s \
+// RUN:        | llvm-objdump -d --mattr=+v9.4a - | FileCheck %s --check-prefix=CHECK-INST
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+v9.4a -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+umax    x0, x0, x0
+// CHECK-INST: umax    x0, x0, x0
+// CHECK-ENCODING: [0x00,0x64,0xc0,0x9a]
+// CHECK-ERROR: instruction requires: cssc
+
+umax    x21, x10, x21
+// CHECK-INST: umax    x21, x10, x21
+// CHECK-ENCODING: [0x55,0x65,0xd5,0x9a]
+// CHECK-ERROR: instruction requires: cssc
+
+umax    x23, x13, x8
+// CHECK-INST: umax    x23, x13, x8
+// CHECK-ENCODING: [0xb7,0x65,0xc8,0x9a]
+// CHECK-ERROR: instruction requires: cssc
+
+umax    xzr, xzr, xzr
+// CHECK-INST: umax    xzr, xzr, xzr
+// CHECK-ENCODING: [0xff,0x67,0xdf,0x9a]
+// CHECK-ERROR: instruction requires: cssc

llvm/test/MC/AArch64/CSSC/umin_32_imm.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding --print-imm-hex=false -mattr=+v9.4a < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+v9.4a < %s \
+// RUN:        | llvm-objdump -d --print-imm-hex=false --mattr=+v9.4a - \
+// RUN:        | FileCheck %s --check-prefix=CHECK-INST
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+v9.4a -disassemble -show-encoding \
+// RUN:           --print-imm-hex=false \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+umin    w0, w0, #0
+// CHECK-INST: umin    w0, w0, #0
+// CHECK-ENCODING: [0x00,0x00,0xcc,0x11]
+// CHECK-ERROR: instruction requires: cssc
+
+umin    w21, w10, #85
+// CHECK-INST: umin    w21, w10, #85
+// CHECK-ENCODING: [0x55,0x55,0xcd,0x11]
+// CHECK-ERROR: instruction requires: cssc
+
+umin    w23, w13, #59
+// CHECK-INST: umin    w23, w13, #59
+// CHECK-ENCODING: [0xb7,0xed,0xcc,0x11]
+// CHECK-ERROR: instruction requires: cssc
+
+umin    wzr, wzr, #255
+// CHECK-INST: umin    wzr, wzr, #255
+// CHECK-ENCODING: [0xff,0xff,0xcf,0x11]
+// CHECK-ERROR: instruction requires: cssc

llvm/test/MC/AArch64/CSSC/umin_32_reg.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+v9.4a < %s \
+// RUN:        | llvm-objdump -d --mattr=+v9.4a - | FileCheck %s --check-prefix=CHECK-INST
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+v9.4a -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+umin    w0, w0, w0
+// CHECK-INST: umin    w0, w0, w0
+// CHECK-ENCODING: [0x00,0x6c,0xc0,0x1a]
+// CHECK-ERROR: instruction requires: cssc
+
+umin    w21, w10, w21
+// CHECK-INST: umin    w21, w10, w21
+// CHECK-ENCODING: [0x55,0x6d,0xd5,0x1a]
+// CHECK-ERROR: instruction requires: cssc
+
+umin    w23, w13, w8
+// CHECK-INST: umin    w23, w13, w8
+// CHECK-ENCODING: [0xb7,0x6d,0xc8,0x1a]
+// CHECK-ERROR: instruction requires: cssc
+
+umin    wzr, wzr, wzr
+// CHECK-INST: umin    wzr, wzr, wzr
+// CHECK-ENCODING: [0xff,0x6f,0xdf,0x1a]
+// CHECK-ERROR: instruction requires: cssc

llvm/test/MC/AArch64/CSSC/umin_64_imm.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding --print-imm-hex=false -mattr=+v9.4a < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+v9.4a < %s \
+// RUN:        | llvm-objdump -d --print-imm-hex=false --mattr=+v9.4a - \
+// RUN:        | FileCheck %s --check-prefix=CHECK-INST
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+v9.4a -disassemble -show-encoding \
+// RUN:           --print-imm-hex=false \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+umin    x0, x0, #0
+// CHECK-INST: umin    x0, x0, #0
+// CHECK-ENCODING: [0x00,0x00,0xcc,0x91]
+// CHECK-ERROR: instruction requires: cssc
+
+umin    x21, x10, #85
+// CHECK-INST: umin    x21, x10, #85
+// CHECK-ENCODING: [0x55,0x55,0xcd,0x91]
+// CHECK-ERROR: instruction requires: cssc
+
+umin    x23, x13, #59
+// CHECK-INST: umin    x23, x13, #59
+// CHECK-ENCODING: [0xb7,0xed,0xcc,0x91]
+// CHECK-ERROR: instruction requires: cssc
+
+umin    xzr, xzr, #255
+// CHECK-INST: umin    xzr, xzr, #255
+// CHECK-ENCODING: [0xff,0xff,0xcf,0x91]
+// CHECK-ERROR: instruction requires: cssc

llvm/test/MC/AArch64/CSSC/umin_64_reg.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+v9.4a < %s \
+// RUN:        | llvm-objdump -d --mattr=+v9.4a - | FileCheck %s --check-prefix=CHECK-INST
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+v9.4a -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+umin    x0, x0, x0
+// CHECK-INST: umin    x0, x0, x0
+// CHECK-ENCODING: [0x00,0x6c,0xc0,0x9a]
+// CHECK-ERROR: instruction requires: cssc
+
+umin    x21, x10, x21
+// CHECK-INST: umin    x21, x10, x21
+// CHECK-ENCODING: [0x55,0x6d,0xd5,0x9a]
+// CHECK-ERROR: instruction requires: cssc
+
+umin    x23, x13, x8
+// CHECK-INST: umin    x23, x13, x8
+// CHECK-ENCODING: [0xb7,0x6d,0xc8,0x9a]
+// CHECK-ERROR: instruction requires: cssc
+
+umin    xzr, xzr, xzr
+// CHECK-INST: umin    xzr, xzr, xzr
+// CHECK-ENCODING: [0xff,0x6f,0xdf,0x9a]
+// CHECK-ERROR: instruction requires: cssc

llvm/test/MC/AArch64/armv8.9a-cssc.s

+// RUN:     llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v9.4a < %s      | FileCheck %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu                -mattr=+v8.8a < %s 2>&1 | FileCheck --check-prefix=NO-CSSC-ERR %s
+// RUN:     llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.9a < %s      | FileCheck %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu                -mattr=+v9.3a < %s 2>&1 | FileCheck --check-prefix=NO-CSSC-ERR %s
+
+            abs     x0, x1
+// CHECK:   abs     x0, x1       // encoding: [0x20,0x20,0xc0,0xda]
+// NO-CSSC-ERR: [[@LINE-2]]:13: error: instruction requires: cssc
+            abs     w0, w1
+// CHECK:   abs     w0, w1       // encoding: [0x20,0x20,0xc0,0x5a]
+// NO-CSSC-ERR: [[@LINE-2]]:13: error: instruction requires: cssc
+            cnt     x0, x1
+// CHECK:   cnt     x0, x1       // encoding: [0x20,0x1c,0xc0,0xda]
+// NO-CSSC-ERR: [[@LINE-2]]:13: error: instruction requires: cssc
+            cnt     w0, w1
+// CHECK:   cnt     w0, w1       // encoding: [0x20,0x1c,0xc0,0x5a]
+// NO-CSSC-ERR: [[@LINE-2]]:13: error: instruction requires: cssc
+            ctz     x0, x1
+// CHECK:   ctz     x0, x1       // encoding: [0x20,0x18,0xc0,0xda]
+// NO-CSSC-ERR: [[@LINE-2]]:13: error: instruction requires: cssc
+            ctz     w0, w1
+// CHECK:   ctz     w0, w1       // encoding: [0x20,0x18,0xc0,0x5a]
+// NO-CSSC-ERR: [[@LINE-2]]:13: error: instruction requires: cssc
+
+            smax    x1, x2, x3
+// CHECK:   smax    x1, x2, x3   // encoding: [0x41,0x60,0xc3,0x9a]
+// NO-CSSC-ERR: [[@LINE-2]]:13: error: instruction requires: cssc
+            smax    x1, x2, #3
+// CHECK:   smax    x1, x2, #3   // encoding: [0x41,0x0c,0xc0,0x91]
+// NO-CSSC-ERR: [[@LINE-2]]:13: error: instruction requires: cssc
+            smax    w1, w2, w3
+// CHECK:   smax    w1, w2, w3   // encoding: [0x41,0x60,0xc3,0x1a]
+// NO-CSSC-ERR: [[@LINE-2]]:13: error: instruction requires: cssc
+            smax    w1, w2, #3
+// CHECK:   smax    w1, w2, #3   // encoding: [0x41,0x0c,0xc0,0x11]
+// NO-CSSC-ERR: [[@LINE-2]]:13: error: instruction requires: cssc
+            smin    x1, x2, x3
+// CHECK:   smin    x1, x2, x3   // encoding: [0x41,0x68,0xc3,0x9a]
+// NO-CSSC-ERR: [[@LINE-2]]:13: error: instruction requires: cssc
+            smin    x1, x2, #3
+// CHECK:   smin    x1, x2, #3   // encoding: [0x41,0x0c,0xc8,0x91]
+// NO-CSSC-ERR: [[@LINE-2]]:13: error: instruction requires: cssc
+            smin    w1, w2, w3
+// CHECK:   smin    w1, w2, w3   // encoding: [0x41,0x68,0xc3,0x1a]
+// NO-CSSC-ERR: [[@LINE-2]]:13: error: instruction requires: cssc
+            smin    w1, w2, #3
+// CHECK:   smin    w1, w2, #3   // encoding: [0x41,0x0c,0xc8,0x11]
+// NO-CSSC-ERR: [[@LINE-2]]:13: error: instruction requires: cssc
+            umax    x1, x2, x3
+// CHECK:   umax    x1, x2, x3   // encoding: [0x41,0x64,0xc3,0x9a]
+// NO-CSSC-ERR: [[@LINE-2]]:13: error: instruction requires: cssc
+            umax    x1, x2, #3
+// CHECK:   umax    x1, x2, #3   // encoding: [0x41,0x0c,0xc4,0x91]
+// NO-CSSC-ERR: [[@LINE-2]]:13: error: instruction requires: cssc
+            umax    w1, w2, w3
+// CHECK:   umax    w1, w2, w3   // encoding: [0x41,0x64,0xc3,0x1a]
+// NO-CSSC-ERR: [[@LINE-2]]:13: error: instruction requires: cssc
+            umax    w1, w2, #3
+// CHECK:   umax    w1, w2, #3   // encoding: [0x41,0x0c,0xc4,0x11]
+// NO-CSSC-ERR: [[@LINE-2]]:13: error: instruction requires: cssc
+            umin    x1, x2, x3
+// CHECK:   umin    x1, x2, x3   // encoding: [0x41,0x6c,0xc3,0x9a]
+// NO-CSSC-ERR: [[@LINE-2]]:13: error: instruction requires: cssc
+            umin    x1, x2, #3
+// CHECK:   umin    x1, x2, #3   // encoding: [0x41,0x0c,0xcc,0x91]
+// NO-CSSC-ERR: [[@LINE-2]]:13: error: instruction requires: cssc
+            umin    w1, w2, w3
+// CHECK:   umin    w1, w2, w3   // encoding: [0x41,0x6c,0xc3,0x1a]
+// NO-CSSC-ERR: [[@LINE-2]]:13: error: instruction requires: cssc
+            umin    w1, w2, #3
+// CHECK:   umin    w1, w2, #3   // encoding: [0x41,0x0c,0xcc,0x11]
+// NO-CSSC-ERR: [[@LINE-2]]:13: error: instruction requires: cssc
+
+
+            umax    wzr, wzr, #255
+// CHECK:   umax    wzr, wzr, #255    // encoding: [0xff,0xff,0xc7,0x11]
+// NO-CSSC-ERR: [[@LINE-2]]:13: error: instruction requires: cssc
+            umax    xzr, xzr, #255
+// CHECK:   umax    xzr, xzr, #255    // encoding: [0xff,0xff,0xc7,0x91]
+// NO-CSSC-ERR: [[@LINE-2]]:13: error: instruction requires: cssc
+            umin    xzr, xzr, #255
+// CHECK:   umin    xzr, xzr, #255     // encoding: [0xff,0xff,0xcf,0x91]
+// NO-CSSC-ERR: [[@LINE-2]]:13: error: instruction requires: cssc
+            umin    wzr, wzr, #255
+// CHECK:   umin    wzr, wzr, #255    // encoding: [0xff,0xff,0xcf,0x11]
+// NO-CSSC-ERR: [[@LINE-2]]:13: error: instruction requires: cssc
+            smax    xzr, xzr, #-1
+// CHECK:   smax    xzr, xzr, #-1     // encoding: [0xff,0xff,0xc3,0x91]
+// NO-CSSC-ERR: [[@LINE-2]]:13: error: instruction requires: cssc
+            smax    wzr, wzr, #-1
+// CHECK:   smax    wzr, wzr, #-1     // encoding: [0xff,0xff,0xc3,0x11]
+// NO-CSSC-ERR: [[@LINE-2]]:13: error: instruction requires: cssc
+            smin    xzr, xzr, #-1
+// CHECK:   smin    xzr, xzr, #-1     // encoding: [0xff,0xff,0xcb,0x91]
+// NO-CSSC-ERR: [[@LINE-2]]:13: error: instruction requires: cssc
+            smin    wzr, wzr, #-1
+// CHECK:   smin    wzr, wzr, #-1   // encoding: [0xff,0xff,0xcb,0x11]
+// NO-CSSC-ERR: [[@LINE-2]]:13: error: instruction requires: cssc

llvm/test/MC/AArch64/rprfm.s

+// RPRFM is now a v8.0a optional instruction, and overlaps with PRFM. This test
+// checks we can assemble as PRFM, and we always disassemble as RPRFM.
+
+// RUN: llvm-mc -triple=aarch64 -show-encoding --print-imm-hex=false < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj < %s \
+// RUN:        | llvm-objdump -d --print-imm-hex=false - | FileCheck %s --check-prefix=CHECK-INST
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -disassemble -show-encoding --print-imm-hex=false \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+rprfm #0, x0, [x0]
+// CHECK-INST: rprfm pldkeep, x0, [x0]
+// CHECK-ENCODING: [0x18,0x48,0xa0,0xf8]
+
+rprfm #1, x0, [x0]
+// CHECK-INST: rprfm pstkeep, x0, [x0]
+// CHECK-ENCODING: [0x19,0x48,0xa0,0xf8]
+
+rprfm #2, x0, [x0]
+// CHECK-INST: rprfm #2, x0, [x0]
+// CHECK-ENCODING: [0x1a,0x48,0xa0,0xf8]
+
+rprfm #3, x0, [x0]
+// CHECK-INST: rprfm #3, x0, [x0]
+// CHECK-ENCODING: [0x1b,0x48,0xa0,0xf8]
+
+rprfm #4, x0, [x0]
+// CHECK-INST: rprfm pldstrm, x0, [x0]
+// CHECK-ENCODING: [0x1c,0x48,0xa0,0xf8]
+
+rprfm #5, x0, [x0]
+// CHECK-INST: rprfm pststrm, x0, [x0]
+// CHECK-ENCODING: [0x1d,0x48,0xa0,0xf8]
+
+rprfm #6, x0, [x0]
+// CHECK-INST: rprfm #6, x0, [x0]
+// CHECK-ENCODING: [0x1e,0x48,0xa0,0xf8]
+
+rprfm #7, x0, [x0]
+// CHECK-INST: rprfm #7, x0, [x0]
+// CHECK-ENCODING: [0x1f,0x48,0xa0,0xf8]
+
+rprfm #8, x0, [x0]
+// CHECK-INST: rprfm #8, x0, [x0]
+// CHECK-ENCODING: [0x18,0x58,0xa0,0xf8]
+
+rprfm #9, x0, [x0]
+// CHECK-INST: rprfm #9, x0, [x0]
+// CHECK-ENCODING: [0x19,0x58,0xa0,0xf8]
+
+rprfm #10, x0, [x0]
+// CHECK-INST: rprfm #10, x0, [x0]
+// CHECK-ENCODING: [0x1a,0x58,0xa0,0xf8]
+
+rprfm #11, x0, [x0]
+// CHECK-INST: rprfm #11, x0, [x0]
+// CHECK-ENCODING: [0x1b,0x58,0xa0,0xf8]
+
+rprfm #12, x0, [x0]
+// CHECK-INST: rprfm #12, x0, [x0]
+// CHECK-ENCODING: [0x1c,0x58,0xa0,0xf8]
+
+rprfm #13, x0, [x0]
+// CHECK-INST: rprfm #13, x0, [x0]
+// CHECK-ENCODING: [0x1d,0x58,0xa0,0xf8]
+
+rprfm #14, x0, [x0]
+// CHECK-INST: rprfm #14, x0, [x0]
+// CHECK-ENCODING: [0x1e,0x58,0xa0,0xf8]
+
+rprfm #15, x0, [x0]
+// CHECK-INST: rprfm #15, x0, [x0]
+// CHECK-ENCODING: [0x1f,0x58,0xa0,0xf8]
+
+rprfm #16, x0, [x0]
+// CHECK-INST: rprfm #16, x0, [x0]
+// CHECK-ENCODING: [0x18,0x68,0xa0,0xf8]
+
+rprfm #17, x0, [x0]
+// CHECK-INST: rprfm #17, x0, [x0]
+// CHECK-ENCODING: [0x19,0x68,0xa0,0xf8]
+
+rprfm #18, x0, [x0]
+// CHECK-INST: rprfm #18, x0, [x0]
+// CHECK-ENCODING: [0x1a,0x68,0xa0,0xf8]
+
+rprfm #19, x0, [x0]
+// CHECK-INST: rprfm #19, x0, [x0]
+// CHECK-ENCODING: [0x1b,0x68,0xa0,0xf8]
+
+rprfm #20, x0, [x0]
+// CHECK-INST: rprfm #20, x0, [x0]
+// CHECK-ENCODING: [0x1c,0x68,0xa0,0xf8]
+
+rprfm #21, x0, [x0]
+// CHECK-INST: rprfm #21, x0, [x0]
+// CHECK-ENCODING: [0x1d,0x68,0xa0,0xf8]
+
+rprfm #22, x0, [x0]
+// CHECK-INST: rprfm #22, x0, [x0]
+// CHECK-ENCODING: [0x1e,0x68,0xa0,0xf8]
+
+rprfm #23, x0, [x0]
+// CHECK-INST: rprfm #23, x0, [x0]
+// CHECK-ENCODING: [0x1f,0x68,0xa0,0xf8]
+
+rprfm #24, x0, [x0]
+// CHECK-INST: rprfm #24, x0, [x0]
+// CHECK-ENCODING: [0x18,0x78,0xa0,0xf8]
+
+rprfm #25, x0, [x0]
+// CHECK-INST: rprfm #25, x0, [x0]
+// CHECK-ENCODING: [0x19,0x78,0xa0,0xf8]
+
+rprfm #26, x0, [x0]
+// CHECK-INST: rprfm #26, x0, [x0]
+// CHECK-ENCODING: [0x1a,0x78,0xa0,0xf8]
+
+rprfm #27, x0, [x0]
+// CHECK-INST: rprfm #27, x0, [x0]
+// CHECK-ENCODING: [0x1b,0x78,0xa0,0xf8]
+
+rprfm #28, x0, [x0]
+// CHECK-INST: rprfm #28, x0, [x0]
+// CHECK-ENCODING: [0x1c,0x78,0xa0,0xf8]
+
+rprfm #29, x0, [x0]
+// CHECK-INST: rprfm #29, x0, [x0]
+// CHECK-ENCODING: [0x1d,0x78,0xa0,0xf8]
+
+rprfm #30, x0, [x0]
+// CHECK-INST: rprfm #30, x0, [x0]
+// CHECK-ENCODING: [0x1e,0x78,0xa0,0xf8]
+
+rprfm #31, x0, [x0]
+// CHECK-INST: rprfm #31, x0, [x0]
+// CHECK-ENCODING: [0x1f,0x78,0xa0,0xf8]
+
+rprfm #32, x0, [x0]
+// CHECK-INST: rprfm #32, x0, [x0]
+// CHECK-ENCODING: [0x18,0xc8,0xa0,0xf8]
+
+rprfm #33, x0, [x0]
+// CHECK-INST: rprfm #33, x0, [x0]
+// CHECK-ENCODING: [0x19,0xc8,0xa0,0xf8]
+
+rprfm #34, x0, [x0]
+// CHECK-INST: rprfm #34, x0, [x0]
+// CHECK-ENCODING: [0x1a,0xc8,0xa0,0xf8]
+
+rprfm #35, x0, [x0]
+// CHECK-INST: rprfm #35, x0, [x0]
+// CHECK-ENCODING: [0x1b,0xc8,0xa0,0xf8]
+
+rprfm #36, x0, [x0]
+// CHECK-INST: rprfm #36, x0, [x0]
+// CHECK-ENCODING: [0x1c,0xc8,0xa0,0xf8]
+
+rprfm #37, x0, [x0]
+// CHECK-INST: rprfm #37, x0, [x0]
+// CHECK-ENCODING: [0x1d,0xc8,0xa0,0xf8]
+
+rprfm #38, x0, [x0]
+// CHECK-INST: rprfm #38, x0, [x0]
+// CHECK-ENCODING: [0x1e,0xc8,0xa0,0xf8]
+
+rprfm #39, x0, [x0]
+// CHECK-INST: rprfm #39, x0, [x0]
+// CHECK-ENCODING: [0x1f,0xc8,0xa0,0xf8]
+
+rprfm #40, x0, [x0]
+// CHECK-INST: rprfm #40, x0, [x0]
+// CHECK-ENCODING: [0x18,0xd8,0xa0,0xf8]
+
+rprfm #41, x0, [x0]
+// CHECK-INST: rprfm #41, x0, [x0]
+// CHECK-ENCODING: [0x19,0xd8,0xa0,0xf8]
+
+rprfm #42, x0, [x0]
+// CHECK-INST: rprfm #42, x0, [x0]
+// CHECK-ENCODING: [0x1a,0xd8,0xa0,0xf8]
+
+rprfm #43, x0, [x0]
+// CHECK-INST: rprfm #43, x0, [x0]
+// CHECK-ENCODING: [0x1b,0xd8,0xa0,0xf8]
+
+rprfm #44, x0, [x0]
+// CHECK-INST: rprfm #44, x0, [x0]
+// CHECK-ENCODING: [0x1c,0xd8,0xa0,0xf8]
+
+rprfm #45, x0, [x0]
+// CHECK-INST: rprfm #45, x0, [x0]
+// CHECK-ENCODING: [0x1d,0xd8,0xa0,0xf8]
+
+rprfm #46, x0, [x0]
+// CHECK-INST: rprfm #46, x0, [x0]
+// CHECK-ENCODING: [0x1e,0xd8,0xa0,0xf8]
+
+rprfm #47, x0, [x0]
+// CHECK-INST: rprfm #47, x0, [x0]
+// CHECK-ENCODING: [0x1f,0xd8,0xa0,0xf8]
+
+rprfm #48, x0, [x0]
+// CHECK-INST: rprfm #48, x0, [x0]
+// CHECK-ENCODING: [0x18,0xe8,0xa0,0xf8]
+
+rprfm #49, x0, [x0]
+// CHECK-INST: rprfm #49, x0, [x0]
+// CHECK-ENCODING: [0x19,0xe8,0xa0,0xf8]
+
+rprfm #50, x0, [x0]
+// CHECK-INST: rprfm #50, x0, [x0]
+// CHECK-ENCODING: [0x1a,0xe8,0xa0,0xf8]
+
+rprfm #51, x0, [x0]
+// CHECK-INST: rprfm #51, x0, [x0]
+// CHECK-ENCODING: [0x1b,0xe8,0xa0,0xf8]
+
+rprfm #52, x0, [x0]
+// CHECK-INST: rprfm #52, x0, [x0]
+// CHECK-ENCODING: [0x1c,0xe8,0xa0,0xf8]
+
+rprfm #53, x0, [x0]
+// CHECK-INST: rprfm #53, x0, [x0]
+// CHECK-ENCODING: [0x1d,0xe8,0xa0,0xf8]
+
+rprfm #54, x0, [x0]
+// CHECK-INST: rprfm #54, x0, [x0]
+// CHECK-ENCODING: [0x1e,0xe8,0xa0,0xf8]
+
+rprfm #55, x0, [x0]
+// CHECK-INST: rprfm #55, x0, [x0]
+// CHECK-ENCODING: [0x1f,0xe8,0xa0,0xf8]
+
+rprfm #56, x0, [x0]
+// CHECK-INST: rprfm #56, x0, [x0]
+// CHECK-ENCODING: [0x18,0xf8,0xa0,0xf8]
+
+rprfm #57, x0, [x0]
+// CHECK-INST: rprfm #57, x0, [x0]
+// CHECK-ENCODING: [0x19,0xf8,0xa0,0xf8]
+
+rprfm #58, x0, [x0]
+// CHECK-INST: rprfm #58, x0, [x0]
+// CHECK-ENCODING: [0x1a,0xf8,0xa0,0xf8]
+
+rprfm #59, x0, [x0]
+// CHECK-INST: rprfm #59, x0, [x0]
+// CHECK-ENCODING: [0x1b,0xf8,0xa0,0xf8]
+
+rprfm #60, x0, [x0]
+// CHECK-INST: rprfm #60, x0, [x0]
+// CHECK-ENCODING: [0x1c,0xf8,0xa0,0xf8]
+
+rprfm #61, x0, [x0]
+// CHECK-INST: rprfm #61, x0, [x0]
+// CHECK-ENCODING: [0x1d,0xf8,0xa0,0xf8]
+
+rprfm #62, x0, [x0]
+// CHECK-INST: rprfm #62, x0, [x0]
+// CHECK-ENCODING: [0x1e,0xf8,0xa0,0xf8]
+
+rprfm #63, x0, [x0]
+// CHECK-INST: rprfm #63, x0, [x0]
+// CHECK-ENCODING: [0x1f,0xf8,0xa0,0xf8]
+
+// Aliases
+// -----------------------------------------------------------------------------
+
+prfm #24, [x0, w0, uxtw]
+// CHECK-INST: rprfm pldkeep, x0, [x0]
+// CHECK-ENCODING: [0x18,0x48,0xa0,0xf8]
+
+prfm #25, [x0, w0, uxtw]
+// CHECK-INST: rprfm pstkeep, x0, [x0]
+// CHECK-ENCODING: [0x19,0x48,0xa0,0xf8]
+
+prfm #26, [x0, w0, uxtw]
+// CHECK-INST: rprfm #2, x0, [x0]
+// CHECK-ENCODING: [0x1a,0x48,0xa0,0xf8]
+
+prfm #27, [x0, w0, uxtw]
+// CHECK-INST: rprfm #3, x0, [x0]
+// CHECK-ENCODING: [0x1b,0x48,0xa0,0xf8]
+
+prfm #28, [x0, w0, uxtw]
+// CHECK-INST: rprfm pldstrm, x0, [x0]
+// CHECK-ENCODING: [0x1c,0x48,0xa0,0xf8]
+
+prfm #29, [x0, w0, uxtw]
+// CHECK-INST: rprfm pststrm, x0, [x0]
+// CHECK-ENCODING: [0x1d,0x48,0xa0,0xf8]
+
+prfm #30, [x0, w0, uxtw]
+// CHECK-INST: rprfm #6, x0, [x0]
+// CHECK-ENCODING: [0x1e,0x48,0xa0,0xf8]
+
+prfm #31, [x0, w0, uxtw]
+// CHECK-INST: rprfm #7, x0, [x0]
+// CHECK-ENCODING: [0x1f,0x48,0xa0,0xf8]
+
+prfm #24, [x0, w0, uxtw #3]
+// CHECK-INST: rprfm #8, x0, [x0]
+// CHECK-ENCODING: [0x18,0x58,0xa0,0xf8]
+
+prfm #25, [x0, w0, uxtw #3]
+// CHECK-INST: rprfm #9, x0, [x0]
+// CHECK-ENCODING: [0x19,0x58,0xa0,0xf8]
+
+prfm #26, [x0, w0, uxtw #3]
+// CHECK-INST: rprfm #10, x0, [x0]
+// CHECK-ENCODING: [0x1a,0x58,0xa0,0xf8]
+
+prfm #27, [x0, w0, uxtw #3]
+// CHECK-INST: rprfm #11, x0, [x0]
+// CHECK-ENCODING: [0x1b,0x58,0xa0,0xf8]
+
+prfm #28, [x0, w0, uxtw #3]
+// CHECK-INST: rprfm #12, x0, [x0]
+// CHECK-ENCODING: [0x1c,0x58,0xa0,0xf8]
+
+prfm #29, [x0, w0, uxtw #3]
+// CHECK-INST: rprfm #13, x0, [x0]
+// CHECK-ENCODING: [0x1d,0x58,0xa0,0xf8]
+
+prfm #30, [x0, w0, uxtw #3]
+// CHECK-INST: rprfm #14, x0, [x0]
+// CHECK-ENCODING: [0x1e,0x58,0xa0,0xf8]
+
+prfm #31, [x0, w0, uxtw #3]
+// CHECK-INST: rprfm #15, x0, [x0]
+// CHECK-ENCODING: [0x1f,0x58,0xa0,0xf8]
+
+prfm #24, [x0, x0]
+// CHECK-INST: rprfm #16, x0, [x0]
+// CHECK-ENCODING: [0x18,0x68,0xa0,0xf8]
+
+prfm #25, [x0, x0]
+// CHECK-INST: rprfm #17, x0, [x0]
+// CHECK-ENCODING: [0x19,0x68,0xa0,0xf8]
+
+prfm #26, [x0, x0]
+// CHECK-INST: rprfm #18, x0, [x0]
+// CHECK-ENCODING: [0x1a,0x68,0xa0,0xf8]
+
+prfm #27, [x0, x0]
+// CHECK-INST: rprfm #19, x0, [x0]
+// CHECK-ENCODING: [0x1b,0x68,0xa0,0xf8]
+
+prfm #28, [x0, x0]
+// CHECK-INST: rprfm #20, x0, [x0]
+// CHECK-ENCODING: [0x1c,0x68,0xa0,0xf8]
+
+prfm #29, [x0, x0]
+// CHECK-INST: rprfm #21, x0, [x0]
+// CHECK-ENCODING: [0x1d,0x68,0xa0,0xf8]
+
+prfm #30, [x0, x0]
+// CHECK-INST: rprfm #22, x0, [x0]
+// CHECK-ENCODING: [0x1e,0x68,0xa0,0xf8]
+
+prfm #31, [x0, x0]
+// CHECK-INST: rprfm #23, x0, [x0]
+// CHECK-ENCODING: [0x1f,0x68,0xa0,0xf8]
+
+prfm #24, [x0, x0, lsl #3]
+// CHECK-INST: rprfm #24, x0, [x0]
+// CHECK-ENCODING: [0x18,0x78,0xa0,0xf8]
+
+prfm #25, [x0, x0, lsl #3]
+// CHECK-INST: rprfm #25, x0, [x0]
+// CHECK-ENCODING: [0x19,0x78,0xa0,0xf8]
+
+prfm #26, [x0, x0, lsl #3]
+// CHECK-INST: rprfm #26, x0, [x0]
+// CHECK-ENCODING: [0x1a,0x78,0xa0,0xf8]
+
+prfm #27, [x0, x0, lsl #3]
+// CHECK-INST: rprfm #27, x0, [x0]
+// CHECK-ENCODING: [0x1b,0x78,0xa0,0xf8]
+
+prfm #28, [x0, x0, lsl #3]
+// CHECK-INST: rprfm #28, x0, [x0]
+// CHECK-ENCODING: [0x1c,0x78,0xa0,0xf8]
+
+prfm #29, [x0, x0, lsl #3]
+// CHECK-INST: rprfm #29, x0, [x0]
+// CHECK-ENCODING: [0x1d,0x78,0xa0,0xf8]
+
+prfm #30, [x0, x0, lsl #3]
+// CHECK-INST: rprfm #30, x0, [x0]
+// CHECK-ENCODING: [0x1e,0x78,0xa0,0xf8]
+
+prfm #31, [x0, x0, lsl #3]
+// CHECK-INST: rprfm #31, x0, [x0]
+// CHECK-ENCODING: [0x1f,0x78,0xa0,0xf8]
+
+prfm #24, [x0, w0, sxtw]
+// CHECK-INST: rprfm #32, x0, [x0]
+// CHECK-ENCODING: [0x18,0xc8,0xa0,0xf8]
+
+prfm #25, [x0, w0, sxtw]
+// CHECK-INST: rprfm #33, x0, [x0]
+// CHECK-ENCODING: [0x19,0xc8,0xa0,0xf8]
+
+prfm #26, [x0, w0, sxtw]
+// CHECK-INST: rprfm #34, x0, [x0]
+// CHECK-ENCODING: [0x1a,0xc8,0xa0,0xf8]
+
+prfm #27, [x0, w0, sxtw]
+// CHECK-INST: rprfm #35, x0, [x0]
+// CHECK-ENCODING: [0x1b,0xc8,0xa0,0xf8]
+
+prfm #28, [x0, w0, sxtw]
+// CHECK-INST: rprfm #36, x0, [x0]
+// CHECK-ENCODING: [0x1c,0xc8,0xa0,0xf8]
+
+prfm #29, [x0, w0, sxtw]
+// CHECK-INST: rprfm #37, x0, [x0]
+// CHECK-ENCODING: [0x1d,0xc8,0xa0,0xf8]
+
+prfm #30, [x0, w0, sxtw]
+// CHECK-INST: rprfm #38, x0, [x0]
+// CHECK-ENCODING: [0x1e,0xc8,0xa0,0xf8]
+
+prfm #31, [x0, w0, sxtw]
+// CHECK-INST: rprfm #39, x0, [x0]
+// CHECK-ENCODING: [0x1f,0xc8,0xa0,0xf8]
+
+prfm #24, [x0, w0, sxtw #3]
+// CHECK-INST: rprfm #40, x0, [x0]
+// CHECK-ENCODING: [0x18,0xd8,0xa0,0xf8]
+
+prfm #25, [x0, w0, sxtw #3]
+// CHECK-INST: rprfm #41, x0, [x0]
+// CHECK-ENCODING: [0x19,0xd8,0xa0,0xf8]
+
+prfm #26, [x0, w0, sxtw #3]
+// CHECK-INST: rprfm #42, x0, [x0]
+// CHECK-ENCODING: [0x1a,0xd8,0xa0,0xf8]
+
+prfm #27, [x0, w0, sxtw #3]
+// CHECK-INST: rprfm #43, x0, [x0]
+// CHECK-ENCODING: [0x1b,0xd8,0xa0,0xf8]
+
+prfm #28, [x0, w0, sxtw #3]
+// CHECK-INST: rprfm #44, x0, [x0]
+// CHECK-ENCODING: [0x1c,0xd8,0xa0,0xf8]
+
+prfm #29, [x0, w0, sxtw #3]
+// CHECK-INST: rprfm #45, x0, [x0]
+// CHECK-ENCODING: [0x1d,0xd8,0xa0,0xf8]
+
+prfm #30, [x0, w0, sxtw #3]
+// CHECK-INST: rprfm #46, x0, [x0]
+// CHECK-ENCODING: [0x1e,0xd8,0xa0,0xf8]
+
+prfm #31, [x0, w0, sxtw #3]
+// CHECK-INST: rprfm #47, x0, [x0]
+// CHECK-ENCODING: [0x1f,0xd8,0xa0,0xf8]
+
+prfm #24, [x0, x0, sxtx]
+// CHECK-INST: rprfm #48, x0, [x0]
+// CHECK-ENCODING: [0x18,0xe8,0xa0,0xf8]
+
+prfm #25, [x0, x0, sxtx]
+// CHECK-INST: rprfm #49, x0, [x0]
+// CHECK-ENCODING: [0x19,0xe8,0xa0,0xf8]
+
+prfm #26, [x0, x0, sxtx]
+// CHECK-INST: rprfm #50, x0, [x0]
+// CHECK-ENCODING: [0x1a,0xe8,0xa0,0xf8]
+
+prfm #27, [x0, x0, sxtx]
+// CHECK-INST: rprfm #51, x0, [x0]
+// CHECK-ENCODING: [0x1b,0xe8,0xa0,0xf8]
+
+prfm #28, [x0, x0, sxtx]
+// CHECK-INST: rprfm #52, x0, [x0]
+// CHECK-ENCODING: [0x1c,0xe8,0xa0,0xf8]
+
+prfm #29, [x0, x0, sxtx]
+// CHECK-INST: rprfm #53, x0, [x0]
+// CHECK-ENCODING: [0x1d,0xe8,0xa0,0xf8]
+
+prfm #30, [x0, x0, sxtx]
+// CHECK-INST: rprfm #54, x0, [x0]
+// CHECK-ENCODING: [0x1e,0xe8,0xa0,0xf8]
+
+prfm #31, [x0, x0, sxtx]
+// CHECK-INST: rprfm #55, x0, [x0]
+// CHECK-ENCODING: [0x1f,0xe8,0xa0,0xf8]
+
+prfm #24, [x0, x0, sxtx #3]
+// CHECK-INST: rprfm #56, x0, [x0]
+// CHECK-ENCODING: [0x18,0xf8,0xa0,0xf8]
+
+prfm #25, [x0, x0, sxtx #3]
+// CHECK-INST: rprfm #57, x0, [x0]
+// CHECK-ENCODING: [0x19,0xf8,0xa0,0xf8]
+
+prfm #26, [x0, x0, sxtx #3]
+// CHECK-INST: rprfm #58, x0, [x0]
+// CHECK-ENCODING: [0x1a,0xf8,0xa0,0xf8]
+
+prfm #27, [x0, x0, sxtx #3]
+// CHECK-INST: rprfm #59, x0, [x0]
+// CHECK-ENCODING: [0x1b,0xf8,0xa0,0xf8]
+
+prfm #28, [x0, x0, sxtx #3]
+// CHECK-INST: rprfm #60, x0, [x0]
+// CHECK-ENCODING: [0x1c,0xf8,0xa0,0xf8]
+
+prfm #29, [x0, x0, sxtx #3]
+// CHECK-INST: rprfm #61, x0, [x0]
+// CHECK-ENCODING: [0x1d,0xf8,0xa0,0xf8]
+
+prfm #30, [x0, x0, sxtx #3]
+// CHECK-INST: rprfm #62, x0, [x0]
+// CHECK-ENCODING: [0x1e,0xf8,0xa0,0xf8]
+
+prfm #31, [x0, x0, sxtx #3]
+// CHECK-INST: rprfm #63, x0, [x0]
+// CHECK-ENCODING: [0x1f,0xf8,0xa0,0xf8]
+

llvm/test/MC/Disassembler/AArch64/armv8.9a-cssc.txt

+# RUN:     llvm-mc -triple aarch64-none-linux-gnu -disassemble -mattr=+v9.4a < %s      | FileCheck %s
+# RUN: not llvm-mc -triple aarch64-none-linux-gnu -disassemble -mattr=+v8.8a < %s 2>&1 | FileCheck --check-prefix=NO-V94A-ERR %s
+# RUN:     llvm-mc -triple aarch64-none-linux-gnu -disassemble -mattr=+v8.9a < %s      | FileCheck %s
+# RUN: not llvm-mc -triple aarch64-none-linux-gnu -disassemble -mattr=+v9.3a < %s 2>&1 | FileCheck --check-prefix=NO-V94A-ERR %s
+
+[0x20,0x20,0xc0,0xda]
+# CHECK:   abs     x0, x1
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x20,0x20,0xc0,0x5a]
+# CHECK:   abs     w0, w1
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x20,0x1c,0xc0,0xda]
+# CHECK:   cnt     x0, x1
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x20,0x1c,0xc0,0x5a]
+# CHECK:   cnt     w0, w1
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x20,0x18,0xc0,0xda]
+# CHECK:   ctz     x0, x1
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x20,0x18,0xc0,0x5a]
+# CHECK:   ctz     w0, w1
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x41,0x60,0xc3,0x9a]
+# CHECK:   smax    x1, x2, x3
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x41,0x0c,0xc0,0x91]
+# CHECK:   smax    x1, x2, #3
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x41,0x60,0xc3,0x1a]
+# CHECK:   smax    w1, w2, w3
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x41,0x0c,0xc0,0x11]
+# CHECK:   smax    w1, w2, #3
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x41,0x68,0xc3,0x9a]
+# CHECK:   smin    x1, x2, x3
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x41,0x0c,0xc8,0x91]
+# CHECK:   smin    x1, x2, #3
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x41,0x68,0xc3,0x1a]
+# CHECK:   smin    w1, w2, w3
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x41,0x0c,0xc8,0x11]
+# CHECK:   smin    w1, w2, #3
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x41,0x64,0xc3,0x9a]
+# CHECK:   umax    x1, x2, x3
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x41,0x0c,0xc4,0x91]
+# CHECK:   umax    x1, x2, #3
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x41,0x64,0xc3,0x1a]
+# CHECK:   umax    w1, w2, w3
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x41,0x0c,0xc4,0x11]
+# CHECK:   umax    w1, w2, #3
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x41,0x6c,0xc3,0x9a]
+# CHECK:   umin    x1, x2, x3
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x41,0x0c,0xcc,0x91]
+# CHECK:   umin    x1, x2, #3
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x41,0x6c,0xc3,0x1a]
+# CHECK:   umin    w1, w2, w3
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x41,0x0c,0xcc,0x11]
+# CHECK:   umin    w1, w2, #3
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding

llvm/unittests/Support/TargetParserTest.cpp

std::vector<uint64_t> Extensions = {
       AArch64::AEK_RCPC,    AArch64::AEK_RAND,     AArch64::AEK_MTE,
       AArch64::AEK_SSBS,    AArch64::AEK_SB,       AArch64::AEK_PREDRES,
       AArch64::AEK_BF16,    AArch64::AEK_I8MM,     AArch64::AEK_F32MM,
       AArch64::AEK_F64MM,   AArch64::AEK_TME,      AArch64::AEK_LS64,
       AArch64::AEK_BRBE,    AArch64::AEK_PAUTH,    AArch64::AEK_FLAGM,
       AArch64::AEK_SME,     AArch64::AEK_SMEF64F64, AArch64::AEK_SMEI16I64,
       AArch64::AEK_SME2,    AArch64::AEK_HBC,      AArch64::AEK_MOPS,
       AArch64::AEK_PERFMON, AArch64::AEK_SVE2p1,   AArch64::AEK_SME2p1,
-      AArch64::AEK_B16B16,  AArch64::AEK_SMEF16F16};
+      AArch64::AEK_B16B16,  AArch64::AEK_SMEF16F16, AArch64::AEK_CSSC};
 
   std::vector<StringRef> Features;
 
   uint64_t ExtVal = 0;
   for (auto Ext : Extensions)
     ExtVal |= Ext;
 
   // INVALID and NONE have no feature names.
TEST(TargetParserTest, AArch64ExtensionFeatures) {
   EXPECT_TRUE(llvm::is_contained(Features, "+sme-f64f64"));
   EXPECT_TRUE(llvm::is_contained(Features, "+sme-i16i64"));
   EXPECT_TRUE(llvm::is_contained(Features, "+sme-f16f16"));
   EXPECT_TRUE(llvm::is_contained(Features, "+sme2"));
   EXPECT_TRUE(llvm::is_contained(Features, "+sme2p1"));
   EXPECT_TRUE(llvm::is_contained(Features, "+hbc"));
   EXPECT_TRUE(llvm::is_contained(Features, "+mops"));
   EXPECT_TRUE(llvm::is_contained(Features, "+perfmon"));
+  EXPECT_TRUE(llvm::is_contained(Features, "+cssc"));
 
   // Assuming we listed every extension above, this should produce the same
   // result. (note that AEK_NONE doesn't have a name so it won't be in the
   // result despite its bit being set)
   std::vector<StringRef> AllFeatures;
   EXPECT_TRUE(AArch64::getExtensionFeatures(-1, AllFeatures));
   EXPECT_THAT(Features, ::testing::ContainerEq(AllFeatures));
 }