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llvm/test/Transforms/LoopVectorize/RISCV/select-cmp-reduction.ll | ||
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10 | It might be worth making sure that some of the variants in Transforms/LoopVectorize/AArch64/sve-select-cmp.ll also work for RISCV? In particular, @pred_select_const_i32_from_icmp since that exposed a bug when I first landed support for this idiom. |
Add new test cases that are copied from Transforms/LoopVectorize/AArch64/sve-select-cmp.ll.
LGTM
Just to check, you've confirmed the actual codegen for this looks vaguely reasonable right? I don't see anything in the IR which worries me too much, just asking for the confirmation.
It does to me yeah - the output looks similar to llvm/test/Transforms/LoopVectorize/AArch64/sve-select-cmp.ll and we have the same pattern of compares/selects in the vector loop, as well as compares + or reduce in the middle block. None of the tests crash and the RISCV version bails out in the same way as AArch64 for @select_const_f32_from_icmp.
The tests in this patch don't test interleaving like the tests in llvm/test/Transforms/LoopVectorize/AArch64/sve-select-cmp.ll do, but I figured that they are going down the same code path by this point and wasn't sure if it would add much value being tested again here.
Codegen looks good.
Here is how I use to confirm codegen:
opt -loop-vectorize -force-vector-interleave=1 -force-vector-width=4 -scalable-vectorization=on -S Transforms/LoopVectorize/RISCV/select-cmp-reduction.ll > select-cmp-reduction.gen.ll llc -mtriple=riscv64 -mattr=+m,+f,+v -verify-machineinstrs -target-abi=lp64d -riscv-v-vector-bits-min=-1 < select-cmp-reduction.gen.ll > select-cmp-reduction.gen.s
It might be worth making sure that some of the variants in Transforms/LoopVectorize/AArch64/sve-select-cmp.ll also work for RISCV? In particular, @pred_select_const_i32_from_icmp since that exposed a bug when I first landed support for this idiom.