[AArch64] RME MEC instructions and system registers

[keith.walker.arm]

Summary

This patch adds assembler/disassembler support for
RME MEC (Memory Encryption Contexts).

Cache maintence instructions added:

• DC CIPAPA
• DC CIGDPAPA

System registers added:

• MECIDR_EL2
• MECID_P0_EL2
• MECID_A0_EL2
• MECID_P1_EL2
• MECID_A1_EL2
• VMECID_P_EL2
• VMECID_A_EL2
• MECID_RL_A_EL3

Memory Encryption Contexts were announced in

https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-2022

The instruction encodings for the MEC feature is available at

https://developer.arm.com/documentation/ddi0602/2022-09/Base-Instructions/DC--Data-Cache-operation--an-alias-of-SYS-?lang=en

The system register encodings available at

https://developer.arm.com/documentation/ddi0601/2022-09/AArch64-Registers?lang=en

Based on patches by Son Tuan Vu

[lenary]

Sorry, a quick drive-by comment. I'll try to get back to this to do a fuller review on Wednesday.

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

3500

This should not be included. These names are supposed to be the same as command-line extension options, which MEC doesn't have.

At the very least, it's also untested, but I think it should be removed, not tested.

[keith.walker.arm]

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

3500

So I assume we want uses of MEC to be gated on the use of AArch64::FeatureRME instead.

[lenary]

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

3500

Not quite. This array is only for allowing .arch_extension <string> to enable specific features, which is part of the public interface, and we don't want if there's not a corresponding extension for -march=<version>+<string>

FeatureMEC in AArch64.td should remain.

[keith.walker.arm]

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

3500

The reason I asked is because removing just this line causes the tests to fail with an errors like:

error: DC CIGDPAE requires: (unknown)

and

error: expected writable system register or pstate

So it looks to me like this line is required.

[lenary]

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

3500

Ah, my mistake. This is annoying it's used for both, but for this patch leave this in.

[lenary]

Cool, did a more in-depth review against the specification. LGTM!

llvm/docs/ReleaseNotes.rst

 Changes to TableGen
 -------------------
 
 Changes to the AArch64 Backend
 ------------------------------
 
 * Added support for the Cortex-A715 CPU.
 * Added support for the Cortex-X3 CPU.
+* Added support for assembly for RME MEC (Memory Encryption Contexts).
 
 Changes to the AMDGPU Backend
 -----------------------------
 
 Changes to the ARM Backend
 --------------------------
 
 * Support for targeting armv2, armv2A, armv3 and armv3M has been removed.

llvm/lib/Target/AArch64/AArch64.td

 def FeatureFixCortexA53_835769 : SubtargetFeature<"fix-cortex-a53-835769",
   "FixCortexA53_835769", "true", "Mitigate Cortex-A53 Erratum 835769">;
 
 def FeatureNoBTIAtReturnTwice : SubtargetFeature<"no-bti-at-return-twice",
                                                  "NoBTIAtReturnTwice", "true",
                                                  "Don't place a BTI instruction "
                                                  "after a return-twice">;
 
+def FeatureMEC : SubtargetFeature<"mec", "HasMEC",
+    "true", "Enable Memory Encryption Contexts Extension", [FeatureRME]>;
+
 //===----------------------------------------------------------------------===//
 // Architectures.
 //
 def HasV8_0aOps : SubtargetFeature<"v8a", "HasV8_0aOps", "true",
   "Support ARM v8.0a instructions", [FeatureEL2VMSA, FeatureEL3]>;
 
 def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
   "Support ARM v8.1a instructions", [HasV8_0aOps, FeatureCRC, FeatureLSE,
def HasV8_7aOps : SubtargetFeature<
   [HasV8_6aOps, FeatureXS, FeatureWFxT, FeatureHCX]>;
 
 def HasV8_8aOps : SubtargetFeature<
   "v8.8a", "HasV8_8aOps", "true", "Support ARM v8.8a instructions",
   [HasV8_7aOps, FeatureHBC, FeatureMOPS]>;
 
 def HasV9_0aOps : SubtargetFeature<
   "v9a", "HasV9_0aOps", "true", "Support ARM v9a instructions",
-  [HasV8_5aOps, FeatureSVE2]>;
+  [HasV8_5aOps, FeatureMEC, FeatureSVE2]>;
 
 def HasV9_1aOps : SubtargetFeature<
   "v9.1a", "HasV9_1aOps", "true", "Support ARM v9.1a instructions",
   [HasV8_6aOps, HasV9_0aOps]>;
 
 def HasV9_2aOps : SubtargetFeature<
   "v9.2a", "HasV9_2aOps", "true", "Support ARM v9.2a instructions",
   [HasV8_7aOps, HasV9_1aOps]>;

llvm/lib/Target/AArch64/AArch64SystemOperands.td

 def : DC<"CIGDSW",  0b000, 0b0111, 0b1110, 0b110>;
 def : DC<"CGDVAC",  0b011, 0b0111, 0b1010, 0b101>;
 def : DC<"CGDVAP",  0b011, 0b0111, 0b1100, 0b101>;
 def : DC<"CGDVADP", 0b011, 0b0111, 0b1101, 0b101>;
 def : DC<"CIGDVAC", 0b011, 0b0111, 0b1110, 0b101>;
 def : DC<"GZVA",    0b011, 0b0111, 0b0100, 0b100>;
 }
 
+let Requires = [{ {AArch64::FeatureMEC} }] in {
+def : DC<"CIGDPAE", 0b100, 0b0111, 0b1110, 0b000>;
+def : DC<"CIPAE",   0b100, 0b0111, 0b1110, 0b111>;
+}
+
 //===----------------------------------------------------------------------===//
 // IC (instruction cache maintenance) instruction options.
 //===----------------------------------------------------------------------===//
 
 class IC<string name, bits<3> op1, bits<4> crn, bits<4> crm, bits<3> op2,
          bit needsreg> : SearchableTable {
   let SearchableFields = ["Name", "Encoding"];
   let EnumValueField = "Encoding";

 
 // v9a Realm Management Extension registers
 let Requires = [{ {AArch64::FeatureRME} }] in {
 def : RWSysReg<"MFAR_EL3",  0b11, 0b110, 0b0110, 0b0000, 0b101>;
 def : RWSysReg<"GPCCR_EL3", 0b11, 0b110, 0b0010, 0b0001, 0b110>;
 def : RWSysReg<"GPTBR_EL3", 0b11, 0b110, 0b0010, 0b0001, 0b100>;
 }
 
+// v9a Memory Encryption Contexts Extension registers
+let Requires = [{ {AArch64::FeatureMEC} }] in {
+def : ROSysReg<"MECIDR_EL2",     0b11, 0b100, 0b1010, 0b1000, 0b111>;
+def : RWSysReg<"MECID_P0_EL2",   0b11, 0b100, 0b1010, 0b1000, 0b000>;
+def : RWSysReg<"MECID_A0_EL2",   0b11, 0b100, 0b1010, 0b1000, 0b001>;
+def : RWSysReg<"MECID_P1_EL2",   0b11, 0b100, 0b1010, 0b1000, 0b010>;
+def : RWSysReg<"MECID_A1_EL2",   0b11, 0b100, 0b1010, 0b1000, 0b011>;
+def : RWSysReg<"VMECID_P_EL2",   0b11, 0b100, 0b1010, 0b1001, 0b000>;
+def : RWSysReg<"VMECID_A_EL2",   0b11, 0b100, 0b1010, 0b1001, 0b001>;
+def : RWSysReg<"MECID_RL_A_EL3", 0b11, 0b110, 0b1010, 0b1010, 0b001>;
+}
+
 // v9-a Scalable Matrix Extension (SME) registers
 //                                 Op0   Op1    CRn     CRm     Op2
 let Requires = [{ {AArch64::FeatureSME} }] in {
 def : ROSysReg<"ID_AA64SMFR0_EL1", 0b11, 0b000, 0b0000, 0b0100, 0b101>;
 }
 
 //===----------------------
 // Write-only regs

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

const FeatureBitset Features;
     {"rme", {AArch64::FeatureRME}},
     {"sme", {AArch64::FeatureSME}},
     {"sme-f64f64", {AArch64::FeatureSMEF64F64}},
     {"sme-i16i64", {AArch64::FeatureSMEI16I64}},
     {"sme2", {AArch64::FeatureSME2}},
     {"sme2p1", {AArch64::FeatureSME2p1}},
     {"hbc", {AArch64::FeatureHBC}},
     {"mops", {AArch64::FeatureMOPS}},
+    {"mec", {AArch64::FeatureMEC}},
     // FIXME: Unsupported extensions
     {"lor", {}},
     {"rdma", {}},
     {"profile", {}},
 };
 
 static void setRequiredFeatureString(FeatureBitset FBS, std::string &Str) {
   if (FBS[AArch64::HasV8_0aOps])

llvm/test/MC/AArch64/armv9a-mec.s

+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+mec < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v9a < %s | FileCheck %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu < %s 2>&1 | FileCheck --check-prefix=CHECK-NO-MEC %s
+
+          mrs x0, MECIDR_EL2
+// CHECK: mrs   x0, MECIDR_EL2       // encoding: [0xe0,0xa8,0x3c,0xd5]
+// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register
+          mrs x0, MECID_P0_EL2
+// CHECK: mrs   x0, MECID_P0_EL2      // encoding: [0x00,0xa8,0x3c,0xd5]
+// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register
+          mrs x0, MECID_A0_EL2
+// CHECK: mrs   x0, MECID_A0_EL2      // encoding: [0x20,0xa8,0x3c,0xd5]
+// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register
+          mrs x0, MECID_P1_EL2
+// CHECK: mrs   x0, MECID_P1_EL2      // encoding: [0x40,0xa8,0x3c,0xd5]
+// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register
+          mrs x0, MECID_A1_EL2
+// CHECK: mrs   x0, MECID_A1_EL2      // encoding: [0x60,0xa8,0x3c,0xd5]
+// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register
+          mrs x0, VMECID_P_EL2
+// CHECK: mrs   x0, VMECID_P_EL2     // encoding: [0x00,0xa9,0x3c,0xd5]
+// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register
+          mrs x0, VMECID_A_EL2
+// CHECK: mrs   x0, VMECID_A_EL2     // encoding: [0x20,0xa9,0x3c,0xd5]
+// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register
+          mrs x0, MECID_RL_A_EL3
+// CHECK: mrs   x0, MECID_RL_A_EL3   // encoding: [0x20,0xaa,0x3e,0xd5]
+// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register
+          msr MECID_P0_EL2,    x0
+// CHECK: msr   MECID_P0_EL2, x0      // encoding: [0x00,0xa8,0x1c,0xd5]
+// CHECK-NO-MEC: [[@LINE-2]]:15: error: expected writable system register or pstate
+          msr MECID_A0_EL2,    x0
+// CHECK: msr   MECID_A0_EL2, x0      // encoding: [0x20,0xa8,0x1c,0xd5]
+// CHECK-NO-MEC: [[@LINE-2]]:15: error: expected writable system register or pstate
+          msr MECID_P1_EL2,    x0
+// CHECK: msr   MECID_P1_EL2, x0      // encoding: [0x40,0xa8,0x1c,0xd5]
+// CHECK-NO-MEC: [[@LINE-2]]:15: error: expected writable system register or pstate
+          msr MECID_A1_EL2,    x0
+// CHECK: msr   MECID_A1_EL2, x0      // encoding: [0x60,0xa8,0x1c,0xd5]
+// CHECK-NO-MEC: [[@LINE-2]]:15: error: expected writable system register or pstate
+          msr VMECID_P_EL2,   x0
+// CHECK: msr   VMECID_P_EL2, x0     // encoding: [0x00,0xa9,0x1c,0xd5]
+// CHECK-NO-MEC: [[@LINE-2]]:15: error: expected writable system register or pstate
+          msr VMECID_A_EL2,   x0
+// CHECK: msr   VMECID_A_EL2, x0     // encoding: [0x20,0xa9,0x1c,0xd5]
+// CHECK-NO-MEC: [[@LINE-2]]:15: error: expected writable system register or pstate
+          msr MECID_RL_A_EL3, x0
+// CHECK: msr   MECID_RL_A_EL3, x0   // encoding: [0x20,0xaa,0x1e,0xd5]
+// CHECK-NO-MEC: [[@LINE-2]]:15: error: expected writable system register or pstate
+
+          dc cigdpae, x0
+// CHECK: dc cigdpae, x0             // encoding: [0x00,0x7e,0x0c,0xd5]
+// CHECK-NO-MEC: [[@LINE-2]]:14: error: DC CIGDPAE requires: mec
+          dc cipae, x0
+// CHECK: dc cipae, x0               // encoding: [0xe0,0x7e,0x0c,0xd5]
+// CHECK-NO-MEC: [[@LINE-2]]:14: error: DC CIPAE requires: mec

llvm/test/MC/Disassembler/AArch64/armv9a-mec.txt

+# RUN: llvm-mc -triple=aarch64             -mattr=+mec -disassemble %s      | FileCheck %s
+# RUN: llvm-mc -triple=aarch64 -mattr=+v9a             -disassemble %s      | FileCheck %s
+# RUN: llvm-mc -triple=aarch64                         -disassemble %s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-MEC
+
+[0xe0,0xa8,0x3c,0xd5]
+# CHECK: mrs x0, MECIDR_EL2
+# CHECK-NO-MEC: mrs x0, S3_4_C10_C8_7
+[0x00,0xa8,0x3c,0xd5]
+# CHECK: mrs x0, MECID_P0_EL2
+# CHECK-NO-MEC: mrs x0, S3_4_C10_C8_0
+[0x20,0xa8,0x3c,0xd5]
+# CHECK: mrs x0, MECID_A0_EL2
+# CHECK-NO-MEC: mrs x0, S3_4_C10_C8_1
+[0x40,0xa8,0x3c,0xd5]
+# CHECK: mrs x0, MECID_P1_EL2
+# CHECK-NO-MEC: mrs x0, S3_4_C10_C8_2
+[0x60,0xa8,0x3c,0xd5]
+# CHECK: mrs x0, MECID_A1_EL2
+# CHECK-NO-MEC: mrs x0, S3_4_C10_C8_3
+[0x00,0xa9,0x3c,0xd5]
+# CHECK: mrs x0, VMECID_P_EL2
+# CHECK-NO-MEC: mrs x0, S3_4_C10_C9_0
+[0x20,0xa9,0x3c,0xd5]
+# CHECK: mrs x0, VMECID_A_EL2
+# CHECK-NO-MEC: mrs x0, S3_4_C10_C9_1
+[0x20,0xaa,0x3e,0xd5]
+# CHECK: mrs x0, MECID_RL_A_EL3
+# CHECK-NO-MEC: mrs x0, S3_6_C10_C10_1
+[0x00,0xa8,0x1c,0xd5]
+# CHECK: msr MECID_P0_EL2,    x0
+# CHECK-NO-MEC: msr S3_4_C10_C8_0, x0
+[0x20,0xa8,0x1c,0xd5]
+# CHECK: msr MECID_A0_EL2,    x0
+# CHECK-NO-MEC: msr S3_4_C10_C8_1, x0
+[0x40,0xa8,0x1c,0xd5]
+# CHECK: msr MECID_P1_EL2,    x0
+# CHECK-NO-MEC: msr S3_4_C10_C8_2, x0
+[0x60,0xa8,0x1c,0xd5]
+# CHECK: msr MECID_A1_EL2,    x0
+# CHECK-NO-MEC: msr S3_4_C10_C8_3, x0
+[0x00,0xa9,0x1c,0xd5]
+# CHECK: msr VMECID_P_EL2,   x0
+# CHECK-NO-MEC: msr S3_4_C10_C9_0, x0
+[0x20,0xa9,0x1c,0xd5]
+# CHECK: msr VMECID_A_EL2,   x0
+# CHECK-NO-MEC: msr S3_4_C10_C9_1, x0
+[0x20,0xaa,0x1e,0xd5]
+# CHECK: msr MECID_RL_A_EL3, x0
+# CHECK-NO-MEC: msr S3_6_C10_C10_1, x0
+[0x00,0x7e,0x0c,0xd5]
+# CHECK: dc cigdpae, x0
+# CHECK-NO-MEC: sys #4, c7, c14, #0, x0
+[0xe0,0x7e,0x0c,0xd5]
+# CHECK: dc cipae, x0
+# CHECK-NO-MEC: sys #4, c7, c14, #7, x0