lib/CodeGen: Compile with -fvisibility=hidden when possible

[tstellar]

Summary

I don't think there is any code there that is meant to be part of the
public LLVM API. This helps reduce the number of exported symbols in
the library:

Before:
$ nm -D libLLVM-16git.so | wc -l
33240

After:
$ nm -D libLLVM-16git.so | wc -l
26987

[tstellar]

I just realized my test build was not using LLVM_LINK_LLVM_DYLIB, so I missed some symbols that are actually used, so I need to add some export annotations for some functions.

[MaskRay]

The motivation looks good but a bunch of llvm/include/CodeGen APIs are used outside of llvm/ (note, clang/ flang/ bolt/ uses also count): https://sourcegraph.com/search?q=context:global+include+%22llvm/CodeGen/+-file:llvm/lib/+-file:llvm/include/llvm/+-file:llvm/unittests/&patternType=standard

[compnerd]

I do like the idea in concept less in practice. The problem is that this is specific to the ELFish targets. I would prefer to handle this like my previously suggested approach of annotations (see D109192).

[mstorsjo]

In D137398#3925885, @compnerd wrote:

I do like the idea in concept less in practice. The problem is that this is specific to the ELFish targets. I would prefer to handle this like my previously suggested approach of annotations (see D109192).

Well they're not mutually exclusive either. The existing approach with visibility works for some configurations, and can be extended to cover more areas of the libraries, without blocking D109192 when that is ready in a mergeable shape, right?

(FWIW, hidden visibility is usable on mingw targets these days too, so it's not only ELF.)

[tstellar]

Export functions needs for other sub-projects. Still not enough to run
unittests.

[MaskRay]

Is this version working with various llvm dependent projects? You as a distributor shall know:)

[tstellar]

In D137398#3926293, @MaskRay wrote:

Is this version working with various llvm dependent projects? You as a distributor shall know:)

No, so far I'm testing with a build of clang;lld;lldb;compiler-rt and there are still unittests that won't compile. I wanted to get the patch update in Phabricator to get feedback on how the API annotations are done, before I go through and update everything.

[tstellar]

In D137398#3925885, @compnerd wrote:

I do like the idea in concept less in practice. The problem is that this is specific to the ELFish targets. I would prefer to handle this like my previously suggested approach of annotations (see D109192).

I've updated my patch with some annotations now. Is this more what you had in mind?

[compnerd]

llvm/CMakeLists.txt

1183

This condition is pretty unmanageable IMO. Can we perhaps split it up into a set of named conditions?

llvm/CMakeLists.txt

if( MINGW AND NOT "${CMAKE_CXX_COMPILER_ID}" MATCHES "Clang" )
   # build also uses -O2 for that reason:
   llvm_replace_compiler_option(CMAKE_CXX_FLAGS_RELEASE "-O3" "-O2")
 endif()
 
 if(LLVM_INCLUDE_TESTS)
   umbrella_lit_testsuite_begin(check-all)
 endif()
 
+if (NOT BUILD_SHARED_LIBS AND NOT APPLE AND
+    (NOT (WIN32 OR CYGWIN) OR (MINGW AND CMAKE_CXX_COMPILER_ID MATCHES "Clang")) AND
+    NOT (${CMAKE_SYSTEM_NAME} MATCHES "AIX") AND
+    NOT DEFINED CMAKE_CXX_VISIBILITY_PRESET)
+  set(LLVM_CAN_USE_HIDDEN_VISIBILITY ON)
+endif()
+
 # Put this before tblgen. Else we have a circular dependence.
 add_subdirectory(lib/Demangle)
 add_subdirectory(lib/Support)
 add_subdirectory(lib/TableGen)
 
 add_subdirectory(utils/TableGen)
 
 add_subdirectory(include/llvm)

llvm/include/llvm/CodeGen/CommandFlags.h

 
 namespace llvm {
 
 class Module;
 class AttrBuilder;
 class Function;
 class Triple;
 
-namespace codegen {
+namespace codegen LLVM_EXTERNAL_VISIBILITY {
 
 std::string getMArch();
 
 std::string getMCPU();
 
 std::vector<std::string> getMAttrs();
 
 Reloc::Model getRelocModel();

 bool getDebugStrictDwarf();
 
 unsigned getAlignLoops();
 
 bool getJMCInstrument();
 
 /// Create this object with static storage to register codegen-related command
 /// line options.
-struct RegisterCodeGenFlags {
+struct LLVM_EXTERNAL_VISIBILITY RegisterCodeGenFlags {
   RegisterCodeGenFlags();
 };
 
 llvm::BasicBlockSection getBBSectionsMode(llvm::TargetOptions &Options);
 
 /// Common utility function tightly tied to the options listed here. Initializes
 /// a TargetOptions object with CodeGen flags and returns it.
 /// \p TheTriple is used to determine the default value for options if

 
 /// Set function attributes of functions in Module M based on CPU,
 /// Features, and command line flags.
 void setFunctionAttributes(StringRef CPU, StringRef Features, Module &M);
 
 /// Should value-tracking variable locations / instruction referencing be
 /// enabled by default for this triple?
 bool getDefaultValueTrackingVariableLocations(const llvm::Triple &T);
-} // namespace codegen
+} // namespace LLVM_EXTERNAL_VISIBILITY
 } // namespace llvm
 
 #endif // LLVM_CODEGEN_COMMANDFLAGS_H

llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h

 private:
   SrcType Ty;
 };
 
 /// Helper class to build MachineInstr.
 /// It keeps internally the insertion point and debug location for all
 /// the new instructions we want to create.
 /// This information can be modify via the related setters.
+LLVM_EXTERNAL_VISIBILITY // For unittests
 class MachineIRBuilder {
 
   MachineIRBuilderState State;
 
 protected:
   void validateTruncExt(const LLT Dst, const LLT Src, bool IsExtend);
 
   void validateUnaryOp(const LLT Res, const LLT Op0);

llvm/include/llvm/CodeGen/MIRParser/MIRParser.h

 class SMDiagnostic;
 class StringRef;
 
 typedef llvm::function_ref<Optional<std::string>(StringRef)>
     DataLayoutCallbackTy;
 
 /// This class initializes machine functions by applying the state loaded from
 /// a MIR file.
-class MIRParser {
+class LLVM_EXTERNAL_VISIBILITY MIRParser {
   std::unique_ptr<MIRParserImpl> Impl;
 
 public:
   MIRParser(std::unique_ptr<MIRParserImpl> Impl);
   MIRParser(const MIRParser &) = delete;
   ~MIRParser();
 
   /// Parses the optional LLVM IR module in the MIR file.

 /// LLVM IR module and initialize the machine functions by parsing the machine
 /// function's state.
 ///
 /// \param Filename - The name of the file to parse.
 /// \param Error - Error result info.
 /// \param Context - Context which will be used for the parsed LLVM IR module.
 /// \param ProcessIRFunction - function to run on every IR function or stub
 /// loaded from the MIR file.
+LLVM_EXTERNAL_VISIBILITY
 std::unique_ptr<MIRParser> createMIRParserFromFile(
     StringRef Filename, SMDiagnostic &Error, LLVMContext &Context,
     std::function<void(Function &)> ProcessIRFunction = nullptr);
 
 /// This function is another interface to the MIR serialization format parser.
 ///
 /// It returns a MIR parser that works with the given memory buffer and that can
 /// parse the embedded LLVM IR module and initialize the machine functions by
 /// parsing the machine function's state.
 ///
 /// \param Contents - The MemoryBuffer containing the machine level IR.
 /// \param Context - Context which will be used for the parsed LLVM IR module.
+LLVM_EXTERNAL_VISIBILITY
 std::unique_ptr<MIRParser>
 createMIRParser(std::unique_ptr<MemoryBuffer> Contents, LLVMContext &Context,
                 std::function<void(Function &)> ProcessIRFunction = nullptr);
 
 } // end namespace llvm
 
 #endif // LLVM_CODEGEN_MIRPARSER_MIRPARSER_H

llvm/include/llvm/CodeGen/MIRPrinter.h

 //===- MIRPrinter.h - MIR serialization format printer ----------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file declares the functions that print out the LLVM IR and the machine
 // functions using the MIR serialization format.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_CODEGEN_MIRPRINTER_H
 #define LLVM_CODEGEN_MIRPRINTER_H
 
+#include "llvm/Support/Compiler.h"
+
 namespace llvm {
 
 class MachineBasicBlock;
 class MachineFunction;
 class Module;
 class raw_ostream;
 template <typename T> class SmallVectorImpl;
 
 /// Print LLVM IR using the MIR serialization format to the given output stream.
+LLVM_EXTERNAL_VISIBILITY
 void printMIR(raw_ostream &OS, const Module &M);
 
 /// Print a machine function using the MIR serialization format to the given
 /// output stream.
+LLVM_EXTERNAL_VISIBILITY
 void printMIR(raw_ostream &OS, const MachineFunction &MF);
 
 /// Determine a possible list of successors of a basic block based on the
 /// basic block machine operand being used inside the block. This should give
 /// you the correct list of successor blocks in most cases except for things
 /// like jump tables where the basic block references can't easily be found.
 /// The MIRPRinter will skip printing successors if they match the result of
 /// this funciton and the parser will use this function to construct a list if
 /// it is missing.
 void guessSuccessors(const MachineBasicBlock &MBB,
                      SmallVectorImpl<MachineBasicBlock*> &Result,
                      bool &IsFallthrough);
 
 } // end namespace llvm
 
 #endif

llvm/include/llvm/CodeGen/MachineBasicBlock.h

struct MBBSectionID {
 
   bool operator!=(const MBBSectionID &Other) const { return !(*this == Other); }
 
 private:
   // This is only used to construct the special cold and exception sections.
   MBBSectionID(SectionType T) : Type(T), Number(0) {}
 };
 
-template <> struct ilist_traits<MachineInstr> {
+template <> struct LLVM_EXTERNAL_VISIBILITY ilist_traits<MachineInstr> {
 private:
   friend class MachineBasicBlock; // Set by the owning MachineBasicBlock.
 
   MachineBasicBlock *Parent;
 
   using instr_iterator =
       simple_ilist<MachineInstr, ilist_sentinel_tracking<true>>::iterator;
 
 public:
   void addNodeToList(MachineInstr *N);
   void removeNodeFromList(MachineInstr *N);
   void transferNodesFromList(ilist_traits &FromList, instr_iterator First,
                              instr_iterator Last);
   void deleteNode(MachineInstr *MI);
 };
 
-class MachineBasicBlock
+class LLVM_EXTERNAL_VISIBILITY MachineBasicBlock
     : public ilist_node_with_parent<MachineBasicBlock, MachineFunction> {
 public:
   /// Pair of physical register and lane mask.
   /// This is not simply a std::pair typedef because the members should be named
   /// clearly as they both have an integer type.
   struct RegisterMaskPair {
   public:
     MCPhysReg PhysReg;

llvm/include/llvm/CodeGen/MachineDominators.h

 
 using MachineDomTree = DomTreeBase<MachineBasicBlock>;
 using MachineDomTreeNode = DomTreeNodeBase<MachineBasicBlock>;
 
 //===-------------------------------------
 /// DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to
 /// compute a normal dominator tree.
 ///
-class MachineDominatorTree : public MachineFunctionPass {
+class LLVM_EXTERNAL_VISIBILITY MachineDominatorTree : public MachineFunctionPass {
   /// Helper structure used to hold all the basic blocks
   /// involved in the split of a critical edge.
   struct CriticalEdge {
     MachineBasicBlock *FromBB;
     MachineBasicBlock *ToBB;
     MachineBasicBlock *NewBB;
   };
 

llvm/include/llvm/CodeGen/MachineFrameInfo.h

 /// objects).
 ///
 /// When prolog/epilog code emission is performed, the final stack frame is
 /// built and the machine instructions are modified to refer to the actual
 /// stack offsets of the object, eliminating all MO_FrameIndex operands from
 /// the program.
 ///
 /// Abstract Stack Frame Information
-class MachineFrameInfo {
+class LLVM_EXTERNAL_VISIBILITY MachineFrameInfo {
 public:
   /// Stack Smashing Protection (SSP) rules require that vulnerable stack
   /// allocations are located close the stack protector.
   enum SSPLayoutKind {
     SSPLK_None,       ///< Did not trigger a stack protector.  No effect on data
                       ///< layout.
     SSPLK_LargeArray, ///< Array or nested array >= SSP-buffer-size.  Closest
                       ///< to the stack protector.

llvm/include/llvm/CodeGen/MachineFunction.h

 class TargetSubtargetInfo;
 struct WasmEHFuncInfo;
 struct WinEHFuncInfo;
 
 template <> struct ilist_alloc_traits<MachineBasicBlock> {
   void deleteNode(MachineBasicBlock *MBB);
 };
 
-template <> struct ilist_callback_traits<MachineBasicBlock> {
+template <> struct LLVM_EXTERNAL_VISIBILITY ilist_callback_traits<MachineBasicBlock> {
   void addNodeToList(MachineBasicBlock* N);
   void removeNodeFromList(MachineBasicBlock* N);
 
   template <class Iterator>
   void transferNodesFromList(ilist_callback_traits &OldList, Iterator, Iterator) {
     assert(this == &OldList && "never transfer MBBs between functions");
   }
 };

llvm/include/llvm/CodeGen/MachineFunctionPass.h

 #include "llvm/Pass.h"
 
 namespace llvm {
 
 /// MachineFunctionPass - This class adapts the FunctionPass interface to
 /// allow convenient creation of passes that operate on the MachineFunction
 /// representation. Instead of overriding runOnFunction, subclasses
 /// override runOnMachineFunction.
-class MachineFunctionPass : public FunctionPass {
+class LLVM_EXTERNAL_VISIBILITY MachineFunctionPass : public FunctionPass {
 public:
   bool doInitialization(Module&) override {
     // Cache the properties info at module-init time so we don't have to
     // construct them for every function.
     RequiredProperties = getRequiredProperties();
     SetProperties = getSetProperties();
     ClearedProperties = getClearedProperties();
     return false;

llvm/include/llvm/CodeGen/MachineInstr.h

 
 //===----------------------------------------------------------------------===//
 /// Representation of each machine instruction.
 ///
 /// This class isn't a POD type, but it must have a trivial destructor. When a
 /// MachineFunction is deleted, all the contained MachineInstrs are deallocated
 /// without having their destructor called.
 ///
-class MachineInstr
+class LLVM_EXTERNAL_VISIBILITY MachineInstr
     : public ilist_node_with_parent<MachineInstr, MachineBasicBlock,
                                     ilist_sentinel_tracking<true>> {
 public:
   using mmo_iterator = ArrayRef<MachineMemOperand *>::iterator;
 
   /// Flags to specify different kinds of comments to output in
   /// assembly code.  These flags carry semantic information not
   /// otherwise easily derivable from the IR text.

llvm/include/llvm/CodeGen/MachineModuleInfo.h

 #ifndef LLVM_CODEGEN_MACHINEMODULEINFO_H
 #define LLVM_CODEGEN_MACHINEMODULEINFO_H
 
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/ADT/PointerIntPair.h"
 #include "llvm/IR/PassManager.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/Pass.h"
+#include "llvm/Support/Compiler.h"
 #include <memory>
 #include <utility>
 #include <vector>
 
 namespace llvm {
 
 class Function;
 class LLVMTargetMachine;
protected:
   static SymbolListTy getSortedStubs(DenseMap<MCSymbol*, StubValueTy>&);
 };
 
 //===----------------------------------------------------------------------===//
 /// This class contains meta information specific to a module.  Queries can be
 /// made by different debugging and exception handling schemes and reformated
 /// for specific use.
 ///
-class MachineModuleInfo {
+class LLVM_EXTERNAL_VISIBILITY MachineModuleInfo {
   friend class MachineModuleInfoWrapperPass;
   friend class MachineModuleAnalysis;
 
   const LLVMTargetMachine &TM;
 
   /// This is the MCContext used for the entire code generator.
   MCContext Context;
   // This is an external context, that if assigned, will be used instead of the
public:
 
   // MMI owes MCContext. It should never be invalidated.
   bool invalidate(Module &, const PreservedAnalyses &,
                   ModuleAnalysisManager::Invalidator &) {
     return false;
   }
 }; // End class MachineModuleInfo
 
-class MachineModuleInfoWrapperPass : public ImmutablePass {
+class LLVM_EXTERNAL_VISIBILITY MachineModuleInfoWrapperPass
+    : public ImmutablePass {
   MachineModuleInfo MMI;
 
 public:
   static char ID; // Pass identification, replacement for typeid
   explicit MachineModuleInfoWrapperPass(const LLVMTargetMachine *TM = nullptr);
 
   explicit MachineModuleInfoWrapperPass(const LLVMTargetMachine *TM,
                                         MCContext *ExtContext);

llvm/include/llvm/CodeGen/MachineModuleSlotTracker.h

 //===-- llvm/CodeGen/MachineModuleInfo.h ------------------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_CODEGEN_MACHINEMODULESLOTTRACKER_H
 #define LLVM_CODEGEN_MACHINEMODULESLOTTRACKER_H
 
 #include "llvm/IR/ModuleSlotTracker.h"
+#include "llvm/Support/Compiler.h"
 
 namespace llvm {
 
 class AbstractSlotTrackerStorage;
 class Function;
 class MachineModuleInfo;
 class MachineFunction;
 class Module;
 
-class MachineModuleSlotTracker : public ModuleSlotTracker {
+class LLVM_EXTERNAL_VISIBILITY MachineModuleSlotTracker
+    : public ModuleSlotTracker {
   const Function &TheFunction;
   const MachineModuleInfo &TheMMI;
   unsigned MDNStartSlot = 0, MDNEndSlot = 0;
 
   void processMachineFunctionMetadata(AbstractSlotTrackerStorage *AST,
                                       const MachineFunction &MF);
   void processMachineModule(AbstractSlotTrackerStorage *AST, const Module *M,
                             bool ShouldInitializeAllMetadata);

llvm/include/llvm/CodeGen/MachineOperand.h

 
 /// MachineOperand class - Representation of each machine instruction operand.
 ///
 /// This class isn't a POD type because it has a private constructor, but its
 /// destructor must be trivial. Functions like MachineInstr::addOperand(),
 /// MachineRegisterInfo::moveOperands(), and MF::DeleteMachineInstr() depend on
 /// not having to call the MachineOperand destructor.
 ///
-class MachineOperand {
+class LLVM_EXTERNAL_VISIBILITY MachineOperand {
 public:
   enum MachineOperandType : unsigned char {
     MO_Register,          ///< Register operand.
     MO_Immediate,         ///< Immediate operand
     MO_CImmediate,        ///< Immediate >64bit operand
     MO_FPImmediate,       ///< Floating-point immediate operand
     MO_MachineBasicBlock, ///< MachineBasicBlock reference
     MO_FrameIndex,        ///< Abstract Stack Frame Index

llvm/include/llvm/CodeGen/MachineRegisterInfo.h

 
 /// Convenient type to represent either a register class or a register bank.
 using RegClassOrRegBank =
     PointerUnion<const TargetRegisterClass *, const RegisterBank *>;
 
 /// MachineRegisterInfo - Keep track of information for virtual and physical
 /// registers, including vreg register classes, use/def chains for registers,
 /// etc.
-class MachineRegisterInfo {
+class LLVM_EXTERNAL_VISIBILITY MachineRegisterInfo {
 public:
   class Delegate {
     virtual void anchor();
 
   public:
     virtual ~Delegate() = default;
 
     virtual void MRI_NoteNewVirtualRegister(Register Reg) = 0;

llvm/include/llvm/CodeGen/NonRelocatableStringpool.h

 #include <vector>
 
 namespace llvm {
 
 /// A string table that doesn't need relocations.
 ///
 /// Use this class when a string table doesn't need relocations.
 /// This class provides this ability by just associating offsets with strings.
-class NonRelocatableStringpool {
+class LLVM_EXTERNAL_VISIBILITY NonRelocatableStringpool {
 public:
   /// Entries are stored into the StringMap and simply linked together through
   /// the second element of this pair in order to keep track of insertion
   /// order.
   using MapTy = StringMap<DwarfStringPoolEntry, BumpPtrAllocator>;
 
   NonRelocatableStringpool(
       std::function<StringRef(StringRef Input)> Translator = nullptr,

llvm/include/llvm/CodeGen/Passes.h

 class ModulePass;
 class Pass;
 class TargetMachine;
 class raw_ostream;
 
 } // End llvm namespace
 
 // List of target independent CodeGen pass IDs.
-namespace llvm {
+namespace llvm LLVM_EXTERNAL_VISIBILITY {
 
   /// AtomicExpandPass - At IR level this pass replace atomic instructions with
   /// __atomic_* library calls, or target specific instruction which implement the
   /// same semantics in a way which better fits the target backend.
   FunctionPass *createAtomicExpandPass();
 
   /// createUnreachableBlockEliminationPass - The LLVM code generator does not
   /// work well with unreachable basic blocks (what live ranges make sense for a

llvm/include/llvm/CodeGen/PseudoSourceValue.h

public:
   static bool classof(const PseudoSourceValue *V) {
     return V->kind() == ExternalSymbolCallEntry;
   }
 
   const char *getSymbol() const { return ES; }
 };
 
 /// Manages creation of pseudo source values.
-class PseudoSourceValueManager {
+class LLVM_EXTERNAL_VISIBILITY PseudoSourceValueManager {
   const TargetMachine &TM;
   const PseudoSourceValue StackPSV, GOTPSV, JumpTablePSV, ConstantPoolPSV;
   std::map<int, std::unique_ptr<FixedStackPseudoSourceValue>> FSValues;
   StringMap<std::unique_ptr<const ExternalSymbolPseudoSourceValue>>
       ExternalCallEntries;
   ValueMap<const GlobalValue *,
            std::unique_ptr<const GlobalValuePseudoSourceValue>>
       GlobalCallEntries;

llvm/include/llvm/CodeGen/SchedulerRegistry.h

public:
 
   static void setListener(MachinePassRegistryListener<FunctionPassCtor> *L) {
     Registry.setListener(L);
   }
 };
 
 /// createBURRListDAGScheduler - This creates a bottom up register usage
 /// reduction list scheduler.
+LLVM_EXTERNAL_VISIBILITY
 ScheduleDAGSDNodes *createBURRListDAGScheduler(SelectionDAGISel *IS,
                                                CodeGenOpt::Level OptLevel);
 
 /// createBURRListDAGScheduler - This creates a bottom up list scheduler that
 /// schedules nodes in source code order when possible.
+LLVM_EXTERNAL_VISIBILITY
 ScheduleDAGSDNodes *createSourceListDAGScheduler(SelectionDAGISel *IS,
                                                  CodeGenOpt::Level OptLevel);
 
 /// createHybridListDAGScheduler - This creates a bottom up register pressure
 /// aware list scheduler that make use of latency information to avoid stalls
 /// for long latency instructions in low register pressure mode. In high
 /// register pressure mode it schedules to reduce register pressure.
+LLVM_EXTERNAL_VISIBILITY
 ScheduleDAGSDNodes *createHybridListDAGScheduler(SelectionDAGISel *IS,
                                                  CodeGenOpt::Level);
 
 /// createILPListDAGScheduler - This creates a bottom up register pressure
 /// aware list scheduler that tries to increase instruction level parallelism
 /// in low register pressure mode. In high register pressure mode it schedules
 /// to reduce register pressure.
+LLVM_EXTERNAL_VISIBILITY
 ScheduleDAGSDNodes *createILPListDAGScheduler(SelectionDAGISel *IS,
                                               CodeGenOpt::Level);
 
 /// createFastDAGScheduler - This creates a "fast" scheduler.
 ///
+LLVM_EXTERNAL_VISIBILITY
 ScheduleDAGSDNodes *createFastDAGScheduler(SelectionDAGISel *IS,
                                            CodeGenOpt::Level OptLevel);
 
 /// createVLIWDAGScheduler - Scheduler for VLIW targets. This creates top down
 /// DFA driven list scheduler with clustering heuristic to control
 /// register pressure.
+LLVM_EXTERNAL_VISIBILITY
 ScheduleDAGSDNodes *createVLIWDAGScheduler(SelectionDAGISel *IS,
                                            CodeGenOpt::Level OptLevel);
 /// createDefaultScheduler - This creates an instruction scheduler appropriate
 /// for the target.
+LLVM_EXTERNAL_VISIBILITY
 ScheduleDAGSDNodes *createDefaultScheduler(SelectionDAGISel *IS,
                                            CodeGenOpt::Level OptLevel);
 
 /// createDAGLinearizer - This creates a "no-scheduling" scheduler which
 /// linearize the DAG using topological order.
+LLVM_EXTERNAL_VISIBILITY
 ScheduleDAGSDNodes *createDAGLinearizer(SelectionDAGISel *IS,
                                         CodeGenOpt::Level OptLevel);
 
 } // end namespace llvm
 
 #endif // LLVM_CODEGEN_SCHEDULERREGISTRY_H

llvm/include/llvm/CodeGen/TargetPassConfig.h

public:
   }
 };
 
 
 /// Target-Independent Code Generator Pass Configuration Options.
 ///
 /// This is an ImmutablePass solely for the purpose of exposing CodeGen options
 /// to the internals of other CodeGen passes.
-class TargetPassConfig : public ImmutablePass {
+class LLVM_EXTERNAL_VISIBILITY TargetPassConfig : public ImmutablePass {
 private:
   PassManagerBase *PM = nullptr;
   AnalysisID StartBefore = nullptr;
   AnalysisID StartAfter = nullptr;
   AnalysisID StopBefore = nullptr;
   AnalysisID StopAfter = nullptr;
 
   unsigned StartBeforeInstanceNum = 0;

llvm/include/llvm/IR/BuiltinGCs.h

 //===-- BuiltinGCs.h - Garbage collector linkage hacks --------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains hack functions to force linking in the builtin GC
 // components.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_IR_BUILTINGCS_H
 #define LLVM_IR_BUILTINGCS_H
 
+#include "llvm/Support/Compiler.h"
+
 namespace llvm {
 
 /// FIXME: Collector instances are not useful on their own. These no longer
 ///        serve any purpose except to link in the plugins.
 
 /// Ensure the definition of the builtin GCs gets linked in
 void linkAllBuiltinGCs();
 
 /// Creates an ocaml-compatible metadata printer.
+LLVM_EXTERNAL_VISIBILITY
 void linkOcamlGCPrinter();
 
 /// Creates an erlang-compatible metadata printer.
+LLVM_EXTERNAL_VISIBILITY
 void linkErlangGCPrinter();
 
 } // namespace llvm
 
 #endif // LLVM_IR_BUILTINGCS_H

llvm/include/llvm/InitializePasses.h

 //===- llvm/InitializePasses.h - Initialize All Passes ----------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains the declarations for the pass initialization routines
 // for the entire LLVM project.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_INITIALIZEPASSES_H
 #define LLVM_INITIALIZEPASSES_H
 
-namespace llvm {
+#include "llvm/Support/Compiler.h"
+
+namespace llvm LLVM_EXTERNAL_VISIBILITY {
 
 class PassRegistry;
 
 /// Initialize all passes linked into the Core library.
 void initializeCore(PassRegistry&);
 
 /// Initialize all passes linked into the TransformUtils library.
 void initializeTransformUtils(PassRegistry&);

llvm/lib/CodeGen/CMakeLists.txt

+if (LLVM_CAN_USE_HIDDEN_VISIBILITY)
+  set(CMAKE_CXX_VISIBILITY_PRESET hidden)
+endif()
+
 if (DEFINED LLVM_HAVE_TF_AOT OR DEFINED LLVM_HAVE_TF_API)
   include(TensorFlowCompile)
   set(LLVM_RAEVICT_MODEL_PATH_DEFAULT "models/regalloc-eviction")
 
   set(LLVM_RAEVICT_MODEL_CURRENT_URL "<UNSPECIFIED>" CACHE STRING "URL to download the LLVM register allocator eviction model")
 
   if (DEFINED LLVM_HAVE_TF_AOT)
     tf_find_and_compile(

llvm/lib/Target/CMakeLists.txt

add_llvm_component_library(LLVMTarget
   Analysis
   Core
   MC
   Support
   )
 
 # When building shared objects for each target there are some internal APIs
 # that are used across shared objects which we can't hide.
-if (NOT BUILD_SHARED_LIBS AND NOT APPLE AND
-    (NOT (WIN32 OR CYGWIN) OR (MINGW AND CMAKE_CXX_COMPILER_ID MATCHES "Clang")) AND
-    NOT (${CMAKE_SYSTEM_NAME} MATCHES "AIX") AND
-    NOT DEFINED CMAKE_CXX_VISIBILITY_PRESET)
-  # Set default visibility to hidden, so we don't export all the Target classes
-  # in libLLVM.so.
+if (LLVM_CAN_USE_HIDDEN_VISIBILITY)
   set(CMAKE_CXX_VISIBILITY_PRESET hidden)
 endif()
 
 foreach(t ${LLVM_TARGETS_TO_BUILD})
   message(STATUS "Targeting ${t}")
   add_subdirectory(${t})
 endforeach()
 
 # Currently we do not allow libraries from lib to reference targets directly.
 # This property is used to enforce that convention. It is important because the
 # logic in llvm_map_components_to_libnames is order dependent on the target
 # libraries being created.
 set_property(GLOBAL PROPERTY LLVM_TARGETS_CONFIGURED On)