[DAG] select Cond, C, -1 --> or (sext (not Cond)), C when C is MVT::i1

[deadalnix]

Summary

In the spirit of D130765 . Get rid of cbranches and/or cmov. Usually shorter, but sometime not, becaus eit's hard to prededict when dependency breaking xor will be introduced.

[RKSimon]

llvm/test/CodeGen/X86/cmov-promotion.ll

124 ↗

(On Diff #463214)

Some of these test need duplicating as we need to retain test coverage for the cases where cmov will still be used (i.e. the RHS select != -1) , but also keep these tests for the cmov-less coverage.

[deadalnix]

Add a test case for this spercifically in select_const and modify cmov-promotion so that this optimization doesn't kick in.

[RKSimon]

LGTM

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

if (shouldConvertSelectOfConstantsToMath(Cond, VT, TLI)) {
       }
 
       // select Cond, -1, C --> or (sext Cond), C
       if (C1->isAllOnes()) {
         Cond = DAG.getSExtOrTrunc(Cond, DL, VT);
         return DAG.getNode(ISD::OR, DL, VT, Cond, N2);
       }
 
+      // select Cond, C, -1 --> or (sext (not Cond)), C
+      if (C2->isAllOnes()) {
+        SDValue NotCond = DAG.getNOT(DL, Cond, MVT::i1);
+        NotCond = DAG.getSExtOrTrunc(NotCond, DL, VT);
+        return DAG.getNode(ISD::OR, DL, VT, NotCond, N1);
+      }
+
       if (SDValue V = foldSelectOfConstantsUsingSra(N, DAG))
         return V;
     }
 
     return SDValue();
   }
 
   // fold (select Cond, 0, 1) -> (xor Cond, 1)

llvm/test/CodeGen/X86/pr16031.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=i386-unknown-linux-gnu -mcpu=corei7-avx -enable-misched=false | FileCheck %s
 
 define i64 @main(i1 %tobool1) nounwind {
 ; CHECK-LABEL: main:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    testb $1, {{[0-9]+}}(%esp)
-; CHECK-NEXT:    movl $-12, %ecx
-; CHECK-NEXT:    movl $-1, %eax
-; CHECK-NEXT:    cmovnel %ecx, %eax
+; CHECK-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    andl $1, %eax
+; CHECK-NEXT:    decl %eax
+; CHECK-NEXT:    orl $-12, %eax
 ; CHECK-NEXT:    xorl %ecx, %ecx
 ; CHECK-NEXT:    movl %eax, %edx
 ; CHECK-NEXT:    addl $-1, %edx
 ; CHECK-NEXT:    movl $0, %edx
 ; CHECK-NEXT:    adcl $-2, %edx
 ; CHECK-NEXT:    cmovsl %ecx, %eax
 ; CHECK-NEXT:    xorl %edx, %edx
 ; CHECK-NEXT:    retl

llvm/test/CodeGen/X86/select_const.ll

 }
 
 ; No LEA with 8-bit, but this shouldn't need branches or cmov.
 
 define i8 @sel_1_neg1(i32 %x) {
 ; CHECK-LABEL: sel_1_neg1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    cmpl $43, %edi
-; CHECK-NEXT:    setge %al
-; CHECK-NEXT:    shlb $2, %al
-; CHECK-NEXT:    decb %al
+; CHECK-NEXT:    setl %al
+; CHECK-NEXT:    negb %al
+; CHECK-NEXT:    orb $3, %al
 ; CHECK-NEXT:    retq
   %cmp = icmp sgt i32 %x, 42
   %sel = select i1 %cmp, i8 3, i8 -1
   ret i8 %sel
 }
 
 ; We get an LEA for 16-bit because we ignore the high-bits.
 

 ; CHECK-NEXT:    retq
   %sel = select i1 %cond, i32 421, i32 42
   ret i32 %sel
 }
 
 define i32 @select_n_or_minus1(i1 signext %cond) {
 ; CHECK-LABEL: select_n_or_minus1:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    testb $1, %dil
-; CHECK-NEXT:    movl $12414, %ecx # imm = 0x307E
-; CHECK-NEXT:    movl $-1, %eax
-; CHECK-NEXT:    cmovnel %ecx, %eax
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    notl %eax
+; CHECK-NEXT:    orl $12414, %eax # imm = 0x307E
 ; CHECK-NEXT:    retq
   %sel = select i1 %cond, i32 12414, i32 -1
   ret i32 %sel
 }
 
 ; select (x == 2), 2, (x + 1) --> select (x == 2), x, (x + 1)
 
 define i64 @select_2_or_inc(i64 %x) {

llvm/test/CodeGen/X86/zext-sext.ll

 ; CHECK-LABEL: func:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    movslq (%rsi), %rax
 ; CHECK-NEXT:    movl $4, %esi
 ; CHECK-NEXT:    subq %rax, %rsi
 ; CHECK-NEXT:    movq (%rdx), %rax
 ; CHECK-NEXT:    movswl 8(%rdi), %edx
 ; CHECK-NEXT:    movswl (%rax,%rsi,2), %eax
-; CHECK-NEXT:    movl $1, %esi
 ; CHECK-NEXT:    imull %edx, %eax
-; CHECK-NEXT:    xorl %edx, %edx
 ; CHECK-NEXT:    addl $2138875574, %eax # imm = 0x7F7CA6B6
-; CHECK-NEXT:    cmpl $-8608074, %eax # imm = 0xFF7CA6B6
-; CHECK-NEXT:    movslq %eax, %rdi
-; CHECK-NEXT:    setl %dl
 ; CHECK-NEXT:    cmpl $2138875574, %eax # imm = 0x7F7CA6B6
-; CHECK-NEXT:    movq %rdi, %r8
-; CHECK-NEXT:    leal -1(%rdx,%rdx), %edx
-; CHECK-NEXT:    cmovll %edx, %esi
-; CHECK-NEXT:    subq %rax, %r8
+; CHECK-NEXT:    setl %sil
+; CHECK-NEXT:    cmpl $-8608074, %eax # imm = 0xFF7CA6B6
+; CHECK-NEXT:    setge %dl
+; CHECK-NEXT:    andb %sil, %dl
+; CHECK-NEXT:    movslq %eax, %rsi
+; CHECK-NEXT:    movzbl %dl, %edx
+; CHECK-NEXT:    movq %rsi, %rdi
+; CHECK-NEXT:    subq %rax, %rdi
+; CHECK-NEXT:    negl %edx
 ; CHECK-NEXT:    xorl %eax, %eax
-; CHECK-NEXT:    cmpl $1, %esi
-; CHECK-NEXT:    cmovneq %rax, %r8
-; CHECK-NEXT:    testl %edi, %edi
-; CHECK-NEXT:    cmovnsq %rax, %r8
+; CHECK-NEXT:    testl $-2, %edx
+; CHECK-NEXT:    cmovneq %rax, %rdi
+; CHECK-NEXT:    testl %esi, %esi
+; CHECK-NEXT:    cmovnsq %rax, %rdi
 ; CHECK-NEXT:    movq (%rcx), %rax
-; CHECK-NEXT:    subq %r8, %rdi
-; CHECK-NEXT:    leaq -2138875574(%rax,%rdi), %rax
+; CHECK-NEXT:    subq %rdi, %rsi
+; CHECK-NEXT:    leaq -2138875574(%rax,%rsi), %rax
 ; CHECK-NEXT:    movq %rax, (%rcx)
 ; CHECK-NEXT:    retq
 entry:
   %tmp103 = getelementptr inbounds [40 x i16], ptr %a, i64 0, i64 4
   %tmp104 = load i16, ptr %tmp103, align 2
   %tmp105 = sext i16 %tmp104 to i32
   %tmp106 = load i32, ptr %b, align 4
   %tmp107 = sub nsw i32 4, %tmp106