[Clang][LoongArch] Add inline asm support for constraints k/m/ZB/ZC

[SixWeining]

Summary

Reference: https://gcc.gnu.org/onlinedocs/gccint/Machine-Constraints.html

k: A memory operand whose address is formed by a base register and
(optionally scaled) index register.

m: A memory operand whose address is formed by a base register and
offset that is suitable for use in instructions with the same
addressing mode as st.w and ld.w.

ZB: An address that is held in a general-purpose register. The offset
is zero.

ZC: A memory operand whose address is formed by a base register and
offset that is suitable for use in instructions with the same
addressing mode as ll.w and sc.w.

Note:
The INLINEASM SDNode flags in below tests are updated because the new
introduced enum Constraint_k is added before Constraint_m.

llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
llvm/test/CodeGen/X86/callbr-asm-kill.mir

This patch passes ninja check-all on a X86 machine with all official
targets and the LoongArch target enabled.

[xen0n]

The test cases look good to me. We should be pretty close to passing ninja check natively. Thanks!

[rengolin]

Looks good, with some nits. Thanks!

llvm/lib/Target/LoongArch/LoongArchAsmPrinter.cpp

76

NIT: Use early exit.

if (ExtraCode)
  return false;

llvm/test/CodeGen/LoongArch/inline-asm-constraint-ZC.ll

17

Same comment as before, these CHECK lines look identical for both targets...

[MaskRay]

clang/lib/Basic/Targets/LoongArch.cpp

103

++Name

117

First std::string can be omitted

118

pre-increment

[MaskRay]

llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp

92

Prefer initializing the variable when it is declared

113

Prefer initializing the variable when it is declared

[SixWeining]

Address comments from @rengolin and @MaskRay. Thanks.

clang/lib/Basic/Targets/LoongArch.cpp

117

Thanks.

llvm/lib/Target/LoongArch/LoongArchAsmPrinter.cpp

76

Thanks. But we should return true but not false.

llvm/test/CodeGen/LoongArch/inline-asm-constraint-ZC.ll

17

Unfortunately this is not the case becuase different instructions like add.w/add.d are used by LA32 and LA64 respectively.

[SixWeining]

Handle k and ZB in llvm/include/llvm/IR/InlineAsm.h::getMemConstraintName and add relevant tests.

[SixWeining]

Remove the first line "Assertions" in inline-asm-constraint-ZB.ll as it is not autogenerated.

[MaskRay]

Constraint_k somehow broke AArch64 and X86 inlineasm. Please run at least check-llvm check-clang for generic changes which may have farreaching effects to other targets.

[SixWeining]

The flag in the INLINEASM SDNode in llvm/test/CodeGen/X86/callbr-asm-kill.mir is updated because enum Constraint_k is added before Constraint_m.

[SixWeining]

In D134638#3822926, @MaskRay wrote:

Constraint_k somehow broke AArch64 and X86 inlineasm. Please run at least check-llvm check-clang for generic changes which may have farreaching effects to other targets.

Sorry for that. I have fix it. The fail is casued by a hard coded INLINEASM SDNode flag. I have updated it. Thanks.

[xen0n]

The previous test results (with some of my WIP patches but unrelated to this) before the fix:

Failed Tests (6):
  LLVM :: CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll
  LLVM :: CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
  LLVM :: CodeGen/Generic/vector.ll
  LLVM :: CodeGen/PowerPC/2007-11-19-VectorSplitting.ll
  LLVM :: CodeGen/X86/callbr-asm-kill.mir
  LLVM :: DebugInfo/Generic/missing-abstract-variable.ll

Sure enough it was caught by my native build with all targets enabled, anyway it's important to at least enable the "big" targets such as X86 and AArch64 when configuring the local dev env. ;-)

[SixWeining]

update CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll and CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll

[SixWeining]

In D134638#3823379, @xen0n wrote:

The previous test results (with some of my WIP patches but unrelated to this) before the fix:

Failed Tests (6):
  LLVM :: CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll
  LLVM :: CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
  LLVM :: CodeGen/Generic/vector.ll
  LLVM :: CodeGen/PowerPC/2007-11-19-VectorSplitting.ll
  LLVM :: CodeGen/X86/callbr-asm-kill.mir
  LLVM :: DebugInfo/Generic/missing-abstract-variable.ll

Sure enough it was caught by my native build with all targets enabled, anyway it's important to at least enable the "big" targets such as X86 and AArch64 when configuring the local dev env. ;-)

Thanks for the tip. Just now I enabled all official targets and LoongArch and find 2 more fail tests (for same reason) for AArch64 and AMDGPU. I have fixed them and updated the patch.

Sorry again...

[SixWeining]

A polite ping...

clang/lib/Basic/Targets/LoongArch.h

public:
   const char *getClobbers() const override { return ""; }
 
   ArrayRef<const char *> getGCCRegNames() const override;
 
   ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
 
   bool validateAsmConstraint(const char *&Name,
                              TargetInfo::ConstraintInfo &Info) const override;
+  std::string convertConstraint(const char *&Constraint) const override;
 
   bool hasBitIntType() const override { return true; }
 };
 
 class LLVM_LIBRARY_VISIBILITY LoongArch32TargetInfo
     : public LoongArchTargetInfo {
 public:
   LoongArch32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)

clang/lib/Basic/Targets/LoongArch.cpp

LoongArchTargetInfo::getGCCRegAliases() const {
   };
   return llvm::makeArrayRef(GCCRegAliases);
 }
 
 bool LoongArchTargetInfo::validateAsmConstraint(
     const char *&Name, TargetInfo::ConstraintInfo &Info) const {
   // See the GCC definitions here:
   // https://gcc.gnu.org/onlinedocs/gccint/Machine-Constraints.html
+  // Note that the 'm' constraint is handled in TargetInfo.
   switch (*Name) {
-  // TODO: handle 'k', 'm', "ZB", "ZC".
   default:
     return false;
   case 'f':
     // A floating-point register (if available).
     Info.setAllowsRegister();
     return true;
+  case 'k':
+    // A memory operand whose address is formed by a base register and
+    // (optionally scaled) index register.
+    Info.setAllowsMemory();
+    return true;
   case 'l':
     // A signed 16-bit constant.
     Info.setRequiresImmediate(-32768, 32767);
     return true;
   case 'I':
     // A signed 12-bit constant (for arithmetic instructions).
     Info.setRequiresImmediate(-2048, 2047);
     return true;
   case 'K':
     // An unsigned 12-bit constant (for logic instructions).
     Info.setRequiresImmediate(0, 4095);
     return true;
+  case 'Z':
+    // ZB: An address that is held in a general-purpose register. The offset is
+    //     zero.
+    // ZC: A memory operand whose address is formed by a base register
+    //     and offset that is suitable for use in instructions with the same
+    //     addressing mode as ll.w and sc.w.
+    if (Name[1] == 'C' || Name[1] == 'B') {
+      Info.setAllowsMemory();
+      ++Name; // Skip over 'Z'.
+      return true;
+    }
+    return false;
+  }
+}
+
+std::string
+LoongArchTargetInfo::convertConstraint(const char *&Constraint) const {
+  std::string R;
+  switch (*Constraint) {
+  case 'Z':
+    // "ZC"/"ZB" are two-character constraints; add "^" hint for later
+    // parsing.
+    R = "^" + std::string(Constraint, 2);
+    ++Constraint;
+    break;
+  default:
+    R = TargetInfo::convertConstraint(Constraint);
+    break;
   }
+  return R;
 }
 
 void LoongArchTargetInfo::getTargetDefines(const LangOptions &Opts,
                                            MacroBuilder &Builder) const {
   Builder.defineMacro("__loongarch__");
   // TODO: Define more macros.
 }
 
 ArrayRef<Builtin::Info> LoongArchTargetInfo::getTargetBuiltins() const {
   // TODO: To be implemented in future.
   return {};
 }

clang/test/CodeGen/LoongArch/inline-asm-constraints.c

 // CHECK: [[FLT_ARG:%[a-zA-Z_0-9]+]] = load float, ptr @f
 // CHECK: call void asm sideeffect "", "f"(float [[FLT_ARG]])
   asm volatile ("" :: "f"(f));
 // CHECK: [[FLT_ARG:%[a-zA-Z_0-9]+]] = load double, ptr @d
 // CHECK: call void asm sideeffect "", "f"(double [[FLT_ARG]])
   asm volatile ("" :: "f"(d));
 }
 
+void test_k(int *p, int idx) {
+// CHECK-LABEL: define{{.*}} void @test_k(ptr noundef %p, i32 noundef{{.*}} %idx)
+// CHECK: call void asm sideeffect "", "*k"(ptr elementtype(i32) %{{.*}})
+  asm volatile("" :: "k"(*(p+idx)));
+}
+
 void test_l(void) {
 // CHECK-LABEL: define{{.*}} void @test_l()
 // CHECK: call void asm sideeffect "", "l"(i32 32767)
   asm volatile ("" :: "l"(32767));
 // CHECK: call void asm sideeffect "", "l"(i32 -32768)
   asm volatile ("" :: "l"(-32768));
 }
 
+void test_m(int *p) {
+// CHECK-LABEL: define{{.*}} void @test_m(ptr noundef %p)
+// CHECK: call void asm sideeffect "", "*m"(ptr nonnull elementtype(i32) %{{.*}})
+  asm volatile("" :: "m"(*(p+4)));
+}
+
 void test_I(void) {
 // CHECK-LABEL: define{{.*}} void @test_I()
 // CHECK: call void asm sideeffect "", "I"(i32 2047)
   asm volatile ("" :: "I"(2047));
 // CHECK: call void asm sideeffect "", "I"(i32 -2048)
   asm volatile ("" :: "I"(-2048));
 }
 
 void test_K(void) {
 // CHECK-LABEL: define{{.*}} void @test_K()
 // CHECK: call void asm sideeffect "", "K"(i32 4095)
   asm volatile ("" :: "K"(4095));
 // CHECK: call void asm sideeffect "", "K"(i32 0)
   asm volatile ("" :: "K"(0));
 }
+
+void test_ZB(int *p) {
+// CHECK-LABEL: define{{.*}} void @test_ZB(ptr noundef %p)
+// CHECK: call void asm sideeffect "", "*^ZB"(ptr elementtype(i32) %p)
+  asm volatile ("" :: "ZB"(*p));
+}
+
+void test_ZC(int *p) {
+// CHECK-LABEL: define{{.*}} void @test_ZC(ptr noundef %p)
+// CHECK: call void asm sideeffect "", "*^ZC"(ptr elementtype(i32) %p)
+  asm volatile ("" :: "ZC"(*p));
+}

llvm/include/llvm/IR/InlineAsm.h

enum : uint32_t {
     // there's plenty of space in the encoding to support the union of all
     // constraint codes for all targets.
     // Addresses are included here as they need to be treated the same by the
     // backend, the only difference is that they are not used to actaully
     // access memory by the instruction.
     Constraint_Unknown = 0,
     Constraint_es,
     Constraint_i,
+    Constraint_k,
     Constraint_m,
     Constraint_o,
     Constraint_v,
     Constraint_A,
     Constraint_Q,
     Constraint_R,
     Constraint_S,
     Constraint_T,
     Constraint_Um,
     Constraint_Un,
     Constraint_Uq,
     Constraint_Us,
     Constraint_Ut,
     Constraint_Uv,
     Constraint_Uy,
     Constraint_X,
     Constraint_Z,
+    Constraint_ZB,
     Constraint_ZC,
     Constraint_Zy,
 
     // Address constraints
     Constraint_p,
     Constraint_ZQ,
     Constraint_ZR,
     Constraint_ZS,

llvm/lib/Target/LoongArch/LoongArchAsmPrinter.h

public:
   }
 
   bool runOnMachineFunction(MachineFunction &MF) override;
 
   void emitInstruction(const MachineInstr *MI) override;
 
   bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
                        const char *ExtraCode, raw_ostream &OS) override;
+  bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
+                             const char *ExtraCode, raw_ostream &OS) override;
 
   // tblgen'erated function.
   bool emitPseudoExpansionLowering(MCStreamer &OutStreamer,
                                    const MachineInstr *MI);
   // Wrapper needed for tblgenned pseudo lowering.
   bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const {
     return lowerLoongArchMachineOperandToMCOperand(MO, MCOp, *this);
   }
 };
 
 } // end namespace llvm
 
 #endif // LLVM_LIB_TARGET_LOONGARCH_LOONGARCHASMPRINTER_H

llvm/lib/Target/LoongArch/LoongArchAsmPrinter.cpp

if (!ExtraCode) {
     default:
       llvm_unreachable("not implemented");
     }
   }
 
   return true;
 }
 
+bool LoongArchAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
+                                                unsigned OpNo,
+                                                const char *ExtraCode,
+                                                raw_ostream &OS) {
+  // TODO: handle extra code.
+  if (ExtraCode)
+    return true;
+
+  const MachineOperand &BaseMO = MI->getOperand(OpNo);
+  // Base address must be a register.
+  if (!BaseMO.isReg())
+    return true;
+  // Print the base address register.
+  OS << "$" << LoongArchInstPrinter::getRegisterName(BaseMO.getReg());
+  // Print the offset register or immediate if has.
+  if (OpNo + 1 < MI->getNumOperands()) {
+    const MachineOperand &OffsetMO = MI->getOperand(OpNo + 1);
+    if (OffsetMO.isReg())
+      OS << ", $" << LoongArchInstPrinter::getRegisterName(OffsetMO.getReg());
+    else if (OffsetMO.isImm())
+      OS << ", " << OffsetMO.getImm();
+    else
+      return true;
+  }
+  return false;
+
+  return AsmPrinter::PrintAsmMemoryOperand(MI, OpNo, ExtraCode, OS);
+}
+
 bool LoongArchAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
   AsmPrinter::runOnMachineFunction(MF);
   return true;
 }
 
 // Force static initialization.
 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeLoongArchAsmPrinter() {
   RegisterAsmPrinter<LoongArchAsmPrinter> X(getTheLoongArch32Target());
   RegisterAsmPrinter<LoongArchAsmPrinter> Y(getTheLoongArch64Target());
 }

llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.h

public:
 
   bool runOnMachineFunction(MachineFunction &MF) override {
     Subtarget = &MF.getSubtarget<LoongArchSubtarget>();
     return SelectionDAGISel::runOnMachineFunction(MF);
   }
 
   void Select(SDNode *Node) override;
 
+  bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
+                                    std::vector<SDValue> &OutOps) override;
+
   bool SelectBaseAddr(SDValue Addr, SDValue &Base);
 
   bool selectShiftMask(SDValue N, unsigned ShiftWidth, SDValue &ShAmt);
   bool selectShiftMaskGRLen(SDValue N, SDValue &ShAmt) {
     return selectShiftMask(N, Subtarget->getGRLen(), ShAmt);
   }
   bool selectShiftMask32(SDValue N, SDValue &ShAmt) {
     return selectShiftMask(N, 32, ShAmt);

llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp

void LoongArchDAGToDAGISel::Select(SDNode *Node) {
   }
     // TODO: Add selection nodes needed later.
   }
 
   // Select the default instruction.
   SelectCode(Node);
 }
 
+bool LoongArchDAGToDAGISel::SelectInlineAsmMemoryOperand(
+    const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) {
+  switch (ConstraintID) {
+  default:
+    llvm_unreachable("unexpected asm memory constraint");
+  // Reg+Reg addressing.
+  case InlineAsm::Constraint_k:
+    OutOps.push_back(Op.getOperand(0));
+    OutOps.push_back(Op.getOperand(1));
+    return false;
+  // Reg+simm12 addressing.
+  case InlineAsm::Constraint_m: {
+    SDValue Base = Op;
+    SDValue Offset =
+        CurDAG->getTargetConstant(0, SDLoc(Op), Subtarget->getGRLenVT());
+    if (CurDAG->isBaseWithConstantOffset(Op)) {
+      ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op.getOperand(1));
+      if (isIntN(12, CN->getSExtValue())) {
+        Base = Op.getOperand(0);
+        Offset = CurDAG->getTargetConstant(CN->getZExtValue(), SDLoc(Op),
+                                           Op.getValueType());
+      }
+    }
+    OutOps.push_back(Base);
+    OutOps.push_back(Offset);
+    return false;
+  }
+  case InlineAsm::Constraint_ZB:
+    OutOps.push_back(Op);
+    // No offset.
+    return false;
+  // Reg+(simm14<<2) addressing.
+  case InlineAsm::Constraint_ZC: {
+    SDValue Base = Op;
+    SDValue Offset =
+        CurDAG->getTargetConstant(0, SDLoc(Op), Subtarget->getGRLenVT());
+    if (CurDAG->isBaseWithConstantOffset(Op)) {
+      ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op.getOperand(1));
+      if (isIntN(16, CN->getSExtValue()) &&
+          isAligned(Align(4ULL), CN->getZExtValue())) {
+        Base = Op.getOperand(0);
+        Offset = CurDAG->getTargetConstant(CN->getZExtValue(), SDLoc(Op),
+                                           Op.getValueType());
+      }
+    }
+    OutOps.push_back(Base);
+    OutOps.push_back(Offset);
+    return false;
+  }
+  }
+  return true;
+}
+
 bool LoongArchDAGToDAGISel::SelectBaseAddr(SDValue Addr, SDValue &Base) {
   // If this is FrameIndex, select it directly. Otherwise just let it get
   // selected to a register independently.
   if (auto *FIN = dyn_cast<FrameIndexSDNode>(Addr))
     Base =
         CurDAG->getTargetFrameIndex(FIN->getIndex(), Subtarget->getGRLenVT());
   else
     Base = Addr;

llvm/lib/Target/LoongArch/LoongArchISelLowering.h

private:
 
   bool isFPImmLegal(const APFloat &Imm, EVT VT,
                     bool ForCodeSize) const override;
 
   bool shouldInsertFencesForAtomic(const Instruction *I) const override;
 
   ConstraintType getConstraintType(StringRef Constraint) const override;
 
+  unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override;
+
   std::pair<unsigned, const TargetRegisterClass *>
   getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
                                StringRef Constraint, MVT VT) const override;
 
   void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
                                     std::vector<SDValue> &Ops,
                                     SelectionDAG &DAG) const override;
 };
 
 } // end namespace llvm
 
 #endif // LLVM_LIB_TARGET_LOONGARCH_LOONGARCHISELLOWERING_H

llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

if (Constraint.size() == 1) {
     default:
       break;
     case 'f':
       return C_RegisterClass;
     case 'l':
     case 'I':
     case 'K':
       return C_Immediate;
+    case 'k':
+      return C_Memory;
     }
   }
 
-  // TODO: handle 'k", "ZB" and "ZC".
+  if (Constraint == "ZC" || Constraint == "ZB")
+    return C_Memory;
 
+  // 'm' is handled here.
   return TargetLowering::getConstraintType(Constraint);
 }
 
+unsigned LoongArchTargetLowering::getInlineAsmMemConstraint(
+    StringRef ConstraintCode) const {
+  return StringSwitch<unsigned>(ConstraintCode)
+      .Case("k", InlineAsm::Constraint_k)
+      .Case("ZB", InlineAsm::Constraint_ZB)
+      .Case("ZC", InlineAsm::Constraint_ZC)
+      .Default(TargetLowering::getInlineAsmMemConstraint(ConstraintCode));
+}
+
 std::pair<unsigned, const TargetRegisterClass *>
 LoongArchTargetLowering::getRegForInlineAsmConstraint(
     const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
   // First, see if this is a constraint that directly corresponds to a LoongArch
   // register class.
   if (Constraint.size() == 1) {
     switch (Constraint[0]) {
     case 'r':

llvm/test/CodeGen/LoongArch/inline-asm-constraint-ZB.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch64 --verify-machineinstrs < %s | FileCheck %s
+
+;; Note amswap.w is not available on loongarch32.
+
+define void @ZB(ptr %p) nounwind {
+; CHECK-LABEL: ZB:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    amswap.w $t0, $t1, $a0
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    ret
+  call void asm "amswap.w $$r12, $$r13, $0", "*^ZB"(ptr elementtype(i32) %p)
+  ret void
+}
+
+define void @ZB_constant_offset(ptr %p) nounwind {
+; CHECK-LABEL: ZB_constant_offset:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi.d $a0, $a0, 1
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    amswap.w $t0, $t1, $a0
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    ret
+  %1 = getelementptr inbounds i8, ptr %p, i32 1
+  call void asm "amswap.w $$r12, $$r13, $0", "*^ZB"(ptr elementtype(i32) %1)
+  ret void
+}
+
+define void @ZB_variable_offset(ptr %p, i32 signext %idx) nounwind {
+; CHECK-LABEL: ZB_variable_offset:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    add.d $a0, $a0, $a1
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    amswap.w $t0, $t1, $a0
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    ret
+  %1 = getelementptr inbounds i8, ptr %p, i32 %idx
+  call void asm "amswap.w $$r12, $$r13, $0", "*^ZB"(ptr elementtype(i32) %1)
+  ret void
+}

llvm/test/CodeGen/LoongArch/inline-asm-constraint-ZC.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --verify-machineinstrs < %s | FileCheck %s --check-prefix=LA32
+; RUN: llc --mtriple=loongarch64 --verify-machineinstrs < %s | FileCheck %s --check-prefix=LA64
+
+define i32 @ZC_offset_neg_32769(ptr %p) nounwind {
+; LA32-LABEL: ZC_offset_neg_32769:
+; LA32:       # %bb.0:
+; LA32-NEXT:    lu12i.w $a1, -9
+; LA32-NEXT:    ori $a1, $a1, 4095
+; LA32-NEXT:    add.w $a0, $a0, $a1
+; LA32-NEXT:    #APP
+; LA32-NEXT:    ll.w $a0, $a0, 0
+; LA32-NEXT:    #NO_APP
+; LA32-NEXT:    ret
+;
+; LA64-LABEL: ZC_offset_neg_32769:
+; LA64:       # %bb.0:
+; LA64-NEXT:    lu12i.w $a1, -9
+; LA64-NEXT:    ori $a1, $a1, 4095
+; LA64-NEXT:    add.d $a0, $a0, $a1
+; LA64-NEXT:    #APP
+; LA64-NEXT:    ll.w $a0, $a0, 0
+; LA64-NEXT:    #NO_APP
+; LA64-NEXT:    ret
+  %1 = getelementptr inbounds i8, ptr %p, i32 -32769
+  %2 = call i32 asm "ll.w $0, $1", "=r,*^ZC"(ptr elementtype(i32) %1)
+  ret i32 %2
+}
+
+define i32 @ZC_offset_neg_32768(ptr %p) nounwind {
+; LA32-LABEL: ZC_offset_neg_32768:
+; LA32:       # %bb.0:
+; LA32-NEXT:    #APP
+; LA32-NEXT:    ll.w $a0, $a0, -32768
+; LA32-NEXT:    #NO_APP
+; LA32-NEXT:    ret
+;
+; LA64-LABEL: ZC_offset_neg_32768:
+; LA64:       # %bb.0:
+; LA64-NEXT:    #APP
+; LA64-NEXT:    ll.w $a0, $a0, -32768
+; LA64-NEXT:    #NO_APP
+; LA64-NEXT:    ret
+  %1 = getelementptr inbounds i8, ptr %p, i32 -32768
+  %2 = call i32 asm "ll.w $0, $1", "=r,*^ZC"(ptr elementtype(i32) %1)
+  ret i32 %2
+}
+
+define i32 @ZC_offset_neg_4(ptr %p) nounwind {
+; LA32-LABEL: ZC_offset_neg_4:
+; LA32:       # %bb.0:
+; LA32-NEXT:    #APP
+; LA32-NEXT:    ll.w $a0, $a0, -4
+; LA32-NEXT:    #NO_APP
+; LA32-NEXT:    ret
+;
+; LA64-LABEL: ZC_offset_neg_4:
+; LA64:       # %bb.0:
+; LA64-NEXT:    #APP
+; LA64-NEXT:    ll.w $a0, $a0, -4
+; LA64-NEXT:    #NO_APP
+; LA64-NEXT:    ret
+  %1 = getelementptr inbounds i8, ptr %p, i32 -4
+  %2 = call i32 asm "ll.w $0, $1", "=r,*^ZC"(ptr elementtype(i32) %1)
+  ret i32 %2
+}
+
+define i32 @ZC_offset_neg_1(ptr %p) nounwind {
+; LA32-LABEL: ZC_offset_neg_1:
+; LA32:       # %bb.0:
+; LA32-NEXT:    addi.w $a0, $a0, -1
+; LA32-NEXT:    #APP
+; LA32-NEXT:    ll.w $a0, $a0, 0
+; LA32-NEXT:    #NO_APP
+; LA32-NEXT:    ret
+;
+; LA64-LABEL: ZC_offset_neg_1:
+; LA64:       # %bb.0:
+; LA64-NEXT:    addi.d $a0, $a0, -1
+; LA64-NEXT:    #APP
+; LA64-NEXT:    ll.w $a0, $a0, 0
+; LA64-NEXT:    #NO_APP
+; LA64-NEXT:    ret
+  %1 = getelementptr inbounds i8, ptr %p, i32 -1
+  %2 = call i32 asm "ll.w $0, $1", "=r,*^ZC"(ptr elementtype(i32) %1)
+  ret i32 %2
+}
+
+define i32 @ZC_offset_0(ptr %p) nounwind {
+; LA32-LABEL: ZC_offset_0:
+; LA32:       # %bb.0:
+; LA32-NEXT:    #APP
+; LA32-NEXT:    ll.w $a0, $a0, 0
+; LA32-NEXT:    #NO_APP
+; LA32-NEXT:    ret
+;
+; LA64-LABEL: ZC_offset_0:
+; LA64:       # %bb.0:
+; LA64-NEXT:    #APP
+; LA64-NEXT:    ll.w $a0, $a0, 0
+; LA64-NEXT:    #NO_APP
+; LA64-NEXT:    ret
+  %1 = call i32 asm "ll.w $0, $1", "=r,*^ZC"(ptr elementtype(i32) %p)
+  ret i32 %1
+}
+
+define i32 @ZC_offset_1(ptr %p) nounwind {
+; LA32-LABEL: ZC_offset_1:
+; LA32:       # %bb.0:
+; LA32-NEXT:    addi.w $a0, $a0, 1
+; LA32-NEXT:    #APP
+; LA32-NEXT:    ll.w $a0, $a0, 0
+; LA32-NEXT:    #NO_APP
+; LA32-NEXT:    ret
+;
+; LA64-LABEL: ZC_offset_1:
+; LA64:       # %bb.0:
+; LA64-NEXT:    addi.d $a0, $a0, 1
+; LA64-NEXT:    #APP
+; LA64-NEXT:    ll.w $a0, $a0, 0
+; LA64-NEXT:    #NO_APP
+; LA64-NEXT:    ret
+  %1 = getelementptr inbounds i8, ptr %p, i32 1
+  %2 = call i32 asm "ll.w $0, $1", "=r,*^ZC"(ptr elementtype(i32) %1)
+  ret i32 %2
+}
+
+define i32 @ZC_offset_32764(ptr %p) nounwind {
+; LA32-LABEL: ZC_offset_32764:
+; LA32:       # %bb.0:
+; LA32-NEXT:    #APP
+; LA32-NEXT:    ll.w $a0, $a0, 32764
+; LA32-NEXT:    #NO_APP
+; LA32-NEXT:    ret
+;
+; LA64-LABEL: ZC_offset_32764:
+; LA64:       # %bb.0:
+; LA64-NEXT:    #APP
+; LA64-NEXT:    ll.w $a0, $a0, 32764
+; LA64-NEXT:    #NO_APP
+; LA64-NEXT:    ret
+  %1 = getelementptr inbounds i8, ptr %p, i32 32764
+  %2 = call i32 asm "ll.w $0, $1", "=r,*^ZC"(ptr elementtype(i32) %1)
+  ret i32 %2
+}
+
+define i32 @ZC_offset_32767(ptr %p) nounwind {
+; LA32-LABEL: ZC_offset_32767:
+; LA32:       # %bb.0:
+; LA32-NEXT:    lu12i.w $a1, 7
+; LA32-NEXT:    ori $a1, $a1, 4095
+; LA32-NEXT:    add.w $a0, $a0, $a1
+; LA32-NEXT:    #APP
+; LA32-NEXT:    ll.w $a0, $a0, 0
+; LA32-NEXT:    #NO_APP
+; LA32-NEXT:    ret
+;
+; LA64-LABEL: ZC_offset_32767:
+; LA64:       # %bb.0:
+; LA64-NEXT:    lu12i.w $a1, 7
+; LA64-NEXT:    ori $a1, $a1, 4095
+; LA64-NEXT:    add.d $a0, $a0, $a1
+; LA64-NEXT:    #APP
+; LA64-NEXT:    ll.w $a0, $a0, 0
+; LA64-NEXT:    #NO_APP
+; LA64-NEXT:    ret
+  %1 = getelementptr inbounds i8, ptr %p, i32 32767
+  %2 = call i32 asm "ll.w $0, $1", "=r,*^ZC"(ptr elementtype(i32) %1)
+  ret i32 %2
+}

llvm/test/CodeGen/LoongArch/inline-asm-constraint-k.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch64 --verify-machineinstrs < %s | FileCheck %s
+
+define i64 @k_variable_offset(ptr %p, i64 %idx) nounwind {
+; CHECK-LABEL: k_variable_offset:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    ldx.d $a0, $a0, $a1
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    ret
+  %1 = getelementptr inbounds i8, ptr %p, i64 %idx
+  %2 = call i64 asm "ldx.d $0, $1", "=r,*k"(ptr elementtype(i64) %1)
+  ret i64 %2
+}
+
+define i64 @k_constant_offset(ptr %p) nounwind {
+; CHECK-LABEL: k_constant_offset:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    ori $a1, $zero, 5
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    ldx.d $a0, $a0, $a1
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    ret
+  %1 = getelementptr inbounds i8, ptr %p, i64 5
+  %2 = call i64 asm "ldx.d $0, $1", "=r,*k"(ptr elementtype(i64) %1)
+  ret i64 %2
+}

llvm/test/CodeGen/LoongArch/inline-asm-constraint-m.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --verify-machineinstrs < %s | FileCheck %s --check-prefix=LA32
+; RUN: llc --mtriple=loongarch64 --verify-machineinstrs < %s | FileCheck %s --check-prefix=LA64
+
+define i32 @m_offset_neg_2049(ptr %p) nounwind {
+; LA32-LABEL: m_offset_neg_2049:
+; LA32:       # %bb.0:
+; LA32-NEXT:    lu12i.w $a1, -1
+; LA32-NEXT:    ori $a1, $a1, 2047
+; LA32-NEXT:    add.w $a0, $a0, $a1
+; LA32-NEXT:    #APP
+; LA32-NEXT:    ld.w $a0, $a0, 0
+; LA32-NEXT:    #NO_APP
+; LA32-NEXT:    ret
+;
+; LA64-LABEL: m_offset_neg_2049:
+; LA64:       # %bb.0:
+; LA64-NEXT:    lu12i.w $a1, -1
+; LA64-NEXT:    ori $a1, $a1, 2047
+; LA64-NEXT:    add.d $a0, $a0, $a1
+; LA64-NEXT:    #APP
+; LA64-NEXT:    ld.w $a0, $a0, 0
+; LA64-NEXT:    #NO_APP
+; LA64-NEXT:    ret
+  %1 = getelementptr inbounds i8, ptr %p, i32 -2049
+  %2 = call i32 asm "ld.w $0, $1", "=r,*m"(ptr elementtype(i32) %1)
+  ret i32 %2
+}
+
+define i32 @m_offset_neg_2048(ptr %p) nounwind {
+; LA32-LABEL: m_offset_neg_2048:
+; LA32:       # %bb.0:
+; LA32-NEXT:    #APP
+; LA32-NEXT:    ld.w $a0, $a0, -2048
+; LA32-NEXT:    #NO_APP
+; LA32-NEXT:    ret
+;
+; LA64-LABEL: m_offset_neg_2048:
+; LA64:       # %bb.0:
+; LA64-NEXT:    #APP
+; LA64-NEXT:    ld.w $a0, $a0, -2048
+; LA64-NEXT:    #NO_APP
+; LA64-NEXT:    ret
+  %1 = getelementptr inbounds i8, ptr %p, i32 -2048
+  %2 = call i32 asm "ld.w $0, $1", "=r,*m"(ptr elementtype(i32) %1)
+  ret i32 %2
+}
+
+define i32 @m_offset_neg_1(ptr %p) nounwind {
+; LA32-LABEL: m_offset_neg_1:
+; LA32:       # %bb.0:
+; LA32-NEXT:    #APP
+; LA32-NEXT:    ld.w $a0, $a0, -1
+; LA32-NEXT:    #NO_APP
+; LA32-NEXT:    ret
+;
+; LA64-LABEL: m_offset_neg_1:
+; LA64:       # %bb.0:
+; LA64-NEXT:    #APP
+; LA64-NEXT:    ld.w $a0, $a0, -1
+; LA64-NEXT:    #NO_APP
+; LA64-NEXT:    ret
+  %1 = getelementptr inbounds i8, ptr %p, i32 -1
+  %2 = call i32 asm "ld.w $0, $1", "=r,*m"(ptr elementtype(i32) %1)
+  ret i32 %2
+}
+
+define i32 @m_offset_0(ptr %p) nounwind {
+; LA32-LABEL: m_offset_0:
+; LA32:       # %bb.0:
+; LA32-NEXT:    #APP
+; LA32-NEXT:    ld.w $a0, $a0, 0
+; LA32-NEXT:    #NO_APP
+; LA32-NEXT:    ret
+;
+; LA64-LABEL: m_offset_0:
+; LA64:       # %bb.0:
+; LA64-NEXT:    #APP
+; LA64-NEXT:    ld.w $a0, $a0, 0
+; LA64-NEXT:    #NO_APP
+; LA64-NEXT:    ret
+  %1 = call i32 asm "ld.w $0, $1", "=r,*m"(ptr elementtype(i32) %p)
+  ret i32 %1
+}
+
+define i32 @m_offset_1(ptr %p) nounwind {
+; LA32-LABEL: m_offset_1:
+; LA32:       # %bb.0:
+; LA32-NEXT:    #APP
+; LA32-NEXT:    ld.w $a0, $a0, 1
+; LA32-NEXT:    #NO_APP
+; LA32-NEXT:    ret
+;
+; LA64-LABEL: m_offset_1:
+; LA64:       # %bb.0:
+; LA64-NEXT:    #APP
+; LA64-NEXT:    ld.w $a0, $a0, 1
+; LA64-NEXT:    #NO_APP
+; LA64-NEXT:    ret
+  %1 = getelementptr inbounds i8, ptr %p, i32 1
+  %2 = call i32 asm "ld.w $0, $1", "=r,*m"(ptr elementtype(i32) %1)
+  ret i32 %2
+}
+
+define i32 @m_offset_2047(ptr %p) nounwind {
+; LA32-LABEL: m_offset_2047:
+; LA32:       # %bb.0:
+; LA32-NEXT:    #APP
+; LA32-NEXT:    ld.w $a0, $a0, 2047
+; LA32-NEXT:    #NO_APP
+; LA32-NEXT:    ret
+;
+; LA64-LABEL: m_offset_2047:
+; LA64:       # %bb.0:
+; LA64-NEXT:    #APP
+; LA64-NEXT:    ld.w $a0, $a0, 2047
+; LA64-NEXT:    #NO_APP
+; LA64-NEXT:    ret
+  %1 = getelementptr inbounds i8, ptr %p, i32 2047
+  %2 = call i32 asm "ld.w $0, $1", "=r,*m"(ptr elementtype(i32) %1)
+  ret i32 %2
+}
+
+define i32 @m_offset_2048(ptr %p) nounwind {
+; LA32-LABEL: m_offset_2048:
+; LA32:       # %bb.0:
+; LA32-NEXT:    ori $a1, $zero, 2048
+; LA32-NEXT:    add.w $a0, $a0, $a1
+; LA32-NEXT:    #APP
+; LA32-NEXT:    ld.w $a0, $a0, 0
+; LA32-NEXT:    #NO_APP
+; LA32-NEXT:    ret
+;
+; LA64-LABEL: m_offset_2048:
+; LA64:       # %bb.0:
+; LA64-NEXT:    ori $a1, $zero, 2048
+; LA64-NEXT:    add.d $a0, $a0, $a1
+; LA64-NEXT:    #APP
+; LA64-NEXT:    ld.w $a0, $a0, 0
+; LA64-NEXT:    #NO_APP
+; LA64-NEXT:    ret
+  %1 = getelementptr inbounds i8, ptr %p, i32 2048
+  %2 = call i32 asm "ld.w $0, $1", "=r,*m"(ptr elementtype(i32) %1)
+  ret i32 %2
+}