[LLVM][AArch64] Explain that X19 is used as the frame base pointer register

[DavidSpickett]

Summary

Fixes #50098

LLVM uses X19 as the frame base pointer, if it needs to. Meaning you
can get warnings if you clobber that with inline asm.

However, it doesn't explain why. The frame base register is not part
of the ABI so it's pretty confusing why you get that warning out of the blue.

This adds a method to explain a reserved register with X19 as the first one.
The logic is the same as getReservedRegs.

I could have added a return parameter to isASMClobberable and friends
but found that there's a lot of things that call isReservedReg in various
ways.

So while one more method on the pile isn't great design, it is simpler
right now to do it this way and only pay the cost if you are actually using
a reserved register.

[DavidSpickett]

Obviously it would be cool to add the other reserved registers e.g. straight line speculation but let's see if I have the API right first.

If reserved regs were a static map I'd just make it a map of register string pair. However, it can change per function so I decided to go with a separate call you can make if you want/are able to print the reason.

[HsiangKai]

llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp

315

"X16" => "X19"

llvm/test/CodeGen/AArch64/inline-asm-clobber-base-frame-pointer.ll

4

"X16" => "X19"

[tschuett]

llvm/include/llvm/CodeGen/TargetRegisterInfo.h

528

You could use an Optional<std::string> instead. It will be seldom used.

llvm/test/CodeGen/AArch64/inline-asm-clobber-base-frame-pointer.ll

12

line break

[DavidSpickett]

llvm/include/llvm/CodeGen/TargetRegisterInfo.h

528

Well in some sense char* is optional string as long as that "string" is constant, and for this specific case I didn't need to format a string so std::string wasn't needed.

That said, you're right this is seldom used so pointer plus bool isn't a concern space wise. In addition, if I add further explanations they *will* need to format a new string e.g. when you try to clobber an SME tile.

So I will do this thanks for the suggestion.

llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp

315

Doh, yeah I don't know why I keep mistyping it as 16.

[DavidSpickett]

I forgot to post a link to the github issue: https://github.com/llvm/llvm-project/issues/50098

[DavidSpickett]

• Return optional<string>
• Cleanup IR test
• Correct X16 -> X19

[DavidSpickett]

@lenary ping! Any thoughts?

[lenary]

LGTM. This seems the simplest and cleanest way to add this information, and fuller error messages are better!

llvm/include/llvm/CodeGen/TargetRegisterInfo.h

 //==- CodeGen/TargetRegisterInfo.h - Target Register Information -*- C++ -*-==//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
public:
   /// - is not allocatable
   /// - is considered always live
   /// - is ignored by liveness tracking
   /// It is often necessary to reserve the super registers of a reserved
   /// register as well, to avoid them getting allocated indirectly. You may use
   /// markSuperRegs() and checkAllSuperRegsMarked() in this case.
   virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
 
+  /// Returns either nullptr or a non null pointer to a string explaining
+  /// why the given register is reserved for the given machine function.
+  virtual const char *explainReservedReg(const MachineFunction &MF,
+                                         MCRegister PhysReg) const {
+    return nullptr;
+  }
+
   /// Returns false if we can't guarantee that Physreg, specified as an IR asm
   /// clobber constraint, will be preserved across the statement.
   virtual bool isAsmClobberable(const MachineFunction &MF,
                                 MCRegister PhysReg) const {
     return true;
   }
 
   /// Returns true if PhysReg cannot be written to in inline asm statements.

llvm/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp

 //===-- AsmPrinterInlineAsm.cpp - AsmPrinter Inline Asm Handling ----------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
if (!RestrRegs.empty()) {
     const char *Note =
         "Reserved registers on the clobber list may not be "
         "preserved across the asm statement, and clobbering them may "
         "lead to undefined behaviour.";
     MMI->getModule()->getContext().diagnose(DiagnosticInfoInlineAsm(
         LocCookie, Msg, DiagnosticSeverity::DS_Warning));
     MMI->getModule()->getContext().diagnose(
         DiagnosticInfoInlineAsm(LocCookie, Note, DiagnosticSeverity::DS_Note));
+
+    for (const Register RR: RestrRegs) {
+      if (const char* reason = TRI->explainReservedReg(*MF, RR)) {
+        MMI->getModule()->getContext().diagnose(
+            DiagnosticInfoInlineAsm(LocCookie, reason, DiagnosticSeverity::DS_Note));
+      }
+    }
   }
 
   emitInlineAsm(OS.str(), getSubtargetInfo(), TM.Options.MCOptions, LocMD,
                 MI->getInlineAsmDialect());
 
   // Emit the #NOAPP end marker.  This has to happen even if verbose-asm isn't
   // enabled, so we use emitRawComment.
   OutStreamer->emitRawComment(MAI->getInlineAsmEnd());

llvm/lib/Target/AArch64/AArch64RegisterInfo.h

 //==- AArch64RegisterInfo.h - AArch64 Register Information Impl --*- C++ -*-==//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
public:
   /// this property
   const uint32_t *getThisReturnPreservedMask(const MachineFunction &MF,
                                              CallingConv::ID) const;
 
   /// Stack probing calls preserve different CSRs to the normal CC.
   const uint32_t *getWindowsStackProbePreservedMask() const;
 
   BitVector getReservedRegs(const MachineFunction &MF) const override;
+  const char *explainReservedReg(const MachineFunction &MF,
+                                 MCRegister PhysReg) const override;
   bool isAsmClobberable(const MachineFunction &MF,
                        MCRegister PhysReg) const override;
   const TargetRegisterClass *
   getPointerRegClass(const MachineFunction &MF,
                      unsigned Kind = 0) const override;
   const TargetRegisterClass *
   getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
 

llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp

 //===- AArch64RegisterInfo.cpp - AArch64 Register Information -------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
if (MF.getSubtarget<AArch64Subtarget>().isTargetDarwin())
     return CSR_Darwin_AArch64_AAPCS_ThisReturn_RegMask;
   return CSR_AArch64_AAPCS_ThisReturn_RegMask;
 }
 
 const uint32_t *AArch64RegisterInfo::getWindowsStackProbePreservedMask() const {
   return CSR_AArch64_StackProbe_Windows_RegMask;
 }
 
+const char *AArch64RegisterInfo::explainReservedReg(const MachineFunction &MF,
+                                                    MCRegister PhysReg) const {
+  if (hasBasePointer(MF) &&
+      (PhysReg == AArch64::X19 || PhysReg == AArch64::W19))
+    return "X16 is used as the frame base pointer register.";
+
+  return nullptr;
+}
+
 BitVector
 AArch64RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
   const AArch64FrameLowering *TFI = getFrameLowering(MF);
 
   // FIXME: avoid re-calculating this every time.
   BitVector Reserved(getNumRegs());
   markSuperRegs(Reserved, AArch64::WSP);
   markSuperRegs(Reserved, AArch64::WZR);

llvm/test/CodeGen/AArch64/inline-asm-clobber-base-frame-pointer.ll

+; RUN: llc <%s -mtriple=aarch64-none-eabi 2>&1 | FileCheck %s
+
+; CHECK: warning: inline asm clobber list contains reserved registers: X19
+; CHECK: note: X16 is used as the frame base pointer register.
+
+define dso_local void @alloca(i64 %size, i8* %base) {
+entryz:
+  %a = alloca i128, i64 %size, align 64
+  call void asm sideeffect "nop", "~{x19}"()
+  ret void
+}
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