[DAGCombiner] Fold vecreduce_xor/or/and(splat_vector(val)) to constant

[Jimerlife]

Summary

fold vecreduce_or/and(splat_vector(val)) -> constant val
fold vecreduce_xor(splat_vector(val)) -> constant zero

Precommit tests D132207

[dmgreen]

XOR will be 0 or val depending on if there are an even number of vector elements.

Can you add some tests for both cases?

[craig.topper]

Do you have real world examples of C code where this occurs?

Would this be better to do in InstCombine?

Where are the test deltas?

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

23506

What if the element count is odd?

[Jimerlife]

In D132206#3734343, @craig.topper wrote:

Do you have real world examples of C code where this occurs?

Would this be better to do in InstCombine?

Where are the test deltas?

I have no real world examples of C code, just think could fold this. I am not sure if this is better to do in InstCombine. I create precommit tests D132207, but this test does't consider vector element count. Element count should also be consider.

[Jimerlife]

In D132206#3734342, @dmgreen wrote:

XOR will be 0 or val depending on if there are an even number of vector elements.

Can you add some tests for both cases?

You are right, should consider element count. Thank you.

[RKSimon]

This might be more useful if you did it in SelectionDAG::computeKnownBits - then it'd work for any case with common bits in every vector element and you'd get constant folding as well.

[david-arm]

Hi @Jimerlife, I think it's common practice to create a chain of patches in your downstream repo where the code change patch is based off the pre-committed test patch. That way we can observe the change in behaviour as part of this patch without having to wait for a rebase. You can edit the parent revision to add the pre-commit as a parent so the chain is clear in Phabricator.

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

if (N0.getOpcode() == ISD::INSERT_SUBVECTOR &&
     SDValue Subvec = N0.getOperand(1);
     if ((Opcode == ISD::VECREDUCE_OR &&
          (N0.getOperand(0).isUndef() || isNullOrNullSplat(Vec))) ||
         (Opcode == ISD::VECREDUCE_AND &&
          (N0.getOperand(0).isUndef() || isAllOnesOrAllOnesSplat(Vec))))
       return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), Subvec);
   }
 
+  // fold vecreduce_or/and(splat_vector(val)) -> constant val
+  // fold vecreduce_xor(splat_vector(val)) -> constant zero
+  APInt SplatVal;
+  if (ISD::isConstantSplatVector(N0.getNode(), SplatVal)) {
+    if (Opcode == ISD::VECREDUCE_XOR)
+      return DAG.getConstant(0, SDLoc(N), N->getValueType(0));
+    if (Opcode == ISD::VECREDUCE_AND || Opcode == ISD::VECREDUCE_OR)
+      return DAG.getConstant(SplatVal, SDLoc(N), N->getValueType(0));
+  }
+
   return SDValue();
 }
 
 SDValue DAGCombiner::visitVPOp(SDNode *N) {
   // VP operations in which all vector elements are disabled - either by
   // determining that the mask is all false or that the EVL is 0 - can be
   // eliminated.
   bool AreAllEltsDisabled = false;