[PowerPC] Add support for extending and truncating values

[Kai]

Summary

Adds/completes support for G_SEXT, G_ZEXT, and G_TRUNC.
Support for G_SEXT and G_ZEXT was already partly implemented.

[tschuett]

Did I miss the tests for G_ANYEXT and G_TRUNC?
Apparently, the solution are MIR-tests like, e.g.,
https://reviews.llvm.org/D37675

[amyk]

llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp

172

Do we need to check if these are valid registers first before getting the register?

llvm/test/CodeGen/PowerPC/GlobalISel/ppc-isel-constant.ll

1

nit: Might be good to autogenerate these LIT tests with -ppc-asm-full-reg-names.

llvm/test/CodeGen/PowerPC/GlobalISel/ppc-isel-logical.ll

11

nit: Might be good to autogenerate these LIT tests with -ppc-asm-full-reg-names here, as well.

[shchenz]

llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp

107

For imm32, seems the implementation in PPCFastISel::PPCMaterialize32BitInt() looks simpler to me.

int64_t Imm = ConstValue.getZExtValue();
if (isInt<16>(Imm))
{
  // a single LI/LI8 is enough
} else if (Imm & 0xFFFF) {
  // Handle the low and high 16 bit seperatedly
} else {
  // only handle the high 16 as the low 16 bits are all 0
}

And for the 64 bit integers, maybe we can also refer to PPCFastISel::PPCMaterialize64BitInt() if we want to have a implementation for them

213

Seems the logic in selectSExt is not what G_SEXT_INREG represents. Can we set action for G_SEXT_INREG as lower and use target independent handling for G_SEXT_INREG like other targets does?

Not sure which test case triggers this generic opcode?

214

G_SEXT seems can be selected automatically in the td files but G_ZEXT can not. So I suppose there should be some codes to select G_ZEXT too? I made a implementation in https://reviews.llvm.org/D135535

llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp

38

This is for i128? Seems no related handling for i128 in this patch?

llvm/test/CodeGen/PowerPC/GlobalISel/ppc-isel-constant.ll

1

And seems the cases are all testing zero/sign extension from i32 -> i64. Should we test other code path as well, like i8/i16 -> i64? And for trunc operation too?

llvm/test/CodeGen/PowerPC/GlobalISel/ppc-isel-logical.ll

2

This test file seems not belong to this patch?

[Kai]

Completely reworked the change.

• Rebased on latest main which has partial implementation of G_ZEXT (Currently, G_ZEXT and G_SEXT are only implemented for extending 32 -> 64 bit.)
• Removed support for G_CONSTANT. I will have a more complete solution ready in a follow up change.
• Added a mir test case to check the generated code

[shchenz]

llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp

109

nit: sounds like here should be dest operand?

112

What will happen if we don't constrain the middle result, like ImpDefReg and result of INSERT_SUBREG? I assume the register class setting in the source code here should match what IMPLICIT_DEF INSERT_SUBREG and the final RLDICL requires?

117

We may need to change the tb for the 8 and 16 bits in another patch. For example add patterns for EXTSB8_32_64 and EXTSH8_32_64?

119

Do we need to handle any arbitrary bit here, like i7/i9? I assume the illegal types should be already handled in legalizer pass?

123

hmm, what if the register class of SrcReg is not g8rc? Directly putting it as operand of PPC::RLDICL seems not right to me. For example if the input is gprc, constraining may change it to g8rc by adding a COPY? but that COPY will not tell how to handle the high 32 bit?

129

Weird that trunc i64 to i32 can not be handled in table gen?
There is pattern:

def : Pat<(i32 (trunc i64:$in)),
          (EXTRACT_SUBREG $in, sub_32)>;

Seems the patterns in the match table are all about trunc from i64/i32 -> i1. Maybe a closely look is needed to understand why for later improvement.

135

Same as sext, directly putting SrcReg as operand of PPC::RLDICL will cause copy like %1:gprc = COPY %3:g8rc and this COPY can not be expanded in later pseudo expansion.

llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp

public:
   bool select(MachineInstr &I) override;
   static const char *getName() { return DEBUG_TYPE; }
 
 private:
   /// tblgen generated 'select' implementation that is used as the initial
   /// selector for the patterns that do not require complex C++.
   bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
 
+  bool selectConst(MachineInstr &I, MachineBasicBlock &MBB,
+                   MachineRegisterInfo &MRI) const;
+  bool selectSExt(MachineInstr &I, MachineBasicBlock &MBB,
+                  MachineRegisterInfo &MRI) const;
+
   const PPCInstrInfo &TII;
   const PPCRegisterInfo &TRI;
   const PPCRegisterBankInfo &RBI;
 
 #define GET_GLOBALISEL_PREDICATES_DECL
 #include "PPCGenGlobalISel.inc"
 #undef GET_GLOBALISEL_PREDICATES_DECL
 
if (!RBI.constrainGenericRegister(DstReg, PPC::G8RCRegClass, MRI))
       return false;
   if (!Register::isPhysicalRegister(SrcReg))
     if (!RBI.constrainGenericRegister(SrcReg, PPC::G8RCRegClass, MRI))
       return false;
 
   return true;
 }
 
+bool PPCInstructionSelector::selectConst(MachineInstr &I,
+                                         MachineBasicBlock &MBB,
+                                         MachineRegisterInfo &MRI) const {
+  assert(I.getOpcode() == TargetOpcode::G_CONSTANT && "Unexpected G code");
+
+  MachineInstr *MI = nullptr;
+  Register DstReg = I.getOperand(0).getReg();
+  APInt ConstValue = I.getOperand(1).getCImm()->getValue();
+  if (ConstValue.isIntN(16)) {
+    bool NeedMask = !ConstValue.isIntN(15);
+    uint64_t Cst = ConstValue.getZExtValue();
+    Register TmpReg =
+        NeedMask ? MRI.createVirtualRegister(&PPC::G8RCRegClass) : DstReg;
+    MI =
+        BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::LI8), TmpReg).addImm(Cst);
+    if (NeedMask) {
+      constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
+      MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::RLDIC), DstReg)
+               .addReg(TmpReg, RegState::Kill)
+               .addImm(0)
+               .addImm(16);
+    }
+  } else if (ConstValue.isSignedIntN(16)) {
+    int64_t Cst = ConstValue.getSExtValue();
+    MI =
+        BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::LI8), DstReg).addImm(Cst);
+  } else if (ConstValue.isSignedIntN(32)) {
+    int64_t Cst = ConstValue.getSExtValue();
+    int64_t UpperCst = Cst >> 16;
+    int64_t LowerCst = Cst & 0xffff;
+    Register TmpReg = MRI.createVirtualRegister(&PPC::G8RCRegClass);
+    MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::LIS8), TmpReg)
+             .addImm(UpperCst);
+    constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
+    MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::ORI8), DstReg)
+             .addReg(TmpReg, RegState::Kill)
+             .addImm(LowerCst);
+  } else if (ConstValue.isIntN(32)) {
+    bool NeedMask = !ConstValue.isIntN(31);
+    uint64_t Cst = ConstValue.getZExtValue();
+    uint64_t UpperCst = Cst >> 16;
+    uint64_t LowerCst = Cst & 0xffff;
+    Register TmpReg =
+        NeedMask ? MRI.createVirtualRegister(&PPC::G8RCRegClass) : DstReg;
+    if (UpperCst == 0xffff && (LowerCst & 0x8000) == 0x8000) {
+      MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::LI8), TmpReg)
+               .addImm(LowerCst);
+    } else {
+      Register Tmp2Reg = MRI.createVirtualRegister(&PPC::G8RCRegClass);
+      MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::LIS8), Tmp2Reg)
+               .addImm(UpperCst);
+      constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
+      MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::ORI8), TmpReg)
+               .addReg(Tmp2Reg, RegState::Kill)
+               .addImm(LowerCst);
+    }
+    if (NeedMask) {
+      constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
+      MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::RLDIC), DstReg)
+               .addReg(TmpReg, RegState::Kill)
+               .addImm(0)
+               .addImm(32);
+    }
+  } else
+    return false;
+  I.eraseFromParent();
+  return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
+}
+
+bool PPCInstructionSelector::selectSExt(MachineInstr &I, MachineBasicBlock &MBB,
+                                        MachineRegisterInfo &MRI) const {
+  assert(I.getOpcode() == TargetOpcode::G_SEXT_INREG && "Unexpected G code");
+
+  Register DstReg = I.getOperand(0).getReg();
+  Register SrcReg = I.getOperand(1).getReg();
+
+  unsigned Opc;
+  switch (I.getOperand(2).getImm()) {
+  case 8:
+    Opc = PPC::EXTSB8;
+    break;
+  case 16:
+    Opc = PPC::EXTSH8;
+    break;
+  case 32:
+    Opc = PPC::EXTSW;
+    break;
+  default:
+    return false;
+  }
+  MachineInstr *MI =
+      BuildMI(MBB, I, I.getDebugLoc(), TII.get(Opc), DstReg).addReg(SrcReg);
+  I.eraseFromParent();
+  return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
+}
+
 bool PPCInstructionSelector::select(MachineInstr &I) {
   auto &MBB = *I.getParent();
   auto &MF = *MBB.getParent();
   auto &MRI = MF.getRegInfo();
 
   if (!isPreISelGenericOpcode(I.getOpcode())) {
     if (I.isCopy())
       return selectCopy(I, TII, MRI, TRI, RBI);
 
     return true;
   }
 
   if (selectImpl(I, *CoverageInfo))
     return true;
+
+  switch (I.getOpcode()) {
+  case TargetOpcode::G_CONSTANT:
+    return selectConst(I, MBB, MRI);
+  case TargetOpcode::G_SEXT_INREG:
+    return selectSExt(I, MBB, MRI);
+  default:
     return false;
   }
+}
 
 namespace llvm {
 InstructionSelector *
 createPPCInstructionSelector(const PPCTargetMachine &TM,
                              const PPCSubtarget &Subtarget,
                              const PPCRegisterBankInfo &RBI) {
   return new PPCInstructionSelector(TM, Subtarget, RBI);
 }
 } // end namespace llvm

llvm/lib/Target/PowerPC/GISel/PPCLegalizerInfo.cpp

 
 #define DEBUG_TYPE "ppc-legalinfo"
 
 using namespace llvm;
 using namespace LegalizeActions;
 
 PPCLegalizerInfo::PPCLegalizerInfo(const PPCSubtarget &ST) {
   using namespace TargetOpcode;
+  const LLT S8 = LLT::scalar(8);
+  const LLT S16 = LLT::scalar(16);
+  const LLT S32 = LLT::scalar(32);
   const LLT S64 = LLT::scalar(64);
   getActionDefinitionsBuilder(G_IMPLICIT_DEF).legalFor({S64});
   getActionDefinitionsBuilder(G_CONSTANT)
       .legalFor({S64})
       .clampScalar(0, S64, S64);
+  getActionDefinitionsBuilder(G_TRUNC)
+      .legalForCartesianProduct({S8, S16, S32}, {S64});
+  getActionDefinitionsBuilder({G_ZEXT, G_SEXT, G_ANYEXT})
+      .legalForCartesianProduct({S64}, {S8, S16, S32})
+      .clampScalar(0, S64, S64);
+  getActionDefinitionsBuilder(G_SEXT_INREG)
+       .legalForTypeWithAnyImm({S64});
   getActionDefinitionsBuilder({G_AND, G_OR, G_XOR})
       .legalFor({S64})
       .clampScalar(0, S64, S64);
   getLegacyLegalizerInfo().computeTables();
 }

llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp

 
 const RegisterBank &
 PPCRegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC,
                                             LLT Ty) const {
   switch (RC.getID()) {
   case PPC::G8RCRegClassID:
   case PPC::G8RC_NOX0RegClassID:
   case PPC::G8RC_and_G8RC_NOX0RegClassID:
+  case PPC::G8pRCRegClassID:
+  case PPC::G8pRC_with_sub_32_in_GPRC_NOR0RegClassID:
     return getRegBank(PPC::GPRRegBankID);
   default:
     llvm_unreachable("Unexpected register class");
   }
 }
 
 const RegisterBankInfo::InstructionMapping &
 PPCRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
PPCRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
   unsigned Cost = 1;
   unsigned MappingID = DefaultMappingID;
 
   switch (Opc) {
     // Bitwise ops.
   case TargetOpcode::G_AND:
   case TargetOpcode::G_OR:
   case TargetOpcode::G_XOR:
+  // Truncation & extension ops.
+  case TargetOpcode::G_SEXT:
+  case TargetOpcode::G_ZEXT:
+  case TargetOpcode::G_ANYEXT:
+  case TargetOpcode::G_TRUNC:
     assert(NumOperands <= 3 &&
            "This code is for instructions with 3 or less operands");
     OperandsMapping = getValueMapping(PMI_GPR64);
     break;
+  case TargetOpcode::G_SEXT_INREG:
+    OperandsMapping = getOperandsMapping(
+        {getValueMapping(PMI_GPR64), getValueMapping(PMI_GPR64), nullptr});
+    break;
   case TargetOpcode::G_CONSTANT:
     OperandsMapping = getOperandsMapping({getValueMapping(PMI_GPR64), nullptr});
     break;
   case TargetOpcode::COPY: {
     Register DstReg = MI.getOperand(0).getReg();
     Register SrcReg = MI.getOperand(1).getReg();
     const RegisterBank *DstRB = getRegBank(DstReg, MRI, TRI);
     const RegisterBank *SrcRB = getRegBank(SrcReg, MRI, TRI);

llvm/test/CodeGen/PowerPC/GlobalISel/ppc-isel-constant.ll

+; RUN: llc -mtriple ppc64le-linux -global-isel -o - < %s | FileCheck %s -check-prefixes=CHECK,LINUX
+
+; CHECK-LABEL: f1:
+; LINUX: li 3, 1
+; LINUX: blr
+define zeroext i32 @f1() {
+  ret i32 1
+}
+
+; CHECK-LABEL: f2:
+; LINUX: li 3, -1
+; LINUX: rldic 3, 3, 0, 32
+; LINUX: blr
+define zeroext i32 @f2() {
+  ret i32 -1
+}
+
+; CHECK-LABEL: f3:
+; LINUX: li 3, 1
+; LINUX: blr
+define signext i32 @f3() {
+  ret i32 1
+}
+
+; CHECK-LABEL: f4:
+; LINUX: li 3, -1
+; LINUX: blr
+define signext i32 @f4() {
+  ret i32 -1
+}
+
+; CHECK-LABEL: f5:
+; LINUX: li 3, -52
+; LINUX: blr
+define signext i32 @f5() {
+  ret i32 -52
+}
+
+; CHECK-LABEL: f6:
+; LINUX: li 3, -13142
+; LINUX: rldic 3, 3, 0, 16
+; LINUX: blr
+define zeroext i32 @f6() {
+  ret i32 52394
+}
+
+; CHECK-LABEL: f7:
+; LINUX: lis 3, -18
+; LINUX: ori 3, 3, 56780
+; LINUX: rldic 3, 3, 0, 32
+; LINUX: blr
+define zeroext i32 @f7() {
+  ret i32 4293844428
+}

llvm/test/CodeGen/PowerPC/GlobalISel/ppc-isel-logical.ll

 ; RUN: llc -mtriple ppc64le-linux -global-isel -o - < %s | FileCheck %s -check-prefixes=CHECK,LINUX
 
 ; CHECK-LABEL: test_andi64:
 ; LINUX: and 3, 3, 4
 ; LINUX: blr
 define i64 @test_andi64(i64 %a, i64 %b) {
   %res = and i64 %a, %b
   ret i64 %res
 }
 
+; CHECK-LABEL: test_andui32:
+; LINUX: li 5, -1
+; LINUX: and 3, 3, 4
+; LINUX: rldic 4, 5, 0, 32
+; LINUX: and 3, 3, 4
+; LINUX: blr
+define zeroext i32 @test_andui32(i32 zeroext %a, i32 zeroext %b) {
+  %res = and i32 %a, %b
+  ret i32 %res
+}
+
+; CHECK-LABEL: test_andsi32:
+; LINUX: and 3, 3, 4
+; LINUX: extsw 3, 3
+; LINUX: blr
+define signext i32 @test_andsi32(i32 signext %a, i32 signext %b) {
+  %res = and i32 %a, %b
+  ret i32 %res
+}
+
+; CHECK-LABEL: test_andui16:
+; LINUX: li 5, -1
+; LINUX: and 3, 3, 4
+; LINUX: rldic 4, 5, 0, 16
+; LINUX: and 3, 3, 4
+; LINUX: blr
+define zeroext i16 @test_andui16(i16 zeroext %a, i16 zeroext %b) {
+  %res = and i16 %a, %b
+  ret i16 %res
+}
+
+; CHECK-LABEL: test_andsi16:
+; LINUX: and 3, 3, 4
+; LINUX: extsh 3, 3
+; LINUX: blr
+define signext i16 @test_andsi16(i16 signext %a, i16 signext %b) {
+  %res = and i16 %a, %b
+  ret i16 %res
+}
+
+; CHECK-LABEL: test_andui8:
+; LINUX: li 5, 255
+; LINUX: and 3, 3, 4
+; LINUX: and 3, 3, 5
+; LINUX: blr
+define zeroext i8 @test_andui8(i8 zeroext %a, i8 zeroext %b) {
+  %res = and i8 %a, %b
+  ret i8 %res
+}
+
+; CHECK-LABEL: test_andsi8:
+; LINUX: and 3, 3, 4
+; LINUX: extsb 3, 3
+; LINUX: blr
+define signext i8 @test_andsi8(i8 signext %a, i8 signext %b) {
+  %res = and i8 %a, %b
+  ret i8 %res
+}
+
 ; CHECK-LABEL: test_nandi64:
 ; LINUX: nand 3, 3, 4
 ; LINUX: blr
 define i64 @test_nandi64(i64 %a, i64 %b) {
   %and = and i64 %a, %b
   %neg = xor i64 %and, -1
   ret i64 %neg
 }