[PowerPC] Extend GlobalISel implementation to emit and/or/xor.

[Kai]

Summary

Adds some more code to GlobalISel to enable instruction selection for and/or/xor.

• Makes G_IMPLICIT_DEF, G_CONSTANT, G_AND, G_OR, G_XOR legal for 64bit register size.
• Implement lowerReturn in CallLowering
• Provides mapping of the operands to register banks.
• Adds register info to G_COPY operands.

The utility functions are all only implemented so far to support this use case.
Especially the functions in PPCGenRegisterBankInfo.def are too simple for
general use.

[tschuett]

Nice! My only comment is that my need some more space in PPCLegalizerInfo. You will have to add a lot more code, see e.g. AARCH64:
https://github.com/llvm/llvm-project/blob/275b2e5243639268033d6f0183b9b3b1a30574be/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp#L41

[Kai]

In D127530#3574466, @tschuett wrote:

Nice! My only comment is that my need some more space in PPCLegalizerInfo. You will have to add a lot more code, see e.g. AARCH64:
https://github.com/llvm/llvm-project/blob/275b2e5243639268033d6f0183b9b3b1a30574be/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp#L41

Sure! This is only meant as a first improvement to the existing infrastructure, to see some real instructions generated. E.g. the register bank info is also very "thin" and needs much more work.

[Kai]

• Fixed a wrong comment
• Legalize G_CONSTANT
• Finish test case for nand

[tschuett]

@arsenm @aemerson

[Kai]

• clamp scalars
• more tests

[Kai]

• Add G8RC_NOX0 to register bank
• Add new test to check lowering to GMIR

[arsenm]

llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp

78–88

I don't see the point of this function. There's no guessing involved and you're returning a static result anyway

94

You still need to at least constrain the source register if it's virtual. You probably should have some MIR tests for every permutation of physical / virtual register copies

llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp

84–87

You shouldn't need to guard these. getRegBank should do the right thing

[Kai]

• Removed function guessRegClass()
• selectCopy() now constraints both src and dst
• Simplified case COPY: in RegisterBankInfo

[Kai]

Thanks for the comments!

Considering your comments on D128106 I guess it makes also sense to remove the ppc-irtranslator test and extend the ppc-isel-logical.ll test with the various non-legal types.

llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp

94

Is this actually needed? I added the code but I see no change.
If I compare this with mipsel-linux:

Before instruction-selection:

  %2:gprb(s32) = COPY $a0
...
  $v0 = COPY %13(s32)

and after instruction-selection:

  %2:gpr32 = COPY $a0
...
  $v0 = COPY %13

So during instruction selection, for the destination virtual register, the register bank is replaced with the actual register class. But in the other case, the virtual source register has no constraint after the instruction-select.
I get similar output when also constraining the source virtual register.

[nemanjai]

llvm/lib/Target/PowerPC/GISel/PPCCallLowering.cpp

41

Is it not possible to add tests at this time that actually extend the return value from i32 (for both sixgnext, zeroext)?

100–105

I understand that you implemented this by looking at other targets that already have this implemented. However, I think it would help other PPC developers (as well as anyone implementing this for a future target) if we add a short comment before each statement here describing what the function call does or what the purpose of the object is.

llvm/lib/Target/PowerPC/GISel/PPCGenRegisterBankInfo.def

11

Can you please add a comment as to why it is not yet auto generated?

27–29

Why are there 3 entries here? Thorough documentation at this stage will make it significantly easier when the time comes to refactor the implementation and add automatic generation, etc.

[Kai]

• Add comments
• Remove test ppc-irtranslator.ll

[Kai]

llvm/lib/Target/PowerPC/GISel/PPCCallLowering.cpp

41

It's not yet possible. signext requires a legal G_SEXT instruction.
zeroext either requires handling G_CONSTANT (to clear the upper bits), or a combiner (redundant_and) to remove the and instruction used to clear the bits.

[shchenz]

llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp

80

Maybe we could move this to target independent handling at line 50? getInstrMappingImpl should able to handle case where register bank of one operand of the copy instruction is known.

[arsenm]

llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp

94

Most of the time it works, since the use constrain also happens to work for the dest instruction. However there are some cases where this doesn't happen, leaving an unconstrained register. You'll need to have different kinds of uses and defs. I can't think of a nice example at the moment

[amyk]

llvm/test/CodeGen/PowerPC/GlobalISel/ppc-isel-logical.ll

2

Maybe we can autogenerate the checks? And perhaps add the -ppc-asm-full-reg-names option (since most of our other test cases also include this)?

[Kai]

• update selectCopy() to constraint all registers
• regenerate test using -ppc-asm-full-reg-names option

[Kai]

llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp

94

Thanks, I see. Changed the code to constrain all registers.

[tschuett]

llvm/lib/Target/PowerPC/GISel/PPCCallLowering.cpp

45

Could you move the implementations out of the anonymous namespace?
https://llvm.org/docs/CodingStandards.html#anonymous-namespaces

[Kai]

Let the generic code handle TargetOpcode::COPY.

llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp

80

Good point, I changed the code.

[Kai]

Moved implementation out of anonymous name space in PPCCallLowering.cpp.

[shchenz]

llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp

86

There is an approved version of selectCopy() in D132942. We may only need to constrain dest virtual register in the COPY instruction and for the source registers, we can defer them to other uses or defs?

[shchenz]

reverse ping, can we move forward for this patch? Thanks. @Kai

[Kai]

Added selectCopy() implementation from D132942

[Kai]

@shchenz Sorry for the delay.
I copied the selectCopy() function from your change. I also added a simplified version of getRegClass(). That is hopefully good enough.

[shchenz]

LGTM. Thanks.

llvm/lib/Target/PowerPC/GISel/PPCCallLowering.cpp

 //===-- PPCCallLowering.h - Call lowering for GlobalISel -------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
 /// This file implements the lowering of LLVM calls to machine code calls for
 /// GlobalISel.
 ///
 //===----------------------------------------------------------------------===//
 
 #include "PPCCallLowering.h"
+#include "PPCCallingConv.h"
 #include "PPCISelLowering.h"
 #include "PPCSubtarget.h"
 #include "PPCTargetMachine.h"
 #include "llvm/CodeGen/CallingConvLower.h"
 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/TargetCallingConv.h"
 #include "llvm/Support/Debug.h"
 
 #define DEBUG_TYPE "ppc-call-lowering"
 
 using namespace llvm;
 
+namespace {
+
+struct OutgoingArgHandler : public CallLowering::OutgoingValueHandler {
+  OutgoingArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
+                     MachineInstrBuilder MIB)
+      : OutgoingValueHandler(MIRBuilder, MRI), MIB(MIB) {}
+
+  void assignValueToReg(Register ValVReg, Register PhysReg,
+                        CCValAssign VA) override;
+  void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
+                            MachinePointerInfo &MPO, CCValAssign &VA) override;
+  Register getStackAddress(uint64_t Size, int64_t Offset,
+                           MachinePointerInfo &MPO,
+                           ISD::ArgFlagsTy Flags) override;
+
+  MachineInstrBuilder MIB;
+};
+} // namespace
+
+void OutgoingArgHandler::assignValueToReg(Register ValVReg, Register PhysReg,
+                                          CCValAssign VA) {
+  MIB.addUse(PhysReg, RegState::Implicit);
+  Register ExtReg = extendRegister(ValVReg, VA);
+  MIRBuilder.buildCopy(PhysReg, ExtReg);
+}
+
+void OutgoingArgHandler::assignValueToAddress(Register ValVReg, Register Addr,
+                                              LLT MemTy,
+                                              MachinePointerInfo &MPO,
+                                              CCValAssign &VA) {
+  llvm_unreachable("unimplemented");
+}
+
+Register OutgoingArgHandler::getStackAddress(uint64_t Size, int64_t Offset,
+                                             MachinePointerInfo &MPO,
+                                             ISD::ArgFlagsTy Flags) {
+  llvm_unreachable("unimplemented");
+}
+
 PPCCallLowering::PPCCallLowering(const PPCTargetLowering &TLI)
     : CallLowering(&TLI) {}
 
 bool PPCCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
                                   const Value *Val, ArrayRef<Register> VRegs,
                                   FunctionLoweringInfo &FLI,
                                   Register SwiftErrorVReg) const {
-  assert(((Val && !VRegs.empty()) || (!Val && VRegs.empty())) &&
-         "Return value without a vreg");
-  if (VRegs.size() > 0)
-    return false;
+  auto MIB = MIRBuilder.buildInstrNoInsert(PPC::BLR8);
+  bool Success = true;
+  MachineFunction &MF = MIRBuilder.getMF();
+  const Function &F = MF.getFunction();
+  MachineRegisterInfo &MRI = MF.getRegInfo();
+  auto &DL = F.getParent()->getDataLayout();
+  if (!VRegs.empty()) {
+    // Setup the information about the return value.
+    ArgInfo OrigArg{VRegs, Val->getType(), 0};
+    setArgFlags(OrigArg, AttributeList::ReturnIndex, DL, F);
 
-  MIRBuilder.buildInstr(PPC::BLR8);
-  return true;
+    // Split the return value into consecutive registers if needed.
+    SmallVector<ArgInfo, 8> SplitArgs;
+    splitToValueTypes(OrigArg, SplitArgs, DL, F.getCallingConv());
+
+    // Use the calling convention callback to determine type and location of
+    // return value.
+    OutgoingValueAssigner ArgAssigner(RetCC_PPC);
+
+    // Handler to move the return value into the correct location.
+    OutgoingArgHandler ArgHandler(MIRBuilder, MRI, MIB);
+
+    // Iterate over all return values, and move them to the assigned location.
+    Success = determineAndHandleAssignments(ArgHandler, ArgAssigner, SplitArgs,
+                                            MIRBuilder, F.getCallingConv(),
+                                            F.isVarArg());
+  }
+  MIRBuilder.insertInstr(MIB);
+  return Success;
 }
 
 bool PPCCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
                                 CallLoweringInfo &Info) const {
   return false;
 }
 
 bool PPCCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,

llvm/lib/Target/PowerPC/GISel/PPCGenRegisterBankInfo.def

+//===- PPCGenRegisterBankInfo.def -------------------------------*- C++ -*-==//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+/// \file
+/// This file defines all the static objects used by PPCRegisterBankInfo.
+/// \todo This should be generated by TableGen, because the logic here can be
+///  derived from register bank definition. Not yet implemented.
+//===----------------------------------------------------------------------===//
+
+namespace llvm {
+RegisterBankInfo::PartialMapping PPCGenRegisterBankInfo::PartMappings[]{
+    /* StartIdx, Length, RegBank */
+    // 0: GPR 64-bit value.
+    {0, 64, PPC::GPRRegBank},
+};
+
+// ValueMappings.
+// Pointers to the entries in this array are returned by getValueMapping() and
+// getCopyMapping().
+//
+// The array has the following structure:
+// - At index 0 is the invalid entry.
+// - After that, the mappings for the register types from PartialMappingIdx
+//   follow. Each mapping consists of 3 entries, which is needed to cover
+//   3-operands instructions.
+// - Last, mappings for cross-register bank moves follow. Since COPY has only
+//   2 operands, a mapping consists of 2 entries.
+RegisterBankInfo::ValueMapping PPCGenRegisterBankInfo::ValMappings[]{
+    /* BreakDown, NumBreakDowns */
+    // 0: invalid
+    {nullptr, 0},
+    // 1: GPR 64-bit value.
+    {&PPCGenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
+    {&PPCGenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
+    {&PPCGenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
+};
+
+// TODO Too simple!
+const RegisterBankInfo::ValueMapping *
+PPCGenRegisterBankInfo::getValueMapping(PartialMappingIdx RBIdx) {
+  assert(RBIdx != PartialMappingIdx::PMI_None && "No mapping needed for that");
+
+  unsigned ValMappingIdx = RBIdx - PMI_Min;
+
+  return &ValMappings[1 + 3 * ValMappingIdx];
+}
+
+// TODO Too simple!
+const RegisterBankInfo::ValueMapping *
+PPCGenRegisterBankInfo::getCopyMapping(unsigned DstBankID, unsigned SrcBankID,
+                                       unsigned Size) {
+  assert(DstBankID < PPC::NumRegisterBanks && "Invalid bank ID");
+  assert(SrcBankID < PPC::NumRegisterBanks && "Invalid bank ID");
+
+  return &ValMappings[1];
+}
+
+} // namespace llvm

llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp

 #include "PPCGenGlobalISel.inc"
 #undef GET_GLOBALISEL_PREDICATES_INIT
 #define GET_GLOBALISEL_TEMPORARIES_INIT
 #include "PPCGenGlobalISel.inc"
 #undef GET_GLOBALISEL_TEMPORARIES_INIT
 {
 }
 
+static const TargetRegisterClass *getRegClass(LLT Ty, const RegisterBank *RB) {
+  if (RB->getID() == PPC::GPRRegBankID) {
+    if (Ty.getSizeInBits() == 64)
+      return &PPC::G8RCRegClass;
+  }
+
+  llvm_unreachable("Unknown RegBank!");
+}
+
+static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII,
+                       MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI,
+                       const RegisterBankInfo &RBI) {
+  Register DstReg = I.getOperand(0).getReg();
+
+  if (DstReg.isPhysical())
+    return true;
+
+  const RegisterBank *DstRegBank = RBI.getRegBank(DstReg, MRI, TRI);
+  const TargetRegisterClass *DstRC =
+      getRegClass(MRI.getType(DstReg), DstRegBank);
+
+  // No need to constrain SrcReg. It will get constrained when we hit another of
+  // its use or its defs.
+  // Copies do not have constraints.
+  if (!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
+    LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode())
+                      << " operand\n");
+    return false;
+  }
+
+  return true;
+}
+
 bool PPCInstructionSelector::select(MachineInstr &I) {
+  auto &MBB = *I.getParent();
+  auto &MF = *MBB.getParent();
+  auto &MRI = MF.getRegInfo();
+
+  if (!isPreISelGenericOpcode(I.getOpcode())) {
+    if (I.isCopy())
+      return selectCopy(I, TII, MRI, TRI, RBI);
+
+    return true;
+  }
+
   if (selectImpl(I, *CoverageInfo))
     return true;
   return false;
 }
 
 namespace llvm {
 InstructionSelector *
 createPPCInstructionSelector(const PPCTargetMachine &TM,
                              const PPCSubtarget &Subtarget,
                              const PPCRegisterBankInfo &RBI) {
   return new PPCInstructionSelector(TM, Subtarget, RBI);
 }
 } // end namespace llvm

llvm/lib/Target/PowerPC/GISel/PPCLegalizerInfo.cpp

 #include "llvm/Support/Debug.h"
 
 #define DEBUG_TYPE "ppc-legalinfo"
 
 using namespace llvm;
 using namespace LegalizeActions;
 
 PPCLegalizerInfo::PPCLegalizerInfo(const PPCSubtarget &ST) {
+  using namespace TargetOpcode;
+  const LLT S64 = LLT::scalar(64);
+  getActionDefinitionsBuilder(G_IMPLICIT_DEF).legalFor({S64});
+  getActionDefinitionsBuilder(G_CONSTANT)
+      .legalFor({S64})
+      .clampScalar(0, S64, S64);
+  getActionDefinitionsBuilder({G_AND, G_OR, G_XOR})
+      .legalFor({S64})
+      .clampScalar(0, S64, S64);
   getLegacyLegalizerInfo().computeTables();
 }

llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.h

 #define GET_REGBANK_DECLARATIONS
 #include "PPCGenRegisterBank.inc"
 
 namespace llvm {
 class TargetRegisterInfo;
 
 class PPCGenRegisterBankInfo : public RegisterBankInfo {
 protected:
+  enum PartialMappingIdx {
+    PMI_None = -1,
+    PMI_GPR64 = 1,
+    PMI_Min = PMI_GPR64,
+  };
+
+  static RegisterBankInfo::PartialMapping PartMappings[];
+  static RegisterBankInfo::ValueMapping ValMappings[];
+  static PartialMappingIdx BankIDToCopyMapIdx[];
+
+  /// Get the pointer to the ValueMapping representing the RegisterBank
+  /// at \p RBIdx.
+  ///
+  /// The returned mapping works for instructions with the same kind of
+  /// operands for up to 3 operands.
+  ///
+  /// \pre \p RBIdx != PartialMappingIdx::None
+  static const RegisterBankInfo::ValueMapping *
+  getValueMapping(PartialMappingIdx RBIdx);
+
+  /// Get the pointer to the ValueMapping of the operands of a copy
+  /// instruction from the \p SrcBankID register bank to the \p DstBankID
+  /// register bank with a size of \p Size.
+  static const RegisterBankInfo::ValueMapping *
+  getCopyMapping(unsigned DstBankID, unsigned SrcBankID, unsigned Size);
+
 #define GET_TARGET_REGBANK_CLASS
 #include "PPCGenRegisterBank.inc"
 };
 
 class PPCRegisterBankInfo final : public PPCGenRegisterBankInfo {
 public:
   PPCRegisterBankInfo(const TargetRegisterInfo &TRI);
+
+  const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC,
+                                             LLT Ty) const override;
+  const InstructionMapping &
+  getInstrMapping(const MachineInstr &MI) const override;
+
+  InstructionMappings
+  getInstrAlternativeMappings(const MachineInstr &MI) const override;
 };
 } // namespace llvm
 
 #endif

llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp

 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/Support/Debug.h"
 
 #define DEBUG_TYPE "ppc-reg-bank-info"
 
 #define GET_TARGET_REGBANK_IMPL
 #include "PPCGenRegisterBank.inc"
 
+// This file will be TableGen'ed at some point.
+#include "PPCGenRegisterBankInfo.def"
+
 using namespace llvm;
 
 PPCRegisterBankInfo::PPCRegisterBankInfo(const TargetRegisterInfo &TRI) {}
+
+const RegisterBank &
+PPCRegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC,
+                                            LLT Ty) const {
+  switch (RC.getID()) {
+  case PPC::G8RCRegClassID:
+  case PPC::G8RC_NOX0RegClassID:
+  case PPC::G8RC_and_G8RC_NOX0RegClassID:
+    return getRegBank(PPC::GPRRegBankID);
+  default:
+    llvm_unreachable("Unexpected register class");
+  }
+}
+
+const RegisterBankInfo::InstructionMapping &
+PPCRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
+  const unsigned Opc = MI.getOpcode();
+
+  // Try the default logic for non-generic instructions that are either copies
+  // or already have some operands assigned to banks.
+  if (!isPreISelGenericOpcode(Opc) || Opc == TargetOpcode::G_PHI) {
+    const RegisterBankInfo::InstructionMapping &Mapping =
+        getInstrMappingImpl(MI);
+    if (Mapping.isValid())
+      return Mapping;
+  }
+
+  unsigned NumOperands = MI.getNumOperands();
+  const ValueMapping *OperandsMapping = nullptr;
+  unsigned Cost = 1;
+  unsigned MappingID = DefaultMappingID;
+
+  switch (Opc) {
+    // Bitwise ops.
+  case TargetOpcode::G_AND:
+  case TargetOpcode::G_OR:
+  case TargetOpcode::G_XOR:
+    assert(NumOperands <= 3 &&
+           "This code is for instructions with 3 or less operands");
+    OperandsMapping = getValueMapping(PMI_GPR64);
+    break;
+  case TargetOpcode::G_CONSTANT:
+    OperandsMapping = getOperandsMapping({getValueMapping(PMI_GPR64), nullptr});
+    break;
+  default:
+    return getInvalidInstructionMapping();
+  }
+
+  return getInstructionMapping(MappingID, Cost, OperandsMapping, NumOperands);
+}
+
+RegisterBankInfo::InstructionMappings
+PPCRegisterBankInfo::getInstrAlternativeMappings(const MachineInstr &MI) const {
+  // TODO Implement.
+  return RegisterBankInfo::getInstrAlternativeMappings(MI);
+}

llvm/lib/Target/PowerPC/GISel/PPCRegisterBanks.td

 //===-- PPCRegisterBanks.td - Describe the PPC Banks -------*- tablegen -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
 /// Define the PPC register banks used for GlobalISel.
 ///
 //===----------------------------------------------------------------------===//
 
 /// General Purpose Registers
-def GPRRegBank : RegisterBank<"GPR", [G8RC]>;
+def GPRRegBank : RegisterBank<"GPR", [G8RC, G8RC_NOX0]>;

llvm/test/CodeGen/PowerPC/GlobalISel/ppc-isel-logical.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple ppc64le-linux -ppc-asm-full-reg-names -global-isel -o - < %s \
+; RUN:     | FileCheck %s
+
+define i64 @test_andi64(i64 %a, i64 %b) {
+; CHECK-LABEL: test_andi64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    and r3, r3, r4
+; CHECK-NEXT:    blr
+  %res = and i64 %a, %b
+  ret i64 %res
+}
+
+define i64 @test_nandi64(i64 %a, i64 %b) {
+; CHECK-LABEL: test_nandi64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    nand r3, r3, r4
+; CHECK-NEXT:    blr
+  %and = and i64 %a, %b
+  %neg = xor i64 %and, -1
+  ret i64 %neg
+}
+
+define i64 @test_andci64(i64 %a, i64 %b) {
+; CHECK-LABEL: test_andci64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    andc r3, r3, r4
+; CHECK-NEXT:    blr
+  %neg = xor i64 %b, -1
+  %and = and i64 %a, %neg
+  ret i64 %and
+}
+
+define i64 @test_ori64(i64 %a, i64 %b) {
+; CHECK-LABEL: test_ori64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    or r3, r3, r4
+; CHECK-NEXT:    blr
+  %res = or i64 %a, %b
+  ret i64 %res
+}
+
+define i64 @test_orci64(i64 %a, i64 %b) {
+; CHECK-LABEL: test_orci64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    orc r3, r3, r4
+; CHECK-NEXT:    blr
+  %neg = xor i64 %b, -1
+  %or = or i64 %a, %neg
+  ret i64 %or
+}
+
+define i64 @test_nori64(i64 %a, i64 %b) {
+; CHECK-LABEL: test_nori64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    nor r3, r3, r4
+; CHECK-NEXT:    blr
+  %or = or i64 %a, %b
+  %neg = xor i64 %or, -1
+  ret i64 %neg
+}
+
+define i64 @test_xori64(i64 %a, i64 %b) {
+; CHECK-LABEL: test_xori64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    blr
+  %res = xor i64 %a, %b
+  ret i64 %res
+}