[PowerPC] Add support for G_ADD and G_SUB.

[Kai]

Summary

Extends the global isel implementation to support G_ADD and G_SUB.

[arsenm]

llvm/test/CodeGen/PowerPC/GlobalISel/ppc-irtranslator.ll

42–43 ↗

(On Diff #438059)

Checking these in an IRTranslator test is pointless

llvm/test/CodeGen/PowerPC/GlobalISel/ppc-isel-arithmentic.ll

11

Probably should also test some illegal types and vectors

[Kai]

• Removed test in ppc-irtranslator.ll
• Added tests for i8, i16, i32.

[Kai]

llvm/test/CodeGen/PowerPC/GlobalISel/ppc-irtranslator.ll

42–43 ↗

(On Diff #438059)

Removed tests.

llvm/test/CodeGen/PowerPC/GlobalISel/ppc-isel-arithmentic.ll

11

Added tests for i8, i16, i32.
Vectors are not yet supported, the base code in D127530 does not even have a register bank for vector res.

[arsenm]

LGTM but I'd recommend generating the test checks

[amyk]

LGTM, and I also think autogenerating the checks would be a good idea.

[amyk]

Also, slight nit, but I think the name of test file should be ppc-isel-arithmetic.ll.

llvm/lib/Target/PowerPC/GISel/PPCLegalizerInfo.cpp

PPCLegalizerInfo::PPCLegalizerInfo(const PPCSubtarget &ST) {
   const LLT S64 = LLT::scalar(64);
   getActionDefinitionsBuilder(G_IMPLICIT_DEF).legalFor({S64});
   getActionDefinitionsBuilder(G_CONSTANT)
       .legalFor({S64})
       .clampScalar(0, S64, S64);
   getActionDefinitionsBuilder({G_AND, G_OR, G_XOR})
       .legalFor({S64})
       .clampScalar(0, S64, S64);
+  getActionDefinitionsBuilder({G_ADD, G_SUB})
+      .legalFor({S64})
+      .clampScalar(0, S64, S64);
   getLegacyLegalizerInfo().computeTables();
 }

llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp

PPCRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
   }
 
   unsigned NumOperands = MI.getNumOperands();
   const ValueMapping *OperandsMapping = nullptr;
   unsigned Cost = 1;
   unsigned MappingID = DefaultMappingID;
 
   switch (Opc) {
+    // Arithmetic ops.
+  case TargetOpcode::G_ADD:
+  case TargetOpcode::G_SUB:
     // Bitwise ops.
   case TargetOpcode::G_AND:
   case TargetOpcode::G_OR:
   case TargetOpcode::G_XOR:
     assert(NumOperands <= 3 &&
            "This code is for instructions with 3 or less operands");
     OperandsMapping = getValueMapping(PMI_GPR64);
     break;

llvm/test/CodeGen/PowerPC/GlobalISel/ppc-isel-arithmentic.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple ppc64le-linux -ppc-asm-full-reg-names -global-isel -o - < %s \
+; RUN:     | FileCheck %s
+
+define i8 @test_addi8(i8 %a, i8 %b) {
+; CHECK-LABEL: test_addi8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    add r3, r3, r4
+; CHECK-NEXT:    blr
+  %res = add i8 %a, %b
+  ret i8 %res
+}
+
+define i16 @test_addi16(i16 %a, i16 %b) {
+; CHECK-LABEL: test_addi16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    add r3, r3, r4
+; CHECK-NEXT:    blr
+  %res = add i16 %a, %b
+  ret i16 %res
+}
+
+define i32 @test_addi32(i32 %a, i32 %b) {
+; CHECK-LABEL: test_addi32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    add r3, r3, r4
+; CHECK-NEXT:    blr
+  %res = add i32 %a, %b
+  ret i32 %res
+}
+
+define i64 @test_addi64(i64 %a, i64 %b) {
+; CHECK-LABEL: test_addi64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    add r3, r3, r4
+; CHECK-NEXT:    blr
+  %res = add i64 %a, %b
+  ret i64 %res
+}
+
+define i8 @test_subi8(i8 %a, i8 %b) {
+; CHECK-LABEL: test_subi8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    blr
+  %res = sub i8 %a, %b
+  ret i8 %res
+}
+
+define i16 @test_subi16(i16 %a, i16 %b) {
+; CHECK-LABEL: test_subi16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    blr
+  %res = sub i16 %a, %b
+  ret i16 %res
+}
+
+define i32 @test_subi32(i32 %a, i32 %b) {
+; CHECK-LABEL: test_subi32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    blr
+  %res = sub i32 %a, %b
+  ret i32 %res
+}
+
+define i64 @test_subi64(i64 %a, i64 %b) {
+; CHECK-LABEL: test_subi64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    blr
+  %res = sub i64 %a, %b
+  ret i64 %res
+}