[PowerPC] Add support for extending and truncating values

[Kai]

Summary

Adds/completes support for G_SEXT, G_ZEXT, and G_TRUNC.
Support for G_SEXT and G_ZEXT was already partly implemented.

[tschuett]

Did I miss the tests for G_ANYEXT and G_TRUNC?
Apparently, the solution are MIR-tests like, e.g.,
https://reviews.llvm.org/D37675

[amyk]

llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp

209

Do we need to check if these are valid registers first before getting the register?

llvm/test/CodeGen/PowerPC/GlobalISel/ppc-isel-constant.ll

1 ↗

(On Diff #450411)

nit: Might be good to autogenerate these LIT tests with -ppc-asm-full-reg-names.

llvm/test/CodeGen/PowerPC/GlobalISel/ppc-isel-logical.ll

11 ↗

(On Diff #450411)

nit: Might be good to autogenerate these LIT tests with -ppc-asm-full-reg-names here, as well.

[shchenz]

llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp

144

For imm32, seems the implementation in PPCFastISel::PPCMaterialize32BitInt() looks simpler to me.

int64_t Imm = ConstValue.getZExtValue();
if (isInt<16>(Imm))
{
  // a single LI/LI8 is enough
} else if (Imm & 0xFFFF) {
  // Handle the low and high 16 bit seperatedly
} else {
  // only handle the high 16 as the low 16 bits are all 0
}

And for the 64 bit integers, maybe we can also refer to PPCFastISel::PPCMaterialize64BitInt() if we want to have a implementation for them

426

Seems the logic in selectSExt is not what G_SEXT_INREG represents. Can we set action for G_SEXT_INREG as lower and use target independent handling for G_SEXT_INREG like other targets does?

Not sure which test case triggers this generic opcode?

427

G_SEXT seems can be selected automatically in the td files but G_ZEXT can not. So I suppose there should be some codes to select G_ZEXT too? I made a implementation in https://reviews.llvm.org/D135535

llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp

38

This is for i128? Seems no related handling for i128 in this patch?

llvm/test/CodeGen/PowerPC/GlobalISel/ppc-isel-constant.ll

1 ↗

(On Diff #450411)

And seems the cases are all testing zero/sign extension from i32 -> i64. Should we test other code path as well, like i8/i16 -> i64? And for trunc operation too?

llvm/test/CodeGen/PowerPC/GlobalISel/ppc-isel-logical.ll

2 ↗

(On Diff #450411)

This test file seems not belong to this patch?

[Kai]

Completely reworked the change.

• Rebased on latest main which has partial implementation of G_ZEXT (Currently, G_ZEXT and G_SEXT are only implemented for extending 32 -> 64 bit.)
• Removed support for G_CONSTANT. I will have a more complete solution ready in a follow up change.
• Added a mir test case to check the generated code

[shchenz]

llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp

247

What will happen if we don't constrain the middle result, like ImpDefReg and result of INSERT_SUBREG? I assume the register class setting in the source code here should match what IMPLICIT_DEF INSERT_SUBREG and the final RLDICL requires?

254

Do we need to handle any arbitrary bit here, like i7/i9? I assume the illegal types should be already handled in legalizer pass?

258

hmm, what if the register class of SrcReg is not g8rc? Directly putting it as operand of PPC::RLDICL seems not right to me. For example if the input is gprc, constraining may change it to g8rc by adding a COPY? but that COPY will not tell how to handle the high 32 bit?

284

nit: sounds like here should be dest operand?

292

We may need to change the tb for the 8 and 16 bits in another patch. For example add patterns for EXTSB8_32_64 and EXTSH8_32_64?

336

Weird that trunc i64 to i32 can not be handled in table gen?
There is pattern:

def : Pat<(i32 (trunc i64:$in)),
          (EXTRACT_SUBREG $in, sub_32)>;

Seems the patterns in the match table are all about trunc from i64/i32 -> i1. Maybe a closely look is needed to understand why for later improvement.

342

Same as sext, directly putting SrcReg as operand of PPC::RLDICL will cause copy like %1:gprc = COPY %3:g8rc and this COPY can not be expanded in later pseudo expansion.

llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp

private:
 
   bool selectFPToInt(MachineInstr &I, MachineBasicBlock &MBB,
                   MachineRegisterInfo &MRI) const;
   bool selectIntToFP(MachineInstr &I, MachineBasicBlock &MBB,
                   MachineRegisterInfo &MRI) const;
 
   bool selectZExt(MachineInstr &I, MachineBasicBlock &MBB,
                   MachineRegisterInfo &MRI) const;
+  bool selectSExt(MachineInstr &I, MachineBasicBlock &MBB,
+                  MachineRegisterInfo &MRI) const;
+  bool selectTrunc(MachineInstr &I, MachineBasicBlock &MBB,
+                   MachineRegisterInfo &MRI) const;
 
   const PPCSubtarget &STI;
   const PPCInstrInfo &TII;
   const PPCRegisterInfo &TRI;
   const PPCRegisterBankInfo &RBI;
 
 #define GET_GLOBALISEL_PREDICATES_DECL
 #include "PPCGenGlobalISel.inc"

 static unsigned selectLoadStoreOp(unsigned GenericOpc, unsigned RegBankID,
                                   unsigned OpSize) {
   const bool IsStore = GenericOpc == TargetOpcode::G_STORE;
   switch (RegBankID) {
   case PPC::GPRRegBankID:
     switch (OpSize) {
     case 32:
       return IsStore ? PPC::STW : PPC::LWZ;
     case 64:
       return IsStore ? PPC::STD : PPC::LD;
     default:
       llvm_unreachable("Unexpected size!");
     }
     break;
   case PPC::FPRRegBankID:
     switch (OpSize) {
     case 32:
bool PPCInstructionSelector::selectFPToInt(MachineInstr &I,
   const Register SrcReg = I.getOperand(1).getReg();
 
   Register CopyReg = MRI.createVirtualRegister(&PPC::VSFRCRegClass);
   BuildMI(MBB, I, DbgLoc, TII.get(TargetOpcode::COPY), CopyReg).addReg(SrcReg);
 
   Register ConvReg = MRI.createVirtualRegister(&PPC::VSFRCRegClass);
 
   bool IsSigned = I.getOpcode() == TargetOpcode::G_FPTOSI;
 
   // single-precision is stored as double-precision on PPC in registers, so
   // always use double-precision convertions.
   unsigned ConvOp = IsSigned ? PPC::XSCVDPSXDS : PPC::XSCVDPUXDS;
 
   BuildMI(MBB, I, DbgLoc, TII.get(ConvOp), ConvReg).addReg(CopyReg);
 
   MachineInstr *MI =
       BuildMI(MBB, I, DbgLoc, TII.get(PPC::MFVSRD), DstReg).addReg(ConvReg);
 
   I.eraseFromParent();
   return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
 }
 
 bool PPCInstructionSelector::selectZExt(MachineInstr &I, MachineBasicBlock &MBB,
                                         MachineRegisterInfo &MRI) const {
   const Register DstReg = I.getOperand(0).getReg();
   const LLT DstTy = MRI.getType(DstReg);
   const RegisterBank *DstRegBank = RBI.getRegBank(DstReg, MRI, TRI);
 
   const Register SrcReg = I.getOperand(1).getReg();
+  MachineInstr *MI;
 
   assert(DstTy.getSizeInBits() == 64 && "Unexpected dest size!");
-  assert(MRI.getType(SrcReg).getSizeInBits() == 32 && "Unexpected src size!");
-
-  Register ImpDefReg =
-      MRI.createVirtualRegister(getRegClass(DstTy, DstRegBank));
+  if (MRI.getType(SrcReg).getSizeInBits() == 32) {
+    const TargetRegisterClass *ImpDefRC = getRegClass(DstTy, DstRegBank);
+    Register ImpDefReg = MRI.createVirtualRegister(ImpDefRC);
     BuildMI(MBB, I, I.getDebugLoc(), TII.get(TargetOpcode::IMPLICIT_DEF),
             ImpDefReg);
+    RBI.constrainGenericRegister(ImpDefReg, *ImpDefRC, MRI);
 
     Register NewDefReg =
         MRI.createVirtualRegister(getRegClass(DstTy, DstRegBank));
-  BuildMI(MBB, I, I.getDebugLoc(), TII.get(TargetOpcode::INSERT_SUBREG),
+    MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(TargetOpcode::INSERT_SUBREG),
                  NewDefReg)
              .addReg(ImpDefReg)
              .addReg(SrcReg)
              .addImm(PPC::sub_32);
+    constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
 
-  MachineInstr *MI =
-      BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::RLDICL), DstReg)
+    MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::RLDICL), DstReg)
              .addReg(NewDefReg)
              .addImm(0)
              .addImm(32);
+  } else {
+    assert(MRI.getType(SrcReg).getSizeInBits() < 32 && "Unexpected src size!");
+    MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::RLDICL), DstReg)
+             .addReg(SrcReg)
+             .addImm(0)
+             .addImm(64 - MRI.getType(SrcReg).getSizeInBits());
+  }
+  I.eraseFromParent();
+  return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
+}
+
+bool PPCInstructionSelector::selectSExt(MachineInstr &I, MachineBasicBlock &MBB,
+                                        MachineRegisterInfo &MRI) const {
+  assert(I.getOpcode() == TargetOpcode::G_SEXT && "Unexpected G code");
 
+  const Register DstReg = I.getOperand(0).getReg();
+  const Register SrcReg = I.getOperand(1).getReg();
+
+  const RegisterBank *DstRB = RBI.getRegBank(DstReg, MRI, TRI);
+  const RegisterBank *SrcRB = RBI.getRegBank(SrcReg, MRI, TRI);
+
+  if (DstRB->getID() != SrcRB->getID()) {
+    LLVM_DEBUG(dbgs() << TII.getName(I.getOpcode())
+                      << " input/output on different banks\n");
+    return false;
+  }
+  // TODO Add vector support.
+  if (DstRB->getID() != PPC::GPRRegBankID)
+    return false;
+
+  assert(MRI.getType(DstReg).getSizeInBits() == 64 &&
+         "Unexpected size of source operand");
+
+  unsigned Opc;
+  switch (MRI.getType(SrcReg).getSizeInBits()) {
+  case 8:
+    Opc = PPC::EXTSB8;
+    break;
+  case 16:
+    Opc = PPC::EXTSH8;
+    break;
+  case 32:
+    // Opcode would be PPC::EXTSW.
+    llvm_unreachable("Should have been handled by TableGen");
+  default:
+    return false;
+  }
+  MachineInstr *MI =
+      BuildMI(MBB, I, I.getDebugLoc(), TII.get(Opc), DstReg).addReg(SrcReg);
   I.eraseFromParent();
   return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
 }
 
+bool PPCInstructionSelector::selectTrunc(MachineInstr &I,
+                                         MachineBasicBlock &MBB,
+                                         MachineRegisterInfo &MRI) const {
+  assert(I.getOpcode() == TargetOpcode::G_TRUNC && "Unexpected G code");
+
+  const Register DstReg = I.getOperand(0).getReg();
+  const Register SrcReg = I.getOperand(1).getReg();
+
+  const LLT DstTy = MRI.getType(DstReg);
+  const LLT SrcTy = MRI.getType(SrcReg);
+
+  const RegisterBank *DstRB = RBI.getRegBank(DstReg, MRI, TRI);
+  const RegisterBank *SrcRB = RBI.getRegBank(SrcReg, MRI, TRI);
+
+  if (DstRB->getID() != SrcRB->getID()) {
+    LLVM_DEBUG(dbgs() << TII.getName(I.getOpcode())
+                      << " input/output on different banks\n");
+    return false;
+  }
+  // TODO Add vector support.
+  if (DstRB->getID() != PPC::GPRRegBankID)
+    return false;
+
+  const TypeSize DstSz = DstTy.getSizeInBits();
+  const TypeSize SrcSz = SrcTy.getSizeInBits();
+  assert(SrcSz == 64 && "Unexpected size of source operand");
+
+  if (DstSz == SrcSz) {
+    I.setDesc(TII.get(TargetOpcode::COPY));
+    return selectCopy(I, TII, MRI, TRI, RBI);
+  } else if (DstSz == 32 && SrcSz == 64) {
+    I.setDesc(TII.get(TargetOpcode::COPY));
+    I.getOperand(1).setSubReg(PPC::sub_32);
+    return selectCopy(I, TII, MRI, TRI, RBI);
+  } else {
+    MachineInstr *MI =
+        BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::RLDICL), DstReg)
+            .addReg(SrcReg)
+            .addImm(0)
+            .addImm(64 - DstSz);
+    I.eraseFromParent();
+    return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
+  }
+}
+
 bool PPCInstructionSelector::select(MachineInstr &I) {
   auto &MBB = *I.getParent();
   auto &MF = *MBB.getParent();
   auto &MRI = MF.getRegInfo();
 
   if (!isPreISelGenericOpcode(I.getOpcode())) {
     if (I.isCopy())
       return selectCopy(I, TII, MRI, TRI, RBI);
case TargetOpcode::G_STORE: {
     return constrainSelectedInstRegOperands(*LoadStore, TII, TRI, RBI);
   }
   case TargetOpcode::G_SITOFP:
   case TargetOpcode::G_UITOFP:
     return selectIntToFP(I, MBB, MRI);
   case TargetOpcode::G_FPTOSI:
   case TargetOpcode::G_FPTOUI:
     return selectFPToInt(I, MBB, MRI);
-  // G_SEXT will be selected in tb-gen pattern.
+  // G_SEXT will be partly selected in tb-gen pattern.
+  case TargetOpcode::G_SEXT:
+    return selectSExt(I, MBB, MRI);
   case TargetOpcode::G_ZEXT:
     return selectZExt(I, MBB, MRI);
+  case TargetOpcode::G_TRUNC:
+    return selectTrunc(I, MBB, MRI);
   }
   return false;
 }
 
 namespace llvm {
 InstructionSelector *
 createPPCInstructionSelector(const PPCTargetMachine &TM,
                              const PPCSubtarget &Subtarget,
                              const PPCRegisterBankInfo &RBI) {
   return new PPCInstructionSelector(TM, Subtarget, RBI);
 }
 } // end namespace llvm

llvm/lib/Target/PowerPC/GISel/PPCLegalizerInfo.cpp

PPCLegalizerInfo::PPCLegalizerInfo(const PPCSubtarget &ST) {
   const LLT S8 = LLT::scalar(8);
   const LLT S16 = LLT::scalar(16);
   const LLT S32 = LLT::scalar(32);
   const LLT S64 = LLT::scalar(64);
   getActionDefinitionsBuilder(G_IMPLICIT_DEF).legalFor({S64});
   getActionDefinitionsBuilder(G_CONSTANT)
       .legalFor({S32, S64})
       .clampScalar(0, S64, S64);
+  getActionDefinitionsBuilder(G_TRUNC)
+      .legalForCartesianProduct({S8, S16, S32}, {S64});
   getActionDefinitionsBuilder({G_ZEXT, G_SEXT})
       .legalForCartesianProduct({S64}, {S8, S16, S32})
       .clampScalar(0, S64, S64);
   getActionDefinitionsBuilder({G_AND, G_OR, G_XOR})
       .legalFor({S64})
       .clampScalar(0, S64, S64);
   getActionDefinitionsBuilder({G_ADD, G_SUB})
       .legalFor({S64})

llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp

 
 const RegisterBank &
 PPCRegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC,
                                             LLT Ty) const {
   switch (RC.getID()) {
   case PPC::G8RCRegClassID:
   case PPC::G8RC_NOX0RegClassID:
   case PPC::G8RC_and_G8RC_NOX0RegClassID:
   case PPC::GPRCRegClassID:
   case PPC::GPRC_NOR0RegClassID:
   case PPC::GPRC_and_GPRC_NOR0RegClassID:
     return getRegBank(PPC::GPRRegBankID);
   case PPC::VSFRCRegClassID:
   case PPC::SPILLTOVSRRC_and_VSFRCRegClassID:
   case PPC::SPILLTOVSRRC_and_VFRCRegClassID:
   case PPC::SPILLTOVSRRC_and_F4RCRegClassID:
   case PPC::F8RCRegClassID:
PPCRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
   switch (Opc) {
     // Arithmetic ops.
   case TargetOpcode::G_ADD:
   case TargetOpcode::G_SUB:
     // Bitwise ops.
   case TargetOpcode::G_AND:
   case TargetOpcode::G_OR:
   case TargetOpcode::G_XOR:
-    // Extension ops.
+    // Truncation & Extension ops.
+  case TargetOpcode::G_TRUNC:
   case TargetOpcode::G_SEXT:
   case TargetOpcode::G_ZEXT:
     assert(NumOperands <= 3 &&
            "This code is for instructions with 3 or less operands");
     OperandsMapping = getValueMapping(PMI_GPR64);
     break;
   case TargetOpcode::G_FADD:
   case TargetOpcode::G_FSUB:

llvm/test/CodeGen/PowerPC/GlobalISel/select-exttrunc.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple ppc64le-linux -ppc-asm-full-reg-names -global-isel \
+# RUN:     -verify-machineinstrs -run-pass=instruction-select -o - %s \
+# RUN:     | FileCheck %s
+---
+name:            trunc8zext
+alignment:       16
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x3' }
+frameInfo:
+  maxAlignment:    1
+machineFunctionInfo: {}
+body:             |
+  bb.1.entry:
+    liveins: $x3
+
+    ; CHECK-LABEL: name: trunc8zext
+    ; CHECK: liveins: $x3
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:g8rc = COPY $x3
+    ; CHECK-NEXT: [[RLDICL:%[0-9]+]]:g8rc = RLDICL [[COPY]], 0, 56
+    ; CHECK-NEXT: [[RLDICL1:%[0-9]+]]:g8rc = RLDICL [[RLDICL]], 0, 56
+    ; CHECK-NEXT: $x3 = COPY [[RLDICL1]]
+    ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $x3
+    %0:gpr(s64) = COPY $x3
+    %1:gpr(s8) = G_TRUNC %0(s64)
+    %2:gpr(s64) = G_ZEXT %1(s8)
+    $x3 = COPY %2(s64)
+    BLR8 implicit $lr8, implicit $rm, implicit $x3
+
+...
+---
+name:            trunc16zext
+alignment:       16
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x3' }
+frameInfo:
+  maxAlignment:    1
+machineFunctionInfo: {}
+body:             |
+  bb.1.entry:
+    liveins: $x3
+
+    ; CHECK-LABEL: name: trunc16zext
+    ; CHECK: liveins: $x3
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:g8rc = COPY $x3
+    ; CHECK-NEXT: [[RLDICL:%[0-9]+]]:g8rc = RLDICL [[COPY]], 0, 48
+    ; CHECK-NEXT: [[RLDICL1:%[0-9]+]]:g8rc = RLDICL [[RLDICL]], 0, 48
+    ; CHECK-NEXT: $x3 = COPY [[RLDICL1]]
+    ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $x3
+    %0:gpr(s64) = COPY $x3
+    %1:gpr(s16) = G_TRUNC %0(s64)
+    %2:gpr(s64) = G_ZEXT %1(s16)
+    $x3 = COPY %2(s64)
+    BLR8 implicit $lr8, implicit $rm, implicit $x3
+
+...
+---
+name:            trunc32zext
+alignment:       16
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x3' }
+frameInfo:
+  maxAlignment:    1
+machineFunctionInfo: {}
+body:             |
+  bb.1.entry:
+    liveins: $x3
+
+    ; CHECK-LABEL: name: trunc32zext
+    ; CHECK: liveins: $x3
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:g8rc = COPY $x3
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprc = COPY [[COPY]].sub_32
+    ; CHECK-NEXT: [[DEF:%[0-9]+]]:g8rc = IMPLICIT_DEF
+    ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:g8rc = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.sub_32
+    ; CHECK-NEXT: [[RLDICL:%[0-9]+]]:g8rc = RLDICL [[INSERT_SUBREG]], 0, 32
+    ; CHECK-NEXT: $x3 = COPY [[RLDICL]]
+    ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $x3
+    %0:gpr(s64) = COPY $x3
+    %1:gpr(s32) = G_TRUNC %0(s64)
+    %2:gpr(s64) = G_ZEXT %1(s32)
+    $x3 = COPY %2(s64)
+    BLR8 implicit $lr8, implicit $rm, implicit $x3
+
+...
+---
+name:            trunc8sext
+alignment:       16
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x3' }
+frameInfo:
+  maxAlignment:    1
+machineFunctionInfo: {}
+body:             |
+  bb.1.entry:
+    liveins: $x3
+
+    ; CHECK-LABEL: name: trunc8sext
+    ; CHECK: liveins: $x3
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:g8rc = COPY $x3
+    ; CHECK-NEXT: [[RLDICL:%[0-9]+]]:g8rc = RLDICL [[COPY]], 0, 56
+    ; CHECK-NEXT: [[EXTSB8_:%[0-9]+]]:g8rc = EXTSB8 [[RLDICL]]
+    ; CHECK-NEXT: $x3 = COPY [[EXTSB8_]]
+    ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $x3
+    %0:gpr(s64) = COPY $x3
+    %1:gpr(s8) = G_TRUNC %0(s64)
+    %2:gpr(s64) = G_SEXT %1(s8)
+    $x3 = COPY %2(s64)
+    BLR8 implicit $lr8, implicit $rm, implicit $x3
+
+...
+---
+name:            trunc16sext
+alignment:       16
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x3' }
+frameInfo:
+  maxAlignment:    1
+machineFunctionInfo: {}
+body:             |
+  bb.1.entry:
+    liveins: $x3
+
+    ; CHECK-LABEL: name: trunc16sext
+    ; CHECK: liveins: $x3
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:g8rc = COPY $x3
+    ; CHECK-NEXT: [[RLDICL:%[0-9]+]]:g8rc = RLDICL [[COPY]], 0, 48
+    ; CHECK-NEXT: [[EXTSH8_:%[0-9]+]]:g8rc = EXTSH8 [[RLDICL]]
+    ; CHECK-NEXT: $x3 = COPY [[EXTSH8_]]
+    ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $x3
+    %0:gpr(s64) = COPY $x3
+    %1:gpr(s16) = G_TRUNC %0(s64)
+    %2:gpr(s64) = G_SEXT %1(s16)
+    $x3 = COPY %2(s64)
+    BLR8 implicit $lr8, implicit $rm, implicit $x3
+
+...
+---
+name:            trunc32sext
+alignment:       16
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+liveins:
+  - { reg: '$x3' }
+frameInfo:
+  maxAlignment:    1
+machineFunctionInfo: {}
+body:             |
+  bb.1.entry:
+    liveins: $x3
+
+    ; CHECK-LABEL: name: trunc32sext
+    ; CHECK: liveins: $x3
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:g8rc = COPY $x3
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprc = COPY [[COPY]].sub_32
+    ; CHECK-NEXT: [[EXTSW_32_64_:%[0-9]+]]:g8rc = EXTSW_32_64 [[COPY1]]
+    ; CHECK-NEXT: $x3 = COPY [[EXTSW_32_64_]]
+    ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $x3
+    %0:gpr(s64) = COPY $x3
+    %1:gpr(s32) = G_TRUNC %0(s64)
+    %2:gpr(s64) = G_SEXT %1(s32)
+    $x3 = COPY %2(s64)
+    BLR8 implicit $lr8, implicit $rm, implicit $x3
+
+...