[PowerPC][GISel] support 32 bit load/store

[shchenz]

Summary

This is a follow up of D134792. This patch supports 32 bit load/store.

[shchenz]

Make load/store selection be parent of constantFP selection patch D133340

[amyk]

llvm/lib/Target/PowerPC/GISel/PPCLegalizerInfo.cpp

49–50

We should update this comment (since as of this patch, we support both 32-bit and 64-bit).

[shchenz]

llvm/lib/Target/PowerPC/GISel/PPCLegalizerInfo.cpp

49–50

good catch, will update.

[shchenz]

fix inaccurate comments

[shchenz]

set right legalizer info

llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp

private:
   /// selector for the patterns that do not require complex C++.
   bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
 
   bool selectFPToInt(MachineInstr &I, MachineBasicBlock &MBB,
                   MachineRegisterInfo &MRI) const;
   bool selectIntToFP(MachineInstr &I, MachineBasicBlock &MBB,
                   MachineRegisterInfo &MRI) const;
 
+  bool selectZExt(MachineInstr &I, MachineBasicBlock &MBB,
+                  MachineRegisterInfo &MRI) const;
+
   const PPCSubtarget &STI;
   const PPCInstrInfo &TII;
   const PPCRegisterInfo &TRI;
   const PPCRegisterBankInfo &RBI;
 
 #define GET_GLOBALISEL_PREDICATES_DECL
 #include "PPCGenGlobalISel.inc"
 #undef GET_GLOBALISEL_PREDICATES_DECL

 #undef GET_GLOBALISEL_TEMPORARIES_INIT
 {
 }
 
 static const TargetRegisterClass *getRegClass(LLT Ty, const RegisterBank *RB) {
   if (RB->getID() == PPC::GPRRegBankID) {
     if (Ty.getSizeInBits() == 64)
       return &PPC::G8RCRegClass;
+    if (Ty.getSizeInBits() == 32)
+      return &PPC::GPRCRegClass;
   }
   if (RB->getID() == PPC::FPRRegBankID) {
     if (Ty.getSizeInBits() == 32)
       return &PPC::F4RCRegClass;
     if (Ty.getSizeInBits() == 64)
       return &PPC::F8RCRegClass;
   }
 

 }
 
 static unsigned selectLoadStoreOp(unsigned GenericOpc, unsigned RegBankID,
                                   unsigned OpSize) {
   const bool IsStore = GenericOpc == TargetOpcode::G_STORE;
   switch (RegBankID) {
   case PPC::GPRRegBankID:
     switch (OpSize) {
+    case 32:
+      return IsStore ? PPC::STW : PPC::LWZ;
     case 64:
       return IsStore ? PPC::STD : PPC::LD;
     default:
       llvm_unreachable("Unexpected size!");
     }
     break;
   case PPC::FPRRegBankID:
     switch (OpSize) {
+    case 32:
+      return IsStore ? PPC::STFS : PPC::LFS;
     case 64:
       return IsStore ? PPC::STFD : PPC::LFD;
     default:
       llvm_unreachable("Unexpected size!");
     }
     break;
   default:
     llvm_unreachable("Unexpected register bank!");
bool PPCInstructionSelector::selectFPToInt(MachineInstr &I,
 
   MachineInstr *MI =
       BuildMI(MBB, I, DbgLoc, TII.get(PPC::MFVSRD), DstReg).addReg(ConvReg);
 
   I.eraseFromParent();
   return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
 }
 
+bool PPCInstructionSelector::selectZExt(MachineInstr &I, MachineBasicBlock &MBB,
+                                        MachineRegisterInfo &MRI) const {
+  const Register DstReg = I.getOperand(0).getReg();
+  const LLT DstTy = MRI.getType(DstReg);
+  const RegisterBank *DstRegBank = RBI.getRegBank(DstReg, MRI, TRI);
+
+  const Register SrcReg = I.getOperand(1).getReg();
+
+  assert(DstTy.getSizeInBits() == 64 && "Unexpected dest size!");
+  assert(MRI.getType(SrcReg).getSizeInBits() == 32 && "Unexpected src size!");
+
+  Register ImpDefReg =
+      MRI.createVirtualRegister(getRegClass(DstTy, DstRegBank));
+  BuildMI(MBB, I, I.getDebugLoc(), TII.get(TargetOpcode::IMPLICIT_DEF),
+          ImpDefReg);
+
+  Register NewDefReg =
+      MRI.createVirtualRegister(getRegClass(DstTy, DstRegBank));
+  BuildMI(MBB, I, I.getDebugLoc(), TII.get(TargetOpcode::INSERT_SUBREG),
+          NewDefReg)
+      .addReg(ImpDefReg)
+      .addReg(SrcReg)
+      .addImm(PPC::sub_32);
+
+  MachineInstr *MI =
+      BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::RLDICL), DstReg)
+          .addReg(NewDefReg)
+          .addImm(0)
+          .addImm(32);
+
+  I.eraseFromParent();
+  return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
+}
+
 bool PPCInstructionSelector::select(MachineInstr &I) {
   auto &MBB = *I.getParent();
   auto &MF = *MBB.getParent();
   auto &MRI = MF.getRegInfo();
 
   if (!isPreISelGenericOpcode(I.getOpcode())) {
     if (I.isCopy())
       return selectCopy(I, TII, MRI, TRI, RBI);
case TargetOpcode::G_STORE: {
     return constrainSelectedInstRegOperands(*LoadStore, TII, TRI, RBI);
   }
   case TargetOpcode::G_SITOFP:
   case TargetOpcode::G_UITOFP:
     return selectIntToFP(I, MBB, MRI);
   case TargetOpcode::G_FPTOSI:
   case TargetOpcode::G_FPTOUI:
     return selectFPToInt(I, MBB, MRI);
+  // G_SEXT will be selected in tb-gen pattern.
+  case TargetOpcode::G_ZEXT:
+    return selectZExt(I, MBB, MRI);
   }
   return false;
 }
 
 namespace llvm {
 InstructionSelector *
 createPPCInstructionSelector(const PPCTargetMachine &TM,
                              const PPCSubtarget &Subtarget,
                              const PPCRegisterBankInfo &RBI) {
   return new PPCInstructionSelector(TM, Subtarget, RBI);
 }
 } // end namespace llvm

llvm/lib/Target/PowerPC/GISel/PPCLegalizerInfo.cpp

 #define DEBUG_TYPE "ppc-legalinfo"
 
 using namespace llvm;
 using namespace LegalizeActions;
 
 PPCLegalizerInfo::PPCLegalizerInfo(const PPCSubtarget &ST) {
   using namespace TargetOpcode;
   const LLT P0 = LLT::pointer(0, 64);
+  const LLT S8 = LLT::scalar(8);
+  const LLT S16 = LLT::scalar(16);
   const LLT S32 = LLT::scalar(32);
   const LLT S64 = LLT::scalar(64);
   getActionDefinitionsBuilder(G_IMPLICIT_DEF).legalFor({S64});
   getActionDefinitionsBuilder(G_CONSTANT)
-      .legalFor({S64})
+      .legalFor({S32, S64})
+      .clampScalar(0, S64, S64);
+  getActionDefinitionsBuilder({G_ZEXT, G_SEXT})
+      .legalForCartesianProduct({S64}, {S8, S16, S32})
       .clampScalar(0, S64, S64);
   getActionDefinitionsBuilder({G_AND, G_OR, G_XOR})
       .legalFor({S64})
       .clampScalar(0, S64, S64);
   getActionDefinitionsBuilder({G_ADD, G_SUB})
       .legalFor({S64})
       .clampScalar(0, S64, S64);
 
   getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV})
       .legalFor({S32, S64});
 
   getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI})
       .legalForCartesianProduct({S64}, {S32, S64});
 
   getActionDefinitionsBuilder({G_SITOFP, G_UITOFP})
       .legalForCartesianProduct({S32, S64}, {S64});
 
-  // For now only handle 64 bit, we only support 64 bit integer and zext/sext is
-  // not ready.
   getActionDefinitionsBuilder({G_LOAD, G_STORE})
-      .legalForTypesWithMemDesc({{S64, P0, S64, 8}});
+      .legalForTypesWithMemDesc({{S64, P0, S64, 8}, {S32, P0, S32, 4}});
 
   getLegacyLegalizerInfo().computeTables();
 }

llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.h

 
 namespace llvm {
 class TargetRegisterInfo;
 
 class PPCGenRegisterBankInfo : public RegisterBankInfo {
 protected:
   enum PartialMappingIdx {
     PMI_None = -1,
-    PMI_GPR64 = 1,
-    PMI_FPR32 = 2,
-    PMI_FPR64 = 3,
-    PMI_Min = PMI_GPR64,
+    PMI_GPR32 = 1,
+    PMI_GPR64 = 2,
+    PMI_FPR32 = 3,
+    PMI_FPR64 = 4,
+    PMI_Min = PMI_GPR32,
   };
 
   static RegisterBankInfo::PartialMapping PartMappings[];
   static RegisterBankInfo::ValueMapping ValMappings[];
   static PartialMappingIdx BankIDToCopyMapIdx[];
 
   /// Get the pointer to the ValueMapping representing the RegisterBank
   /// at \p RBIdx.

llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp

 
 const RegisterBank &
 PPCRegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC,
                                             LLT Ty) const {
   switch (RC.getID()) {
   case PPC::G8RCRegClassID:
   case PPC::G8RC_NOX0RegClassID:
   case PPC::G8RC_and_G8RC_NOX0RegClassID:
+  case PPC::GPRCRegClassID:
+  case PPC::GPRC_NOR0RegClassID:
+  case PPC::GPRC_and_GPRC_NOR0RegClassID:
     return getRegBank(PPC::GPRRegBankID);
   case PPC::VSFRCRegClassID:
   case PPC::SPILLTOVSRRC_and_VSFRCRegClassID:
   case PPC::SPILLTOVSRRC_and_VFRCRegClassID:
   case PPC::SPILLTOVSRRC_and_F4RCRegClassID:
   case PPC::F8RCRegClassID:
   case PPC::VFRCRegClassID:
   case PPC::VSSRCRegClassID:
PPCRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
   switch (Opc) {
     // Arithmetic ops.
   case TargetOpcode::G_ADD:
   case TargetOpcode::G_SUB:
     // Bitwise ops.
   case TargetOpcode::G_AND:
   case TargetOpcode::G_OR:
   case TargetOpcode::G_XOR:
+    // Extension ops.
+  case TargetOpcode::G_SEXT:
+  case TargetOpcode::G_ZEXT:
     assert(NumOperands <= 3 &&
            "This code is for instructions with 3 or less operands");
     OperandsMapping = getValueMapping(PMI_GPR64);
     break;
   case TargetOpcode::G_FADD:
   case TargetOpcode::G_FSUB:
   case TargetOpcode::G_FMUL:
   case TargetOpcode::G_FDIV: {
case TargetOpcode::G_SITOFP: {
     unsigned Size = getSizeInBits(SrcReg, MRI, TRI);
 
     OperandsMapping =
         getOperandsMapping({getValueMapping(Size == 32 ? PMI_FPR32 : PMI_FPR64),
                             getValueMapping(PMI_GPR64)});
     break;
   }
   case TargetOpcode::G_LOAD: {
+    unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
     // Check if that load feeds fp instructions.
     if (any_of(MRI.use_nodbg_instructions(MI.getOperand(0).getReg()),
                [&](const MachineInstr &UseMI) {
                  // If we have at least one direct use in a FP instruction,
                  // assume this was a floating point load in the IR. If it was
                  // not, we would have had a bitcast before reaching that
                  // instruction.
                  //
                  // Int->FP conversion operations are also captured in
                  // onlyDefinesFP().
                  return onlyUsesFP(UseMI, MRI, TRI);
                }))
       OperandsMapping = getOperandsMapping(
-          {getValueMapping(PMI_FPR64), getValueMapping(PMI_GPR64)});
+          {getValueMapping(Size == 64 ? PMI_FPR64 : PMI_FPR32),
+           getValueMapping(PMI_GPR64)});
     else
       OperandsMapping = getOperandsMapping(
-          {getValueMapping(PMI_GPR64), getValueMapping(PMI_GPR64)});
+          {getValueMapping(Size == 64 ? PMI_GPR64 : PMI_GPR32),
+           getValueMapping(PMI_GPR64)});
     break;
   }
   case TargetOpcode::G_STORE: {
     // Check if the store is fed by fp instructions.
     MachineInstr *DefMI = MRI.getVRegDef(MI.getOperand(0).getReg());
+    unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
     if (onlyDefinesFP(*DefMI, MRI, TRI))
       OperandsMapping = getOperandsMapping(
-          {getValueMapping(PMI_FPR64), getValueMapping(PMI_GPR64)});
+          {getValueMapping(Size == 64 ? PMI_FPR64 : PMI_FPR32),
+           getValueMapping(PMI_GPR64)});
     else
       OperandsMapping = getOperandsMapping(
-          {getValueMapping(PMI_GPR64), getValueMapping(PMI_GPR64)});
+          {getValueMapping(Size == 64 ? PMI_GPR64 : PMI_GPR32),
+           getValueMapping(PMI_GPR64)});
     break;
   }
   default:
     return getInvalidInstructionMapping();
   }
 
   return getInstructionMapping(MappingID, Cost, OperandsMapping, NumOperands);
 }

llvm/lib/Target/PowerPC/PPCGenRegisterBankInfo.def

 //===- PPCGenRegisterBankInfo.def -------------------------------*- C++ -*-==//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 /// \file
 /// This file defines all the static objects used by PPCRegisterBankInfo.
 /// \todo This should be generated by TableGen, because the logic here can be
 ///  derived from register bank definition. Not yet implemented.
 //===----------------------------------------------------------------------===//
 
 namespace llvm {
 RegisterBankInfo::PartialMapping PPCGenRegisterBankInfo::PartMappings[]{
     /* StartIdx, Length, RegBank */
-    // 0: GPR 64-bit value.
+    // 0: GPR 32-bit value.
+    {0, 32, PPC::GPRRegBank},
+    // 1: GPR 64-bit value.
     {0, 64, PPC::GPRRegBank},
-    // 1: FPR 32-bit value
+    // 2: FPR 32-bit value
     {0, 32, PPC::FPRRegBank},
-    // 2: FPR 64-bit value
+    // 3: FPR 64-bit value
     {0, 64, PPC::FPRRegBank},
 };
 
 // ValueMappings.
 // Pointers to the entries in this array are returned by getValueMapping() and
 // getCopyMapping().
 //
 // The array has the following structure:
 // - At index 0 is the invalid entry.
 // - After that, the mappings for the register types from PartialMappingIdx
 //   follow. Each mapping consists of 3 entries, which is needed to cover
 //   3-operands instructions.
 // - Last, mappings for cross-register bank moves follow. Since COPY has only
 //   2 operands, a mapping consists of 2 entries.
 RegisterBankInfo::ValueMapping PPCGenRegisterBankInfo::ValMappings[]{
     /* BreakDown, NumBreakDowns */
     // 0: invalid
     {nullptr, 0},
-    // 1: GPR 64-bit value.
+    // 1: GPR 32-bit value.
+    {&PPCGenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
+    {&PPCGenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
+    {&PPCGenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
+    // 4: GPR 64-bit value.
     {&PPCGenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
     {&PPCGenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
     {&PPCGenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
-    // 4: FPR 32-bit value.
+    // 7: FPR 32-bit value.
     {&PPCGenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
     {&PPCGenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
     {&PPCGenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
-    // 7: FPR 64-bit value.
+    // 10: FPR 64-bit value.
     {&PPCGenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
     {&PPCGenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
     {&PPCGenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
 };
 
 // TODO Too simple!
 const RegisterBankInfo::ValueMapping *
 PPCGenRegisterBankInfo::getValueMapping(PartialMappingIdx RBIdx) {

llvm/test/CodeGen/PowerPC/GlobalISel/load-store-32bit.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -global-isel -o - \
+; RUN:   -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs < %s | FileCheck %s
+
+define signext i32 @load_signext_i32(ptr %ptr) {
+; CHECK-LABEL: load_signext_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lwa r3, 0(r3)
+; CHECK-NEXT:    blr
+entry:
+  %ret = load i32, ptr %ptr, align 4
+  ret i32 %ret
+}
+
+define zeroext i32 @load_zeroext_i32(ptr %ptr) {
+; CHECK-LABEL: load_zeroext_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lwz r3, 0(r3)
+; CHECK-NEXT:    blr
+entry:
+  %ret = load i32, ptr %ptr, align 4
+  ret i32 %ret
+}
+
+define float @load_float(ptr %ptr) {
+; CHECK-LABEL: load_float:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lfs f1, 0(r3)
+; CHECK-NEXT:    blr
+entry:
+  %ret = load float, ptr %ptr, align 4
+  ret float %ret
+}
+
+define void @store_i32(ptr %p) {
+; CHECK-LABEL: store_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    li r4, 100
+; CHECK-NEXT:    stw r4, 0(r3)
+; CHECK-NEXT:    blr
+entry:
+  store i32 100, ptr %p, align 4
+  ret void
+}
+
+define void @store_float(ptr %ptr, float %a) {
+; CHECK-LABEL: store_float:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    stfs f1, 0(r3)
+; CHECK-NEXT:    blr
+entry:
+  store float %a, ptr %ptr, align 4
+  ret void
+}