[PowerPC][GISel]select floating point constant from TOC

[shchenz]

Summary

Handle G_FCONSTANT node for PowerPC target.

[arsenm]

If I'm reading this correctly, the DAG handles this by letting the ConstantFP lower to a generic load with a constant pool PseudoSourceValue. I think that would be a better approach, rather than directly selecting G_FCONSTANT. You would avoid needing special 64-bit and 32-bit handling

llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp

650

Return false to fallback is probably a better idea

692

Don't need &*

720

Ditto

[shchenz]

If I'm reading this correctly, the DAG handles this by letting the ConstantFP lower to a generic load with a constant pool PseudoSourceValue. I think that would be a better approach, rather than directly selecting G_FCONSTANT. You would avoid needing special 64-bit and 32-bit handling

Make sense. I updated the patch to generate a generic load while selecting ConstantFP, so that we can handle the load type inside the selection for G_LOAD. We still have to directly select the address for global variables, DAG handles this in both PPCISelDAGTODAG.cpp and td file.

One improvement implemented in DAG and directly selecting, but missing in the new method, we can further improve our code generation for medium code model in further patch:

addi 3, 3, .LCPI0_0@toc@l
lfs 1, 0(3)

->

lfs 1, .LCPI0_0@toc@l(3)

[shchenz]

use generic load node

[shchenz]

llvm/test/CodeGen/PowerPC/GlobalISel/fconstant.ll

22

This can be improved to lfs 1, .LCPI0_0@toc@l(3). DAG adds a peephole to handle this.

[shchenz]

remove the assertion

[shchenz]

rebase

[arsenm]

llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp

301–305

This should have been done in the legalizer, not the selector

[shchenz]

llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp

301–305

I am not quite sure I understand your suggestion here. Do you mean we set action for G_FCONSTANT as custom for S32 and S64 in PPCLegalizerInfo? For my understanding, legalizer should do legalization for the types that are illegal for some opcodes on a certain target, right? float and double are both valid types on PPC. So not sure why we need to legalize them or do I misunderstand your comment? Thank you!

[amyk]

llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp

259

Minor wording suggestion.

261

Minor wording suggestion.

277

Since the large and medium code models looks like they differ from just the opcode, does it make sense to do something like this?

unsigned Opcode = 0;
if (CModel == CodeModel::Large)
  // For large code model, generate LDtocL(CPI, ADDIStocHA8(X2, CPI))
  Opcode = PPC::LDtocL;
else
  // For medium code model, generate ADDItocL(CPI, ADDIStocHA8(X2, CPI))
  Opcode = PPC::ADDItocL;

Register HaAddrReg =
        MRI.createVirtualRegister(&PPC::G8RC_and_G8RC_NOX0RegClass);
BuildMI(*I.getParent(), I, DbgLoc, TII.get(PPC::ADDIStocHA8), HaAddrReg)
        .addReg(PPC::X2)
        .addConstantPoolIndex(CPI);

BuildMI(*I.getParent(), I, DbgLoc, TII.get(Opcode), AddrReg)
          .addConstantPoolIndex(CPI)
          .addReg(HaAddrReg);

[arsenm]

llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp

301–305

Essentially yes, but not quite like that. I think the default lower action for G_CONSTANT/G_FCONSTANT should look like what the DAG does, which produces a constant pool load. You will need to introduce a new generic G_CONSTANT_POOL instruction.

So you would set your action to lower and implement this in the generic LegalizerHelper. Even if float and double are "legal types", the fact that you are replacing these with load indicates constants are not legal.

[shchenz]

address comments from @arsenm and @amyk

llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp

277

Thanks, the operands order for PPC::LDtocL and PPC::ADDItocL is different and the operands number are also different. Indirect access PPC::LDtocL would have a memory operand.

[arsenm]

Can you also add a test in test/MachineVerifier/test_g_constant_pool.mir with the constraints of the instruction

llvm/docs/GlobalISel/GenericOpcode.rst

72

Just G_CONSTANT_POOL?

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

2641

This certainly isn't the alloca addrspace. getDefaultGlobalsAddressSpace maybe?

[shchenz]

address @arsenm comments

[shchenz]

Thanks for review @arsenm , updated accordingly.

llvm/docs/GlobalISel/GenericOpcode.rst

72

I use G_CONSTANT_POOL_INDEX instead of G_CONSTANT_POOL is because of the name used in lib/CodeGen/GlobalISel/MachineIRBuilder.cpp. According to the name convention there, MachineIRBuilder::buildConstantPool() is a little confused to me. If you insist, I can change this to G_CONSTANT_POOL.

[arsenm]

llvm/docs/GlobalISel/GenericOpcode.rst

72

I don't follow what you mean about the convention. The index is just what the source happens to be. This returns a constant pool. It's also called ConstantPool in the dag, so this should be G_CONSTANT_POOL

[shchenz]

rebase and rename G_CONSTANT_POOL_INDEX

[arsenm]

LGTM, thanks. Some test nits

llvm/test/CodeGen/PowerPC/GlobalISel/fconstant-unsupported.ll

2

This doesn't require asserts

4

I prefer -global-isel as the first llc argument

7

Drop -verify-machineinstrs, you only want the legalization error anyway

13

Don't hardcode the register number

[nemanjai]

llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp

670

Is this really the alignment we want? Seems like we should use whatever the ABI alignment is for the type.

678

I understand that this is always PPC::X2 for ELFv2, but can we use getTOCPointerRegister() instead?

llvm/lib/Target/PowerPC/GISel/PPCLegalizerInfo.cpp

57

In SDAG, we have the capability to mark specific FP constants legal. Does a similar capability exist with GISel? Not using constant pool loads for constants such as 0.0 is quite important.
Perhaps a TODO is in order here?

llvm/test/CodeGen/PowerPC/GlobalISel/fconstant-unsupported.ll

2

Hmm, is it that producing FP constants using GISel is not supported or that GISel is not supported at all for BE and 32-bit? I imagine it is the latter.

[arsenm]

llvm/lib/Target/PowerPC/GISel/PPCLegalizerInfo.cpp

57

It's not implemented. You could custom lower it, or use the immediate legal hook in the default lower implementation

[shchenz]

address comments from @arsenm and @nemanjai

llvm/lib/Target/PowerPC/GISel/PPCLegalizerInfo.cpp

57

Yes, GISel has the ability to mark specific FP constants legal/custom/lower at same opcode in the legalizerinfo classs.

llvm/test/CodeGen/PowerPC/GlobalISel/fconstant-unsupported.ll

2

Yes, GISel is not supported at all for BE for now. GISel supports 32 bit, but PPC does not support 32 bit GISel for now.

[nemanjai]

llvm/test/CodeGen/PowerPC/GlobalISel/fconstant-unsupported.ll

2

Right. But I would expect that we simply reject an attempt to use GISel for ppc32 rather than trying to turn it on and possibly selecting an incorrect instruction. Namely, treat it the same as big endian targets are treated.

[shchenz]

llvm/test/CodeGen/PowerPC/GlobalISel/fconstant-unsupported.ll

2

OK. Got your point. At the beginning of GISel, IRTranslator pass, the big endian case triggers an error.
For ppc32, maybe a virtual function isGlobalISelEnabled() is needed in class LLVMTargetMachine and an override version is needed in class PPCTargetMachine and only isELFv2ABI() returns true for now in the PPC's implementation? If so, I can add another patch to do this.

[amyk]

llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp

650

nit: constant pool

687

nit: We can omit the { } since we have one assignment inside.

llvm/test/MachineVerifier/test_g_constant_pool.mir

2

Nit: Spacing before RUN and this line may be too long.

3

A question I had was, do we need a PPC version of this test?

[arsenm]

llvm/test/MachineVerifier/test_g_constant_pool.mir

3

No, this could be any target . This one is simple enough that it might be able to get away with the default target

[shchenz]

address comments from @amyk

llvm/docs/GlobalISel/GenericOpcode.rst

 ^^^^^^^^^^^^
 
 The address of a basic block.
 
 .. code-block:: none
 
   %0:_(p0) = G_BLOCK_ADDR blockaddress(@test_blockaddress, %ir-block.block)
 
+G_CONSTANT_POOL
+^^^^^^^^^^^^^^^
+
+The address of an object in the constant pool.
+
+.. code-block:: none
+
+  %0:_(p0) = G_CONSTANT_POOL %const.0
+
 Integer Extension and Truncation
 --------------------------------
 
 G_ANYEXT
 ^^^^^^^^
 
 Extend the underlying scalar type of an operation, leaving the high bits
 unspecified.

llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h

public:
   /// Perform Bitcast legalize action on G_EXTRACT_VECTOR_ELT.
   LegalizeResult bitcastExtractVectorElt(MachineInstr &MI, unsigned TypeIdx,
                                          LLT CastTy);
 
   /// Perform Bitcast legalize action on G_INSERT_VECTOR_ELT.
   LegalizeResult bitcastInsertVectorElt(MachineInstr &MI, unsigned TypeIdx,
                                         LLT CastTy);
 
+  LegalizeResult lowerFConstant(MachineInstr &MI);
   LegalizeResult lowerBitcast(MachineInstr &MI);
   LegalizeResult lowerLoad(GAnyLoad &MI);
   LegalizeResult lowerStore(GStore &MI);
   LegalizeResult lowerBitCount(MachineInstr &MI);
   LegalizeResult lowerFunnelShiftWithInverse(MachineInstr &MI);
   LegalizeResult lowerFunnelShiftAsShifts(MachineInstr &MI);
   LegalizeResult lowerFunnelShift(MachineInstr &MI);
   LegalizeResult lowerRotateWithReverseRotate(MachineInstr &MI);

llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h

public:
   ///
   /// \pre setBasicBlock or setMI must have been called.
   /// \pre \p Res must be a generic virtual register with pointer type
   ///      in the same address space as \p GV.
   ///
   /// \return a MachineInstrBuilder for the newly created instruction.
   MachineInstrBuilder buildGlobalValue(const DstOp &Res, const GlobalValue *GV);
 
+  /// Build and insert \p Res = G_CONSTANT_POOL \p Idx
+  ///
+  /// G_CONSTANT_POOL materializes the address of an object in the constant
+  /// pool.
+  ///
+  /// \pre setBasicBlock or setMI must have been called.
+  /// \pre \p Res must be a generic virtual register with pointer type.
+  ///
+  /// \return a MachineInstrBuilder for the newly created instruction.
+  MachineInstrBuilder buildConstantPool(const DstOp &Res, unsigned Idx);
+
   /// Build and insert \p Res = G_PTR_ADD \p Op0, \p Op1
   ///
   /// G_PTR_ADD adds \p Op1 addressible units to the pointer specified by \p Op0,
   /// storing the resulting pointer in \p Res. Addressible units are typically
   /// bytes but this can vary between targets.
   ///
   /// \pre setBasicBlock or setMI must have been called.
   /// \pre \p Res and \p Op0 must be generic virtual registers with pointer

llvm/include/llvm/Support/TargetOpcodes.def

 
 /// Generic instruction to materialize the address of an alloca or other
 /// stack-based object.
 HANDLE_TARGET_OPCODE(G_FRAME_INDEX)
 
 /// Generic reference to global value.
 HANDLE_TARGET_OPCODE(G_GLOBAL_VALUE)
 
+/// Generic instruction to materialize the address of an object in the constant
+/// pool.
+HANDLE_TARGET_OPCODE(G_CONSTANT_POOL)
+
 /// Generic instruction to extract blocks of bits from the register given
 /// (typically a sub-register COPY after instruction selection).
 HANDLE_TARGET_OPCODE(G_EXTRACT)
 
 HANDLE_TARGET_OPCODE(G_UNMERGE_VALUES)
 
 /// Generic instruction to insert blocks of bits from the registers given into
 /// the source.

llvm/include/llvm/Target/GenericOpcodes.td

 }
 
 def G_GLOBAL_VALUE : GenericInstruction {
   let OutOperandList = (outs type0:$dst);
   let InOperandList = (ins unknown:$src);
   let hasSideEffects = false;
 }
 
+def G_CONSTANT_POOL : GenericInstruction {
+  let OutOperandList = (outs type0:$dst);
+  let InOperandList = (ins unknown:$src);
+  let hasSideEffects = false;
+}
+
 def G_INTTOPTR : GenericInstruction {
   let OutOperandList = (outs type0:$dst);
   let InOperandList = (ins type1:$src);
   let hasSideEffects = false;
 }
 
 def G_PTRTOINT : GenericInstruction {
   let OutOperandList = (outs type0:$dst);

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
 #include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h"
 #include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
 #include "llvm/CodeGen/GlobalISel/LostDebugLocObserver.h"
 #include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
 #include "llvm/CodeGen/GlobalISel/Utils.h"
+#include "llvm/CodeGen/MachineConstantPool.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/TargetFrameLowering.h"
 #include "llvm/CodeGen/TargetInstrInfo.h"
 #include "llvm/CodeGen/TargetLowering.h"
 #include "llvm/CodeGen/TargetOpcodes.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/IR/Instructions.h"

 static void getUnmergePieces(SmallVectorImpl<Register> &Pieces,
                              MachineIRBuilder &B, Register Src, LLT Ty) {
   auto Unmerge = B.buildUnmerge(Ty, Src);
   for (int I = 0, E = Unmerge->getNumOperands() - 1; I != E; ++I)
     Pieces.push_back(Unmerge.getReg(I));
 }
 
 LegalizerHelper::LegalizeResult
+LegalizerHelper::lowerFConstant(MachineInstr &MI) {
+  Register Dst = MI.getOperand(0).getReg();
+
+  MachineFunction &MF = MIRBuilder.getMF();
+  const DataLayout &DL = MIRBuilder.getDataLayout();
+
+  unsigned AddrSpace = DL.getDefaultGlobalsAddressSpace();
+  LLT AddrPtrTy = LLT::pointer(AddrSpace, DL.getPointerSizeInBits(AddrSpace));
+  Align Alignment = Align(DL.getABITypeAlign(
+      getFloatTypeForLLT(MF.getFunction().getContext(), MRI.getType(Dst))));
+
+  auto Addr = MIRBuilder.buildConstantPool(
+      AddrPtrTy, MF.getConstantPool()->getConstantPoolIndex(
+                     MI.getOperand(1).getFPImm(), Alignment));
+
+  MachineMemOperand *MMO = MF.getMachineMemOperand(
+      MachinePointerInfo::getConstantPool(MF), MachineMemOperand::MOLoad,
+      MRI.getType(Dst), Alignment);
+
+  MIRBuilder.buildLoadInstr(TargetOpcode::G_LOAD, Dst, Addr, *MMO);
+  MI.eraseFromParent();
+
+  return Legalized;
+}
+
+LegalizerHelper::LegalizeResult
 LegalizerHelper::lowerBitcast(MachineInstr &MI) {
   Register Dst = MI.getOperand(0).getReg();
   Register Src = MI.getOperand(1).getReg();
   LLT DstTy = MRI.getType(Dst);
   LLT SrcTy = MRI.getType(Src);
 
   if (SrcTy.isVector()) {
     LLT SrcEltTy = SrcTy.getElementType();

 
 LegalizerHelper::LegalizeResult
 LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT LowerHintTy) {
   using namespace TargetOpcode;
 
   switch(MI.getOpcode()) {
   default:
     return UnableToLegalize;
+  case TargetOpcode::G_FCONSTANT:
+    return lowerFConstant(MI);
   case TargetOpcode::G_BITCAST:
     return lowerBitcast(MI);
   case TargetOpcode::G_SREM:
   case TargetOpcode::G_UREM: {
     LLT Ty = MRI.getType(MI.getOperand(0).getReg());
     auto Quot =
         MIRBuilder.buildInstr(MI.getOpcode() == G_SREM ? G_SDIV : G_UDIV, {Ty},
                               {MI.getOperand(1), MI.getOperand(2)});

llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp

assert(Res.getLLTTy(*getMRI()).getAddressSpace() ==
          "address space mismatch");
 
   auto MIB = buildInstr(TargetOpcode::G_GLOBAL_VALUE);
   Res.addDefToMIB(*getMRI(), MIB);
   MIB.addGlobalAddress(GV);
   return MIB;
 }
 
+MachineInstrBuilder MachineIRBuilder::buildConstantPool(const DstOp &Res,
+                                                        unsigned Idx) {
+  assert(Res.getLLTTy(*getMRI()).isPointer() && "invalid operand type");
+  auto MIB = buildInstr(TargetOpcode::G_CONSTANT_POOL);
+  Res.addDefToMIB(*getMRI(), MIB);
+  MIB.addConstantPoolIndex(Idx);
+  return MIB;
+}
+
 MachineInstrBuilder MachineIRBuilder::buildJumpTable(const LLT PtrTy,
                                                      unsigned JTI) {
   return buildInstr(TargetOpcode::G_JUMP_TABLE, {PtrTy}, {})
       .addJumpTableIndex(JTI);
 }
 
 void MachineIRBuilder::validateUnaryOp(const LLT Res, const LLT Op0) {
   assert((Res.isScalar() || Res.isVector()) && "invalid operand type");

llvm/lib/CodeGen/MachineVerifier.cpp

case TargetOpcode::G_IS_FPCLASS: {
     }
     break;
   }
   case TargetOpcode::G_ASSERT_ALIGN: {
     if (MI->getOperand(2).getImm() < 1)
       report("alignment immediate must be >= 1", MI);
     break;
   }
+  case TargetOpcode::G_CONSTANT_POOL: {
+    if (!MI->getOperand(1).isCPI())
+      report("Src operand 1 must be a constant pool index", MI);
+    if (!MRI->getType(MI->getOperand(0).getReg()).isPointer())
+      report("Dst operand 0 must be a pointer", MI);
+    break;
+  }
   default:
     break;
   }
 }
 
 void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
   const MCInstrDesc &MCID = MI->getDesc();
   if (MI->getNumOperands() < MCID.getNumOperands()) {

llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp

 //===- PPCInstructionSelector.cpp --------------------------------*- C++ -*-==//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 /// \file
 /// This file implements the targeting of the InstructionSelector class for
 /// PowerPC.
 //===----------------------------------------------------------------------===//
 
 #include "PPC.h"
 #include "PPCInstrInfo.h"
+#include "PPCMachineFunctionInfo.h"
 #include "PPCRegisterBankInfo.h"
 #include "PPCSubtarget.h"
 #include "PPCTargetMachine.h"
 #include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
 #include "llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h"
 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
 #include "llvm/CodeGen/MachineConstantPool.h"
private:
 
   bool selectFPToInt(MachineInstr &I, MachineBasicBlock &MBB,
                   MachineRegisterInfo &MRI) const;
   bool selectIntToFP(MachineInstr &I, MachineBasicBlock &MBB,
                   MachineRegisterInfo &MRI) const;
 
   bool selectZExt(MachineInstr &I, MachineBasicBlock &MBB,
                   MachineRegisterInfo &MRI) const;
+  bool selectConstantPool(MachineInstr &I, MachineBasicBlock &MBB,
+                          MachineRegisterInfo &MRI) const;
 
   std::optional<bool> selectI64ImmDirect(MachineInstr &I,
                                          MachineBasicBlock &MBB,
                                          MachineRegisterInfo &MRI, Register Reg,
                                          uint64_t Imm) const;
   bool selectI64Imm(MachineInstr &I, MachineBasicBlock &MBB,
                     MachineRegisterInfo &MRI) const;
 
+  const PPCTargetMachine &TM;
   const PPCSubtarget &STI;
   const PPCInstrInfo &TII;
   const PPCRegisterInfo &TRI;
   const PPCRegisterBankInfo &RBI;
 
 #define GET_GLOBALISEL_PREDICATES_DECL
 #include "PPCGenGlobalISel.inc"
 #undef GET_GLOBALISEL_PREDICATES_DECL
 
 #define GET_GLOBALISEL_TEMPORARIES_DECL
 #include "PPCGenGlobalISel.inc"
 #undef GET_GLOBALISEL_TEMPORARIES_DECL
 };
 
 } // end anonymous namespace
 
 #define GET_GLOBALISEL_IMPL
 #include "PPCGenGlobalISel.inc"
 #undef GET_GLOBALISEL_IMPL
 
 PPCInstructionSelector::PPCInstructionSelector(const PPCTargetMachine &TM,
                                                const PPCSubtarget &STI,
                                                const PPCRegisterBankInfo &RBI)
-    : STI(STI), TII(*STI.getInstrInfo()), TRI(*STI.getRegisterInfo()), RBI(RBI),
+    : TM(TM), STI(STI), TII(*STI.getInstrInfo()), TRI(*STI.getRegisterInfo()),
+      RBI(RBI),
 #define GET_GLOBALISEL_PREDICATES_INIT
 #include "PPCGenGlobalISel.inc"
 #undef GET_GLOBALISEL_PREDICATES_INIT
 #define GET_GLOBALISEL_TEMPORARIES_INIT
 #include "PPCGenGlobalISel.inc"
 #undef GET_GLOBALISEL_TEMPORARIES_INIT
 {
 }
BuildMI(MBB, I, I.getDebugLoc(), TII.get(TargetOpcode::IMPLICIT_DEF),
           ImpDefReg);
 
   Register NewDefReg =
       MRI.createVirtualRegister(getRegClass(DstTy, DstRegBank));
   BuildMI(MBB, I, I.getDebugLoc(), TII.get(TargetOpcode::INSERT_SUBREG),
           NewDefReg)
       .addReg(ImpDefReg)
       .addReg(SrcReg)
       .addImm(PPC::sub_32);
 
   MachineInstr *MI =
       BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::RLDICL), DstReg)
           .addReg(NewDefReg)
           .addImm(0)
           .addImm(32);
 
   I.eraseFromParent();
   return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
 }
 
 // For any 32 < Num < 64, check if the Imm contains at least Num consecutive
 // zeros and return the number of bits by the left of these consecutive zeros.
 static uint32_t findContiguousZerosAtLeast(uint64_t Imm, unsigned Num) {
   uint32_t HiTZ = llvm::countr_zero<uint32_t>(Hi_32(Imm));
   uint32_t LoLZ = llvm::countl_zero<uint32_t>(Lo_32(Imm));
   if ((HiTZ + LoLZ) >= Num)
     return (32 + HiTZ);
   return 0;
 }
 
 // Direct materialization of 64-bit constants by enumerated patterns.
 // Similar to PPCISelDAGToDAG::selectI64ImmDirect().
 std::optional<bool> PPCInstructionSelector::selectI64ImmDirect(MachineInstr &I,
                                                 MachineBasicBlock &MBB,
                                                 MachineRegisterInfo &MRI,
                                                 Register Reg,
                                                 uint64_t Imm) const {
   unsigned TZ = llvm::countr_zero<uint64_t>(Imm);
   unsigned LZ = llvm::countl_zero<uint64_t>(Imm);
   unsigned TO = llvm::countr_one<uint64_t>(Imm);
   unsigned LO = llvm::countl_one<uint64_t>(Imm);
   uint32_t Hi32 = Hi_32(Imm);
   uint32_t Lo32 = Lo_32(Imm);
   uint32_t Shift = 0;
 
   // Following patterns use 1 instructions to materialize the Imm.
 
   // 1-1) Patterns : {zeros}{15-bit valve}
   //                 {ones}{15-bit valve}
   if (isInt<16>(Imm))
     return BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::LI8), Reg)
         .addImm(Imm)
         .constrainAllUses(TII, TRI, RBI);
   // 1-2) Patterns : {zeros}{15-bit valve}{16 zeros}
   //                 {ones}{15-bit valve}{16 zeros}
   if (TZ > 15 && (LZ > 32 || LO > 32))
     return BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::LIS8), Reg)
         .addImm((Imm >> 16) & 0xffff)
         .constrainAllUses(TII, TRI, RBI);
 
   // Following patterns use 2 instructions to materialize the Imm.
 
   assert(LZ < 64 && "Unexpected leading zeros here.");
if (!BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::ORI8), DstReg)
              .addImm(Lo16)
              .constrainAllUses(TII, TRI, RBI))
       return false;
   }
   I.eraseFromParent();
   return true;
 }
 
+bool PPCInstructionSelector::selectConstantPool(
+    MachineInstr &I, MachineBasicBlock &MBB, MachineRegisterInfo &MRI) const {
+  const DebugLoc &DbgLoc = I.getDebugLoc();
+  MachineFunction *MF = MBB.getParent();
+
+  // TODO: handle 32-bit.
+  // TODO: Enabling floating point constant pool selection on AIX requires
+  // global isel on big endian target enabled first.
+  // See CallLowering::enableBigEndian().
+  if (!STI.isPPC64() || !STI.isLittleEndian())
+    return false;
+
+  MF->getInfo<PPCFunctionInfo>()->setUsesTOCBasePtr();
+
+  const Register DstReg = I.getOperand(0).getReg();
+  unsigned CPI = I.getOperand(1).getIndex();
+
+  // Address stored in the TOC entry. This is related to code model and the ABI
+  // we are currently using. For now we only handle 64-bit Linux LE. PowerPC
+  // only supports small, medium and large code model.
+  const CodeModel::Model CModel = TM.getCodeModel();
+  assert(!(CModel == CodeModel::Tiny || CModel == CodeModel::Kernel) &&
+         "PowerPC doesn't support tiny or kernel code models.");
+
+  const MCRegister TOCReg = STI.getTOCPointerRegister();
+  MachineMemOperand *MMO = MF->getMachineMemOperand(
+      MachinePointerInfo::getGOT(*MF), MachineMemOperand::MOLoad,
+      MRI.getType(DstReg), MF->getDataLayout().getPointerABIAlignment(0));
+
+  MachineInstr *MI = nullptr;
+  // For now we only handle 64-bit Linux.
+  if (CModel == CodeModel::Small) {
+    // For small code model, generate LDtocCPT(CPI, X2).
+    MI = BuildMI(MBB, I, DbgLoc, TII.get(PPC::LDtocCPT), DstReg)
+             .addConstantPoolIndex(CPI)
+             .addReg(TOCReg)
+             .addMemOperand(MMO);
+  } else {
+    Register HaAddrReg = MRI.createVirtualRegister(&PPC::G8RCRegClass);
+    BuildMI(MBB, I, DbgLoc, TII.get(PPC::ADDIStocHA8), HaAddrReg)
+        .addReg(TOCReg)
+        .addConstantPoolIndex(CPI);
+
+    if (CModel == CodeModel::Large)
+      // For large code model, generate LDtocL(CPI, ADDIStocHA8(X2, CPI))
+      MI = BuildMI(MBB, I, DbgLoc, TII.get(PPC::LDtocL), DstReg)
+               .addConstantPoolIndex(CPI)
+               .addReg(HaAddrReg)
+               .addMemOperand(MMO);
+    else
+      // For medium code model, generate ADDItocL(CPI, ADDIStocHA8(X2, CPI))
+      MI = BuildMI(MBB, I, DbgLoc, TII.get(PPC::ADDItocL), DstReg)
+               .addReg(HaAddrReg)
+               .addConstantPoolIndex(CPI);
+  }
+
+  I.eraseFromParent();
+  return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
+}
+
 bool PPCInstructionSelector::select(MachineInstr &I) {
   auto &MBB = *I.getParent();
   auto &MF = *MBB.getParent();
   auto &MRI = MF.getRegInfo();
 
   if (!isPreISelGenericOpcode(I.getOpcode())) {
     if (I.isCopy())
       return selectCopy(I, TII, MRI, TRI, RBI);
 
     return true;
   }
 
   if (selectImpl(I, *CoverageInfo))
     return true;
 
   unsigned Opcode = I.getOpcode();
 
   switch (Opcode) {
   default:
     return false;
   case TargetOpcode::G_LOAD:
   case TargetOpcode::G_STORE: {
     GLoadStore &LdSt = cast<GLoadStore>(I);
     LLT PtrTy = MRI.getType(LdSt.getPointerReg());
 
bool PPCInstructionSelector::select(MachineInstr &I) {
   case TargetOpcode::G_FPTOSI:
   case TargetOpcode::G_FPTOUI:
     return selectFPToInt(I, MBB, MRI);
   // G_SEXT will be selected in tb-gen pattern.
   case TargetOpcode::G_ZEXT:
     return selectZExt(I, MBB, MRI);
   case TargetOpcode::G_CONSTANT:
     return selectI64Imm(I, MBB, MRI);
+  case TargetOpcode::G_CONSTANT_POOL:
+    return selectConstantPool(I, MBB, MRI);
   }
   return false;
 }
 
 namespace llvm {
 InstructionSelector *
 createPPCInstructionSelector(const PPCTargetMachine &TM,
                              const PPCSubtarget &Subtarget,
                              const PPCRegisterBankInfo &RBI) {
   return new PPCInstructionSelector(TM, Subtarget, RBI);
 }
 } // end namespace llvm

llvm/lib/Target/PowerPC/GISel/PPCLegalizerInfo.cpp

getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI})
       .legalForCartesianProduct({S64}, {S32, S64});
 
   getActionDefinitionsBuilder({G_SITOFP, G_UITOFP})
       .legalForCartesianProduct({S32, S64}, {S64});
 
   getActionDefinitionsBuilder({G_LOAD, G_STORE})
       .legalForTypesWithMemDesc({{S64, P0, S64, 8}, {S32, P0, S32, 4}});
 
+  getActionDefinitionsBuilder(G_FCONSTANT).lowerFor({S32, S64});
+  getActionDefinitionsBuilder(G_CONSTANT_POOL).legalFor({P0});
+
   getLegacyLegalizerInfo().computeTables();
 }

llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp

OperandsMapping = getOperandsMapping(
         {getValueMapping(PMI_CR), nullptr,
          getValueMapping(CmpSize == 32 ? PMI_FPR32 : PMI_FPR64),
          getValueMapping(CmpSize == 32 ? PMI_FPR32 : PMI_FPR64)});
     break;
   }
   case TargetOpcode::G_CONSTANT:
     OperandsMapping = getOperandsMapping({getValueMapping(PMI_GPR64), nullptr});
     break;
+  case TargetOpcode::G_CONSTANT_POOL:
+    OperandsMapping = getOperandsMapping({getValueMapping(PMI_GPR64), nullptr});
+    break;
   case TargetOpcode::G_FPTOUI:
   case TargetOpcode::G_FPTOSI: {
     Register SrcReg = MI.getOperand(1).getReg();
     unsigned Size = getSizeInBits(SrcReg, MRI, TRI);
 
     OperandsMapping = getOperandsMapping(
         {getValueMapping(PMI_GPR64),
          getValueMapping(Size == 32 ? PMI_FPR32 : PMI_FPR64)});

llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir

 # DEBUG-NEXT: G_FRAME_INDEX (opcode {{[0-9]+}}): 1 type index, 0 imm indices
 # DEBUG-NEXT: .. the first uncovered type index: 1, OK
 # DEBUG-NEXT: .. the first uncovered imm index: 0, OK
 #
 # DEBUG-NEXT: G_GLOBAL_VALUE (opcode {{[0-9]+}}): 1 type index, 0 imm indices
 # DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
 # DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
 #
+# DEBUG-NEXT: G_CONSTANT_POOL (opcode {{[0-9]+}}): 1 type index, 0 imm indices
+# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
+# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
+#
 # DEBUG-NEXT: G_EXTRACT (opcode {{[0-9]+}}): 2 type indices, 1 imm index
 # DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
 # DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
 #
 # DEBUG-NEXT: G_UNMERGE_VALUES (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
 # DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
 # DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
 #

llvm/test/CodeGen/PowerPC/GlobalISel/fconstant-unsupported.ll

+; RUN: not --crash llc -global-isel -mtriple=powerpc-unknown-linux-gnu \
+; RUN:   -o - < %s 2>&1 | FileCheck %s --check-prefix=BE
+; RUN: not --crash llc -global-isel -mtriple=powerpcle-unknown-linux-gnu \
+; RUN:   -o - < %s 2>&1 | FileCheck %s --check-prefix=BIT32
+
+; BE: LLVM ERROR: unable to translate in big endian mode
+
+; BIT32: LLVM ERROR: unable to legalize instruction: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD{{.*}}load (s64) from constant-pool
+
+define double @foo() {
+  entry:
+    ret double 1.000000e+00
+}

llvm/test/CodeGen/PowerPC/GlobalISel/fconstant.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -global-isel -code-model=small \
+; RUN:   -verify-machineinstrs -o - < %s | FileCheck %s --check-prefix=SMALL
+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -global-isel -code-model=medium \
+; RUN:   -verify-machineinstrs -o - < %s | FileCheck %s --check-prefix=MEDIUM
+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -global-isel -code-model=large \
+; RUN:   -verify-machineinstrs -o - < %s | FileCheck %s --check-prefix=LARGE
+
+define float @foo_float() {
+; SMALL-LABEL: foo_float:
+; SMALL:       # %bb.0: # %entry
+; SMALL-NEXT:    ld 3, .LC0@toc(2)
+; SMALL-NEXT:    lfs 1, 0(3)
+; SMALL-NEXT:    blr
+;
+; MEDIUM-LABEL: foo_float:
+; MEDIUM:       # %bb.0: # %entry
+; MEDIUM-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
+; MEDIUM-NEXT:    addi 3, 3, .LCPI0_0@toc@l
+; MEDIUM-NEXT:    lfs 1, 0(3)
+; MEDIUM-NEXT:    blr
+;
+; LARGE-LABEL: foo_float:
+; LARGE:       # %bb.0: # %entry
+; LARGE-NEXT:    addis 3, 2, .LC0@toc@ha
+; LARGE-NEXT:    ld 3, .LC0@toc@l(3)
+; LARGE-NEXT:    lfs 1, 0(3)
+; LARGE-NEXT:    blr
+entry:
+  ret float 1.000000e+00
+}
+
+define double @foo_double() {
+; SMALL-LABEL: foo_double:
+; SMALL:       # %bb.0: # %entry
+; SMALL-NEXT:    ld 3, .LC1@toc(2)
+; SMALL-NEXT:    lfd 1, 0(3)
+; SMALL-NEXT:    blr
+;
+; MEDIUM-LABEL: foo_double:
+; MEDIUM:       # %bb.0: # %entry
+; MEDIUM-NEXT:    addis 3, 2, .LCPI1_0@toc@ha
+; MEDIUM-NEXT:    addi 3, 3, .LCPI1_0@toc@l
+; MEDIUM-NEXT:    lfd 1, 0(3)
+; MEDIUM-NEXT:    blr
+;
+; LARGE-LABEL: foo_double:
+; LARGE:       # %bb.0: # %entry
+; LARGE-NEXT:    addis 3, 2, .LC1@toc@ha
+; LARGE-NEXT:    ld 3, .LC1@toc@l(3)
+; LARGE-NEXT:    lfd 1, 0(3)
+; LARGE-NEXT:    blr
+entry:
+  ret double 1.000000e+00
+}

llvm/test/MachineVerifier/test_g_constant_pool.mir

+# RUN: not --crash llc -o - -march=arm64 -global-isel -run-pass=none \
+# RUN:   -verify-machineinstrs %s 2>&1 | FileCheck %s
+# REQUIRES: aarch64-registered-target
+
+---
+name:            test_constant_pool
+constants:
+  - id:          0
+    value:       'double 3.250000e+00'
+stack:
+  - { id: 0, size: 64, alignment: 8 }
+legalized:       true
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+liveins:
+body:             |
+  bb.0:
+
+    ; CHECK: Bad machine code: Too few operands
+    %0:_(p0) = G_CONSTANT_POOL
+
+    ; CHECK: Bad machine code: Src operand 1 must be a constant pool index
+    %1:_(p0) = G_CONSTANT_POOL 1
+
+    ; CHECK: Bad machine code: Src operand 1 must be a constant pool index
+    %2:_(p0) = G_CONSTANT_POOL i32 1
+
+    ; CHECK: Bad machine code: Src operand 1 must be a constant pool index
+    %3:_(p0) = G_CONSTANT_POOL %stack.0
+
+    ; CHECK: Dst operand 0 must be a pointer
+    %4:_(s32) = G_CONSTANT_POOL %const.0
+
+    ; CHECK: Dst operand 0 must be a pointer
+    %5:_(s64) = G_CONSTANT_POOL %const.0
+
+    ; CHECK-NOT: %6
+    %6:_(p0) = G_CONSTANT_POOL %const.0
+...