[Metadata] Introduce MD_pcsections

[melver]

Summary

Introduces MD_pcsections metadata kind. See added documentation for
more details.

Subsequent patches enable propagating PC sections metadata through code
generation to the AsmPrinter.

RFC: https://discourse.llvm.org/t/rfc-pc-keyed-metadata-at-runtime/64191

[melver]

Associated RFC of this series: https://discourse.llvm.org/t/rfc-pc-keyed-metadata-at-runtime/64191

[dvyukov]

llvm/docs/PCSectionsMetadata.rst

36–37

There seems to be something with wording:
"backend to emit the PC ... to be emitted to all named sections"
"backend to emit the PC ... to all named sections"?

[melver]

Fix typos.

[MaskRay]

This introduces new LangRef constructs. I suggest that you enlarge the reviewer list.

In D130875#3690485, @melver wrote:

Associated RFC of this series: https://discourse.llvm.org/t/rfc-pc-keyed-metadata-at-runtime/64191

This link can be amended into the summary (commit message).

[MaskRay]

llvm/test/CodeGen/AArch64/pcsections.ll

2

One RUN line for the default code model suffices. There is no codegen optimization difference.

A patch should not introduce disabled tests this way. If a dependent patch introduces the functionality, the test should be added to that patch.

[MaskRay]

llvm/docs/PCSectionsMetadata.rst

28

IIRC metadata is a legacy syntax (llvm 3.5 time). New syntax doesn't use metadata. The doc here should use the new syntax.

[melver]

In D130875#3695416, @MaskRay wrote:

This introduces new LangRef constructs. I suggest that you enlarge the reviewer list.

In D130875#3690485, @melver wrote:

Associated RFC of this series: https://discourse.llvm.org/t/rfc-pc-keyed-metadata-at-runtime/64191

This link can be amended into the summary (commit message).

I thought to wait for some comments on the RFC.
I'll add more reviewers after reshuffling the series.

[melver]

llvm/test/CodeGen/AArch64/pcsections.ll

2

I don't understand. Removing any one line here will reduce coverage.

We have RUNs for each -O0 to -O3 with the default code model, and then only O1 with a large code model.

[melver]

llvm/test/CodeGen/AArch64/pcsections.ll

2

Note that e.g. on arm64 -O0 uses GlobalISel and -O1 and above use FastISel+SelectionDAG, so using different optimization levels will test different ISels. Different optimization levels have helped me catch bugs in earlier implementations.

[melver]

Address comments.

[MaskRay]

llvm/test/CodeGen/AArch64/pcsections.ll

2

To exercise all of GlobalISel FastISel SelectionDAG, the best way is to use explicit options like -fast-isel=, -global-isel=, instead of relying on -O0/-O1/-O2/-O3. -O* runs a large set of codegen pipeline which is pretty irrelevant to this patch.

For a patch series, it's not suitable to add BROKEN: in patch a and change them to RUN: in patch b. This should be refactored to just add RUN: in patch b. If you feel that showding the diff is important, change a to add RUN: about the current state and change b to show the difference.

[vitalybuka]

llvm/lib/IR/MDBuilder.cpp

162

There is TEST_F(MDBuilderTest, which can be updated

166

is implicit mapping from Sections[i] to AuxData[i] in interface is neccecary?
can you do SomeMap<StringRef, <ArrayRef<Constant *>> ?

That would be cleaner

174

why do you need nullptr in that array?

[melver]

llvm/lib/IR/MDBuilder.cpp

166

Map doesn't have stable iteration order. So I'm trying ArrayRef<std::pair<StringRef, SmallVector<Constant*>>>. The problem is that the inner array can't be an ArrayRef, otherwise users of the function have to either convert to something that can convert to ArrayRef<std::pair<StringRef, ArrayRef>> ensuring that whatever inner ref they pass lives long enough.

The reason of the earlier interface was to avoid forcing SmallVector or any particular vector onto callers by sticking to ArrayRef. But by wrapping it into a std::pair, the ArrayRef conversion can't be done implicitly anymore, so usability suffers.

This means that in SanitizerBinaryMetadadata, I'm now using a SmallVector<StringRef, SmallVector<Constant*>>> (instead of just a SmallVector<StringRef>) where the inner SmallVector will always be 0-sized, which wastes space but didn't before. Perhaps this was premature optimization.

174

I don't think we do.

llvm/test/CodeGen/AArch64/pcsections.ll

2

In the latest diff of this patch the tests are gone and I moved them to the AsmPrinter patch (now later in the series).

I will additionally add tests to explicitly exercise each ISel there, but want to keep -O* for the additional coverage (whether or not there are irrelevant optimizations being run today, in future this may change).

[vitalybuka]

llvm/docs/PCSectionsMetadata.rst

30

can aux-consts be just an aggregate?

so you have more structured format: section, array, section, array, section, array,....

llvm/lib/IR/MDBuilder.cpp

166

Map doesn't have stable iteration order.

Do you need a particular section order?

pair<stringref, SmallVector> is not nice, but better than obvious mapping.

maybe real builder?

PCSectionsBuilder B =  MDB.getPCSectionsBuilder();
F.setMetadata(
   B.addSection(S, {c1})
      .addSection(S, {}).
      .addSection(S, {c1, c2})
      .buid());

[vitalybuka]

llvm/lib/IR/MDBuilder.cpp

166

Map doesn't have stable iteration order.

Do you need a particular section order?

pair<stringref, SmallVector> is not nice, but better than non-obvious mapping.

maybe real builder?

PCSectionsBuilder B =  MDB.getPCSectionsBuilder();
F.setMetadata(
   B.addSection(S, {c1})
      .addSection(S, {}).
      .addSection(S, {c1, c2})
      .build());

[melver]

• Change MDNode format to take aux constants as another MDNode.
• Change createPCSections interface.
• Add MDBuilderTest test case.

[melver]

llvm/docs/PCSectionsMetadata.rst

30

Yes it can - it's a trade-off. Making it another MDTuple makes interpreting and constructing the MDNode more complex. But it might save space if the same auxiliary data is reused for different sections.

On a whole, placing the auxiliary data into a separate tuple seems nicer, so I've changed the format. However, I feel there's no point in artificially restricting only 1 tuple after a section string, so things like `!0 = !{"sec1", !1, !2, "sec2", ..}` will be allowed (distinguishing MDString and MDNode within the outer tuple is unambiguous).

llvm/lib/IR/MDBuilder.cpp

166

We need order for deterministic compilation and tests. :-/

The main downside of doing pair<StringRef, SmallVector> is a little bit of wasted space. A builder won't help with that and for now just seems more complex. The easiest seems to be to just define MDBuilder::PCSection which users can use as entry type for any type of vector or array.

[vitalybuka]

LGTM. Thanks!

[melver]

Update documentation with "Guarantees on Code Generation".

[melver]

Fix typo.

[melver]

Rebase.

[melver]

Hi all - if there are no more major comments, we intend to land the entire patch series mid-week or early next week.
Thanks!

[vitalybuka]

In D130875#3770686, @melver wrote:

Hi all - if there are no more major comments, we intend to land the entire patch series mid-week or early next week.
Thanks!

I highly recommend do not lend them at once, and have delay in a few hours between patches.
Give a chance to bots maintainers to revert just a single patch when something goes wrong.

[melver]

In D130875#3770826, @vitalybuka wrote:

In D130875#3770686, @melver wrote:

Hi all - if there are no more major comments, we intend to land the entire patch series mid-week or early next week.
Thanks!

I highly recommend do not lend them at once, and have delay in a few hours between patches.
Give a chance to bots maintainers to revert just a single patch when something goes wrong.

Thanks, will do.

llvm/docs/PCSectionsMetadata.rst

+=========================
+LLVM PC Sections Metadata
+=========================
+
+.. contents::
+   :local:
+
+Introduction
+============
+
+PC Sections Metadata can be attached to instructions and functions, for which
+addresses, viz. program counters (PC), are to be emitted in specially encoded
+binary sections. Metadata is assigned as an ``MDNode`` of the ``MD_pcsections``
+kind; the following section describes the metadata format.
+
+Metadata Format
+===============
+
+An arbitrary number of interleaved ``MDString`` and constant operators can be
+added, where a new ``MDString`` always denotes a section name, followed by an
+arbitrary number of auxiliary constant data encoded along the PC of the
+instruction or function. The first operator must be a ``MDString`` denoting the
+first section.
+
+.. code-block:: none
+
+  !0 = metadata !{
+    metadata !"<section#1>"
+    [ , iXX <aux-consts#1> ... ]
+    [ metadata !"<section#2">
+      [ , iXX <aux-consts#2> ... ]
+      ... ]
+  }
+
+The occurrence of "section#1", "section#2", ..., "section#N" in the metadata
+causes the backend to emit the PC for the associated instruction or function to
+be emitted to all named sections. For each emitted PC in a section #N, the
+constants "aux-consts#N" will be emitted after the PC.
+
+Binary Encoding
+===============
+
+*Instructions* result in emitting a single PC, and *functions* result in
+emission of the start of the function and a 32-bit size. This is followed by
+the auxiliary constants that followed the respective section name in the
+``MD_pcsections`` metadata.
+
+To avoid relocations in the final binary, each PC address stored at ``entry``
+is a relative relocation, computed as ``pc - entry``. To decode, a user has to
+compute ``entry + *entry``.
+
+The size of each entry depends on the code model. With large and medium sized
+code models, the entry size matches pointer size. For any smaller code model
+the entry size is just 32 bits.

llvm/docs/Reference.rst

.. toctree::
    HowToSetUpLLVMStyleRTTI
    HowToUseAttributes
    InAlloca
    LangRef
    LibFuzzer
    MarkedUpDisassembly
    MIRLangRef
    OptBisect
+   PCSectionsMetadata
    PDB/index
    PointerAuth
    ScudoHardenedAllocator
    MemTagSanitizer
    Security
    SecurityTransparencyReports
    SegmentedStacks
    StackMaps

llvm/include/llvm/IR/FixedMetadataKinds.def

 LLVM_FIXED_MD_KIND(MD_vcall_visibility, "vcall_visibility", 28)
 LLVM_FIXED_MD_KIND(MD_noundef, "noundef", 29)
 LLVM_FIXED_MD_KIND(MD_annotation, "annotation", 30)
 LLVM_FIXED_MD_KIND(MD_nosanitize, "nosanitize", 31)
 LLVM_FIXED_MD_KIND(MD_func_sanitize, "func_sanitize", 32)
 LLVM_FIXED_MD_KIND(MD_exclude, "exclude", 33)
 LLVM_FIXED_MD_KIND(MD_memprof, "memprof", 34)
 LLVM_FIXED_MD_KIND(MD_callsite, "callsite", 35)
+LLVM_FIXED_MD_KIND(MD_pcsections, "pcsections", 36)

llvm/include/llvm/IR/MDBuilder.h

public:
   /// Merge the new callback encoding \p NewCB into \p ExistingCallbacks.
   MDNode *mergeCallbackEncodings(MDNode *ExistingCallbacks, MDNode *NewCB);
 
   /// Return metadata feeding to the CodeGen about how to generate a function
   /// prologue for the "function" santizier.
   MDNode *createRTTIPointerPrologue(Constant *PrologueSig, Constant *RTTI);
 
   //===------------------------------------------------------------------===//
+  // PC sections metadata.
+  //===------------------------------------------------------------------===//
+
+  /// Return metadata for PC sections.
+  MDNode *createPCSections(ArrayRef<StringRef> Sections,
+                           ArrayRef<ArrayRef<Constant *>> AuxData);
+
+  //===------------------------------------------------------------------===//
   // AA metadata.
   //===------------------------------------------------------------------===//
 
 protected:
   /// Return metadata appropriate for a AA root node (scope or TBAA).
   /// Each returned node is distinct from all other metadata and will never
   /// be identified (uniqued) with anything else.
   MDNode *createAnonymousAARoot(StringRef Name = StringRef(),

llvm/lib/IR/MDBuilder.cpp

 MDNode *MDBuilder::createRTTIPointerPrologue(Constant *PrologueSig,
                                              Constant *RTTI) {
   SmallVector<Metadata *, 4> Ops;
   Ops.push_back(createConstant(PrologueSig));
   Ops.push_back(createConstant(RTTI));
   return MDNode::get(Context, Ops);
 }
 
+MDNode *
+MDBuilder::createPCSections(ArrayRef<StringRef> Sections,
+                            ArrayRef<ArrayRef<Constant *>> AuxData) {
+  SmallVector<Metadata *, 2> Ops;
+
+  for (size_t i = 0; i < Sections.size(); i++) {
+    const StringRef &S = Sections[i];
+    Ops.push_back(createString(S));
+
+    // If auxiliary data for this section exists, append it.
+    if (i < AuxData.size()) {
+      const ArrayRef<Constant *> &AuxConsts = AuxData[i];
+      for (Constant *C : AuxConsts) {
+        if (C)
+          Ops.push_back(createConstant(C));
+      }
+    }
+  }
+
+  return MDNode::get(Context, Ops);
+}
+
 MDNode *MDBuilder::createAnonymousAARoot(StringRef Name, MDNode *Extra) {
   SmallVector<Metadata *, 3> Args(1, nullptr);
   if (Extra)
     Args.push_back(Extra);
   if (!Name.empty())
     Args.push_back(createString(Name));
   MDNode *Root = MDNode::getDistinct(Context, Args);
 

llvm/test/CodeGen/AArch64/pcsections.ll

+; BROKEN: llc -O0 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-UNOPT,DEFCM
+; BROKEN: llc -O1 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPT,DEFCM
+; BROKEN: llc -O2 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPT,DEFCM
+; BROKEN: llc -O3 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPT,DEFCM
+; BROKEN: llc -O1 -code-model=large < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPT,LARGE
+
+target triple = "aarch64-unknown-linux-gnu"
+
+@foo = dso_local global i64 0, align 8
+@bar = dso_local global i64 0, align 8
+
+define i64 @multiple() !pcsections !0 {
+; CHECK-LABEL: multiple:
+; CHECK:       .Lfunc_begin0:
+; CHECK:       // %bb.0: // %entry
+; CHECK:       .Lpcsection0:
+; CHECK-NEXT:    ldr
+; CHECK-NEXT:    ret
+; CHECK:       .section section_no_aux,"awo",@progbits,.text
+; CHECK-NEXT:  .Lpcsection_base0:
+; DEFCM-NEXT:  .word  .Lfunc_begin0-.Lpcsection_base0
+; LARGE-NEXT:  .xword .Lfunc_begin0-.Lpcsection_base0
+; CHECK-NEXT:  .word  .Lfunc_end0-.Lfunc_begin0
+; CHECK-NEXT:  .section section_aux_42,"awo",@progbits,.text
+; CHECK-NEXT:  .Lpcsection_base1:
+; DEFCM-NEXT:  .word  .Lpcsection0-.Lpcsection_base1
+; LARGE-NEXT:  .xword .Lpcsection0-.Lpcsection_base1
+; CHECK-NEXT:  .word  42
+; CHECK-NEXT:  .section section_aux_21264,"awo",@progbits,.text
+; CHECK-NEXT:  .Lpcsection_base2:
+; DEFCM-NEXT:  .word  .Lpcsection0-.Lpcsection_base2
+; LARGE-NEXT:  .xword .Lpcsection0-.Lpcsection_base2
+; CHECK-NEXT:  .word  21264
+; CHECK-NEXT:  .text
+entry:
+  %0 = load i64, i64* @bar, align 8, !pcsections !1
+  ret i64 %0
+}
+
+define i64 @test_simple_atomic() {
+; CHECK-LABEL: test_simple_atomic:
+; CHECK:       .Lpcsection1:
+; CHECK-NEXT:    ldr
+; CHECK-NOT:   .Lpcsection2
+; CHECK:         ldr
+; CHECK:         add
+; CHECK-NEXT:    ret
+; CHECK:       .section section_no_aux,"awo",@progbits,.text
+; CHECK-NEXT:  .Lpcsection_base3:
+; DEFCM-NEXT:  .word  .Lpcsection1-.Lpcsection_base3
+; LARGE-NEXT:  .xword .Lpcsection1-.Lpcsection_base3
+; CHECK-NEXT:  .text
+entry:
+  %0 = load atomic i64, i64* @foo monotonic, align 8, !pcsections !0
+  %1 = load i64, i64* @bar, align 8
+  %add = add nsw i64 %1, %0
+  ret i64 %add
+}
+
+define i64 @test_complex_atomic() {
+; CHECK-LABEL: test_complex_atomic:
+; ---
+; CHECK-OPT:       .Lpcsection2:
+; CHECK-OPT-NEXT:    ldxr
+; CHECK-OPT:       .Lpcsection3:
+; CHECK-OPT-NEXT:    add
+; CHECK-OPT:       .Lpcsection4:
+; CHECK-OPT-NEXT:    stxr
+; CHECK-OPT:       .Lpcsection5:
+; CHECK-OPT-NEXT:    cbnz
+; ---
+; CHECK-UNOPT:     .Lpcsection2:
+; CHECK-UNOPT-NEXT:  ldr
+; CHECK-UNOPT:     .Lpcsection4:
+; CHECK-UNOPT-NEXT:  add
+; CHECK-UNOPT:     .Lpcsection5:
+; CHECK-UNOPT-NEXT:  ldaxr
+; CHECK-UNOPT:     .Lpcsection6:
+; CHECK-UNOPT-NEXT:  cmp
+; CHECK-UNOPT:     .Lpcsection8:
+; CHECK-UNOPT-NEXT:  stlxr
+; CHECK-UNOPT:     .Lpcsection9:
+; CHECK-UNOPT-NEXT:  cbnz
+; CHECK-UNOPT:     .Lpcsection12:
+; CHECK-UNOPT-NEXT:  b
+; ---
+; CHECK-NOT:   .Lpcsection
+; CHECK:         ldr
+; CHECK:         ret
+; CHECK:       .section section_no_aux,"awo",@progbits,.text
+; CHECK-NEXT:  .Lpcsection_base4:
+; DEFCM-NEXT:  .word  .Lpcsection2-.Lpcsection_base4
+; LARGE-NEXT:  .xword .Lpcsection2-.Lpcsection_base4
+; CHECK-NEXT:  .Lpcsection_base5:
+; DEFCM-NEXT:  .word  .Lpcsection3-.Lpcsection_base5
+; LARGE-NEXT:  .xword .Lpcsection3-.Lpcsection_base5
+; CHECK-NEXT:  .Lpcsection_base6:
+; DEFCM-NEXT:  .word  .Lpcsection4-.Lpcsection_base6
+; LARGE-NEXT:  .xword .Lpcsection4-.Lpcsection_base6
+; CHECK-NEXT:  .Lpcsection_base7:
+; DEFCM-NEXT:  .word  .Lpcsection5-.Lpcsection_base7
+; LARGE-NEXT:  .xword .Lpcsection5-.Lpcsection_base7
+; CHECK-UNOPT: .word  .Lpcsection12-.Lpcsection_base14
+; CHECK-NEXT:  .text
+entry:
+  %0 = atomicrmw add i64* @foo, i64 1 monotonic, align 8, !pcsections !0
+  %1 = load i64, i64* @bar, align 8
+  %inc = add nsw i64 %1, 1
+  store i64 %inc, i64* @bar, align 8
+  %add = add nsw i64 %1, %0
+  ret i64 %add
+}
+
+!0 = !{!"section_no_aux"}
+!1 = !{!"section_aux_42", i32 42, !"section_aux_21264", i32 21264}

llvm/test/CodeGen/X86/pcsections.ll

+; BROKEN: llc -O0 < %s | FileCheck %s --check-prefixes=CHECK,DEFCM
+; BROKEN: llc -O1 < %s | FileCheck %s --check-prefixes=CHECK,DEFCM
+; BROKEN: llc -O2 < %s | FileCheck %s --check-prefixes=CHECK,DEFCM
+; BROKEN: llc -O3 < %s | FileCheck %s --check-prefixes=CHECK,DEFCM
+; BROKEN: llc -O1 -code-model=large < %s | FileCheck %s --check-prefixes=CHECK,LARGE
+
+target triple = "x86_64-unknown-linux-gnu"
+
+@foo = dso_local global i64 0, align 8
+@bar = dso_local global i64 0, align 8
+
+define void @empty_no_aux() !pcsections !0 {
+; CHECK-LABEL: empty_no_aux:
+; CHECK-NEXT:  .Lfunc_begin0
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    retq
+; CHECK-NEXT:  .Lfunc_end0:
+; CHECK:       .section section_no_aux,"awo",@progbits,.text
+; CHECK-NEXT:  .Lpcsection_base0:
+; DEFCM-NEXT:  .long  .Lfunc_begin0-.Lpcsection_base0
+; LARGE-NEXT:  .quad  .Lfunc_begin0-.Lpcsection_base0
+; CHECK-NEXT:  .long  .Lfunc_end0-.Lfunc_begin0
+; CHECK-NEXT:  .text
+entry:
+  ret void
+}
+
+define void @empty_aux() !pcsections !1 {
+; CHECK-LABEL: empty_aux:
+; CHECK-NEXT:  .Lfunc_begin1
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    retq
+; CHECK-NEXT:  .Lfunc_end1:
+; CHECK:       .section section_aux,"awo",@progbits,.text
+; CHECK-NEXT:  .Lpcsection_base1:
+; DEFCM-NEXT:  .long  .Lfunc_begin1-.Lpcsection_base1
+; LARGE-NEXT:  .quad  .Lfunc_begin1-.Lpcsection_base1
+; CHECK-NEXT:  .long  .Lfunc_end1-.Lfunc_begin1
+; CHECK-NEXT:  .long  10
+; CHECK-NEXT:  .long  20
+; CHECK-NEXT:  .long  30
+; CHECK-NEXT:  .text
+entry:
+  ret void
+}
+
+define i64 @multiple() !pcsections !0 {
+; CHECK-LABEL: multiple:
+; CHECK-NEXT:  .Lfunc_begin2
+; CHECK:       # %bb.0: # %entry
+; CHECK:       .Lpcsection0:
+; CHECK-NEXT:    movq
+; CHECK-NEXT:    retq
+; CHECK-NEXT:  .Lfunc_end2:
+; CHECK:       .section section_no_aux,"awo",@progbits,.text
+; CHECK-NEXT:  .Lpcsection_base2:
+; DEFCM-NEXT:  .long  .Lfunc_begin2-.Lpcsection_base2
+; LARGE-NEXT:  .quad  .Lfunc_begin2-.Lpcsection_base2
+; CHECK-NEXT:  .long  .Lfunc_end2-.Lfunc_begin2
+; CHECK-NEXT:  .section section_aux_42,"awo",@progbits,.text
+; CHECK-NEXT:  .Lpcsection_base3:
+; DEFCM-NEXT:  .long  .Lpcsection0-.Lpcsection_base3
+; LARGE-NEXT:  .quad  .Lpcsection0-.Lpcsection_base3
+; CHECK-NEXT:  .long  42
+; CHECK-NEXT:  .section section_aux_21264,"awo",@progbits,.text
+; CHECK-NEXT:  .Lpcsection_base4:
+; DEFCM-NEXT:  .long  .Lpcsection0-.Lpcsection_base4
+; LARGE-NEXT:  .quad  .Lpcsection0-.Lpcsection_base4
+; CHECK-NEXT:  .long  21264
+; CHECK-NEXT:  .text
+entry:
+  %0 = load i64, i64* @bar, align 8, !pcsections !2
+  ret i64 %0
+}
+
+define i64 @test_simple_atomic() {
+; CHECK-LABEL: test_simple_atomic:
+; CHECK:       .Lpcsection1:
+; CHECK-NEXT:    movq
+; CHECK-NOT:   .Lpcsection
+; CHECK:         addq
+; CHECK-NEXT:    retq
+; CHECK-NEXT:  .Lfunc_end3:
+; CHECK:       .section section_no_aux,"awo",@progbits,.text
+; CHECK-NEXT:  .Lpcsection_base5:
+; DEFCM-NEXT:  .long  .Lpcsection1-.Lpcsection_base5
+; LARGE-NEXT:  .quad  .Lpcsection1-.Lpcsection_base5
+; CHECK-NEXT:  .text
+entry:
+  %0 = load atomic i64, i64* @foo monotonic, align 8, !pcsections !0
+  %1 = load i64, i64* @bar, align 8
+  %add = add nsw i64 %1, %0
+  ret i64 %add
+}
+
+define i64 @test_complex_atomic() {
+; CHECK-LABEL: test_complex_atomic:
+; CHECK:         movl $1
+; CHECK-NEXT:  .Lpcsection2:
+; CHECK-NEXT:    lock xaddq
+; CHECK-NOT:   .Lpcsection
+; CHECK:         movq
+; CHECK:         addq
+; CHECK:         retq
+; CHECK-NEXT:  .Lfunc_end4:
+; CHECK:       .section section_no_aux,"awo",@progbits,.text
+; CHECK-NEXT:  .Lpcsection_base6:
+; DEFCM-NEXT:  .long  .Lpcsection2-.Lpcsection_base6
+; LARGE-NEXT:  .quad  .Lpcsection2-.Lpcsection_base6
+; CHECK-NEXT:  .text
+entry:
+  %0 = atomicrmw add i64* @foo, i64 1 monotonic, align 8, !pcsections !0
+  %1 = load i64, i64* @bar, align 8
+  %inc = add nsw i64 %1, 1
+  store i64 %inc, i64* @bar, align 8
+  %add = add nsw i64 %1, %0
+  ret i64 %add
+}
+
+!0 = !{!"section_no_aux"}
+!1 = !{!"section_aux", i32 10, i32 20, i32 30}
+!2 = !{!"section_aux_42", i32 42, !"section_aux_21264", i32 21264}