[GlobalISel] Propagate PCSections metadata to MachineInstr

[melver]

Summary

Propagate (most) PC sections metadata to MachineInstr when GlobalISel is
doing instruction selection.

This change results in support for architectures using GlobalISel (such
as -O0 with AArch64). Not all instructions may be supported yet, and
requires further target-specific handling (such as done for AArch64
pseudo-atomics). Expanding supported instructions is planned on a
case-by-case basis and new use cases for PC sections metadata.

Depends on D130885

[melver]

Rebase.

[melver]

Rebase.

[vitalybuka]

LGTM, I guess it's close to NFC
if not, it would be nice see some new CHECKS under llvm/test/CodeGen/AArch64/

[arsenm]

Missing tests

llvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h

while (true) {
 
     case GIR_BuildMI: {
       uint64_t NewInsnID = MatchTable[CurrentIdx++];
       int64_t Opcode = MatchTable[CurrentIdx++];
       if (NewInsnID >= OutMIs.size())
         OutMIs.resize(NewInsnID + 1);
 
       OutMIs[NewInsnID] = BuildMI(*State.MIs[0]->getParent(), State.MIs[0],
-                                  State.MIs[0]->getDebugLoc(), TII.get(Opcode));
+                                  MIMetadata(*State.MIs[0]), TII.get(Opcode));
       DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
                       dbgs() << CurrentIdx << ": GIR_BuildMI(OutMIs["
                              << NewInsnID << "], " << Opcode << ")\n");
       break;
     }
 
     case GIR_Copy: {
       int64_t NewInsnID = MatchTable[CurrentIdx++];

llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h

struct MachineIRBuilderState {
   /// MachineFunction under construction.
   MachineFunction *MF = nullptr;
   /// Information used to access the description of the opcodes.
   const TargetInstrInfo *TII = nullptr;
   /// Information used to verify types are consistent and to create virtual registers.
   MachineRegisterInfo *MRI = nullptr;
   /// Debug location to be set to any instruction we create.
   DebugLoc DL;
+  /// PC sections metadata to be set to any instruction we create.
+  MDNode *PCSections = nullptr;
 
   /// \name Fields describing the insertion point.
   /// @{
   MachineBasicBlock *MBB = nullptr;
   MachineBasicBlock::iterator II;
   /// @}
 
   GISelChangeObserver *Observer = nullptr;
public:
   }
 
   /// Set the insertion point to before MI.
   /// \pre MI must be in getMF().
   void setInstr(MachineInstr &MI) {
     assert(MI.getParent() && "Instruction is not part of a basic block");
     setMBB(*MI.getParent());
     State.II = MI.getIterator();
+    setPCSections(MI.getPCSections());
   }
   /// @}
 
   /// Set the insertion point to before MI, and set the debug loc to MI's loc.
   /// \pre MI must be in getMF().
   void setInstrAndDebugLoc(MachineInstr &MI) {
     setInstr(MI);
     setDebugLoc(MI.getDebugLoc());
   }
 
   void setChangeObserver(GISelChangeObserver &Observer) {
     State.Observer = &Observer;
   }
 
   void stopObservingChanges() { State.Observer = nullptr; }
   /// @}
 
   /// Set the debug location to \p DL for all the next build instructions.
   void setDebugLoc(const DebugLoc &DL) { this->State.DL = DL; }
 
   /// Get the current instruction's debug location.
   const DebugLoc &getDebugLoc() { return State.DL; }
 
+  /// Set the PC sections metadata to \p MD for all the next build instructions.
+  void setPCSections(MDNode *MD) { State.PCSections = MD; }
+
+  /// Get the current instruction's PC sections metadata.
+  MDNode *getPCSections() { return State.PCSections; }
+
   /// Build and insert <empty> = \p Opcode <empty>.
   /// The insertion point is the one set by the last call of either
   /// setBasicBlock or setMI.
   ///
   /// \pre setBasicBlock or setMI must have been called.
   ///
   /// \return a MachineInstrBuilder for the newly created instruction.
   MachineInstrBuilder buildInstr(unsigned Opcode) {

llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp

for (unsigned i = 0; i < PI->getNumIncomingValues(); ++i) {
         }
       }
     }
   }
 }
 
 bool IRTranslator::translate(const Instruction &Inst) {
   CurBuilder->setDebugLoc(Inst.getDebugLoc());
+  CurBuilder->setPCSections(Inst.getMetadata(LLVMContext::MD_pcsections));
 
   auto &TLI = *MF->getSubtarget().getTargetLowering();
   if (TLI.fallBackToDAGISel(Inst))
     return false;
 
   switch (Inst.getOpcode()) {
 #define HANDLE_INST(NUM, OPCODE, CLASS)                                        \
   case Instruction::OPCODE:                                                    \

llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp

 using namespace llvm;
 
 void MachineIRBuilder::setMF(MachineFunction &MF) {
   State.MF = &MF;
   State.MBB = nullptr;
   State.MRI = &MF.getRegInfo();
   State.TII = MF.getSubtarget().getInstrInfo();
   State.DL = DebugLoc();
+  State.PCSections = nullptr;
   State.II = MachineBasicBlock::iterator();
   State.Observer = nullptr;
 }
 
 //------------------------------------------------------------------------------
 // Build instruction variants.
 //------------------------------------------------------------------------------
 
 MachineInstrBuilder MachineIRBuilder::buildInstrNoInsert(unsigned Opcode) {
-  MachineInstrBuilder MIB = BuildMI(getMF(), getDL(), getTII().get(Opcode));
-  return MIB;
+  return BuildMI(getMF(), {getDL(), getPCSections()}, getTII().get(Opcode));
 }
 
 MachineInstrBuilder MachineIRBuilder::insertInstr(MachineInstrBuilder MIB) {
   getMBB().insert(getInsertPt(), MIB);
   recordInsertion(MIB);
   return MIB;
 }
 

llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp

bool AArch64ExpandPseudo::expandMOVImm(MachineBasicBlock &MBB,
   return true;
 }
 
 bool AArch64ExpandPseudo::expandCMP_SWAP(
     MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned LdarOp,
     unsigned StlrOp, unsigned CmpOp, unsigned ExtendImm, unsigned ZeroReg,
     MachineBasicBlock::iterator &NextMBBI) {
   MachineInstr &MI = *MBBI;
-  DebugLoc DL = MI.getDebugLoc();
+  MIMetadata MIMD(MI);
   const MachineOperand &Dest = MI.getOperand(0);
   Register StatusReg = MI.getOperand(1).getReg();
   bool StatusDead = MI.getOperand(1).isDead();
   // Duplicating undef operands into 2 instructions does not guarantee the same
   // value on both; However undef should be replaced by xzr anyway.
   assert(!MI.getOperand(2).isUndef() && "cannot handle undef");
   Register AddrReg = MI.getOperand(2).getReg();
   Register DesiredReg = MI.getOperand(3).getReg();
bool AArch64ExpandPseudo::expandCMP_SWAP(
   MF->insert(++StoreBB->getIterator(), DoneBB);
 
   // .Lloadcmp:
   //     mov wStatus, 0
   //     ldaxr xDest, [xAddr]
   //     cmp xDest, xDesired
   //     b.ne .Ldone
   if (!StatusDead)
-    BuildMI(LoadCmpBB, DL, TII->get(AArch64::MOVZWi), StatusReg)
+    BuildMI(LoadCmpBB, MIMD, TII->get(AArch64::MOVZWi), StatusReg)
       .addImm(0).addImm(0);
-  BuildMI(LoadCmpBB, DL, TII->get(LdarOp), Dest.getReg())
+  BuildMI(LoadCmpBB, MIMD, TII->get(LdarOp), Dest.getReg())
       .addReg(AddrReg);
-  BuildMI(LoadCmpBB, DL, TII->get(CmpOp), ZeroReg)
+  BuildMI(LoadCmpBB, MIMD, TII->get(CmpOp), ZeroReg)
       .addReg(Dest.getReg(), getKillRegState(Dest.isDead()))
       .addReg(DesiredReg)
       .addImm(ExtendImm);
-  BuildMI(LoadCmpBB, DL, TII->get(AArch64::Bcc))
+  BuildMI(LoadCmpBB, MIMD, TII->get(AArch64::Bcc))
       .addImm(AArch64CC::NE)
       .addMBB(DoneBB)
       .addReg(AArch64::NZCV, RegState::Implicit | RegState::Kill);
   LoadCmpBB->addSuccessor(DoneBB);
   LoadCmpBB->addSuccessor(StoreBB);
 
   // .Lstore:
   //     stlxr wStatus, xNew, [xAddr]
   //     cbnz wStatus, .Lloadcmp
-  BuildMI(StoreBB, DL, TII->get(StlrOp), StatusReg)
+  BuildMI(StoreBB, MIMD, TII->get(StlrOp), StatusReg)
       .addReg(NewReg)
       .addReg(AddrReg);
-  BuildMI(StoreBB, DL, TII->get(AArch64::CBNZW))
+  BuildMI(StoreBB, MIMD, TII->get(AArch64::CBNZW))
       .addReg(StatusReg, getKillRegState(StatusDead))
       .addMBB(LoadCmpBB);
   StoreBB->addSuccessor(LoadCmpBB);
   StoreBB->addSuccessor(DoneBB);
 
   DoneBB->splice(DoneBB->end(), &MBB, MI, MBB.end());
   DoneBB->transferSuccessors(&MBB);
 
bool AArch64ExpandPseudo::expandCMP_SWAP(
 
   return true;
 }
 
 bool AArch64ExpandPseudo::expandCMP_SWAP_128(
     MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
     MachineBasicBlock::iterator &NextMBBI) {
   MachineInstr &MI = *MBBI;
-  DebugLoc DL = MI.getDebugLoc();
+  MIMetadata MIMD(MI);
   MachineOperand &DestLo = MI.getOperand(0);
   MachineOperand &DestHi = MI.getOperand(1);
   Register StatusReg = MI.getOperand(2).getReg();
   bool StatusDead = MI.getOperand(2).isDead();
   // Duplicating undef operands into 2 instructions does not guarantee the same
   // value on both; However undef should be replaced by xzr anyway.
   assert(!MI.getOperand(3).isUndef() && "cannot handle undef");
   Register AddrReg = MI.getOperand(3).getReg();
bool AArch64ExpandPseudo::expandCMP_SWAP_128(
   MF->insert(++StoreBB->getIterator(), FailBB);
   MF->insert(++FailBB->getIterator(), DoneBB);
 
   // .Lloadcmp:
   //     ldaxp xDestLo, xDestHi, [xAddr]
   //     cmp xDestLo, xDesiredLo
   //     sbcs xDestHi, xDesiredHi
   //     b.ne .Ldone
-  BuildMI(LoadCmpBB, DL, TII->get(LdxpOp))
+  BuildMI(LoadCmpBB, MIMD, TII->get(LdxpOp))
       .addReg(DestLo.getReg(), RegState::Define)
       .addReg(DestHi.getReg(), RegState::Define)
       .addReg(AddrReg);
-  BuildMI(LoadCmpBB, DL, TII->get(AArch64::SUBSXrs), AArch64::XZR)
+  BuildMI(LoadCmpBB, MIMD, TII->get(AArch64::SUBSXrs), AArch64::XZR)
       .addReg(DestLo.getReg(), getKillRegState(DestLo.isDead()))
       .addReg(DesiredLoReg)
       .addImm(0);
-  BuildMI(LoadCmpBB, DL, TII->get(AArch64::CSINCWr), StatusReg)
+  BuildMI(LoadCmpBB, MIMD, TII->get(AArch64::CSINCWr), StatusReg)
     .addUse(AArch64::WZR)
     .addUse(AArch64::WZR)
     .addImm(AArch64CC::EQ);
-  BuildMI(LoadCmpBB, DL, TII->get(AArch64::SUBSXrs), AArch64::XZR)
+  BuildMI(LoadCmpBB, MIMD, TII->get(AArch64::SUBSXrs), AArch64::XZR)
       .addReg(DestHi.getReg(), getKillRegState(DestHi.isDead()))
       .addReg(DesiredHiReg)
       .addImm(0);
-  BuildMI(LoadCmpBB, DL, TII->get(AArch64::CSINCWr), StatusReg)
+  BuildMI(LoadCmpBB, MIMD, TII->get(AArch64::CSINCWr), StatusReg)
       .addUse(StatusReg, RegState::Kill)
       .addUse(StatusReg, RegState::Kill)
       .addImm(AArch64CC::EQ);
-  BuildMI(LoadCmpBB, DL, TII->get(AArch64::CBNZW))
+  BuildMI(LoadCmpBB, MIMD, TII->get(AArch64::CBNZW))
       .addUse(StatusReg, getKillRegState(StatusDead))
       .addMBB(FailBB);
   LoadCmpBB->addSuccessor(FailBB);
   LoadCmpBB->addSuccessor(StoreBB);
 
   // .Lstore:
   //     stlxp wStatus, xNewLo, xNewHi, [xAddr]
   //     cbnz wStatus, .Lloadcmp
-  BuildMI(StoreBB, DL, TII->get(StxpOp), StatusReg)
+  BuildMI(StoreBB, MIMD, TII->get(StxpOp), StatusReg)
       .addReg(NewLoReg)
       .addReg(NewHiReg)
       .addReg(AddrReg);
-  BuildMI(StoreBB, DL, TII->get(AArch64::CBNZW))
+  BuildMI(StoreBB, MIMD, TII->get(AArch64::CBNZW))
       .addReg(StatusReg, getKillRegState(StatusDead))
       .addMBB(LoadCmpBB);
-  BuildMI(StoreBB, DL, TII->get(AArch64::B)).addMBB(DoneBB);
+  BuildMI(StoreBB, MIMD, TII->get(AArch64::B)).addMBB(DoneBB);
   StoreBB->addSuccessor(LoadCmpBB);
   StoreBB->addSuccessor(DoneBB);
 
   // .Lfail:
   //     stlxp wStatus, xDestLo, xDestHi, [xAddr]
   //     cbnz wStatus, .Lloadcmp
-  BuildMI(FailBB, DL, TII->get(StxpOp), StatusReg)
+  BuildMI(FailBB, MIMD, TII->get(StxpOp), StatusReg)
       .addReg(DestLo.getReg())
       .addReg(DestHi.getReg())
       .addReg(AddrReg);
-  BuildMI(FailBB, DL, TII->get(AArch64::CBNZW))
+  BuildMI(FailBB, MIMD, TII->get(AArch64::CBNZW))
       .addReg(StatusReg, getKillRegState(StatusDead))
       .addMBB(LoadCmpBB);
   FailBB->addSuccessor(LoadCmpBB);
   FailBB->addSuccessor(DoneBB);
 
   DoneBB->splice(DoneBB->end(), &MBB, MI, MBB.end());
   DoneBB->transferSuccessors(&MBB);