[SDAG] narrow truncated sign_extend_inreg

[spatel]

Summary

trunc (sign_ext_inreg X, iM) to iN --> sign_ext_inreg (trunc X to iN), iM

There are improvements on existing tests from this, and there are a pair of large regressions in D127115 for Thumb2 caused by not folding this pattern.

[spatel]

Patch updated:
On closer inspection, we can generalize the fold to only match trunc-of-sext (don't need to match the preceding extend), and that shows improvements on existing tests for x86 and (I think) AMDGPU.

[arsenm]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

13138

Shouldn't really require legal types, but the DAG is lacking in adequate legality checks for sext_inreg

llvm/test/CodeGen/AMDGPU/mul_int24.ll

184–186 ↗

(On Diff #445231)

This is a pretty big improvement

[spatel]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

13138

There are a couple of other sext_inreg folds in DAGCombiner that use something like this:

if (!LegalOperations ||
    TLI.getOperationAction(ISD::SIGN_EXTEND_INREG, ExtVT) ==
    TargetLowering::Legal)

I tried that and don't see any differences vs. this check, so I could use that too, but I think the current predicate would be more conservative just in case there's some unexpected type conversions during legalization.

llvm/test/CodeGen/AMDGPU/mul_int24.ll

184–186 ↗

(On Diff #445231)

Thanks for confirming!

[arsenm]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

13138

This is one of the places where we really need 2 type checks, but I think checking the ExtVT legality is probably enough here

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

     // if the source is larger than the dest, than we just need the truncate.
     if (N0.getOperand(0).getValueType().bitsGT(VT))
       return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, N0.getOperand(0));
     // if the source and dest are the same type, we can drop both the extend
     // and the truncate.
     return N0.getOperand(0);
   }
 
+  // trunc (sign_ext_inreg (anyext iN X), iM) to iN --> sign_ext_inreg X to iM
+  if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+    SDValue N00 = N0.getOperand(0);
+    SDValue N01 = N0.getOperand(1);
+    if (N00.getOpcode() == ISD::ANY_EXTEND &&
+        N00.getOperand(0).getValueType() == VT)
+      return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT,
+                         N00.getOperand(0), N01);
+  }
+
   // If this is anyext(trunc), don't fold it, allow ourselves to be folded.
   if (N->hasOneUse() && (N->use_begin()->getOpcode() == ISD::ANY_EXTEND))
     return SDValue();
 
   // Fold extract-and-trunc into a narrow extract. For example:
   //   i64 x = EXTRACT_VECTOR_ELT(v2i64 val, i32 1)
   //   i32 y = TRUNCATE(i64 x)
   //        -- becomes --