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Differential D129818

AMDGPU: Make default AMDHSA Code Object Version to be 5
ClosedPublic

Authored by cfang on Jul 14 2022, 4:29 PM.

Details

Reviewers
arsenm
b-sumner
jdoerfert
sstefan1
ronlieb
jhenderson
MaskRay
Group Reviewers
Restricted Project
Commits
rG0a8d17e79b02: [AMDGPU] Make default AMDHSA Code Object Version to be 5 (#65410)
Summary

Also update LIT tests and docs.

Diff Detail

Event Timeline

cfang created this revision.Jul 14 2022, 4:29 PM
Herald added a project: Restricted Project. · View Herald TranscriptJul 14 2022, 4:29 PM
Herald added subscribers: kosarev, jsilvanus, foad and 9 others. · View Herald Transcript
cfang requested review of this revision.Jul 14 2022, 4:29 PM
Herald added a reviewer: jdoerfert. · View Herald TranscriptJul 14 2022, 4:29 PM
Herald added a reviewer: sstefan1. · View Herald Transcript
Herald added a project: Restricted Project. · View Herald Transcript
Herald added subscribers: MaskRay, wdng. · View Herald Transcript
Harbormaster completed remote builds in B175534: Diff 444837.Jul 14 2022, 4:30 PM
arsenm added a comment.Jul 14 2022, 5:05 PM

Are we really ready to switch the default? We aren't even optimizing the new locations yet?

arsenm added a comment.Jul 14 2022, 5:05 PM

Typo in patch title

cfang retitled this revision from AMDGPU: Make default AMDHSA Code Pbject Version to be 5 to AMDGPU: Make default AMDHSA Code Object Version to be 5.Jul 14 2022, 5:18 PM
kzhuravl added a comment.Jul 15 2022, 9:42 AM

Need to also update: https://github.com/llvm/llvm-project/blob/main/clang/include/clang/Driver/Options.td#L3626

cfang updated this revision to Diff 445113.Jul 15 2022, 1:10 PM

Update https://github.com/llvm/llvm-project/blob/main/clang/include/clang/Driver/Options.td#L3626
as well as the corresponding LIT tests.

Harbormaster completed remote builds in B175739: Diff 445113.Jul 15 2022, 3:30 PM
arsenm accepted this revision.Nov 16 2022, 3:39 PM

LGTM. I thought this already happened?

This revision is now accepted and ready to land.Nov 16 2022, 3:39 PM
ronlieb requested changes to this revision.Nov 16 2022, 3:46 PM
ronlieb added a subscriber: ronlieb.

lets hold off landing for a few more days?
checking some internal related testing results

Thanks,

This revision now requires changes to proceed.Nov 16 2022, 3:46 PM
lamb-j added a subscriber: lamb-j.May 9 2023, 12:04 PM
lamb-j added inline comments.
clang/test/Driver/hip-device-libs.hip
144

500?

I think we may also need to update the comment here: https://github.com/llvm/llvm-project/blob/e9569748def85a2f6bb8066e516a84e6933ef407/clang/test/Driver/hip-device-libs.hip#LL196C1-L196C83

154

Should this be ABI5? That is, if CodeObjectVersion < 4, should it be set to 5 (instead of 4)?

May also be related to a needed change here: https://github.com/llvm/llvm-project/blob/6db007a0654ed7a6ed5c3aa3b61a937c19a6bc6b/clang/lib/Driver/ToolChains/ROCm.h#L29

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
31–34

We may also want to update this file here:

https://github.com/llvm/llvm-project/blob/e9569748def85a2f6bb8066e516a84e6933ef407/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp#L162

arsenm added a comment.Jun 8 2023, 5:10 PM

ping, my understand is this landed in amd-stg-open and not upstream

cfang marked 3 inline comments as done.Jun 12 2023, 3:07 PM
cfang added inline comments.
clang/test/Driver/hip-device-libs.hip
144

Yes. Should comment as 500 in these places. Thanks.

154

No. it should be 4 if <=4. I think this is mainly for device-lib versions (400.bc vs 500.bc).

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
31–34

You are right. Done.

cfang updated this revision to Diff 530681.Jun 12 2023, 3:10 PM
cfang marked 3 inline comments as done.

Rebase and fixes LIT tests.

Is there any concerns to merge this patch to upstream?

Herald added subscribers: ormris, okura, kuter and 4 others. · View Herald TranscriptJun 12 2023, 3:10 PM
Harbormaster completed remote builds in B238316: Diff 530681.Jun 12 2023, 3:11 PM
saiislam added a subscriber: saiislam.Jun 13 2023, 5:55 AM
In D129818#4407328, @arsenm wrote:

ping, my understand is this landed in amd-stg-open and not upstream

No, it has not landed in amd-stg-open yet.
Konstantin would know the current status.

cfang updated this revision to Diff 530947.Jun 13 2023, 9:42 AM

Rebase

cfang added a comment.Jun 13 2023, 10:07 AM

Ping. This patch needs a permission to go. Thanks.

Harbormaster completed remote builds in B238522: Diff 530947.Jun 13 2023, 11:07 AM
arsenm added a comment.Jun 22 2023, 6:18 AM
In D129818#4418140, @cfang wrote:

Ping. This patch needs a permission to go. Thanks.

I don't fully grasp what the OpenMP issue was. Is the OpenMP handling done?

arsenm added a comment.Aug 30 2023, 1:30 PM

The openmp version handling patch is in, so can this go in now?

arsenm added a child revision: D141700: AMDGPU: Move enqueued block handling into clang.Aug 30 2023, 1:43 PM
saiislam added a comment.Aug 30 2023, 11:31 PM
In D129818#4629302, @arsenm wrote:

The openmp version handling patch is in, so can this go in now?

Yes, I have picked up this patch. Will post a revision soon.

saiislam added a comment.Sep 5 2023, 1:06 PM

I have created a PR for this: https://github.com/llvm/llvm-project/pull/65410

This revision was not accepted when it landed; it landed in state Needs Review.Sep 12 2023, 1:23 AM
This revision was landed with ongoing or failed builds.
Closed by commit rG0a8d17e79b02: [AMDGPU] Make default AMDHSA Code Object Version to be 5 (#65410) (authored by saiislam, committed by GitHub <noreply@github.com>). · Explain Why
This revision was automatically updated to reflect the committed changes.
GitHub <noreply@github.com> added a commit: rG0a8d17e79b02: [AMDGPU] Make default AMDHSA Code Object Version to be 5 (#65410).
Herald added a reviewer: jhenderson. · View Herald TranscriptSep 12 2023, 1:23 AM
Herald added a reviewer: MaskRay. · View Herald Transcript
Herald added projects: Restricted Project, Restricted Project. · View Herald Transcript
Herald added subscribers: openmp-commits, cfe-commits. · View Herald Transcript
GitHub <noreply@github.com> added a reverting change: rG466a8149b369: Revert "[AMDGPU] Make default AMDHSA Code Object Version to be 5 (#65410)"….Sep 12 2023, 2:44 AM

Large Diff

This large diff affects 109 files. Files without inline comments have been collapsed. Expand All Files

Revision Contents

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clang/
include/
clang/
Driver/
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lib/
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ToolChains/
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test/
CodeGenCUDA/
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CodeGenHIP/
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lld/
test/
ELF/
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lto/
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llvm/
docs/
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lib/
Target/
AMDGPU/
Utils/
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AMDGPU/
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Diff 556533

clang/include/clang/Driver/Options.td

clang/lib/Driver/ToolChains/CommonArgs.cpp

clang/test/CodeGenCUDA/amdgpu-code-object-version.cu

clang/test/CodeGenCUDA/amdgpu-workgroup-size.cu

clang/test/CodeGenHIP/default-attributes.hip

clang/test/CodeGenOpenCL/amdgpu-enqueue-kernel.cl

clang/test/CodeGenOpenCL/builtins-amdgcn.cl

clang/test/Driver/hip-device-libs.hip

Show First 20 Lines • Show All 135 Lines • ▼ Show 20 Lines
// Test -fast-math // Test -fast-math
// RUN: %clang -### --target=x86_64-linux-gnu --offload-arch=gfx900 \ // RUN: %clang -### --target=x86_64-linux-gnu --offload-arch=gfx900 \
// RUN: -ffast-math --rocm-path=%S/Inputs/rocm \ // RUN: -ffast-math --rocm-path=%S/Inputs/rocm \
// RUN: %S/Inputs/hip_multiple_inputs/b.hip \ // RUN: %S/Inputs/hip_multiple_inputs/b.hip \
// RUN: 2>&1 | FileCheck %s --check-prefixes=FAST // RUN: 2>&1 | FileCheck %s --check-prefixes=FAST
// Test -ffinite-math-only // Test -ffinite-math-only
// RUN: %clang -### --target=x86_64-linux-gnu --offload-arch=gfx900 \ // RUN: %clang -### --target=x86_64-linux-gnu --offload-arch=gfx900 \
// RUN: -ffinite-math-only --rocm-path=%S/Inputs/rocm \ // RUN: -ffinite-math-only --rocm-path=%S/Inputs/rocm \
lamb-jUnsubmitted
Done
ReplyInline Actions

500?

I think we may also need to update the comment here: https://github.com/llvm/llvm-project/blob/e9569748def85a2f6bb8066e516a84e6933ef407/clang/test/Driver/hip-device-libs.hip#LL196C1-L196C83

lamb-j: 500? I think we may also need to update the comment here: https://github.com/llvm/llvm…
cfangAuthorUnsubmitted
Done
ReplyInline Actions

Yes. Should comment as 500 in these places. Thanks.

cfang: Yes. Should comment as 500 in these places. Thanks.
// RUN: %S/Inputs/hip_multiple_inputs/b.hip \ // RUN: %S/Inputs/hip_multiple_inputs/b.hip \
// RUN: 2>&1 | FileCheck %s --check-prefixes=FINITE // RUN: 2>&1 | FileCheck %s --check-prefixes=FINITE
// Test -funsafe-math-optimizations // Test -funsafe-math-optimizations
// RUN: %clang -### --target=x86_64-linux-gnu --offload-arch=gfx900 \ // RUN: %clang -### --target=x86_64-linux-gnu --offload-arch=gfx900 \
// RUN: -funsafe-math-optimizations --rocm-path=%S/Inputs/rocm \ // RUN: -funsafe-math-optimizations --rocm-path=%S/Inputs/rocm \
// RUN: %S/Inputs/hip_multiple_inputs/b.hip \ // RUN: %S/Inputs/hip_multiple_inputs/b.hip \
// RUN: 2>&1 | FileCheck %s --check-prefixes=UNSAFE // RUN: 2>&1 | FileCheck %s --check-prefixes=UNSAFE
// Test -fno-hip-fp32-correctly-rounded-divide-sqrt // Test -fno-hip-fp32-correctly-rounded-divide-sqrt
lamb-jUnsubmitted
Done
ReplyInline Actions

Should this be ABI5? That is, if CodeObjectVersion < 4, should it be set to 5 (instead of 4)?

May also be related to a needed change here: https://github.com/llvm/llvm-project/blob/6db007a0654ed7a6ed5c3aa3b61a937c19a6bc6b/clang/lib/Driver/ToolChains/ROCm.h#L29

lamb-j: Should this be ABI5? That is, if CodeObjectVersion < 4, should it be set to 5 (instead of 4)?
cfangAuthorUnsubmitted
Done
ReplyInline Actions

No. it should be 4 if <=4. I think this is mainly for device-lib versions (400.bc vs 500.bc).

cfang: No. it should be 4 if <=4. I think this is mainly for device-lib versions (400.bc vs 500.bc).
// RUN: %clang -### --target=x86_64-linux-gnu --offload-arch=gfx900 \ // RUN: %clang -### --target=x86_64-linux-gnu --offload-arch=gfx900 \
// RUN: -fno-hip-fp32-correctly-rounded-divide-sqrt \ // RUN: -fno-hip-fp32-correctly-rounded-divide-sqrt \
// RUN: --rocm-path=%S/Inputs/rocm %S/Inputs/hip_multiple_inputs/b.hip \ // RUN: --rocm-path=%S/Inputs/rocm %S/Inputs/hip_multiple_inputs/b.hip \
// RUN: 2>&1 | FileCheck %s --check-prefixes=DIVSQRT // RUN: 2>&1 | FileCheck %s --check-prefixes=DIVSQRT
// Test default code object version. // Test default code object version.
// RUN: %clang -### --target=x86_64-linux-gnu --offload-arch=gfx900 \ // RUN: %clang -### --target=x86_64-linux-gnu --offload-arch=gfx900 \
// RUN: --rocm-path=%S/Inputs/rocm %S/Inputs/hip_multiple_inputs/b.hip \ // RUN: --rocm-path=%S/Inputs/rocm %S/Inputs/hip_multiple_inputs/b.hip \
// RUN: 2>&1 | FileCheck %s --check-prefixes=ABI4 // RUN: 2>&1 | FileCheck %s --check-prefixes=ABI5
// Test default code object version with old device library without abi_version_400.bc // Test default code object version with old device library without abi_version_500.bc
// RUN: %clang -### --target=x86_64-linux-gnu --offload-arch=gfx900 \ // RUN: not %clang -### --target=x86_64-linux-gnu --offload-arch=gfx900 \
// RUN: --hip-device-lib-path=%S/Inputs/rocm/amdgcn/bitcode-no-abi-ver \ // RUN: --hip-device-lib-path=%S/Inputs/rocm/amdgcn/bitcode-no-abi-ver \
// RUN: --rocm-path=%S/Inputs/rocm %S/Inputs/hip_multiple_inputs/b.hip \ // RUN: --rocm-path=%S/Inputs/rocm %S/Inputs/hip_multiple_inputs/b.hip \
// RUN: 2>&1 | FileCheck %s --check-prefixes=NOABI4 // RUN: 2>&1 | FileCheck %s --check-prefixes=NOABI5
// Test -mcode-object-version=3 // Test -mcode-object-version=3
// RUN: %clang -### --target=x86_64-linux-gnu --offload-arch=gfx900 \ // RUN: %clang -### --target=x86_64-linux-gnu --offload-arch=gfx900 \
// RUN: -mcode-object-version=3 \ // RUN: -mcode-object-version=3 \
// RUN: --rocm-path=%S/Inputs/rocm %S/Inputs/hip_multiple_inputs/b.hip \ // RUN: --rocm-path=%S/Inputs/rocm %S/Inputs/hip_multiple_inputs/b.hip \
// RUN: 2>&1 | FileCheck %s --check-prefixes=ABI4 // RUN: 2>&1 | FileCheck %s --check-prefixes=ABI4
// Test -mcode-object-version=4 // Test -mcode-object-version=4
Show All 10 Lines
// RUN: 2>&1 | FileCheck %s --check-prefixes=NOABI4 // RUN: 2>&1 | FileCheck %s --check-prefixes=NOABI4
// Test -mcode-object-version=5 // Test -mcode-object-version=5
// RUN: %clang -### --target=x86_64-linux-gnu --offload-arch=gfx900 \ // RUN: %clang -### --target=x86_64-linux-gnu --offload-arch=gfx900 \
// RUN: -mcode-object-version=5 \ // RUN: -mcode-object-version=5 \
// RUN: --rocm-path=%S/Inputs/rocm %S/Inputs/hip_multiple_inputs/b.hip \ // RUN: --rocm-path=%S/Inputs/rocm %S/Inputs/hip_multiple_inputs/b.hip \
// RUN: 2>&1 | FileCheck %s --check-prefixes=ABI5 // RUN: 2>&1 | FileCheck %s --check-prefixes=ABI5
// Test -mcode-object-version=5 with old device library without abi_version_400.bc // Test -mcode-object-version=4 with old device library without abi_version_400.bc
// RUN: not %clang -### --target=x86_64-linux-gnu --offload-arch=gfx900 \ // RUN: %clang -### --target=x86_64-linux-gnu --offload-arch=gfx900 \
// RUN: -mcode-object-version=5 \ // RUN: -mcode-object-version=4 \
// RUN: --hip-device-lib-path=%S/Inputs/rocm/amdgcn/bitcode-no-abi-ver \ // RUN: --hip-device-lib-path=%S/Inputs/rocm/amdgcn/bitcode-no-abi-ver \
// RUN: --rocm-path=%S/Inputs/rocm %S/Inputs/hip_multiple_inputs/b.hip \ // RUN: --rocm-path=%S/Inputs/rocm %S/Inputs/hip_multiple_inputs/b.hip \
// RUN: 2>&1 | FileCheck %s --check-prefixes=NOABI5 // RUN: 2>&1 | FileCheck %s --check-prefixes=NOABI4
// ALL-NOT: error: // ALL-NOT: error:
// ALL: {{"[^"]*clang[^"]*"}} // ALL: {{"[^"]*clang[^"]*"}}
// RESDIR-SAME: "-mlink-builtin-bitcode" "[[DEVICELIB_DIR:[^"]+(/|\\\\)rocm_resource_dir(/|\\\\)lib(64)?(/|\\\\)amdgcn(/|\\\\).*]]hip.bc" // RESDIR-SAME: "-mlink-builtin-bitcode" "[[DEVICELIB_DIR:[^"]+(/|\\\\)rocm_resource_dir(/|\\\\)lib(64)?(/|\\\\)amdgcn(/|\\\\).*]]hip.bc"
// ROCMDIR-SAME: "-mlink-builtin-bitcode" "[[DEVICELIB_DIR:[^"]+(/|\\\\)rocm(/|\\\\)amdgcn(/|\\\\).*]]hip.bc" // ROCMDIR-SAME: "-mlink-builtin-bitcode" "[[DEVICELIB_DIR:[^"]+(/|\\\\)rocm(/|\\\\)amdgcn(/|\\\\).*]]hip.bc"
// ALL-SAME: "-mlink-builtin-bitcode" "[[DEVICELIB_DIR]]ocml.bc" // ALL-SAME: "-mlink-builtin-bitcode" "[[DEVICELIB_DIR]]ocml.bc"
Show All 40 Lines

lld/test/ELF/emulation-amdgpu.s

lld/test/ELF/lto/amdgcn-oses.ll

llvm/docs/AMDGPUUsage.rst

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

Show All 22 Lines
#include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/Support/AMDHSAKernelDescriptor.h" #include "llvm/Support/AMDHSAKernelDescriptor.h"
#include "llvm/Support/CommandLine.h" #include "llvm/Support/CommandLine.h"
#include "llvm/TargetParser/TargetParser.h" #include "llvm/TargetParser/TargetParser.h"
#include <optional> #include <optional>
#define GET_INSTRINFO_NAMED_OPS #define GET_INSTRINFO_NAMED_OPS
#define GET_INSTRMAP_INFO #define GET_INSTRMAP_INFO
#include "AMDGPUGenInstrInfo.inc" #include "AMDGPUGenInstrInfo.inc"
static llvm::cl::opt<unsigned> static llvm::cl::opt<unsigned>
lamb-jUnsubmitted
Done
ReplyInline Actions

We may also want to update this file here:

https://github.com/llvm/llvm-project/blob/e9569748def85a2f6bb8066e516a84e6933ef407/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp#L162

lamb-j: We may also want to update this file here: https://github.com/llvm/llvm…
cfangAuthorUnsubmitted
Done
ReplyInline Actions

You are right. Done.

cfang: You are right. Done.
AmdhsaCodeObjectVersion("amdhsa-code-object-version", llvm::cl::Hidden, AmdhsaCodeObjectVersion("amdhsa-code-object-version", llvm::cl::Hidden,
llvm::cl::desc("AMDHSA Code Object Version"), llvm::cl::desc("AMDHSA Code Object Version"),
llvm::cl::init(4)); llvm::cl::init(5));
namespace { namespace {
/// \returns Bit mask for given bit \p Shift and bit \p Width. /// \returns Bit mask for given bit \p Shift and bit \p Width.
unsigned getBitMask(unsigned Shift, unsigned Width) { unsigned getBitMask(unsigned Shift, unsigned Width) {
return ((1 << Width) - 1) << Shift; return ((1 << Width) - 1) << Shift;
} }
▲ Show 20 Lines • Show All 126 Lines • ▼ Show 20 Lines
unsigned getCodeObjectVersion(const Module &M) { unsigned getCodeObjectVersion(const Module &M) {
if (auto Ver = mdconst::extract_or_null<ConstantInt>( if (auto Ver = mdconst::extract_or_null<ConstantInt>(
M.getModuleFlag("amdgpu_code_object_version"))) { M.getModuleFlag("amdgpu_code_object_version"))) {
return (unsigned)Ver->getZExtValue() / 100; return (unsigned)Ver->getZExtValue() / 100;
} }
// Default code object version. // Default code object version.
return AMDHSA_COV4; return AMDHSA_COV5;
} }
unsigned getMultigridSyncArgImplicitArgPosition(unsigned CodeObjectVersion) { unsigned getMultigridSyncArgImplicitArgPosition(unsigned CodeObjectVersion) {
switch (CodeObjectVersion) { switch (CodeObjectVersion) {
case AMDHSA_COV2: case AMDHSA_COV2:
case AMDHSA_COV3: case AMDHSA_COV3:
case AMDHSA_COV4: case AMDHSA_COV4:
return 48; return 48;
▲ Show 20 Lines • Show All 2,595 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/crash-stack-address-O0.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/dropped_debug_info_assert.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constant-fold-vector-op.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sibling-call.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-tail-call.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.is.private.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.is.shared.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll

llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll

llvm/test/CodeGen/AMDGPU/addrspacecast-constantexpr.ll

llvm/test/CodeGen/AMDGPU/addrspacecast.gfx6.ll

llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll

llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa-call.ll

llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll

llvm/test/CodeGen/AMDGPU/attributor-noopt.ll

llvm/test/CodeGen/AMDGPU/blender-no-live-segment-at-def-implicit-def.ll

llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll

llvm/test/CodeGen/AMDGPU/call-alias-register-usage-agpr.ll

llvm/test/CodeGen/AMDGPU/call-alias-register-usage0.ll

llvm/test/CodeGen/AMDGPU/call-alias-register-usage1.ll

llvm/test/CodeGen/AMDGPU/call-alias-register-usage2.ll

llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll

llvm/test/CodeGen/AMDGPU/call-argument-types.ll

llvm/test/CodeGen/AMDGPU/call-waitcnt.ll

llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs-fixed-abi.ll

llvm/test/CodeGen/AMDGPU/cc-update.ll

llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll

llvm/test/CodeGen/AMDGPU/codegen-internal-only-func.ll

llvm/test/CodeGen/AMDGPU/collapse-endcf.ll

llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll

llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll

llvm/test/CodeGen/AMDGPU/dagcombine-lshr-and-cmp.ll

llvm/test/CodeGen/AMDGPU/ds_read2.ll

llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll

llvm/test/CodeGen/AMDGPU/elf-header-osabi.ll

llvm/test/CodeGen/AMDGPU/flat-scratch-init.ll

llvm/test/CodeGen/AMDGPU/fneg-fabs.ll

llvm/test/CodeGen/AMDGPU/gfx11-user-sgpr-init16-bug.ll

llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll

llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll

llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll

llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll

llvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll

llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll

llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll

llvm/test/CodeGen/AMDGPU/lds-frame-extern.ll

llvm/test/CodeGen/AMDGPU/lds-global-non-entry-func.ll

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.shared.ll

llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll

llvm/test/CodeGen/AMDGPU/lower-kernargs.ll

llvm/test/CodeGen/AMDGPU/lower-module-lds-via-hybrid.ll

llvm/test/CodeGen/AMDGPU/lower-module-lds-via-table.ll

llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll

llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll

llvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll

llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll

llvm/test/CodeGen/AMDGPU/promote-alloca-calling-conv.ll

llvm/test/CodeGen/AMDGPU/reqd-work-group-size.ll

llvm/test/CodeGen/AMDGPU/sgpr-spill-no-vgprs.ll

llvm/test/CodeGen/AMDGPU/sgpr-spill-update-only-slot-indexes.ll

llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll

llvm/test/CodeGen/AMDGPU/sopk-no-literal.ll

llvm/test/CodeGen/AMDGPU/spill-m0.ll

llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll

llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-all-any.ll

llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-all-not-supported.ll

llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-all-off.ll

llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-all-on.ll

llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-any-off-1.ll

llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-any-off-2.ll

llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-any-on-1.ll

llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-any-on-2.ll

llvm/test/CodeGen/AMDGPU/tid-one-func-xnack-any.ll

llvm/test/CodeGen/AMDGPU/tid-one-func-xnack-not-supported.ll

llvm/test/CodeGen/AMDGPU/tid-one-func-xnack-off.ll

llvm/test/CodeGen/AMDGPU/tid-one-func-xnack-on.ll

llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll

llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll

llvm/test/CodeGen/AMDGPU/vgpr-spill-placement-issue61083.ll

llvm/test/CodeGen/AMDGPU/vgpr_constant_to_sgpr.ll

llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-gfx10.s

llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-gfx90a.s

llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-sgpr.s

llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-vgpr.s

llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-zeroed-gfx10.s

openmp/libomptarget/test/offloading/thread_limit.c