- User Since
- Nov 30 2015, 11:41 AM (193 w, 5 d)
May 8 2019
Mar 29 2019
Mar 26 2019
Mar 25 2019
I am working on a regression caused by this patch. It is a memory access fault actually.
However, if we put back the original consition, my test would pass.
Mar 15 2019
Add comment to the test
update the test with update_test_checks.py
Mar 14 2019
Fix a typo and add a test.
Mar 13 2019
Feb 26 2019
Feb 20 2019
Feb 18 2019
Remove the unused Target Instruction Info argument in a couple functions.
Use MachineInstr::mayAlias to replace areMemAccessesTriviallyDisjoint in LoadStoreOptimizer pass.
Feb 15 2019
Jan 16 2019
Update based on reviewer's suggestions:
- addrspace(0) is not needed.
Update based on the comments from the reviewers:
Jan 15 2019
update the test based on the following suggestion:
There should be no unnamed variables left.
Jan 8 2019
Jan 4 2019
Jan 3 2019
Dec 17 2018
Cheap check first.
Dec 13 2018
Dec 11 2018
Dec 10 2018
Dec 5 2018
Dec 3 2018
Oct 15 2018
Add test for non-uniform case.
Oct 5 2018
Sep 25 2018
May 17 2018
Thanks Justin for your comment. I added Daniel as a reviewer.
May 16 2018
Updated the test based on the comments
Right. Reverse Post Order (RPO) should be the fundamental order. But apparently there are some cases that pure RPO does not work.
That's the reason loop depth was introduced to guard the ordering of the nodes.
We need this fix to unblock some important tasks. So if there is no additional comments, we need the permission
to integrate the patch. Thanks.
May 15 2018
May 10 2018
May 9 2018
Any additional comments/suggestions? Thanks!
Update based on Matt's comments.
May 7 2018
Correct indentation error and typo.
May 4 2018
May 3 2018
Handle the case that the infinite loop is controlled by a conditional branch. In such case, the two edges of the branch
are both backedges.
May 2 2018
Update the test:
Update the test:
- Remove the -amdgiz from the triple since it is no longer necessary;
- Add "-data-layout=A5" to explicitly specify the data layout for address space 5 for alloca
- and to remove the "target:" line for the same data layout purpose.
May 1 2018
Apr 27 2018
Apr 26 2018
What do you think of the test?
What should we do if we don't add the following line?
target datalayout = "A5"
What do you think of the test? Thanks;
Apr 25 2018
Combine !isAtomic and !isVolatile checks as isSimple
Fix addrspacecast in the test since generic address space is 0 (default) now. Thanks, Sam!
Apr 24 2018
Add a test.
Apr 23 2018
Add reviewers and ping.
Apr 12 2018
Apr 3 2018
Feb 16 2018
Update LIT tests before landing since the patch was developed a long time back.
Feb 15 2018
full context diff
Feb 14 2018
Feb 8 2018
Feb 7 2018
Jan 31 2018
Update tests to expose the LLVM-ERROR withput the patch.
Jan 29 2018
For MIMG, to determine the data size for d16, we need to know whether the target has the feature UnpackedD16VMem (gfx8.0),
- if that feature is set, the data size is the same as without D16 bit set;
- if that feature is not set, then the data size is "half" of the size because we can packed two f16 into one register.
Add Disassembler tests based on Reviewers' suggestion. Thanks.
Jan 26 2018
Jan 25 2018
Jan 18 2018
Patch committed to trunk:
Patched updated! Request for reviewer's check. Thanks.
<still I could not receive message of the diff update>
Update based on Matt's suggestion: Factor out the common defs.
Jan 17 2018
Jan 16 2018
Don't know why I didn't received a message after I updated the patch. So ping here with the updating message:
Jan 15 2018
- sync with the buffer d16 support patch to reuse some of the functionalities;
- Remove unnecessary functions that print "d16" in the AsmPrinter;
- Update based on Matt's other comments.