[DAG] Fold (srl (shl x, c1), c2) -> and(shl/srl(x, c3), m)

[RKSimon]

Summary

Similar to the existing (shl (srl x, c1), c2) fold

Part of the work to fix the regressions in D77804

[RKSimon]

rebase

[RKSimon]

rebase

[foad]

Surely the (srl (shl x, c1), c2) form is better for targets which aren't good at doing an AND-with-large-immediate-value. Is this supposed to be a canonicalization, which targets will undo later as appropriate?

[RKSimon]

In D125836#3577140, @foad wrote:

Surely the (srl (shl x, c1), c2) form is better for targets which aren't good at doing an AND-with-large-immediate-value. Is this supposed to be a canonicalization, which targets will undo later as appropriate?

We have the TLI shouldFoldConstantShiftPairToMask callback to allow targets to control this.

[craig.topper]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

9444

Why is the last SDLoc from N0?

[RKSimon]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

9444

It was copy+pasted from the (shl (srl x, c1), c2) variant

[craig.topper]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

9444

Is that correct? Can you swap the order of debug locs? The N0 debug loc is now after the N location in the DAG

[RKSimon]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

9444

I'll take a look

[RKSimon]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

9444

D127772

[RKSimon]

Fix SDLoc mismatch

[RKSimon]

Extend AArch64TargetLowering::shouldFoldConstantShiftPairToMask so that we don't lose the srl(shl(x,c1),c2) pair if it would likely break a UBFX pattern.

[dmgreen]

The AArch64 change sounds OK to me.

[RKSimon]

Thank @dmgreen - does anyone have more comments?

[spatel]

LGTM - noted a close call in x86 tests, but that can be addressed if we find real regressions.

llvm/test/CodeGen/X86/shift-mask.ll

597

This and the next diff might be worse depending on uarch, so that suggests a possible refinement for the x86 TLI hook for 64-bit integer.