[TableGen][DirectX] Add tableGen backend to generate DXIL operation for DirectX backend.

[python3kgae]

Summary

A new tableGen backend gen-dxil-enum is added to generate enum for DXIL operation and operation class.

A new file "DXILConstants.inc" will be generated when build DirectX target which include the enums.

More tableGen backends will be added to replace manually written table in DirectX backend.
The unused fields in dxil_inst will be used in future PR.

[nhaehnle]

+1 for creating this stuff using TableGen.

Part of it may be my unfamiliarity with the finer points of DXIL, part of it may be that not enough of what you're planning to do with it is visible, but some of the TableGen dialect here is quite unclear. What's a counter, what's a class, what's a category? What do those things mean and why should TableGen have to care?

It may be helpful if you augmented this patch with a bit more than just sin...

llvm/lib/Target/DirectX/DXIL.td

37–38

It's hard to tell how you're going to use these variables, but I suspect that a more idiomatic solution would be to have DxilClass and Category classes here; they can be dummy "marker" classes, like so:

class dxil_class;
class dxil_category;

def unary : dxil_class;
def unary_float : dxil_category;

51

How about making this of type Intrinsic so you can have a more "type-safe" link between dxil_inst and the underlying intrinsics?

Okay, so that won't actually work verbatim if you sometimes want to not have an llvm_intrinsic. What you could do, and what aligns more with how TableGen is used in other backends, would be a second class. Basically, remove this variable here and add a class:

class dxil_map_intrinsic<Intrinsic llvm_intrinsic_> { Intrinsic llvm_intrinsic = llvm_intrinsic_; }

... which you can then use below as:

def Sin : dxil_op<"Sin", 13, "Unary", "returns sine(theta) for theta in radians.",
              "half;float;", "rn",
              [
                dxil_param<0, "$o", "", "operation result">,
                dxil_param<1, "i32", "opcode", "DXIL opcode">,
                dxil_param<2, "$o", "value", "input value">
              ]>,
             dxil_map_intrinsic<int_sin>;

53

What's a "counter"?

[beanz]

llvm/lib/Target/DirectX/DXIL.td

37

Does DXIL Class need to be a string field here or can it just be the TableGen record class?

[python3kgae]

llvm/lib/Target/DirectX/DXIL.td

37

I'll change it to TableGen record class.

37–38

dxil_class is to group dxil operations which can share same function signature. Dxil operations with same dxil class will share same function declaration to reduce number of function declarations added for dxil operations.

dxil_category is not that important. It is used to sort dxil operation and dxil class so similar operation/class are together in the enum.

I'll add the "marker" classes.

51

Thanks for the suggestion.
I'll add dxil_map_intrinsic.

53

Counter is used for stats like how many atomic/float/uint/int/... instructions are used in the program.

It will be added in later PR, but not a high priority right now.

[python3kgae]

Update for comments.

[python3kgae]

Add umax.

[python3kgae]

Rename to prepare for make all tableGen work for DXIL operation in one tableGen backend.

[python3kgae]

Gentle Ping.

The intrinsic map is added in https://reviews.llvm.org/D125519 which dependent on this PR.

[bogner]

LGTM with a few minor nitpicks / clean ups

llvm/lib/Target/DirectX/DXIL.td

32

Why is this comment quoted?

llvm/test/CodeGen/DirectX/umax.ll

5 ↗

(On Diff #434725)

Probably better to put these check lines in the function bodies near what they're checking, and add CHECK-LABEL for the function names to anchor them. It doesn't matter much when the test is small like this, but it's good practice and makes it easier to add more test cases in the future

11 ↗

(On Diff #434725)

Better to name functions after what they're testing (test_umax_i32 or something), for similar reasons as my comment about CHECKs - it makes it easier / more obvious when adding more tests to a test file.

34 ↗

(On Diff #434725)

You can delete the llvm.module.flags and llvm.ident metadata, it won't affect this test

[python3kgae]

Clean comments and test.

[python3kgae]

Updated the comments and test.
Thanks for the review.

llvm/lib/Target/DirectX/CMakeLists.txt

 add_llvm_component_group(DirectX)
 
 set(LLVM_TARGET_DEFINITIONS DirectX.td)
 
 tablegen(LLVM DirectXGenSubtargetInfo.inc -gen-subtarget)
 
+set(LLVM_TARGET_DEFINITIONS DXIL.td)
+tablegen(LLVM DXILOperation.inc -gen-dxil-enum)
+
 add_public_tablegen_target(DirectXCommonTableGen)
 
 add_llvm_target(DirectXCodeGen
   DirectXSubtarget.cpp
   DirectXTargetMachine.cpp
   DXILOpLowering.cpp
   DXILPointerType.cpp
   DXILPrepare.cpp

llvm/lib/Target/DirectX/DXIL.td

+//- DXIL.td - Describe DXIL operation -------------------------*- tablegen -*-//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+///
+/// \file
+/// This is a target description file for DXIL operation.
+///
+//===----------------------------------------------------------------------===//
+
+include "llvm/IR/Intrinsics.td"
+
+class dxil_class;
+class dxil_category;
+
+def Unary : dxil_class;
+def unary_float : dxil_category;
+
+
+// "The parameter description for a DXIL instruction"
+class dxil_param<int _pos, string type, string _name, string _doc,
+                 bit _is_const = 0, string _enum_name = "",
+                 int _max_value = 0> {
+  int pos = _pos;           // position in parameter list
+  string llvm_type = type; // llvm type name, $o for overload, $r for resource
+                           // type, $cb for legacy cbuffer, $u4 for u4 struct
+  string name = _name;      // short, unique name
+  string doc = _doc;        // the documentation description of this parameter
+  bit is_const =
+      _is_const; // whether this argument requires a constant value in the IR
+  string enum_name = _enum_name; // the name of the enum type if applicable
+  int max_value =
+      _max_value; // the maximum value for this parameter if applicable
+}
+
+// "A representation for a DXIL instruction"
+class dxil_inst<string _name> {
+  string name = _name; // short, unique name
+
+  string dxil_op = "";       // name of DXIL operation
+  int dxil_opid = 0;         // ID of DXIL operation
+  dxil_class  op_class;      // name of the opcode class
+  dxil_category category;    // classification for this instruction
+  string doc = "";           // the documentation description of this instruction
+  list<dxil_param> ops = []; // the operands that this instruction takes
+  string oload_types = "";   // overload types if applicable
+  string fn_attr = "";       // attribute shorthands: rn=does not access
+                             // memory,ro=only reads from memory,
+  bit is_deriv = 0;          // whether this is some kind of derivative
+  bit is_gradient = 0;       // whether this requires a gradient calculation
+  bit is_feedback = 0;       // whether this is a sampler feedback op
+  bit is_wave = 0; // whether this requires in-wave, cross-lane functionality
+  bit requires_uniform_inputs = 0; // whether this operation requires that all
+                                   // of its inputs are uniform across the wave
+  // Group dxil operation for stats.
+  // Like how many atomic/float/uint/int/... instructions used in the program.
+  list<string> stats_group = [];
+}
+
+class dxil_op<string name, int code_id, dxil_class code_class, dxil_category op_category, string _doc,
+              string _oload_types, string _fn_attr, list<dxil_param> op_params,
+              list<string> _stats_group = []> : dxil_inst<name> {
+  let dxil_op = name;
+  let dxil_opid = code_id;
+  let doc = _doc;
+  let ops = op_params;
+  let op_class = code_class;
+  let category = op_category;
+  let oload_types = _oload_types;
+  let fn_attr = _fn_attr;
+  let stats_group = _stats_group;
+}
+
+// The intrinsic which map directly to this dxil op.
+class dxil_map_intrinsic<Intrinsic llvm_intrinsic_> { Intrinsic llvm_intrinsic = llvm_intrinsic_; }
+
+def Sin : dxil_op<"Sin", 13, Unary, unary_float, "returns sine(theta) for theta in radians.",
+              "half;float;", "rn",
+              [
+                dxil_param<0, "$o", "", "operation result">,
+                dxil_param<1, "i32", "opcode", "DXIL opcode">,
+                dxil_param<2, "$o", "value", "input value">
+              ],
+              ["floats"]>,
+             dxil_map_intrinsic<int_sin>;

llvm/lib/Target/DirectX/DXILConstants.h

 //===- DXILConstants.h - Essential DXIL constants -------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file This file contains essential DXIL constants.
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_DIRECTX_DXILCONSTANTS_H
 #define LLVM_LIB_TARGET_DIRECTX_DXILCONSTANTS_H
 
 namespace llvm {
 namespace DXIL {
-// Enumeration for operations specified by DXIL
-enum class OpCode : unsigned {
-  Sin = 13, // returns sine(theta) for theta in radians.
-};
-// Groups for DXIL operations with equivalent function templates
-enum class OpCodeClass : unsigned {
-  Unary,
-};
+
+#define DXIL_OP_ENUM
+#include "DXILOperation.inc"
+#undef DXIL_OP_ENUM
 
 } // namespace DXIL
 } // namespace llvm
 
 #endif

llvm/utils/TableGen/CMakeLists.txt

add_tablegen(llvm-tblgen LLVM
   DAGISelMatcherGen.cpp
   DAGISelMatcherOpt.cpp
   DAGISelMatcher.cpp
   DecoderEmitter.cpp
   DFAEmitter.cpp
   DFAPacketizerEmitter.cpp
   DirectiveEmitter.cpp
   DisassemblerEmitter.cpp
+  DXILEmitter.cpp
   ExegesisEmitter.cpp
   FastISelEmitter.cpp
   GICombinerEmitter.cpp
   GlobalISelEmitter.cpp
   InfoByHwMode.cpp
   InstrInfoEmitter.cpp
   InstrDocsEmitter.cpp
   IntrinsicEmitter.cpp

llvm/utils/TableGen/DXILEmitter.cpp

+//===- DXILEmitter.cpp - DXIL operation Emitter ---------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// DXILEmitter uses the descriptions of DXIL operation to construct enum and
+// helper functions for DXIL operation.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/ADT/MapVector.h"
+#include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/ADT/StringSet.h"
+#include "llvm/TableGen/Error.h"
+#include "llvm/TableGen/Record.h"
+
+using namespace llvm;
+
+namespace {
+
+struct DXILShaderModel {
+  int Major;
+  int Minor;
+};
+struct DXILParam {
+  int Pos;        // position in parameter list
+  StringRef Type; // llvm type name, $o for overload, $r for resource
+                  // type, $cb for legacy cbuffer, $u4 for u4 struct
+  StringRef Name; // short, unique name
+  StringRef Doc;  // the documentation description of this parameter
+  bool IsConst;   // whether this argument requires a constant value in the IR
+  StringRef EnumName; // the name of the enum type if applicable
+  int MaxValue;       // the maximum value for this parameter if applicable
+  DXILParam(const Record *R) {
+    Name = R->getValueAsString("name");
+    Pos = R->getValueAsInt("pos");
+    Type = R->getValueAsString("llvm_type");
+    if (R->getValue("doc"))
+      Doc = R->getValueAsString("doc");
+    IsConst = R->getValueAsBit("is_const");
+    EnumName = R->getValueAsString("enum_name");
+    MaxValue = R->getValueAsInt("max_value");
+  }
+};
+
+struct DXILOperationData {
+  StringRef Name; // short, unique name
+
+  StringRef DXILOp;      // name of DXIL operation
+  int DXILOpID;          // ID of DXIL operation
+  std::string DXILClass; // name of the opcode class
+  std::string Category;  // classification for this instruction
+  StringRef Doc;         // the documentation description of this instruction
+
+  SmallVector<DXILParam> Params; // the operands that this instruction takes
+  StringRef OverloadTypes;       // overload types if applicable
+  StringRef FnAttr;              // attribute shorthands: rn=does not access
+                                 // memory,ro=only reads from memory,
+  bool IsDeriv;                  // whether this is some kind of derivative
+  bool IsGradient;               // whether this requires a gradient calculation
+  bool IsFeedback;               // whether this is a sampler feedback op
+  bool IsWave; // whether this requires in-wave, cross-lane functionality
+  bool RequiresUniformInputs; // whether this operation requires that all
+                              // of its inputs are uniform across the wave
+  SmallVector<StringRef, 4>
+      ShaderStages; // shader stages to which this applies, empty for all.
+  DXILShaderModel ShaderModel;           // minimum shader model required
+  DXILShaderModel ShaderModelTranslated; // minimum shader model required with
+                                         // translation by linker
+  SmallVector<StringRef, 4> counters;    // counters for this inst.
+  DXILOperationData(const Record *R) {
+    Name = R->getValueAsString("name");
+    DXILOp = R->getValueAsString("dxil_op");
+    DXILOpID = R->getValueAsInt("dxil_opid");
+    DXILClass = R->getValue("op_class")->getValue()->getAsString();
+    Category = R->getValue("category")->getValue()->getAsString();
+
+    Doc = R->getValueAsString("doc");
+    ListInit *ParamList = R->getValueAsListInit("ops");
+    for (unsigned i = 0; i < ParamList->size(); ++i) {
+      Record *Param = ParamList->getElementAsRecord(i);
+      Params.emplace_back(DXILParam(Param));
+    }
+    OverloadTypes = R->getValueAsString("oload_types");
+    FnAttr = R->getValueAsString("fn_attr");
+  }
+};
+} // end anonymous namespace
+
+static void emitDXILOpEnum(DXILOperationData &DXILOp, raw_ostream &OS) {
+  // Name = ID, // Doc
+  OS << DXILOp.Name << " = " << DXILOp.DXILOpID << ", // " << DXILOp.Doc
+     << "\n";
+}
+
+static std::string buildCategoryStr(StringSet<> &Cetegorys) {
+  std::string Str;
+  raw_string_ostream OS(Str);
+  for (auto &It : Cetegorys) {
+    OS << " " << It.getKey();
+  }
+  return OS.str();
+}
+
+static void emitDXILEnums(std::vector<DXILOperationData> &DXILOps,
+                          raw_ostream &OS) {
+  // Sort by Category + OpName.
+  std::sort(DXILOps.begin(), DXILOps.end(),
+            [](DXILOperationData &A, DXILOperationData &B) {
+              // Group by Category first.
+              if (A.Category == B.Category)
+                // Inside same Category, order by OpName.
+                return A.DXILOp < B.DXILOp;
+              else
+                return A.Category < B.Category;
+            });
+
+  OS << "// Enumeration for operations specified by DXIL\n";
+  OS << "enum class OpCode : unsigned {\n";
+
+  StringMap<StringSet<>> ClassMap;
+  StringRef PrevCategory = "";
+  for (auto &DXILOp : DXILOps) {
+    StringRef Category = DXILOp.Category;
+    if (Category != PrevCategory) {
+      OS << "\n// " << Category << "\n";
+      PrevCategory = Category;
+    }
+    emitDXILOpEnum(DXILOp, OS);
+    auto It = ClassMap.find(DXILOp.DXILClass);
+    if (It != ClassMap.end()) {
+      It->second.insert(DXILOp.Category);
+    } else {
+      ClassMap[DXILOp.DXILClass].insert(DXILOp.Category);
+    }
+  }
+
+  OS << "\n};\n\n";
+
+  std::vector<std::pair<std::string, std::string>> ClassVec;
+  for (auto &It : ClassMap) {
+    ClassVec.emplace_back(
+        std::make_pair(It.getKey().str(), buildCategoryStr(It.second)));
+  }
+  // Sort by Category + ClassName.
+  std::sort(ClassVec.begin(), ClassVec.end(),
+            [](std::pair<std::string, std::string> &A,
+               std::pair<std::string, std::string> &B) {
+              StringRef ClassA = A.first;
+              StringRef CategoryA = A.second;
+              StringRef ClassB = B.first;
+              StringRef CategoryB = B.second;
+              // Group by Category first.
+              if (CategoryA == CategoryB)
+                // Inside same Category, order by ClassName.
+                return ClassA < ClassB;
+              else
+                return CategoryA < CategoryB;
+            });
+
+  OS << "// Groups for DXIL operations with equivalent function templates\n";
+  OS << "enum class OpCodeClass : unsigned {\n";
+  PrevCategory = "";
+  for (auto It : ClassVec) {
+
+    StringRef Category = It.second;
+    if (Category != PrevCategory) {
+      OS << "\n// " << Category << "\n";
+      PrevCategory = Category;
+    }
+    StringRef Name = It.first;
+    OS << Name << ",\n";
+  }
+  OS << "\n};\n\n";
+}
+
+namespace llvm {
+// Emit enum declaration for DXIL.
+void EmitDXILEnum(RecordKeeper &Records, raw_ostream &OS) {
+  std::vector<Record *> Ops = Records.getAllDerivedDefinitions("dxil_op");
+  OS << "// Generated code, do not edit.\n";
+  OS << "\n";
+  std::vector<DXILOperationData> DXILOps;
+  DXILOps.reserve(Ops.size());
+  for (auto *Record : Ops) {
+    DXILOps.emplace_back(DXILOperationData(Record));
+  }
+
+  OS << "#ifdef DXIL_OP_ENUM\n";
+  emitDXILEnums(DXILOps, OS);
+  OS << "#endif\n\n";
+
+  OS << "\n";
+}
+
+} // namespace llvm

llvm/utils/TableGen/TableGen.cpp

enum ActionType {
   GenX86EVEX2VEXTables,
   GenX86FoldTables,
   GenX86MnemonicTables,
   GenRegisterBank,
   GenExegesis,
   GenAutomata,
   GenDirectivesEnumDecl,
   GenDirectivesEnumImpl,
+  GenDXILEnum,
 };
 
 namespace llvm {
 cl::opt<bool> EmitLongStrLiterals(
     "long-string-literals",
     cl::desc("when emitting large string tables, prefer string literals over "
              "comma-separated char literals. This can be a readability and "
              "compile-time performance win, but upsets some compilers"),
cl::values(
         clEnumValN(GenRegisterBank, "gen-register-bank",
                    "Generate registers bank descriptions"),
         clEnumValN(GenExegesis, "gen-exegesis",
                    "Generate llvm-exegesis tables"),
         clEnumValN(GenAutomata, "gen-automata", "Generate generic automata"),
         clEnumValN(GenDirectivesEnumDecl, "gen-directive-decl",
                    "Generate directive related declaration code (header file)"),
         clEnumValN(GenDirectivesEnumImpl, "gen-directive-impl",
-                   "Generate directive related implementation code")));
+                   "Generate directive related implementation code"),
+        clEnumValN(GenDXILEnum, "gen-dxil-enum", "Generate enum for DXIL")));
 
 cl::OptionCategory PrintEnumsCat("Options for -print-enums");
 cl::opt<std::string> Class("class", cl::desc("Print Enum list for this class"),
                            cl::value_desc("class name"),
                            cl::cat(PrintEnumsCat));
 
 bool LLVMTableGenMain(raw_ostream &OS, RecordKeeper &Records) {
   switch (Action) {
case GenAutomata:
     EmitAutomata(Records, OS);
     break;
   case GenDirectivesEnumDecl:
     EmitDirectivesDecl(Records, OS);
     break;
   case GenDirectivesEnumImpl:
     EmitDirectivesImpl(Records, OS);
     break;
+  case GenDXILEnum:
+    EmitDXILEnum(Records, OS);
+    break;
   }
 
   return false;
 }
 }
 
 int main(int argc, char **argv) {
   InitLLVM X(argc, argv);

llvm/utils/TableGen/TableGenBackends.h

 void EmitX86EVEX2VEXTables(RecordKeeper &RK, raw_ostream &OS);
 void EmitX86FoldTables(RecordKeeper &RK, raw_ostream &OS);
 void EmitX86MnemonicTables(RecordKeeper &RK, raw_ostream &OS);
 void EmitRegisterBank(RecordKeeper &RK, raw_ostream &OS);
 void EmitExegesis(RecordKeeper &RK, raw_ostream &OS);
 void EmitAutomata(RecordKeeper &RK, raw_ostream &OS);
 void EmitDirectivesDecl(RecordKeeper &RK, raw_ostream &OS);
 void EmitDirectivesImpl(RecordKeeper &RK, raw_ostream &OS);
+void EmitDXILEnum(RecordKeeper &RK, raw_ostream &OS);
 
 } // End llvm namespace
 
 #endif