[ELF][AArch64] Fix unneeded thunk for branches to hidden undefined weak

[MaskRay]

Summary

Similar to D119787 for PPC64.

A hidden undefined weak may change its binding to local before some
isUndefinedWeak code, so some isUndefinedWeak code needs to be changed to
isUndefined. The undefined non-weak case has been errored, so just using
isUndefined is fine.

The Linux kernel recently has a usage that a branch from 0xffff800008491ee0
references a hidden undefined weak symbol vfio_group_set_kvm.
It relies on the behavior that a branch to undefined weak resolving to the next
instruction, otherwise it'd see spurious relocation out of range errors.

Fixes https://github.com/ClangBuiltLinux/linux/issues/1624

[peter.smith]

LGTM. One small suggestion for the comment.

lld/ELF/Arch/AArch64.cpp

260

Nit: An undefined non-weak symbol will have been errored.

lld/ELF/Arch/AArch64.cpp

relocateNoSym(buf, R_AARCH64_ADR_PREL_PG_HI21,
                 getAArch64Page(gotPltEntryAddr) - getAArch64Page(pltEntryAddr));
   relocateNoSym(buf + 4, R_AARCH64_LDST64_ABS_LO12_NC, gotPltEntryAddr);
   relocateNoSym(buf + 8, R_AARCH64_ADD_ABS_LO12_NC, gotPltEntryAddr);
 }
 
 bool AArch64::needsThunk(RelExpr expr, RelType type, const InputFile *file,
                          uint64_t branchAddr, const Symbol &s,
                          int64_t a) const {
-  // If s is an undefined weak symbol and does not have a PLT entry then it
-  // will be resolved as a branch to the next instruction.
-  if (s.isUndefWeak() && !s.isInPlt())
+  // If s is an undefined weak symbol and does not have a PLT entry then it will
+  // be resolved as a branch to the next instruction. If it is hidden, its
+  // binding has been converted to local, so we just check isUndefined() here. A
+  // undefined non-weak symbol will have been errored.
+  if (s.isUndefined() && !s.isInPlt())
     return false;
   // ELF for the ARM 64-bit architecture, section Call and Jump relocations
   // only permits range extension thunks for R_AARCH64_CALL26 and
   // R_AARCH64_JUMP26 relocation types.
   if (type != R_AARCH64_CALL26 && type != R_AARCH64_JUMP26 &&
       type != R_AARCH64_PLT32)
     return false;
   uint64_t dst = expr == R_PLT_PC ? s.getPltVA() : s.getVA(a);

lld/ELF/InputSection.cpp

case R_RISCV_PC_INDIRECT: {
     return 0;
   }
   case R_PC:
   case R_ARM_PCA: {
     uint64_t dest;
     if (expr == R_ARM_PCA)
       // Some PC relative ARM (Thumb) relocations align down the place.
       p = p & 0xfffffffc;
-    if (sym.isUndefWeak()) {
+    if (sym.isUndefined()) {
       // On ARM and AArch64 a branch to an undefined weak resolves to the next
       // instruction, otherwise the place. On RISCV, resolve an undefined weak
       // to the same instruction to cause an infinite loop (making the user
       // aware of the issue) while ensuring no overflow.
+      // Note: if the symbol is hidden, its binding has been converted to local,
+      // so we just check isUndefined() here.
       if (config->emachine == EM_ARM)
         dest = getARMUndefinedRelativeWeakVA(type, a, p);
       else if (config->emachine == EM_AARCH64)
         dest = getAArch64UndefinedRelativeWeakVA(type, p) + a;
       else if (config->emachine == EM_PPC)
         dest = p;
       else if (config->emachine == EM_RISCV)
         dest = getRISCVUndefinedRelativeWeakVA(type, p) + a;

lld/test/ELF/aarch64-undefined-weak.s

 // REQUIRES: aarch64
 // RUN: llvm-mc -filetype=obj -triple=aarch64-none-linux %s -o %t.o
 // RUN: ld.lld --image-base=0x10000000 %t.o -o %t
 // RUN: llvm-objdump -d --no-show-raw-insn %t | FileCheck %s
 
 // Check that the ARM 64-bit ABI rules for undefined weak symbols are applied.
 // Branch instructions are resolved to the next instruction. Undefined
 // Symbols in relative are resolved to the place so S - P + A = A.
 // We place the image-base at 0x10000000 to test that a range extensions thunk
 // is not generated.
  .weak target
 
+.weak undefweak2
+.hidden undefweak2
+
  .text
  .global _start
 _start:
 // R_AARCH64_JUMP26
  b target
 // R_AARCH64_CALL26
  bl target
 // R_AARCH64_CONDBR19

  .word target - .
 // R_AARCH64_PREL64
  .xword target - .
 // R_AARCH64_PREL16
  .hword target - .
 // R_AARCH64_PLT32
  .word target@PLT - .
 
+bl_undefweak2:
+ bl undefweak2
+
 // CHECK: Disassembly of section .text:
 // CHECK-EMPTY:
 // CHECK-NEXT: 0000000010010120 <_start>:
 // CHECK-NEXT: 10010120: b       0x10010124
 // CHECK-NEXT: 10010124: bl      0x10010128
 // CHECK-NEXT: 10010128: b.eq    0x1001012c
 // CHECK-NEXT: 1001012c: cbz     x1, 0x10010130
 // CHECK-NEXT: 10010130: adr     x0, #0
 // CHECK-NEXT: 10010134: adrp    x0, 0x10010000
 // CHECK-NEXT: 10010138: ldr     x8, 0x10010138
 // CHECK:      1001013c: 00 00 00 00     .word   0x00000000
 // CHECK-NEXT: 10010140: 00 00 00 00     .word   0x00000000
 // CHECK-NEXT: 10010144: 00 00 00 00     .word   0x00000000
 // CHECK-NEXT: 10010148: 00 00 00 00     .word   0x00000000
 // CHECK-NEXT: 1001014c: 00 00           .short  0x0000
+// CHECK-LABEL: <bl_undefweak2>:
+// CHECK-NEXT:    bl {{.*}} <bl_undefweak2+0x4>