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Differential D121504

[DAGCombine] add tests for bswap-shift optimization
ClosedPublic

Authored by Chenbing.Zheng on Mar 11 2022, 6:53 PM.

Details

Reviewers
craig.topper
frasercrmck
RKSimon
lebedev.ri
luismarques
asb
benshi001
spatel
Commits
rG6a01b676cfb2: [DAGCombine] add tests for bswap-shift optimization
Summary

This patch add some tests to show some optimization opportunities for bswap-shift.

Diff Detail

Event Timeline

Chenbing.Zheng created this revision.Mar 11 2022, 6:53 PM
Herald added a project: Restricted Project. · View Herald TranscriptMar 11 2022, 6:53 PM
Herald added subscribers: luke957, apazos, sameer.abuasal and 17 others. · View Herald Transcript
Chenbing.Zheng requested review of this revision.Mar 11 2022, 6:53 PM
Herald added subscribers: llvm-commits, • pcwang-thead, jacquesguan, MaskRay. · View Herald TranscriptMar 11 2022, 6:53 PM
Chenbing.Zheng mentioned this in D120648: [DAGCombine] fold (bswap(srl (bswap c), 8*x)) -> (shl c, 8*x).Mar 11 2022, 7:11 PM
Harbormaster completed remote builds in B153871: Diff 414785.Mar 11 2022, 7:54 PM
Chenbing.Zheng updated this revision to Diff 418511.Mar 28 2022, 1:11 AM
Chenbing.Zheng retitled this revision from [DAGCombine] precommit tests for (bswap(srl (bswap c), x)) -> (shl c, x) to [DAGCombine] add tests for bswap-shift optimization.
Chenbing.Zheng edited the summary of this revision. (Show Details)
Chenbing.Zheng added a reviewer: spatel.
Herald added a subscriber: StephenFan. · View Herald TranscriptMar 28 2022, 1:11 AM
Chenbing.Zheng set the repository for this revision to rG LLVM Github Monorepo.Mar 28 2022, 1:13 AM
RKSimon added inline comments.Mar 28 2022, 5:14 AM
llvm/test/CodeGen/X86/combine-bswap.ll
43

Please can you add one i16 + i64 test case each as well? i16 as it lowers to a rotate and i64 so we can check its correctly handled on 32-bit targets

Chenbing.Zheng updated this revision to Diff 418759.Mar 28 2022, 7:23 PM

address comment

RKSimon accepted this revision.Mar 29 2022, 12:49 AM

LGTM

This revision is now accepted and ready to land.Mar 29 2022, 12:49 AM
This revision was landed with ongoing or failed builds.Mar 29 2022, 1:37 AM
Closed by commit rG6a01b676cfb2: [DAGCombine] add tests for bswap-shift optimization (authored by Chenbing.Zheng). · Explain Why
This revision was automatically updated to reflect the committed changes.
Chenbing.Zheng added a commit: rG6a01b676cfb2: [DAGCombine] add tests for bswap-shift optimization.
Harbormaster completed remote builds in B156676: Diff 418759.Mar 29 2022, 9:27 PM

Revision Contents

PathSize
llvm/
test/
CodeGen/
RISCV/
271 lines
X86/
141 lines

Diff 418818

llvm/test/CodeGen/RISCV/bswap-shift.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+zbb -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefixes=RV32ZB
; RUN: llc -mtriple=riscv64 -mattr=+zbb -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefixes=RV64ZB
; RUN: llc -mtriple=riscv32 -mattr=+zbkb -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefixes=RV32ZB
; RUN: llc -mtriple=riscv64 -mattr=+zbkb -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefixes=RV64ZB
; TODO: These tests can be optmised, with x%8 == 0
; fold (bswap(srl (bswap c), x)) -> (shl c, x)
; fold (bswap(shl (bswap c), x)) -> (srl c, x)
declare i16 @llvm.bswap.i16(i16)
declare i32 @llvm.bswap.i32(i32)
declare i64 @llvm.bswap.i64(i64)
define i16 @test_bswap_srli_7_bswap_i16(i16 %a) nounwind {
; RV32ZB-LABEL: test_bswap_srli_7_bswap_i16:
; RV32ZB: # %bb.0:
; RV32ZB-NEXT: rev8 a0, a0
; RV32ZB-NEXT: srli a0, a0, 23
; RV32ZB-NEXT: rev8 a0, a0
; RV32ZB-NEXT: srli a0, a0, 16
; RV32ZB-NEXT: ret
;
; RV64ZB-LABEL: test_bswap_srli_7_bswap_i16:
; RV64ZB: # %bb.0:
; RV64ZB-NEXT: rev8 a0, a0
; RV64ZB-NEXT: srli a0, a0, 55
; RV64ZB-NEXT: rev8 a0, a0
; RV64ZB-NEXT: srli a0, a0, 48
; RV64ZB-NEXT: ret
%1 = call i16 @llvm.bswap.i16(i16 %a)
%2 = lshr i16 %1, 7
%3 = call i16 @llvm.bswap.i16(i16 %2)
ret i16 %3
}
define i16 @test_bswap_srli_8_bswap_i16(i16 %a) nounwind {
; RV32ZB-LABEL: test_bswap_srli_8_bswap_i16:
; RV32ZB: # %bb.0:
; RV32ZB-NEXT: andi a0, a0, 255
; RV32ZB-NEXT: rev8 a0, a0
; RV32ZB-NEXT: srli a0, a0, 16
; RV32ZB-NEXT: ret
;
; RV64ZB-LABEL: test_bswap_srli_8_bswap_i16:
; RV64ZB: # %bb.0:
; RV64ZB-NEXT: andi a0, a0, 255
; RV64ZB-NEXT: rev8 a0, a0
; RV64ZB-NEXT: srli a0, a0, 48
; RV64ZB-NEXT: ret
%1 = call i16 @llvm.bswap.i16(i16 %a)
%2 = lshr i16 %1, 8
%3 = call i16 @llvm.bswap.i16(i16 %2)
ret i16 %3
}
define i32 @test_bswap_srli_8_bswap_i32(i32 %a) nounwind {
; RV32ZB-LABEL: test_bswap_srli_8_bswap_i32:
; RV32ZB: # %bb.0:
; RV32ZB-NEXT: rev8 a0, a0
; RV32ZB-NEXT: srli a0, a0, 8
; RV32ZB-NEXT: rev8 a0, a0
; RV32ZB-NEXT: ret
;
; RV64ZB-LABEL: test_bswap_srli_8_bswap_i32:
; RV64ZB: # %bb.0:
; RV64ZB-NEXT: rev8 a0, a0
; RV64ZB-NEXT: srli a0, a0, 40
; RV64ZB-NEXT: rev8 a0, a0
; RV64ZB-NEXT: srli a0, a0, 32
; RV64ZB-NEXT: ret
%1 = call i32 @llvm.bswap.i32(i32 %a)
%2 = lshr i32 %1, 8
%3 = call i32 @llvm.bswap.i32(i32 %2)
ret i32 %3
}
define i32 @test_bswap_srli_16_bswap_i32(i32 %a) nounwind {
; RV32ZB-LABEL: test_bswap_srli_16_bswap_i32:
; RV32ZB: # %bb.0:
; RV32ZB-NEXT: rev8 a0, a0
; RV32ZB-NEXT: srli a0, a0, 16
; RV32ZB-NEXT: rev8 a0, a0
; RV32ZB-NEXT: ret
;
; RV64ZB-LABEL: test_bswap_srli_16_bswap_i32:
; RV64ZB: # %bb.0:
; RV64ZB-NEXT: rev8 a0, a0
; RV64ZB-NEXT: srli a0, a0, 48
; RV64ZB-NEXT: rev8 a0, a0
; RV64ZB-NEXT: srli a0, a0, 32
; RV64ZB-NEXT: ret
%1 = call i32 @llvm.bswap.i32(i32 %a)
%2 = lshr i32 %1, 16
%3 = call i32 @llvm.bswap.i32(i32 %2)
ret i32 %3
}
define i32 @test_bswap_srli_24_bswap_i32(i32 %a) nounwind {
; RV32ZB-LABEL: test_bswap_srli_24_bswap_i32:
; RV32ZB: # %bb.0:
; RV32ZB-NEXT: andi a0, a0, 255
; RV32ZB-NEXT: rev8 a0, a0
; RV32ZB-NEXT: ret
;
; RV64ZB-LABEL: test_bswap_srli_24_bswap_i32:
; RV64ZB: # %bb.0:
; RV64ZB-NEXT: andi a0, a0, 255
; RV64ZB-NEXT: rev8 a0, a0
; RV64ZB-NEXT: srli a0, a0, 32
; RV64ZB-NEXT: ret
%1 = call i32 @llvm.bswap.i32(i32 %a)
%2 = lshr i32 %1, 24
%3 = call i32 @llvm.bswap.i32(i32 %2)
ret i32 %3
}
define i64 @test_bswap_srli_48_bswap_i64(i64 %a) nounwind {
; RV32ZB-LABEL: test_bswap_srli_48_bswap_i64:
; RV32ZB: # %bb.0:
; RV32ZB-NEXT: rev8 a0, a0
; RV32ZB-NEXT: srli a0, a0, 16
; RV32ZB-NEXT: rev8 a1, a0
; RV32ZB-NEXT: li a0, 0
; RV32ZB-NEXT: ret
;
; RV64ZB-LABEL: test_bswap_srli_48_bswap_i64:
; RV64ZB: # %bb.0:
; RV64ZB-NEXT: rev8 a0, a0
; RV64ZB-NEXT: srli a0, a0, 48
; RV64ZB-NEXT: rev8 a0, a0
; RV64ZB-NEXT: ret
%1 = call i64 @llvm.bswap.i64(i64 %a)
%2 = lshr i64 %1, 48
%3 = call i64 @llvm.bswap.i64(i64 %2)
ret i64 %3
}
define i16 @test_bswap_shli_7_bswap_i16(i16 %a) nounwind {
; RV32ZB-LABEL: test_bswap_shli_7_bswap_i16:
; RV32ZB: # %bb.0:
; RV32ZB-NEXT: rev8 a0, a0
; RV32ZB-NEXT: srli a0, a0, 9
; RV32ZB-NEXT: andi a0, a0, -128
; RV32ZB-NEXT: rev8 a0, a0
; RV32ZB-NEXT: srli a0, a0, 16
; RV32ZB-NEXT: ret
;
; RV64ZB-LABEL: test_bswap_shli_7_bswap_i16:
; RV64ZB: # %bb.0:
; RV64ZB-NEXT: rev8 a0, a0
; RV64ZB-NEXT: srli a0, a0, 41
; RV64ZB-NEXT: andi a0, a0, -128
; RV64ZB-NEXT: rev8 a0, a0
; RV64ZB-NEXT: srli a0, a0, 48
; RV64ZB-NEXT: ret
%1 = call i16 @llvm.bswap.i16(i16 %a)
%2 = shl i16 %1, 7
%3 = call i16 @llvm.bswap.i16(i16 %2)
ret i16 %3
}
define i16 @test_bswap_shli_8_bswap_i16(i16 %a) nounwind {
; RV32ZB-LABEL: test_bswap_shli_8_bswap_i16:
; RV32ZB: # %bb.0:
; RV32ZB-NEXT: andi a0, a0, -256
; RV32ZB-NEXT: rev8 a0, a0
; RV32ZB-NEXT: srli a0, a0, 16
; RV32ZB-NEXT: ret
;
; RV64ZB-LABEL: test_bswap_shli_8_bswap_i16:
; RV64ZB: # %bb.0:
; RV64ZB-NEXT: andi a0, a0, -256
; RV64ZB-NEXT: rev8 a0, a0
; RV64ZB-NEXT: srli a0, a0, 48
; RV64ZB-NEXT: ret
%1 = call i16 @llvm.bswap.i16(i16 %a)
%2 = shl i16 %1, 8
%3 = call i16 @llvm.bswap.i16(i16 %2)
ret i16 %3
}
define i32 @test_bswap_shli_8_bswap_i32(i32 %a) nounwind {
; RV32ZB-LABEL: test_bswap_shli_8_bswap_i32:
; RV32ZB: # %bb.0:
; RV32ZB-NEXT: rev8 a0, a0
; RV32ZB-NEXT: slli a0, a0, 8
; RV32ZB-NEXT: rev8 a0, a0
; RV32ZB-NEXT: ret
;
; RV64ZB-LABEL: test_bswap_shli_8_bswap_i32:
; RV64ZB: # %bb.0:
; RV64ZB-NEXT: rev8 a0, a0
; RV64ZB-NEXT: srli a0, a0, 24
; RV64ZB-NEXT: andi a0, a0, -256
; RV64ZB-NEXT: rev8 a0, a0
; RV64ZB-NEXT: srli a0, a0, 32
; RV64ZB-NEXT: ret
%1 = call i32 @llvm.bswap.i32(i32 %a)
%2 = shl i32 %1, 8
%3 = call i32 @llvm.bswap.i32(i32 %2)
ret i32 %3
}
define i32 @test_bswap_shli_16_bswap_i32(i32 %a) nounwind {
; RV32ZB-LABEL: test_bswap_shli_16_bswap_i32:
; RV32ZB: # %bb.0:
; RV32ZB-NEXT: rev8 a0, a0
; RV32ZB-NEXT: slli a0, a0, 16
; RV32ZB-NEXT: rev8 a0, a0
; RV32ZB-NEXT: ret
;
; RV64ZB-LABEL: test_bswap_shli_16_bswap_i32:
; RV64ZB: # %bb.0:
; RV64ZB-NEXT: rev8 a0, a0
; RV64ZB-NEXT: srli a0, a0, 32
; RV64ZB-NEXT: slli a0, a0, 16
; RV64ZB-NEXT: rev8 a0, a0
; RV64ZB-NEXT: srli a0, a0, 32
; RV64ZB-NEXT: ret
%1 = call i32 @llvm.bswap.i32(i32 %a)
%2 = shl i32 %1, 16
%3 = call i32 @llvm.bswap.i32(i32 %2)
ret i32 %3
}
define i32 @test_bswap_shli_24_bswap_i32(i32 %a) nounwind {
; RV32ZB-LABEL: test_bswap_shli_24_bswap_i32:
; RV32ZB: # %bb.0:
; RV32ZB-NEXT: lui a1, 1044480
; RV32ZB-NEXT: and a0, a0, a1
; RV32ZB-NEXT: rev8 a0, a0
; RV32ZB-NEXT: ret
;
; RV64ZB-LABEL: test_bswap_shli_24_bswap_i32:
; RV64ZB: # %bb.0:
; RV64ZB-NEXT: lui a1, 1044480
; RV64ZB-NEXT: and a0, a0, a1
; RV64ZB-NEXT: rev8 a0, a0
; RV64ZB-NEXT: srli a0, a0, 32
; RV64ZB-NEXT: ret
%1 = call i32 @llvm.bswap.i32(i32 %a)
%2 = shl i32 %1, 24
%3 = call i32 @llvm.bswap.i32(i32 %2)
ret i32 %3
}
define i64 @test_bswap_shli_48_bswap_i64(i64 %a) nounwind {
; RV32ZB-LABEL: test_bswap_shli_48_bswap_i64:
; RV32ZB: # %bb.0:
; RV32ZB-NEXT: rev8 a0, a1
; RV32ZB-NEXT: slli a0, a0, 16
; RV32ZB-NEXT: rev8 a0, a0
; RV32ZB-NEXT: li a1, 0
; RV32ZB-NEXT: ret
;
; RV64ZB-LABEL: test_bswap_shli_48_bswap_i64:
; RV64ZB: # %bb.0:
; RV64ZB-NEXT: rev8 a0, a0
; RV64ZB-NEXT: slli a0, a0, 48
; RV64ZB-NEXT: rev8 a0, a0
; RV64ZB-NEXT: ret
%1 = call i64 @llvm.bswap.i64(i64 %a)
%2 = shl i64 %1, 48
%3 = call i64 @llvm.bswap.i64(i64 %2)
ret i64 %3
}

llvm/test/CodeGen/X86/combine-bswap.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X86 ; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X86
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s --check-prefix=X64 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s --check-prefix=X64
; These tests just check that the plumbing is in place for @llvm.bswap. The ; These tests just check that the plumbing is in place for @llvm.bswap. The
; actual output is massive at the moment as llvm.bswap is not yet legal. ; actual output is massive at the moment as llvm.bswap is not yet legal.
declare i16 @llvm.bswap.i16(i16) readnone
declare i32 @llvm.bswap.i32(i32) readnone declare i32 @llvm.bswap.i32(i32) readnone
declare i64 @llvm.bswap.i64(i64) readnone declare i64 @llvm.bswap.i64(i64) readnone
declare i32 @llvm.bswap.v4i32(i32) readnone declare i32 @llvm.bswap.v4i32(i32) readnone
; fold (bswap undef) -> undef ; fold (bswap undef) -> undef
define i32 @test_undef() nounwind { define i32 @test_undef() nounwind {
; X86-LABEL: test_undef: ; X86-LABEL: test_undef:
; X86: # %bb.0: ; X86: # %bb.0:
Show All 17 Lines
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: movl %edi, %eax ; X64-NEXT: movl %edi, %eax
; X64-NEXT: retq ; X64-NEXT: retq
%b = call i32 @llvm.bswap.i32(i32 %a0) %b = call i32 @llvm.bswap.i32(i32 %a0)
%c = call i32 @llvm.bswap.i32(i32 %b) %c = call i32 @llvm.bswap.i32(i32 %b)
ret i32 %c ret i32 %c
} }
; TODO: fold (bswap(srl (bswap c), x)) -> (shl c, x)
define i16 @test_bswap_srli_8_bswap_i16(i16 %a) nounwind {
RKSimonUnsubmitted
Not Done
ReplyInline Actions

Please can you add one i16 + i64 test case each as well? i16 as it lowers to a rotate and i64 so we can check its correctly handled on 32-bit targets

RKSimon: Please can you add one i16 + i64 test case each as well? i16 as it lowers to a rotate and i64…
; X86-LABEL: test_bswap_srli_8_bswap_i16:
; X86: # %bb.0:
; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; X86-NEXT: rolw $8, %ax
; X86-NEXT: # kill: def $ax killed $ax killed $eax
; X86-NEXT: retl
;
; X64-LABEL: test_bswap_srli_8_bswap_i16:
; X64: # %bb.0:
; X64-NEXT: movzbl %dil, %eax
; X64-NEXT: rolw $8, %ax
; X64-NEXT: # kill: def $ax killed $ax killed $eax
; X64-NEXT: retq
%1 = call i16 @llvm.bswap.i16(i16 %a)
%2 = lshr i16 %1, 8
%3 = call i16 @llvm.bswap.i16(i16 %2)
ret i16 %3
}
define i32 @test_bswap_srli_8_bswap_i32(i32 %a) nounwind {
; X86-LABEL: test_bswap_srli_8_bswap_i32:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: bswapl %eax
; X86-NEXT: shrl $8, %eax
; X86-NEXT: bswapl %eax
; X86-NEXT: retl
;
; X64-LABEL: test_bswap_srli_8_bswap_i32:
; X64: # %bb.0:
; X64-NEXT: movl %edi, %eax
; X64-NEXT: bswapl %eax
; X64-NEXT: shrl $8, %eax
; X64-NEXT: bswapl %eax
; X64-NEXT: retq
%1 = call i32 @llvm.bswap.i32(i32 %a)
%2 = lshr i32 %1, 8
%3 = call i32 @llvm.bswap.i32(i32 %2)
ret i32 %3
}
define i64 @test_bswap_srli_16_bswap_i64(i64 %a) nounwind {
; X86-LABEL: test_bswap_srli_16_bswap_i64:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: bswapl %edx
; X86-NEXT: bswapl %eax
; X86-NEXT: shrdl $16, %eax, %edx
; X86-NEXT: shrl $16, %eax
; X86-NEXT: bswapl %edx
; X86-NEXT: bswapl %eax
; X86-NEXT: retl
;
; X64-LABEL: test_bswap_srli_16_bswap_i64:
; X64: # %bb.0:
; X64-NEXT: movq %rdi, %rax
; X64-NEXT: bswapq %rax
; X64-NEXT: shrq $16, %rax
; X64-NEXT: bswapq %rax
; X64-NEXT: retq
%1 = call i64 @llvm.bswap.i64(i64 %a)
%2 = lshr i64 %1, 16
%3 = call i64 @llvm.bswap.i64(i64 %2)
ret i64 %3
}
; TODO: fold (bswap(shl (bswap c), x)) -> (srl c, x)
define i16 @test_bswap_shli_8_bswap_i16(i16 %a) nounwind {
; X86-LABEL: test_bswap_shli_8_bswap_i16:
; X86: # %bb.0:
; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; X86-NEXT: shll $8, %eax
; X86-NEXT: rolw $8, %ax
; X86-NEXT: # kill: def $ax killed $ax killed $eax
; X86-NEXT: retl
;
; X64-LABEL: test_bswap_shli_8_bswap_i16:
; X64: # %bb.0:
; X64-NEXT: movl %edi, %eax
; X64-NEXT: andl $65280, %eax # imm = 0xFF00
; X64-NEXT: rolw $8, %ax
; X64-NEXT: # kill: def $ax killed $ax killed $eax
; X64-NEXT: retq
%1 = call i16 @llvm.bswap.i16(i16 %a)
%2 = shl i16 %1, 8
%3 = call i16 @llvm.bswap.i16(i16 %2)
ret i16 %3
}
define i32 @test_bswap_shli_8_bswap_i32(i32 %a) nounwind {
; X86-LABEL: test_bswap_shli_8_bswap_i32:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: bswapl %eax
; X86-NEXT: shll $8, %eax
; X86-NEXT: bswapl %eax
; X86-NEXT: retl
;
; X64-LABEL: test_bswap_shli_8_bswap_i32:
; X64: # %bb.0:
; X64-NEXT: movl %edi, %eax
; X64-NEXT: bswapl %eax
; X64-NEXT: shll $8, %eax
; X64-NEXT: bswapl %eax
; X64-NEXT: retq
%1 = call i32 @llvm.bswap.i32(i32 %a)
%2 = shl i32 %1, 8
%3 = call i32 @llvm.bswap.i32(i32 %2)
ret i32 %3
}
define i64 @test_bswap_shli_16_bswap_i64(i64 %a) nounwind {
; X86-LABEL: test_bswap_shli_16_bswap_i64:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: bswapl %ecx
; X86-NEXT: bswapl %eax
; X86-NEXT: shldl $16, %ecx, %eax
; X86-NEXT: bswapl %eax
; X86-NEXT: rolw $8, %cx
; X86-NEXT: movzwl %cx, %edx
; X86-NEXT: retl
;
; X64-LABEL: test_bswap_shli_16_bswap_i64:
; X64: # %bb.0:
; X64-NEXT: movq %rdi, %rax
; X64-NEXT: bswapq %rax
; X64-NEXT: shlq $16, %rax
; X64-NEXT: bswapq %rax
; X64-NEXT: retq
%1 = call i64 @llvm.bswap.i64(i64 %a)
%2 = shl i64 %1, 16
%3 = call i64 @llvm.bswap.i64(i64 %2)
ret i64 %3
}
define i32 @test_demandedbits_bswap(i32 %a0) nounwind { define i32 @test_demandedbits_bswap(i32 %a0) nounwind {
; X86-LABEL: test_demandedbits_bswap: ; X86-LABEL: test_demandedbits_bswap:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: bswapl %eax ; X86-NEXT: bswapl %eax
; X86-NEXT: andl $-65536, %eax # imm = 0xFFFF0000 ; X86-NEXT: andl $-65536, %eax # imm = 0xFFFF0000
; X86-NEXT: retl ; X86-NEXT: retl
; ;
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