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Differential D115694

[ARM] Introduce an empty "armv8.8-a" architecture.
ClosedPublic

Authored by tyb0807 on Dec 13 2021, 6:55 PM.

Details

Reviewers
tmatheson
simon_tatham
dmgreen
SjoerdMeijer
pratlucas
chill
Commits
rGd50072f74e3e: [ARM] Introduce an empty "armv8.8-a" architecture.
Summary

This is the first commit in a series that implements support for
"armv8.8-a" architecture. This should contain all the necessary
boilerplate to make the 8.8-A architecture exist from LLVM and Clang's
point of view: it adds the new arch as a subtarget feature, a definition
in TargetParser, a name on the command line, an appropriate set of
predefined macros, and adds appropriate tests. The new architecture name
is supported in both AArch32 and AArch64.

However, in this commit, no actual _functionality_ is added as part of
the new architecture. If you specify -march=armv8.8a, the compiler
will accept it and set the right predefines, but generate no code any
differently.

Patch by Simon Tatham

Diff Detail

Event Timeline

tyb0807 created this revision.Dec 13 2021, 6:55 PM
Herald added subscribers: dexonsmith, hiraditya, kristof.beyls. · View Herald TranscriptDec 13 2021, 6:55 PM
tyb0807 requested review of this revision.Dec 13 2021, 6:55 PM
Herald added projects: Restricted Project, Restricted Project. · View Herald TranscriptDec 13 2021, 6:55 PM
Herald added subscribers: llvm-commits, cfe-commits. · View Herald Transcript
tyb0807 updated this revision to Diff 394116.Dec 13 2021, 7:04 PM

Allow linting

tyb0807 updated this revision to Diff 394120.Dec 13 2021, 7:13 PM
tyb0807 edited the summary of this revision. (Show Details)

Update commit message

tyb0807 added reviewers: tmatheson, simon_tatham.Dec 13 2021, 7:14 PM
Harbormaster completed remote builds in B139132: Diff 394120.Dec 13 2021, 8:35 PM
tmatheson accepted this revision.Dec 16 2021, 6:15 AM

LGTM

This revision is now accepted and ready to land.Dec 16 2021, 6:15 AM
chill added a subscriber: chill.Dec 22 2021, 6:37 AM
chill added inline comments.
llvm/include/llvm/Support/ARMTargetParser.def
125

... here.

chill mentioned this in D116160: [AArch64] ACLE feature macro for Armv8.8-A MOPS.Dec 22 2021, 6:41 AM
tmatheson added a child revision: D116156: [AArch64] Adding "armv8.8-a" BC instruction..Dec 27 2021, 9:56 AM
tmatheson added a child revision: D116158: [ARM][AArch64] Introduce Armv9.3-A.Dec 27 2021, 9:59 AM
tmatheson added reviewers: dmgreen, SjoerdMeijer, pratlucas, chill.Dec 31 2021, 1:22 AM
pratlucas accepted this revision.Dec 31 2021, 3:50 AM

LGTM

tmatheson updated this revision to Diff 396779.Dec 31 2021, 5:35 AM

Rebase

tmatheson updated this revision to Diff 396780.Dec 31 2021, 5:38 AM

Minor fix after rebase

Harbormaster completed remote builds in B141104: Diff 396780.Dec 31 2021, 7:01 AM
This revision was landed with ongoing or failed builds.Dec 31 2021, 8:44 AM
Closed by commit rGd50072f74e3e: [ARM] Introduce an empty "armv8.8-a" architecture. (authored by simon_tatham, committed by tmatheson). · Explain Why
This revision was automatically updated to reflect the committed changes.
tmatheson added a commit: rGd50072f74e3e: [ARM] Introduce an empty "armv8.8-a" architecture..

Revision Contents

PathSize
clang/
lib/
Basic/
Targets/
2 lines
11 lines
3 lines
Driver/
ToolChains/
Arch/
8 lines
test/
Driver/
16 lines
17 lines
Preprocessor/
5 lines
llvm/
include/
llvm/
ADT/
1 line
Support/
7 lines
6 lines
lib/
Support/
2 lines
3 lines
2 lines
Target/
AArch64/
4 lines
1 line
AsmParser/
4 lines
ARM/
17 lines
3 lines
unittests/
Support/
55 lines

Diff 396807

clang/lib/Basic/Targets/AArch64.h

Show First 20 Lines • Show All 86 Lines • ▼ Show 20 Linespublic:
void getTargetDefinesARMV84A(const LangOptions &Opts, void getTargetDefinesARMV84A(const LangOptions &Opts,
MacroBuilder &Builder) const; MacroBuilder &Builder) const;
void getTargetDefinesARMV85A(const LangOptions &Opts, void getTargetDefinesARMV85A(const LangOptions &Opts,
MacroBuilder &Builder) const; MacroBuilder &Builder) const;
void getTargetDefinesARMV86A(const LangOptions &Opts, void getTargetDefinesARMV86A(const LangOptions &Opts,
MacroBuilder &Builder) const; MacroBuilder &Builder) const;
void getTargetDefinesARMV87A(const LangOptions &Opts, void getTargetDefinesARMV87A(const LangOptions &Opts,
MacroBuilder &Builder) const; MacroBuilder &Builder) const;
void getTargetDefinesARMV88A(const LangOptions &Opts,
MacroBuilder &Builder) const;
void getTargetDefinesARMV9A(const LangOptions &Opts, void getTargetDefinesARMV9A(const LangOptions &Opts,
MacroBuilder &Builder) const; MacroBuilder &Builder) const;
void getTargetDefinesARMV91A(const LangOptions &Opts, void getTargetDefinesARMV91A(const LangOptions &Opts,
MacroBuilder &Builder) const; MacroBuilder &Builder) const;
void getTargetDefinesARMV92A(const LangOptions &Opts, void getTargetDefinesARMV92A(const LangOptions &Opts,
MacroBuilder &Builder) const; MacroBuilder &Builder) const;
void getTargetDefines(const LangOptions &Opts, void getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const override; MacroBuilder &Builder) const override;
▲ Show 20 Lines • Show All 137 Lines • Show Last 20 Lines

clang/lib/Basic/Targets/AArch64.cpp

Show First 20 Lines • Show All 217 Lines • ▼ Show 20 Lines
} }
void AArch64TargetInfo::getTargetDefinesARMV87A(const LangOptions &Opts, void AArch64TargetInfo::getTargetDefinesARMV87A(const LangOptions &Opts,
MacroBuilder &Builder) const { MacroBuilder &Builder) const {
// Also include the Armv8.6 defines // Also include the Armv8.6 defines
getTargetDefinesARMV86A(Opts, Builder); getTargetDefinesARMV86A(Opts, Builder);
} }
void AArch64TargetInfo::getTargetDefinesARMV88A(const LangOptions &Opts,
MacroBuilder &Builder) const {
// Also include the Armv8.7 defines
getTargetDefinesARMV87A(Opts, Builder);
}
void AArch64TargetInfo::getTargetDefinesARMV9A(const LangOptions &Opts, void AArch64TargetInfo::getTargetDefinesARMV9A(const LangOptions &Opts,
MacroBuilder &Builder) const { MacroBuilder &Builder) const {
// Armv9-A maps to Armv8.5-A // Armv9-A maps to Armv8.5-A
getTargetDefinesARMV85A(Opts, Builder); getTargetDefinesARMV85A(Opts, Builder);
} }
void AArch64TargetInfo::getTargetDefinesARMV91A(const LangOptions &Opts, void AArch64TargetInfo::getTargetDefinesARMV91A(const LangOptions &Opts,
MacroBuilder &Builder) const { MacroBuilder &Builder) const {
▲ Show 20 Lines • Show All 207 Lines • ▼ Show 20 Lines case llvm::AArch64::ArchKind::ARMV8_5A:
getTargetDefinesARMV85A(Opts, Builder); getTargetDefinesARMV85A(Opts, Builder);
break; break;
case llvm::AArch64::ArchKind::ARMV8_6A: case llvm::AArch64::ArchKind::ARMV8_6A:
getTargetDefinesARMV86A(Opts, Builder); getTargetDefinesARMV86A(Opts, Builder);
break; break;
case llvm::AArch64::ArchKind::ARMV8_7A: case llvm::AArch64::ArchKind::ARMV8_7A:
getTargetDefinesARMV87A(Opts, Builder); getTargetDefinesARMV87A(Opts, Builder);
break; break;
case llvm::AArch64::ArchKind::ARMV8_8A:
getTargetDefinesARMV88A(Opts, Builder);
break;
case llvm::AArch64::ArchKind::ARMV9A: case llvm::AArch64::ArchKind::ARMV9A:
getTargetDefinesARMV9A(Opts, Builder); getTargetDefinesARMV9A(Opts, Builder);
break; break;
case llvm::AArch64::ArchKind::ARMV9_1A: case llvm::AArch64::ArchKind::ARMV9_1A:
getTargetDefinesARMV91A(Opts, Builder); getTargetDefinesARMV91A(Opts, Builder);
break; break;
case llvm::AArch64::ArchKind::ARMV9_2A: case llvm::AArch64::ArchKind::ARMV9_2A:
getTargetDefinesARMV92A(Opts, Builder); getTargetDefinesARMV92A(Opts, Builder);
▲ Show 20 Lines • Show All 141 Lines • ▼ Show 20 Lines for (const auto &Feature : Features) {
if (Feature == "+v8.4a") if (Feature == "+v8.4a")
ArchKind = llvm::AArch64::ArchKind::ARMV8_4A; ArchKind = llvm::AArch64::ArchKind::ARMV8_4A;
if (Feature == "+v8.5a") if (Feature == "+v8.5a")
ArchKind = llvm::AArch64::ArchKind::ARMV8_5A; ArchKind = llvm::AArch64::ArchKind::ARMV8_5A;
if (Feature == "+v8.6a") if (Feature == "+v8.6a")
ArchKind = llvm::AArch64::ArchKind::ARMV8_6A; ArchKind = llvm::AArch64::ArchKind::ARMV8_6A;
if (Feature == "+v8.7a") if (Feature == "+v8.7a")
ArchKind = llvm::AArch64::ArchKind::ARMV8_7A; ArchKind = llvm::AArch64::ArchKind::ARMV8_7A;
if (Feature == "+v8.8a")
ArchKind = llvm::AArch64::ArchKind::ARMV8_8A;
if (Feature == "+v9a") if (Feature == "+v9a")
ArchKind = llvm::AArch64::ArchKind::ARMV9A; ArchKind = llvm::AArch64::ArchKind::ARMV9A;
if (Feature == "+v9.1a") if (Feature == "+v9.1a")
ArchKind = llvm::AArch64::ArchKind::ARMV9_1A; ArchKind = llvm::AArch64::ArchKind::ARMV9_1A;
if (Feature == "+v9.2a") if (Feature == "+v9.2a")
ArchKind = llvm::AArch64::ArchKind::ARMV9_2A; ArchKind = llvm::AArch64::ArchKind::ARMV9_2A;
if (Feature == "+v8r") if (Feature == "+v8r")
ArchKind = llvm::AArch64::ArchKind::ARMV8R; ArchKind = llvm::AArch64::ArchKind::ARMV8R;
▲ Show 20 Lines • Show All 426 Lines • Show Last 20 Lines

clang/lib/Basic/Targets/ARM.cpp

Show First 20 Lines • Show All 206 Lines • ▼ Show 20 LinesStringRef ARMTargetInfo::getCPUAttr() const {
case llvm::ARM::ArchKind::ARMV8_4A: case llvm::ARM::ArchKind::ARMV8_4A:
return "8_4A"; return "8_4A";
case llvm::ARM::ArchKind::ARMV8_5A: case llvm::ARM::ArchKind::ARMV8_5A:
return "8_5A"; return "8_5A";
case llvm::ARM::ArchKind::ARMV8_6A: case llvm::ARM::ArchKind::ARMV8_6A:
return "8_6A"; return "8_6A";
case llvm::ARM::ArchKind::ARMV8_7A: case llvm::ARM::ArchKind::ARMV8_7A:
return "8_7A"; return "8_7A";
case llvm::ARM::ArchKind::ARMV8_8A:
return "8_8A";
case llvm::ARM::ArchKind::ARMV9A: case llvm::ARM::ArchKind::ARMV9A:
return "9A"; return "9A";
case llvm::ARM::ArchKind::ARMV9_1A: case llvm::ARM::ArchKind::ARMV9_1A:
return "9_1A"; return "9_1A";
case llvm::ARM::ArchKind::ARMV9_2A: case llvm::ARM::ArchKind::ARMV9_2A:
return "9_2A"; return "9_2A";
case llvm::ARM::ArchKind::ARMV8MBaseline: case llvm::ARM::ArchKind::ARMV8MBaseline:
return "8M_BASE"; return "8M_BASE";
▲ Show 20 Lines • Show All 702 Lines • ▼ Show 20 Lines case llvm::ARM::ArchKind::ARMV8_1A:
break; break;
case llvm::ARM::ArchKind::ARMV8_2A: case llvm::ARM::ArchKind::ARMV8_2A:
getTargetDefinesARMV82A(Opts, Builder); getTargetDefinesARMV82A(Opts, Builder);
break; break;
case llvm::ARM::ArchKind::ARMV8_3A: case llvm::ARM::ArchKind::ARMV8_3A:
case llvm::ARM::ArchKind::ARMV8_4A: case llvm::ARM::ArchKind::ARMV8_4A:
case llvm::ARM::ArchKind::ARMV8_5A: case llvm::ARM::ArchKind::ARMV8_5A:
case llvm::ARM::ArchKind::ARMV8_6A: case llvm::ARM::ArchKind::ARMV8_6A:
case llvm::ARM::ArchKind::ARMV8_8A:
case llvm::ARM::ArchKind::ARMV9A: case llvm::ARM::ArchKind::ARMV9A:
case llvm::ARM::ArchKind::ARMV9_1A: case llvm::ARM::ArchKind::ARMV9_1A:
case llvm::ARM::ArchKind::ARMV9_2A: case llvm::ARM::ArchKind::ARMV9_2A:
getTargetDefinesARMV83A(Opts, Builder); getTargetDefinesARMV83A(Opts, Builder);
break; break;
} }
} }
▲ Show 20 Lines • Show All 445 Lines • Show Last 20 Lines

clang/lib/Driver/ToolChains/Arch/AArch64.cpp

Show First 20 Lines • Show All 92 Lines • ▼ Show 20 Lines else if (Feature == "sve2-bitperm" || Feature == "sve2-sha3" ||
Features.push_back("-sve2-sm4"); Features.push_back("-sve2-sm4");
} else if (Feature == "nosve2") { } else if (Feature == "nosve2") {
Features.push_back("-sve2-bitperm"); Features.push_back("-sve2-bitperm");
Features.push_back("-sve2-sha3"); Features.push_back("-sve2-sha3");
Features.push_back("-sve2-aes"); Features.push_back("-sve2-aes");
Features.push_back("-sve2-sm4"); Features.push_back("-sve2-sm4");
} }
// +sve implies +f32mm if the base architecture is v8.6A, v8.7A, v9.1A or // +sve implies +f32mm if the base architecture is >= v8.6A (except v9A)
// v9.2A. It isn't the case in general that sve implies both f64mm and f32mm // It isn't the case in general that sve implies both f64mm and f32mm
if ((ArchKind == llvm::AArch64::ArchKind::ARMV8_6A || if ((ArchKind == llvm::AArch64::ArchKind::ARMV8_6A ||
ArchKind == llvm::AArch64::ArchKind::ARMV8_7A || ArchKind == llvm::AArch64::ArchKind::ARMV8_7A ||
ArchKind == llvm::AArch64::ArchKind::ARMV8_8A ||
ArchKind == llvm::AArch64::ArchKind::ARMV9_1A || ArchKind == llvm::AArch64::ArchKind::ARMV9_1A ||
ArchKind == llvm::AArch64::ArchKind::ARMV9_2A) && ArchKind == llvm::AArch64::ArchKind::ARMV9_2A) &&
Feature == "sve") Feature == "sve")
Features.push_back("+f32mm"); Features.push_back("+f32mm");
} }
return true; return true;
} }
▲ Show 20 Lines • Show All 272 Lines • ▼ Show 20 Linesfp16_fml_fallthrough:
bool NoCrypto = false; bool NoCrypto = false;
if (HasCrypto && HasNoCrypto) { if (HasCrypto && HasNoCrypto) {
if (PosNoCrypto < PosCrypto) if (PosNoCrypto < PosCrypto)
NoCrypto = true; NoCrypto = true;
} }
if (std::find(ItBegin, ItEnd, "+v8.4a") != ItEnd || if (std::find(ItBegin, ItEnd, "+v8.4a") != ItEnd ||
std::find(ItBegin, ItEnd, "+v8.8a") != ItEnd ||
std::find(ItBegin, ItEnd, "+v9a") != ItEnd || std::find(ItBegin, ItEnd, "+v9a") != ItEnd ||
std::find(ItBegin, ItEnd, "+v9.1a") != ItEnd || std::find(ItBegin, ItEnd, "+v9.1a") != ItEnd ||
std::find(ItBegin, ItEnd, "+v9.2a") != ItEnd) { std::find(ItBegin, ItEnd, "+v9.2a") != ItEnd) {
if (HasCrypto && !NoCrypto) { if (HasCrypto && !NoCrypto) {
// Check if we have NOT disabled an algorithm with something like: // Check if we have NOT disabled an algorithm with something like:
// +crypto, -algorithm // +crypto, -algorithm
// And if "-algorithm" does not occur, we enable that crypto algorithm. // And if "-algorithm" does not occur, we enable that crypto algorithm.
const bool HasSM4 = (std::find(ItBegin, ItEnd, "-sm4") == ItEnd); const bool HasSM4 = (std::find(ItBegin, ItEnd, "-sm4") == ItEnd);
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines if (HasCrypto && !NoCrypto) {
Features.push_back("-aes"); Features.push_back("-aes");
if (HasV82a || HasV83a || HasV84a) { if (HasV82a || HasV83a || HasV84a) {
Features.push_back("-sm4"); Features.push_back("-sm4");
Features.push_back("-sha3"); Features.push_back("-sha3");
} }
} }
} }
const char *Archs[] = {"+v8.6a", "+v8.7a", "+v9.1a", "+v9.2a"}; const char *Archs[] = {"+v8.6a", "+v8.7a", "+v8.8a", "+v9.1a", "+v9.2a"};
auto Pos = std::find_first_of(Features.begin(), Features.end(), auto Pos = std::find_first_of(Features.begin(), Features.end(),
std::begin(Archs), std::end(Archs)); std::begin(Archs), std::end(Archs));
if (Pos != std::end(Features)) if (Pos != std::end(Features))
Pos = Features.insert(std::next(Pos), {"+i8mm", "+bf16"}); Pos = Features.insert(std::next(Pos), {"+i8mm", "+bf16"});
if (Arg *A = Args.getLastArg(options::OPT_mno_unaligned_access, if (Arg *A = Args.getLastArg(options::OPT_mno_unaligned_access,
options::OPT_munaligned_access)) { options::OPT_munaligned_access)) {
if (A->getOption().matches(options::OPT_mno_unaligned_access)) if (A->getOption().matches(options::OPT_mno_unaligned_access))
▲ Show 20 Lines • Show All 120 Lines • Show Last 20 Lines

clang/test/Driver/aarch64-cpus.c

Show First 20 Lines • Show All 797 Lines • ▼ Show 20 Lines
// GENERICV87A-BE: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" "generic" "-target-feature" "+neon" "-target-feature" "+v8.7a" // GENERICV87A-BE: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" "generic" "-target-feature" "+neon" "-target-feature" "+v8.7a"
// Tha LD64B/ST64B accelerator extension is disabled by default. // Tha LD64B/ST64B accelerator extension is disabled by default.
// RUN: %clang -target aarch64 -march=armv8.7a -### -c %s 2>&1 | FileCheck -check-prefix=NO-LS64 %s // RUN: %clang -target aarch64 -march=armv8.7a -### -c %s 2>&1 | FileCheck -check-prefix=NO-LS64 %s
// RUN: %clang -target aarch64 -march=armv8.7a+ls64 -### -c %s 2>&1 | FileCheck -check-prefix=LS64 %s // RUN: %clang -target aarch64 -march=armv8.7a+ls64 -### -c %s 2>&1 | FileCheck -check-prefix=LS64 %s
// NO-LS64-NOT: "-target-feature" "+ls64" // NO-LS64-NOT: "-target-feature" "+ls64"
// LS64: "-target-feature" "+ls64" // LS64: "-target-feature" "+ls64"
// RUN: %clang -target aarch64 -march=armv8.8a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV88A %s
// RUN: %clang -target aarch64 -march=armv8.8-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV88A %s
// RUN: %clang -target aarch64 -mlittle-endian -march=armv8.8a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV88A %s
// RUN: %clang -target aarch64 -mlittle-endian -march=armv8.8-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV88A %s
// RUN: %clang -target aarch64_be -mlittle-endian -march=armv8.8a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV88A %s
// RUN: %clang -target aarch64_be -mlittle-endian -march=armv8.8-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV88A %s
// GENERICV88A: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+neon" "-target-feature" "+v8.8a"
// RUN: %clang -target aarch64_be -march=armv8.8a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV88A-BE %s
// RUN: %clang -target aarch64_be -march=armv8.8-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV88A-BE %s
// RUN: %clang -target aarch64 -mbig-endian -march=armv8.8a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV88A-BE %s
// RUN: %clang -target aarch64 -mbig-endian -march=armv8.8-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV88A-BE %s
// RUN: %clang -target aarch64_be -mbig-endian -march=armv8.8a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV88A-BE %s
// RUN: %clang -target aarch64_be -mbig-endian -march=armv8.8-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV88A-BE %s
// GENERICV88A-BE: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" "generic" "-target-feature" "+neon" "-target-feature" "+v8.8a"
//
// RUN: %clang -target aarch64 -march=armv9a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV9A %s // RUN: %clang -target aarch64 -march=armv9a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV9A %s
// RUN: %clang -target aarch64 -march=armv9-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV9A %s // RUN: %clang -target aarch64 -march=armv9-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV9A %s
// RUN: %clang -target aarch64 -mlittle-endian -march=armv9a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV9A %s // RUN: %clang -target aarch64 -mlittle-endian -march=armv9a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV9A %s
// RUN: %clang -target aarch64 -mlittle-endian -march=armv9-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV9A %s // RUN: %clang -target aarch64 -mlittle-endian -march=armv9-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV9A %s
// RUN: %clang -target aarch64_be -mlittle-endian -march=armv9a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV9A %s // RUN: %clang -target aarch64_be -mlittle-endian -march=armv9a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV9A %s
// RUN: %clang -target aarch64_be -mlittle-endian -march=armv9-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV9A %s // RUN: %clang -target aarch64_be -mlittle-endian -march=armv9-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV9A %s
// GENERICV9A: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+neon" "-target-feature" "+v9a" "-target-feature" "+sve" "-target-feature" "+sve2" // GENERICV9A: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+neon" "-target-feature" "+v9a" "-target-feature" "+sve" "-target-feature" "+sve2"
▲ Show 20 Lines • Show All 98 Lines • Show Last 20 Lines

clang/test/Driver/arm-cortex-cpus.c

Show First 20 Lines • Show All 363 Lines • ▼ Show 20 Lines
// RUN: %clang -target armebv8.7a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V87A %s // RUN: %clang -target armebv8.7a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V87A %s
// RUN: %clang -target armv8.7a -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V87A %s // RUN: %clang -target armv8.7a -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V87A %s
// RUN: %clang -target armeb -march=armebv8.7a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V87A %s // RUN: %clang -target armeb -march=armebv8.7a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V87A %s
// RUN: %clang -target armeb -march=armebv8.7-a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V87A %s // RUN: %clang -target armeb -march=armebv8.7-a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V87A %s
// RUN: %clang -target arm -march=armebv8.7a -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V87A %s // RUN: %clang -target arm -march=armebv8.7a -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V87A %s
// RUN: %clang -target arm -march=armebv8.7-a -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V87A %s // RUN: %clang -target arm -march=armebv8.7-a -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V87A %s
// CHECK-BE-V87A: "-cc1"{{.*}} "-triple" "armebv8.7{{.*}}" "-target-cpu" "generic" // CHECK-BE-V87A: "-cc1"{{.*}} "-triple" "armebv8.7{{.*}}" "-target-cpu" "generic"
// RUN: %clang -target armv8.8a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V88A %s
// RUN: %clang -target arm -march=armv8.8a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V88A %s
// RUN: %clang -target arm -march=armv8.8-a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V88A %s
// RUN: %clang -target arm -march=armv8.8a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V88A %s
// RUN: %clang -target armv8.8a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V88A %s
// RUN: %clang -target arm -march=armv8.8a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V88A %s
// RUN: %clang -target arm -mlittle-endian -march=armv8.8-a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V88A %s
// CHECK-V88A: "-cc1"{{.*}} "-triple" "armv8.8{{.*}}" "-target-cpu" "generic"
// RUN: %clang -target armebv8.8a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V88A %s
// RUN: %clang -target armv8.8a -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V88A %s
// RUN: %clang -target armeb -march=armebv8.8a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V88A %s
// RUN: %clang -target armeb -march=armebv8.8-a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V88A %s
// RUN: %clang -target arm -march=armebv8.8a -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V88A %s
// RUN: %clang -target arm -march=armebv8.8-a -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V88A %s
// CHECK-BE-V88A: "-cc1"{{.*}} "-triple" "armebv8.8{{.*}}" "-target-cpu" "generic"
// RUN: %clang -target armv9a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V9A %s // RUN: %clang -target armv9a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V9A %s
// RUN: %clang -target arm -march=armv9a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V9A %s // RUN: %clang -target arm -march=armv9a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V9A %s
// RUN: %clang -target arm -march=armv9-a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V9A %s // RUN: %clang -target arm -march=armv9-a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V9A %s
// RUN: %clang -target arm -march=armv9a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V9A %s // RUN: %clang -target arm -march=armv9a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V9A %s
// RUN: %clang -target armv9a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V9A %s // RUN: %clang -target armv9a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V9A %s
// RUN: %clang -target arm -march=armv9a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V9A %s // RUN: %clang -target arm -march=armv9a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V9A %s
// RUN: %clang -target arm -mlittle-endian -march=armv9-a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V9A %s // RUN: %clang -target arm -mlittle-endian -march=armv9-a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V9A %s
// CHECK-V9A: "-cc1"{{.*}} "-triple" "armv9{{.*}}" "-target-cpu" "generic" // CHECK-V9A: "-cc1"{{.*}} "-triple" "armv9{{.*}}" "-target-cpu" "generic"
▲ Show 20 Lines • Show All 619 Lines • Show Last 20 Lines

clang/test/Preprocessor/arm-target-features.c

Show First 20 Lines • Show All 853 Lines • ▼ Show 20 Lines
// CHECK-V86A: #define __ARM_ARCH_8_6A__ 1 // CHECK-V86A: #define __ARM_ARCH_8_6A__ 1
// CHECK-V86A: #define __ARM_ARCH_PROFILE 'A' // CHECK-V86A: #define __ARM_ARCH_PROFILE 'A'
// RUN: %clang -target armv8.7a-none-none-eabi -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=CHECK-V87A %s // RUN: %clang -target armv8.7a-none-none-eabi -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=CHECK-V87A %s
// CHECK-V87A: #define __ARM_ARCH 8 // CHECK-V87A: #define __ARM_ARCH 8
// CHECK-V87A: #define __ARM_ARCH_8_7A__ 1 // CHECK-V87A: #define __ARM_ARCH_8_7A__ 1
// CHECK-V87A: #define __ARM_ARCH_PROFILE 'A' // CHECK-V87A: #define __ARM_ARCH_PROFILE 'A'
// RUN: %clang -target armv8.8a-none-none-eabi -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=CHECK-V88A %s
// CHECK-V88A: #define __ARM_ARCH 8
// CHECK-V88A: #define __ARM_ARCH_8_8A__ 1
// CHECK-V88A: #define __ARM_ARCH_PROFILE 'A'
//
// RUN: %clang -target armv9a-none-none-eabi -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=CHECK-V9A %s // RUN: %clang -target armv9a-none-none-eabi -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=CHECK-V9A %s
// CHECK-V9A: #define __ARM_ARCH 9 // CHECK-V9A: #define __ARM_ARCH 9
// CHECK-V9A: #define __ARM_ARCH_9A__ 1 // CHECK-V9A: #define __ARM_ARCH_9A__ 1
// CHECK-V9A: #define __ARM_ARCH_PROFILE 'A' // CHECK-V9A: #define __ARM_ARCH_PROFILE 'A'
// RUN: %clang -target armv9.1a-none-none-eabi -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=CHECK-V91A %s // RUN: %clang -target armv9.1a-none-none-eabi -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=CHECK-V91A %s
// CHECK-V91A: #define __ARM_ARCH 9 // CHECK-V91A: #define __ARM_ARCH 9
// CHECK-V91A: #define __ARM_ARCH_9_1A__ 1 // CHECK-V91A: #define __ARM_ARCH_9_1A__ 1
▲ Show 20 Lines • Show All 61 Lines • Show Last 20 Lines

llvm/include/llvm/ADT/Triple.h

Show First 20 Lines • Show All 104 Lines • ▼ Show 20 Lines enum ArchType {
LastArchType = ve LastArchType = ve
}; };
enum SubArchType { enum SubArchType {
NoSubArch, NoSubArch,
ARMSubArch_v9_2a, ARMSubArch_v9_2a,
ARMSubArch_v9_1a, ARMSubArch_v9_1a,
ARMSubArch_v9, ARMSubArch_v9,
ARMSubArch_v8_8a,
ARMSubArch_v8_7a, ARMSubArch_v8_7a,
ARMSubArch_v8_6a, ARMSubArch_v8_6a,
ARMSubArch_v8_5a, ARMSubArch_v8_5a,
ARMSubArch_v8_4a, ARMSubArch_v8_4a,
ARMSubArch_v8_3a, ARMSubArch_v8_3a,
ARMSubArch_v8_2a, ARMSubArch_v8_2a,
ARMSubArch_v8_1a, ARMSubArch_v8_1a,
ARMSubArch_v8, ARMSubArch_v8,
▲ Show 20 Lines • Show All 850 Lines • Show Last 20 Lines

llvm/include/llvm/Support/AArch64TargetParser.def

Show First 20 Lines • Show All 52 Lines • ▼ Show 20 LinesAARCH64_ARCH("armv8.6-a", ARMV8_6A, "8.6-A", "v8.6a",
AArch64::AEK_SHA2 | AArch64::AEK_AES | AArch64::AEK_I8MM)) AArch64::AEK_SHA2 | AArch64::AEK_AES | AArch64::AEK_I8MM))
AARCH64_ARCH("armv8.7-a", ARMV8_7A, "8.7-A", "v8.7a", AARCH64_ARCH("armv8.7-a", ARMV8_7A, "8.7-A", "v8.7a",
ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8, ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8,
(AArch64::AEK_CRC | AArch64::AEK_FP | (AArch64::AEK_CRC | AArch64::AEK_FP |
AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE | AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE |
AArch64::AEK_RDM | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD | AArch64::AEK_RDM | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD |
AArch64::AEK_SM4 | AArch64::AEK_SHA3 | AArch64::AEK_BF16 | AArch64::AEK_SM4 | AArch64::AEK_SHA3 | AArch64::AEK_BF16 |
AArch64::AEK_SHA2 | AArch64::AEK_AES | AArch64::AEK_I8MM)) AArch64::AEK_SHA2 | AArch64::AEK_AES | AArch64::AEK_I8MM))
AARCH64_ARCH("armv8.8-a", ARMV8_8A, "8.8-A", "v8.8a",
ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8,
(AArch64::AEK_CRC | AArch64::AEK_FP |
AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE |
AArch64::AEK_RDM | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD |
AArch64::AEK_SM4 | AArch64::AEK_SHA3 | AArch64::AEK_BF16 |
AArch64::AEK_SHA2 | AArch64::AEK_AES | AArch64::AEK_I8MM))
AARCH64_ARCH("armv9-a", ARMV9A, "9-A", "v9a", AARCH64_ARCH("armv9-a", ARMV9A, "9-A", "v9a",
ARMBuildAttrs::CPUArch::v8_A, FK_NEON_FP_ARMV8, ARMBuildAttrs::CPUArch::v8_A, FK_NEON_FP_ARMV8,
(AArch64::AEK_CRC | AArch64::AEK_FP | (AArch64::AEK_CRC | AArch64::AEK_FP |
AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE | AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE |
AArch64::AEK_RDM | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD | AArch64::AEK_RDM | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD |
AArch64::AEK_SVE2)) AArch64::AEK_SVE2))
AARCH64_ARCH("armv9.1-a", ARMV9_1A, "9.1-A", "v9.1a", AARCH64_ARCH("armv9.1-a", ARMV9_1A, "9.1-A", "v9.1a",
ARMBuildAttrs::CPUArch::v8_A, FK_NEON_FP_ARMV8, ARMBuildAttrs::CPUArch::v8_A, FK_NEON_FP_ARMV8,
▲ Show 20 Lines • Show All 208 Lines • Show Last 20 Lines

llvm/include/llvm/Support/ARMTargetParser.def

Show First 20 Lines • Show All 116 Lines • ▼ Show 20 LinesARM_ARCH("armv8.6-a", ARMV8_6A, "8.6-A", "v8.6a",
(ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM | (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS | ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS |
ARM::AEK_DOTPROD | ARM::AEK_BF16 | ARM::AEK_I8MM)) ARM::AEK_DOTPROD | ARM::AEK_BF16 | ARM::AEK_I8MM))
ARM_ARCH("armv8.7-a", ARMV8_7A, "8.7-A", "v8.7a", ARM_ARCH("armv8.7-a", ARMV8_7A, "8.7-A", "v8.7a",
ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8, ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8,
(ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM | (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS | ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS |
ARM::AEK_DOTPROD | ARM::AEK_BF16 | ARM::AEK_I8MM)) ARM::AEK_DOTPROD | ARM::AEK_BF16 | ARM::AEK_I8MM))
ARM_ARCH("armv8.8-a", ARMV8_8A, "8.8-A", "v8.8a",
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ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8,
(ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS |
ARM::AEK_DOTPROD | ARM::AEK_BF16 | ARM::AEK_SHA2 | ARM::AEK_AES |
ARM::AEK_I8MM))
ARM_ARCH("armv9-a", ARMV9A, "9-A", "v9a", ARM_ARCH("armv9-a", ARMV9A, "9-A", "v9a",
ARMBuildAttrs::CPUArch::v8_A, FK_NEON_FP_ARMV8, ARMBuildAttrs::CPUArch::v8_A, FK_NEON_FP_ARMV8,
(ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM | (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS | ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS |
ARM::AEK_DOTPROD)) ARM::AEK_DOTPROD))
ARM_ARCH("armv9.1-a", ARMV9_1A, "9.1-A", "v9.1a", ARM_ARCH("armv9.1-a", ARMV9_1A, "9.1-A", "v9.1a",
ARMBuildAttrs::CPUArch::v8_A, FK_NEON_FP_ARMV8, ARMBuildAttrs::CPUArch::v8_A, FK_NEON_FP_ARMV8,
(ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM | (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
▲ Show 20 Lines • Show All 209 Lines • Show Last 20 Lines

llvm/lib/Support/AArch64TargetParser.cpp

Show First 20 Lines • Show All 130 Lines • ▼ Show 20 Linesbool AArch64::getArchFeatures(AArch64::ArchKind AK,
if (AK == ArchKind::ARMV8_4A) if (AK == ArchKind::ARMV8_4A)
Features.push_back("+v8.4a"); Features.push_back("+v8.4a");
if (AK == ArchKind::ARMV8_5A) if (AK == ArchKind::ARMV8_5A)
Features.push_back("+v8.5a"); Features.push_back("+v8.5a");
if (AK == AArch64::ArchKind::ARMV8_6A) if (AK == AArch64::ArchKind::ARMV8_6A)
Features.push_back("+v8.6a"); Features.push_back("+v8.6a");
if (AK == AArch64::ArchKind::ARMV8_7A) if (AK == AArch64::ArchKind::ARMV8_7A)
Features.push_back("+v8.7a"); Features.push_back("+v8.7a");
if (AK == AArch64::ArchKind::ARMV8_8A)
Features.push_back("+v8.8a");
if (AK == AArch64::ArchKind::ARMV9A) if (AK == AArch64::ArchKind::ARMV9A)
Features.push_back("+v9a"); Features.push_back("+v9a");
if (AK == AArch64::ArchKind::ARMV9_1A) if (AK == AArch64::ArchKind::ARMV9_1A)
Features.push_back("+v9.1a"); Features.push_back("+v9.1a");
if (AK == AArch64::ArchKind::ARMV9_2A) if (AK == AArch64::ArchKind::ARMV9_2A)
Features.push_back("+v9.2a"); Features.push_back("+v9.2a");
if(AK == AArch64::ArchKind::ARMV8R) if(AK == AArch64::ArchKind::ARMV8R)
Features.push_back("+v8r"); Features.push_back("+v8r");
▲ Show 20 Lines • Show All 97 Lines • Show Last 20 Lines

llvm/lib/Support/ARMTargetParser.cpp

Show First 20 Lines • Show All 71 Lines • ▼ Show 20 Linesunsigned ARM::parseArchVersion(StringRef Arch) {
case ArchKind::ARMV8A: case ArchKind::ARMV8A:
case ArchKind::ARMV8_1A: case ArchKind::ARMV8_1A:
case ArchKind::ARMV8_2A: case ArchKind::ARMV8_2A:
case ArchKind::ARMV8_3A: case ArchKind::ARMV8_3A:
case ArchKind::ARMV8_4A: case ArchKind::ARMV8_4A:
case ArchKind::ARMV8_5A: case ArchKind::ARMV8_5A:
case ArchKind::ARMV8_6A: case ArchKind::ARMV8_6A:
case ArchKind::ARMV8_7A: case ArchKind::ARMV8_7A:
case ArchKind::ARMV8_8A:
case ArchKind::ARMV8R: case ArchKind::ARMV8R:
case ArchKind::ARMV8MBaseline: case ArchKind::ARMV8MBaseline:
case ArchKind::ARMV8MMainline: case ArchKind::ARMV8MMainline:
case ArchKind::ARMV8_1MMainline: case ArchKind::ARMV8_1MMainline:
return 8; return 8;
case ArchKind::ARMV9A: case ArchKind::ARMV9A:
case ArchKind::ARMV9_1A: case ArchKind::ARMV9_1A:
case ArchKind::ARMV9_2A: case ArchKind::ARMV9_2A:
Show All 24 LinesARM::ProfileKind ARM::parseArchProfile(StringRef Arch) {
case ArchKind::ARMV8A: case ArchKind::ARMV8A:
case ArchKind::ARMV8_1A: case ArchKind::ARMV8_1A:
case ArchKind::ARMV8_2A: case ArchKind::ARMV8_2A:
case ArchKind::ARMV8_3A: case ArchKind::ARMV8_3A:
case ArchKind::ARMV8_4A: case ArchKind::ARMV8_4A:
case ArchKind::ARMV8_5A: case ArchKind::ARMV8_5A:
case ArchKind::ARMV8_6A: case ArchKind::ARMV8_6A:
case ArchKind::ARMV8_7A: case ArchKind::ARMV8_7A:
case ArchKind::ARMV8_8A:
case ArchKind::ARMV9A: case ArchKind::ARMV9A:
case ArchKind::ARMV9_1A: case ArchKind::ARMV9_1A:
case ArchKind::ARMV9_2A: case ArchKind::ARMV9_2A:
return ProfileKind::A; return ProfileKind::A;
case ArchKind::ARMV2: case ArchKind::ARMV2:
case ArchKind::ARMV2A: case ArchKind::ARMV2A:
case ArchKind::ARMV3: case ArchKind::ARMV3:
case ArchKind::ARMV3M: case ArchKind::ARMV3M:
Show All 31 Lines return StringSwitch<StringRef>(Arch)
.Cases("v8", "v8a", "v8l", "aarch64", "arm64", "v8-a") .Cases("v8", "v8a", "v8l", "aarch64", "arm64", "v8-a")
.Case("v8.1a", "v8.1-a") .Case("v8.1a", "v8.1-a")
.Case("v8.2a", "v8.2-a") .Case("v8.2a", "v8.2-a")
.Case("v8.3a", "v8.3-a") .Case("v8.3a", "v8.3-a")
.Case("v8.4a", "v8.4-a") .Case("v8.4a", "v8.4-a")
.Case("v8.5a", "v8.5-a") .Case("v8.5a", "v8.5-a")
.Case("v8.6a", "v8.6-a") .Case("v8.6a", "v8.6-a")
.Case("v8.7a", "v8.7-a") .Case("v8.7a", "v8.7-a")
.Case("v8.8a", "v8.8-a")
.Case("v8r", "v8-r") .Case("v8r", "v8-r")
.Cases("v9", "v9a", "v9-a") .Cases("v9", "v9a", "v9-a")
.Case("v9.1a", "v9.1-a") .Case("v9.1a", "v9.1-a")
.Case("v9.2a", "v9.2-a") .Case("v9.2a", "v9.2-a")
.Case("v8m.base", "v8-m.base") .Case("v8m.base", "v8-m.base")
.Case("v8m.main", "v8-m.main") .Case("v8m.main", "v8-m.main")
.Case("v8.1m.main", "v8.1-m.main") .Case("v8.1m.main", "v8.1-m.main")
.Default(Arch); .Default(Arch);
▲ Show 20 Lines • Show All 460 Lines • Show Last 20 Lines

llvm/lib/Support/Triple.cpp

Show First 20 Lines • Show All 657 Lines • ▼ Show 20 Linesstatic Triple::SubArchType parseSubArch(StringRef SubArchName) {
case ARM::ArchKind::ARMV8_4A: case ARM::ArchKind::ARMV8_4A:
return Triple::ARMSubArch_v8_4a; return Triple::ARMSubArch_v8_4a;
case ARM::ArchKind::ARMV8_5A: case ARM::ArchKind::ARMV8_5A:
return Triple::ARMSubArch_v8_5a; return Triple::ARMSubArch_v8_5a;
case ARM::ArchKind::ARMV8_6A: case ARM::ArchKind::ARMV8_6A:
return Triple::ARMSubArch_v8_6a; return Triple::ARMSubArch_v8_6a;
case ARM::ArchKind::ARMV8_7A: case ARM::ArchKind::ARMV8_7A:
return Triple::ARMSubArch_v8_7a; return Triple::ARMSubArch_v8_7a;
case ARM::ArchKind::ARMV8_8A:
return Triple::ARMSubArch_v8_8a;
case ARM::ArchKind::ARMV9A: case ARM::ArchKind::ARMV9A:
return Triple::ARMSubArch_v9; return Triple::ARMSubArch_v9;
case ARM::ArchKind::ARMV9_1A: case ARM::ArchKind::ARMV9_1A:
return Triple::ARMSubArch_v9_1a; return Triple::ARMSubArch_v9_1a;
case ARM::ArchKind::ARMV9_2A: case ARM::ArchKind::ARMV9_2A:
return Triple::ARMSubArch_v9_2a; return Triple::ARMSubArch_v9_2a;
case ARM::ArchKind::ARMV8R: case ARM::ArchKind::ARMV8R:
return Triple::ARMSubArch_v8r; return Triple::ARMSubArch_v8r;
▲ Show 20 Lines • Show All 1,136 Lines • Show Last 20 Lines

llvm/lib/Target/AArch64/AArch64.td

Show First 20 Lines • Show All 491 Lines • ▼ Show 20 Linesdef HasV8_6aOps : SubtargetFeature<
"v8.6a", "HasV8_6aOps", "true", "Support ARM v8.6a instructions", "v8.6a", "HasV8_6aOps", "true", "Support ARM v8.6a instructions",
[HasV8_5aOps, FeatureAMVS, FeatureBF16, FeatureFineGrainedTraps, [HasV8_5aOps, FeatureAMVS, FeatureBF16, FeatureFineGrainedTraps,
FeatureEnhancedCounterVirtualization, FeatureMatMulInt8]>; FeatureEnhancedCounterVirtualization, FeatureMatMulInt8]>;
def HasV8_7aOps : SubtargetFeature< def HasV8_7aOps : SubtargetFeature<
"v8.7a", "HasV8_7aOps", "true", "Support ARM v8.7a instructions", "v8.7a", "HasV8_7aOps", "true", "Support ARM v8.7a instructions",
[HasV8_6aOps, FeatureXS, FeatureWFxT, FeatureHCX]>; [HasV8_6aOps, FeatureXS, FeatureWFxT, FeatureHCX]>;
def HasV8_8aOps : SubtargetFeature<
"v8.8a", "HasV8_8aOps", "true", "Support ARM v8.8a instructions",
[HasV8_7aOps]>;
def HasV9_0aOps : SubtargetFeature< def HasV9_0aOps : SubtargetFeature<
"v9a", "HasV9_0aOps", "true", "Support ARM v9a instructions", "v9a", "HasV9_0aOps", "true", "Support ARM v9a instructions",
[HasV8_5aOps, FeatureSVE2]>; [HasV8_5aOps, FeatureSVE2]>;
def HasV9_1aOps : SubtargetFeature< def HasV9_1aOps : SubtargetFeature<
"v9.1a", "HasV9_1aOps", "true", "Support ARM v9.1a instructions", "v9.1a", "HasV9_1aOps", "true", "Support ARM v9.1a instructions",
[HasV8_6aOps, HasV9_0aOps]>; [HasV8_6aOps, HasV9_0aOps]>;
▲ Show 20 Lines • Show All 707 Lines • Show Last 20 Lines

llvm/lib/Target/AArch64/AArch64Subtarget.h

Show First 20 Lines • Show All 88 Lines • ▼ Show 20 Linesprotected:
bool HasV8_0aOps = false; bool HasV8_0aOps = false;
bool HasV8_1aOps = false; bool HasV8_1aOps = false;
bool HasV8_2aOps = false; bool HasV8_2aOps = false;
bool HasV8_3aOps = false; bool HasV8_3aOps = false;
bool HasV8_4aOps = false; bool HasV8_4aOps = false;
bool HasV8_5aOps = false; bool HasV8_5aOps = false;
bool HasV8_6aOps = false; bool HasV8_6aOps = false;
bool HasV8_7aOps = false; bool HasV8_7aOps = false;
bool HasV8_8aOps = false;
bool HasV9_0aOps = false; bool HasV9_0aOps = false;
bool HasV9_1aOps = false; bool HasV9_1aOps = false;
bool HasV9_2aOps = false; bool HasV9_2aOps = false;
bool HasV8_0rOps = false; bool HasV8_0rOps = false;
bool HasCONTEXTIDREL2 = false; bool HasCONTEXTIDREL2 = false;
bool HasEL2VMSA = false; bool HasEL2VMSA = false;
bool HasEL3 = false; bool HasEL3 = false;
▲ Show 20 Lines • Show All 571 Lines • Show Last 20 Lines

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

Show First 20 Lines • Show All 3,301 Lines • ▼ Show 20 Linesstatic void setRequiredFeatureString(FeatureBitset FBS, std::string &Str) {
else if (FBS[AArch64::HasV8_4aOps]) else if (FBS[AArch64::HasV8_4aOps])
Str += "ARMv8.4a"; Str += "ARMv8.4a";
else if (FBS[AArch64::HasV8_5aOps]) else if (FBS[AArch64::HasV8_5aOps])
Str += "ARMv8.5a"; Str += "ARMv8.5a";
else if (FBS[AArch64::HasV8_6aOps]) else if (FBS[AArch64::HasV8_6aOps])
Str += "ARMv8.6a"; Str += "ARMv8.6a";
else if (FBS[AArch64::HasV8_7aOps]) else if (FBS[AArch64::HasV8_7aOps])
Str += "ARMv8.7a"; Str += "ARMv8.7a";
else if (FBS[AArch64::HasV8_8aOps])
Str += "ARMv8.8a";
else if (FBS[AArch64::HasV9_0aOps]) else if (FBS[AArch64::HasV9_0aOps])
Str += "ARMv9-a"; Str += "ARMv9-a";
else if (FBS[AArch64::HasV9_1aOps]) else if (FBS[AArch64::HasV9_1aOps])
Str += "ARMv9.1a"; Str += "ARMv9.1a";
else if (FBS[AArch64::HasV9_2aOps]) else if (FBS[AArch64::HasV9_2aOps])
Str += "ARMv9.2a"; Str += "ARMv9.2a";
else if (FBS[AArch64::HasV8_0rOps]) else if (FBS[AArch64::HasV8_0rOps])
Str += "ARMv8r"; Str += "ARMv8r";
▲ Show 20 Lines • Show All 2,608 Lines • ▼ Show 20 Lines if (!NoCrypto && Crypto) {
case AArch64::ArchKind::ARMV8_3A: case AArch64::ArchKind::ARMV8_3A:
RequestedExtensions.push_back("sha2"); RequestedExtensions.push_back("sha2");
RequestedExtensions.push_back("aes"); RequestedExtensions.push_back("aes");
break; break;
case AArch64::ArchKind::ARMV8_4A: case AArch64::ArchKind::ARMV8_4A:
case AArch64::ArchKind::ARMV8_5A: case AArch64::ArchKind::ARMV8_5A:
case AArch64::ArchKind::ARMV8_6A: case AArch64::ArchKind::ARMV8_6A:
case AArch64::ArchKind::ARMV8_7A: case AArch64::ArchKind::ARMV8_7A:
case AArch64::ArchKind::ARMV8_8A:
case AArch64::ArchKind::ARMV9A: case AArch64::ArchKind::ARMV9A:
case AArch64::ArchKind::ARMV9_1A: case AArch64::ArchKind::ARMV9_1A:
case AArch64::ArchKind::ARMV9_2A: case AArch64::ArchKind::ARMV9_2A:
case AArch64::ArchKind::ARMV8R: case AArch64::ArchKind::ARMV8R:
RequestedExtensions.push_back("sm4"); RequestedExtensions.push_back("sm4");
RequestedExtensions.push_back("sha3"); RequestedExtensions.push_back("sha3");
RequestedExtensions.push_back("sha2"); RequestedExtensions.push_back("sha2");
RequestedExtensions.push_back("aes"); RequestedExtensions.push_back("aes");
Show All 9 Lines if (!NoCrypto && Crypto) {
case AArch64::ArchKind::ARMV8_3A: case AArch64::ArchKind::ARMV8_3A:
RequestedExtensions.push_back("nosha2"); RequestedExtensions.push_back("nosha2");
RequestedExtensions.push_back("noaes"); RequestedExtensions.push_back("noaes");
break; break;
case AArch64::ArchKind::ARMV8_4A: case AArch64::ArchKind::ARMV8_4A:
case AArch64::ArchKind::ARMV8_5A: case AArch64::ArchKind::ARMV8_5A:
case AArch64::ArchKind::ARMV8_6A: case AArch64::ArchKind::ARMV8_6A:
case AArch64::ArchKind::ARMV8_7A: case AArch64::ArchKind::ARMV8_7A:
case AArch64::ArchKind::ARMV8_8A:
case AArch64::ArchKind::ARMV9A: case AArch64::ArchKind::ARMV9A:
case AArch64::ArchKind::ARMV9_1A: case AArch64::ArchKind::ARMV9_1A:
case AArch64::ArchKind::ARMV9_2A: case AArch64::ArchKind::ARMV9_2A:
RequestedExtensions.push_back("nosm4"); RequestedExtensions.push_back("nosm4");
RequestedExtensions.push_back("nosha3"); RequestedExtensions.push_back("nosha3");
RequestedExtensions.push_back("nosha2"); RequestedExtensions.push_back("nosha2");
RequestedExtensions.push_back("noaes"); RequestedExtensions.push_back("noaes");
break; break;
▲ Show 20 Lines • Show All 938 Lines • Show Last 20 Lines

llvm/lib/Target/ARM/ARM.td

Show First 20 Lines • Show All 547 Lines • ▼ Show 20 Linesdef HasV8_6aOps : SubtargetFeature<"v8.6a", "HasV8_6aOps", "true",
"Support ARM v8.6a instructions", "Support ARM v8.6a instructions",
[HasV8_5aOps, FeatureBF16, [HasV8_5aOps, FeatureBF16,
FeatureMatMulInt8]>; FeatureMatMulInt8]>;
def HasV8_7aOps : SubtargetFeature<"v8.7a", "HasV8_7aOps", "true", def HasV8_7aOps : SubtargetFeature<"v8.7a", "HasV8_7aOps", "true",
"Support ARM v8.7a instructions", "Support ARM v8.7a instructions",
[HasV8_6aOps]>; [HasV8_6aOps]>;
def HasV8_8aOps : SubtargetFeature<"v8.8a", "HasV8_8aOps", "true",
"Support ARM v8.8a instructions",
[HasV8_7aOps]>;
def HasV9_0aOps : SubtargetFeature<"v9a", "HasV9_0aOps", "true", def HasV9_0aOps : SubtargetFeature<"v9a", "HasV9_0aOps", "true",
"Support ARM v9a instructions", "Support ARM v9a instructions",
[HasV8_5aOps]>; [HasV8_5aOps]>;
def HasV9_1aOps : SubtargetFeature<"v9.1a", "HasV9_1aOps", "true", def HasV9_1aOps : SubtargetFeature<"v9.1a", "HasV9_1aOps", "true",
"Support ARM v9.1a instructions", "Support ARM v9.1a instructions",
[HasV8_6aOps, HasV9_0aOps]>; [HasV8_6aOps, HasV9_0aOps]>;
▲ Show 20 Lines • Show All 325 Lines • ▼ Show 20 Linesdef ARMv87a : Architecture<"armv8.7-a", "ARMv87a", [HasV8_7aOps,
FeatureDSP, FeatureDSP,
FeatureTrustZone, FeatureTrustZone,
FeatureMP, FeatureMP,
FeatureVirtualization, FeatureVirtualization,
FeatureCrypto, FeatureCrypto,
FeatureCRC, FeatureCRC,
FeatureRAS, FeatureRAS,
FeatureDotProd]>; FeatureDotProd]>;
def ARMv88a : Architecture<"armv8.8-a", "ARMv88a", [HasV8_8aOps,
FeatureAClass,
FeatureDB,
FeatureFPARMv8,
FeatureNEON,
FeatureDSP,
FeatureTrustZone,
FeatureMP,
FeatureVirtualization,
FeatureCrypto,
FeatureCRC,
FeatureRAS,
FeatureDotProd]>;
def ARMv9a : Architecture<"armv9-a", "ARMv9a", [HasV9_0aOps, def ARMv9a : Architecture<"armv9-a", "ARMv9a", [HasV9_0aOps,
FeatureAClass, FeatureAClass,
FeatureDB, FeatureDB,
FeatureFPARMv8, FeatureFPARMv8,
FeatureNEON, FeatureNEON,
FeatureDSP, FeatureDSP,
FeatureTrustZone, FeatureTrustZone,
▲ Show 20 Lines • Show All 589 Lines • Show Last 20 Lines

llvm/lib/Target/ARM/ARMSubtarget.h

Show First 20 Lines • Show All 115 Lines • ▼ Show 20 Lines enum ARMArchEnum {
ARMv7ve, ARMv7ve,
ARMv81a, ARMv81a,
ARMv82a, ARMv82a,
ARMv83a, ARMv83a,
ARMv84a, ARMv84a,
ARMv85a, ARMv85a,
ARMv86a, ARMv86a,
ARMv87a, ARMv87a,
ARMv88a,
ARMv8a, ARMv8a,
ARMv8mBaseline, ARMv8mBaseline,
ARMv8mMainline, ARMv8mMainline,
ARMv8r, ARMv8r,
ARMv81mMainline, ARMv81mMainline,
ARMv9a, ARMv9a,
ARMv91a, ARMv91a,
ARMv92a, ARMv92a,
Show All 37 Linesprotected:
bool HasV7Ops = false; bool HasV7Ops = false;
bool HasV8Ops = false; bool HasV8Ops = false;
bool HasV8_1aOps = false; bool HasV8_1aOps = false;
bool HasV8_2aOps = false; bool HasV8_2aOps = false;
bool HasV8_3aOps = false; bool HasV8_3aOps = false;
bool HasV8_4aOps = false; bool HasV8_4aOps = false;
bool HasV8_5aOps = false; bool HasV8_5aOps = false;
bool HasV8_6aOps = false; bool HasV8_6aOps = false;
bool HasV8_8aOps = false;
bool HasV8_7aOps = false; bool HasV8_7aOps = false;
bool HasV9_0aOps = false; bool HasV9_0aOps = false;
bool HasV9_1aOps = false; bool HasV9_1aOps = false;
bool HasV9_2aOps = false; bool HasV9_2aOps = false;
bool HasV8MBaselineOps = false; bool HasV8MBaselineOps = false;
bool HasV8MMainlineOps = false; bool HasV8MMainlineOps = false;
bool HasV8_1MMainlineOps = false; bool HasV8_1MMainlineOps = false;
bool HasMVEIntegerOps = false; bool HasMVEIntegerOps = false;
▲ Show 20 Lines • Show All 445 Lines • ▼ Show 20 Linespublic:
bool hasV8Ops() const { return HasV8Ops; } bool hasV8Ops() const { return HasV8Ops; }
bool hasV8_1aOps() const { return HasV8_1aOps; } bool hasV8_1aOps() const { return HasV8_1aOps; }
bool hasV8_2aOps() const { return HasV8_2aOps; } bool hasV8_2aOps() const { return HasV8_2aOps; }
bool hasV8_3aOps() const { return HasV8_3aOps; } bool hasV8_3aOps() const { return HasV8_3aOps; }
bool hasV8_4aOps() const { return HasV8_4aOps; } bool hasV8_4aOps() const { return HasV8_4aOps; }
bool hasV8_5aOps() const { return HasV8_5aOps; } bool hasV8_5aOps() const { return HasV8_5aOps; }
bool hasV8_6aOps() const { return HasV8_6aOps; } bool hasV8_6aOps() const { return HasV8_6aOps; }
bool hasV8_7aOps() const { return HasV8_7aOps; } bool hasV8_7aOps() const { return HasV8_7aOps; }
bool hasV8_8aOps() const { return HasV8_8aOps; }
bool hasV9_0aOps() const { return HasV9_0aOps; } bool hasV9_0aOps() const { return HasV9_0aOps; }
bool hasV9_1aOps() const { return HasV9_1aOps; } bool hasV9_1aOps() const { return HasV9_1aOps; }
bool hasV9_2aOps() const { return HasV9_2aOps; } bool hasV9_2aOps() const { return HasV9_2aOps; }
bool hasV8MBaselineOps() const { return HasV8MBaselineOps; } bool hasV8MBaselineOps() const { return HasV8MBaselineOps; }
bool hasV8MMainlineOps() const { return HasV8MMainlineOps; } bool hasV8MMainlineOps() const { return HasV8MMainlineOps; }
bool hasV8_1MMainlineOps() const { return HasV8_1MMainlineOps; } bool hasV8_1MMainlineOps() const { return HasV8_1MMainlineOps; }
bool hasMVEIntegerOps() const { return HasMVEIntegerOps; } bool hasMVEIntegerOps() const { return HasMVEIntegerOps; }
bool hasMVEFloatOps() const { return HasMVEFloatOps; } bool hasMVEFloatOps() const { return HasMVEFloatOps; }
▲ Show 20 Lines • Show All 319 Lines • Show Last 20 Lines

llvm/unittests/Support/TargetParserTest.cpp

Show All 12 Lines
#include "llvm/Support/FormatVariadic.h" #include "llvm/Support/FormatVariadic.h"
#include "gtest/gtest.h" #include "gtest/gtest.h"
#include <string> #include <string>
using namespace llvm; using namespace llvm;
namespace { namespace {
const char *ARMArch[] = { const char *ARMArch[] = {
"armv2", "armv2a", "armv3", "armv3m", "armv4", "armv2", "armv2a", "armv3", "armv3m", "armv4",
"armv4t", "armv5", "armv5t", "armv5e", "armv5te", "armv4t", "armv5", "armv5t", "armv5e", "armv5te",
"armv5tej", "armv6", "armv6j", "armv6k", "armv6hl", "armv5tej", "armv6", "armv6j", "armv6k", "armv6hl",
"armv6t2", "armv6kz", "armv6z", "armv6zk", "armv6-m", "armv6t2", "armv6kz", "armv6z", "armv6zk", "armv6-m",
"armv6m", "armv6sm", "armv6s-m", "armv7-a", "armv7", "armv6m", "armv6sm", "armv6s-m", "armv7-a", "armv7",
"armv7a", "armv7ve", "armv7hl", "armv7l", "armv7-r", "armv7a", "armv7ve", "armv7hl", "armv7l", "armv7-r",
"armv7r", "armv7-m", "armv7m", "armv7k", "armv7s", "armv7r", "armv7-m", "armv7m", "armv7k", "armv7s",
"armv7e-m", "armv7em", "armv8-a", "armv8", "armv8a", "armv7e-m", "armv7em", "armv8-a", "armv8", "armv8a",
"armv8l", "armv8.1-a", "armv8.1a", "armv8.2-a", "armv8.2a", "armv8l", "armv8.1-a", "armv8.1a", "armv8.2-a", "armv8.2a",
"armv8.3-a", "armv8.3a", "armv8.4-a", "armv8.4a", "armv8.5-a", "armv8.3-a", "armv8.3a", "armv8.4-a", "armv8.4a", "armv8.5-a",
"armv8.5a", "armv8.6-a", "armv8.6a", "armv8.7-a", "armv8.7a", "armv8.5a", "armv8.6-a", "armv8.6a", "armv8.7-a", "armv8.7a",
"armv8-r", "armv8r", "armv8-m.base","armv8m.base", "armv8-m.main", "armv8.8-a", "armv8.8a", "armv8-r", "armv8r", "armv8-m.base",
"armv8m.main", "iwmmxt", "iwmmxt2", "xscale", "armv8.1-m.main", "armv8m.base", "armv8-m.main", "armv8m.main", "iwmmxt", "iwmmxt2",
"armv9-a", "armv9", "armv9a", "armv9.1-a", "armv9.1a", "xscale", "armv8.1-m.main", "armv9-a", "armv9", "armv9a",
"armv9.2-a", "armv9.2a", "armv9.1-a", "armv9.1a", "armv9.2-a", "armv9.2a",
}; };
template <ARM::ISAKind ISAKind> template <ARM::ISAKind ISAKind>
std::string FormatExtensionFlags(uint64_t Flags) { std::string FormatExtensionFlags(uint64_t Flags) {
std::vector<StringRef> Features; std::vector<StringRef> Features;
if (ISAKind == ARM::ISAKind::AARCH64) { if (ISAKind == ARM::ISAKind::AARCH64) {
// AEK_NONE is not meant to be shown to the user so the target parser // AEK_NONE is not meant to be shown to the user so the target parser
▲ Show 20 Lines • Show All 452 Lines • ▼ Show 20 Lines EXPECT_TRUE(
testARMArch("armv8.5-a", "generic", "v8.5a", testARMArch("armv8.5-a", "generic", "v8.5a",
ARMBuildAttrs::CPUArch::v8_A)); ARMBuildAttrs::CPUArch::v8_A));
EXPECT_TRUE( EXPECT_TRUE(
testARMArch("armv8.6-a", "generic", "v8.6a", testARMArch("armv8.6-a", "generic", "v8.6a",
ARMBuildAttrs::CPUArch::v8_A)); ARMBuildAttrs::CPUArch::v8_A));
EXPECT_TRUE( EXPECT_TRUE(
testARMArch("armv8.7-a", "generic", "v8.7a", testARMArch("armv8.7-a", "generic", "v8.7a",
ARMBuildAttrs::CPUArch::v8_A)); ARMBuildAttrs::CPUArch::v8_A));
EXPECT_TRUE(testARMArch("armv8.8-a", "generic", "v8.8a",
ARMBuildAttrs::CPUArch::v8_A));
EXPECT_TRUE( EXPECT_TRUE(
testARMArch("armv9-a", "generic", "v9a", testARMArch("armv9-a", "generic", "v9a",
ARMBuildAttrs::CPUArch::v8_A)); ARMBuildAttrs::CPUArch::v8_A));
EXPECT_TRUE( EXPECT_TRUE(
testARMArch("armv9.1-a", "generic", "v9.1a", testARMArch("armv9.1-a", "generic", "v9.1a",
ARMBuildAttrs::CPUArch::v8_A)); ARMBuildAttrs::CPUArch::v8_A));
EXPECT_TRUE( EXPECT_TRUE(
testARMArch("armv9.2-a", "generic", "v9.2a", testARMArch("armv9.2-a", "generic", "v9.2a",
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 LinesTEST(TargetParserTest, ARMparseHWDiv) {
const char *hwdiv[] = {"thumb", "arm", "arm,thumb", "thumb,arm"}; const char *hwdiv[] = {"thumb", "arm", "arm,thumb", "thumb,arm"};
for (unsigned i = 0; i < array_lengthof(hwdiv); i++) for (unsigned i = 0; i < array_lengthof(hwdiv); i++)
EXPECT_NE(ARM::AEK_INVALID, ARM::parseHWDiv((StringRef)hwdiv[i])); EXPECT_NE(ARM::AEK_INVALID, ARM::parseHWDiv((StringRef)hwdiv[i]));
} }
TEST(TargetParserTest, ARMparseArchEndianAndISA) { TEST(TargetParserTest, ARMparseArchEndianAndISA) {
const char *Arch[] = { const char *Arch[] = {
"v2", "v2a", "v3", "v3m", "v4", "v4t", "v5", "v5t", "v2", "v2a", "v3", "v3m", "v4", "v4t",
"v5e", "v5te", "v5tej", "v6", "v6j", "v6k", "v6hl", "v6t2", "v5", "v5t", "v5e", "v5te", "v5tej", "v6",
"v6kz", "v6z", "v6zk", "v6-m", "v6m", "v6sm", "v6s-m", "v7-a", "v6j", "v6k", "v6hl", "v6t2", "v6kz", "v6z",
"v7", "v7a", "v7ve", "v7hl", "v7l", "v7-r", "v7r", "v7-m", "v6zk", "v6-m", "v6m", "v6sm", "v6s-m", "v7-a",
"v7m", "v7k", "v7s", "v7e-m", "v7em", "v8-a", "v8", "v8a", "v7", "v7a", "v7ve", "v7hl", "v7l", "v7-r",
"v8l", "v8.1-a", "v8.1a", "v8.2-a", "v8.2a", "v8.3-a", "v8.3a", "v8.4-a", "v7r", "v7-m", "v7m", "v7k", "v7s", "v7e-m",
"v8.4a", "v8.5-a","v8.5a", "v8.6-a", "v8.6a", "v8.7-a", "v8.7a", "v8-r", "v7em", "v8-a", "v8", "v8a", "v8l", "v8.1-a",
"v8m.base", "v8m.main", "v8.1m.main" "v8.1a", "v8.2-a", "v8.2a", "v8.3-a", "v8.3a", "v8.4-a",
}; "v8.4a", "v8.5-a", "v8.5a", "v8.6-a", "v8.6a", "v8.7-a",
"v8.7a", "v8.8-a", "v8.8a", "v8-r", "v8m.base", "v8m.main",
"v8.1m.main"};
for (unsigned i = 0; i < array_lengthof(Arch); i++) { for (unsigned i = 0; i < array_lengthof(Arch); i++) {
std::string arm_1 = "armeb" + (std::string)(Arch[i]); std::string arm_1 = "armeb" + (std::string)(Arch[i]);
std::string arm_2 = "arm" + (std::string)(Arch[i]) + "eb"; std::string arm_2 = "arm" + (std::string)(Arch[i]) + "eb";
std::string arm_3 = "arm" + (std::string)(Arch[i]); std::string arm_3 = "arm" + (std::string)(Arch[i]);
std::string thumb_1 = "thumbeb" + (std::string)(Arch[i]); std::string thumb_1 = "thumbeb" + (std::string)(Arch[i]);
std::string thumb_2 = "thumb" + (std::string)(Arch[i]) + "eb"; std::string thumb_2 = "thumb" + (std::string)(Arch[i]) + "eb";
std::string thumb_3 = "thumb" + (std::string)(Arch[i]); std::string thumb_3 = "thumb" + (std::string)(Arch[i]);
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Lines for (unsigned i = 0; i < array_lengthof(ARMArch); i++) {
case ARM::ArchKind::ARMV8A: case ARM::ArchKind::ARMV8A:
case ARM::ArchKind::ARMV8_1A: case ARM::ArchKind::ARMV8_1A:
case ARM::ArchKind::ARMV8_2A: case ARM::ArchKind::ARMV8_2A:
case ARM::ArchKind::ARMV8_3A: case ARM::ArchKind::ARMV8_3A:
case ARM::ArchKind::ARMV8_4A: case ARM::ArchKind::ARMV8_4A:
case ARM::ArchKind::ARMV8_5A: case ARM::ArchKind::ARMV8_5A:
case ARM::ArchKind::ARMV8_6A: case ARM::ArchKind::ARMV8_6A:
case ARM::ArchKind::ARMV8_7A: case ARM::ArchKind::ARMV8_7A:
case ARM::ArchKind::ARMV8_8A:
case ARM::ArchKind::ARMV9A: case ARM::ArchKind::ARMV9A:
case ARM::ArchKind::ARMV9_1A: case ARM::ArchKind::ARMV9_1A:
case ARM::ArchKind::ARMV9_2A: case ARM::ArchKind::ARMV9_2A:
EXPECT_EQ(ARM::ProfileKind::A, ARM::parseArchProfile(ARMArch[i])); EXPECT_EQ(ARM::ProfileKind::A, ARM::parseArchProfile(ARMArch[i]));
break; break;
default: default:
EXPECT_EQ(ARM::ProfileKind::INVALID, ARM::parseArchProfile(ARMArch[i])); EXPECT_EQ(ARM::ProfileKind::INVALID, ARM::parseArchProfile(ARMArch[i]));
break; break;
▲ Show 20 Lines • Show All 411 Lines • ▼ Show 20 LinesTEST(TargetParserTest, testAArch64Arch) {
EXPECT_TRUE(testAArch64Arch("armv8.4-a", "generic", "v8.4a", EXPECT_TRUE(testAArch64Arch("armv8.4-a", "generic", "v8.4a",
ARMBuildAttrs::CPUArch::v8_A)); ARMBuildAttrs::CPUArch::v8_A));
EXPECT_TRUE(testAArch64Arch("armv8.5-a", "generic", "v8.5a", EXPECT_TRUE(testAArch64Arch("armv8.5-a", "generic", "v8.5a",
ARMBuildAttrs::CPUArch::v8_A)); ARMBuildAttrs::CPUArch::v8_A));
EXPECT_TRUE(testAArch64Arch("armv8.6-a", "generic", "v8.6a", EXPECT_TRUE(testAArch64Arch("armv8.6-a", "generic", "v8.6a",
ARMBuildAttrs::CPUArch::v8_A)); ARMBuildAttrs::CPUArch::v8_A));
EXPECT_TRUE(testAArch64Arch("armv8.7-a", "generic", "v8.7a", EXPECT_TRUE(testAArch64Arch("armv8.7-a", "generic", "v8.7a",
ARMBuildAttrs::CPUArch::v8_A)); ARMBuildAttrs::CPUArch::v8_A));
EXPECT_TRUE(testAArch64Arch("armv8.8-a", "generic", "v8.8a",
ARMBuildAttrs::CPUArch::v8_A));
EXPECT_TRUE(testAArch64Arch("armv9-a", "generic", "v9a", EXPECT_TRUE(testAArch64Arch("armv9-a", "generic", "v9a",
ARMBuildAttrs::CPUArch::v8_A)); ARMBuildAttrs::CPUArch::v8_A));
EXPECT_TRUE(testAArch64Arch("armv9.1-a", "generic", "v9.1a", EXPECT_TRUE(testAArch64Arch("armv9.1-a", "generic", "v9.1a",
ARMBuildAttrs::CPUArch::v8_A)); ARMBuildAttrs::CPUArch::v8_A));
EXPECT_TRUE(testAArch64Arch("armv9.2-a", "generic", "v9.2a", EXPECT_TRUE(testAArch64Arch("armv9.2-a", "generic", "v9.2a",
ARMBuildAttrs::CPUArch::v8_A)); ARMBuildAttrs::CPUArch::v8_A));
} }
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