[AArch64] Add mayRaiseFPException to appropriate instructions

[john.brawn]

Summary

This is mostly handled by adding "let mayRaiseFPException = 1" before the definition of the relevant instruction classes, but there are a couple of complications:

• When we have a multiclass where currently some instantiations are of instructions that can raise an exception and others aren't we need to split that into two multiclasses, one inheriting from the other using a multiclass parameter to enable exceptions.
• In a couple of places in the globalisel instruction selector we need to manually set the NoFPExcept flag. There's also another place that looks like it should need it, but that code is never hit for those opcodes due to them being handled by the generic instruction selector, so I've instead just removed them from the switch.

[dmgreen]

It looks like we have to do this very carefully to do it in a way that doesn't alter non-strict codegen for the worse, especially in making sure that nofpexcept flags are set everywhere. As far as I understand it should be an NFC there. The MachineCombiner isn't propagating flags at the moment, for example.

llvm/lib/Target/AArch64/AArch64InstrFormats.td

5037

Do we need to add this, or is it simpler to pass fpexceptions=0 from where it is used?

[john.brawn]

It looks like the machine combiner thing is a general problem with the AArch64 patterns not preserving MIFlags. I'll look into it.

[john.brawn]

I've created D118621 for making the AArch64 machine combiner patterns preserve MIFlags.

llvm/lib/Target/AArch64/AArch64InstrFormats.td

5037

Doing it this way makes things simpler for the next step, which is marking instructions as reading FPCR, as there's no direct way to express "this multiclass instantiation doesn't use a register that the multiclass does" and the best solution I've come up with is having it be decided in the multiclass by a multiclass parameter.

[john.brawn]

Rebased.

[john.brawn]

Ping.

[john.brawn]

Rebase and ping.

[dmgreen]

The original version of this patch was altering the non-strict codegen because the flags were lost in the machine combiner. Have you done any other testing to make sure that doesn't happen anywhere else? To make sure this doesn't pessimise the performance for the default non-strict case.

[john.brawn]

In D115352#3399965, @dmgreen wrote:

The original version of this patch was altering the non-strict codegen because the flags were lost in the machine combiner. Have you done any other testing to make sure that doesn't happen anywhere else? To make sure this doesn't pessimise the performance for the default non-strict case.

I've build all of the MultiSource and SingleSource tests in llvm-test-suite with and without this patch (and those it depends on) at -O3 and there are no changes to the generated code.

[dmgreen]

In D115352#3419239, @john.brawn wrote:

In D115352#3399965, @dmgreen wrote:

The original version of this patch was altering the non-strict codegen because the flags were lost in the machine combiner. Have you done any other testing to make sure that doesn't happen anywhere else? To make sure this doesn't pessimise the performance for the default non-strict case.

I've build all of the MultiSource and SingleSource tests in llvm-test-suite with and without this patch (and those it depends on) at -O3 and there are no changes to the generated code.

Thanks for checking. There might be other patterns that more rarely come up, but if they don't come up there and in the llvm tests then that's at least a good sign.

LGTM

llvm/lib/Target/AArch64/AArch64InstrFormats.td

 }
 }
 let Predicates = [HasFPARMv8] in {
 
 //---
 // Floating point to integer conversion
 //---
 
+let mayRaiseFPException = 1 in
 class BaseFPToIntegerUnscaled<bits<2> type, bits<2> rmode, bits<3> opcode,
                       RegisterClass srcType, RegisterClass dstType,
                       string asm, list<dag> pattern>
     : I<(outs dstType:$Rd), (ins srcType:$Rn),
          asm, "\t$Rd, $Rn", "", pattern>,
       Sched<[WriteFCvt]> {
   bits<5> Rd;
   bits<5> Rn;
   let Inst{30-29} = 0b00;
   let Inst{28-24} = 0b11110;
   let Inst{23-22} = type;
   let Inst{21}    = 1;
   let Inst{20-19} = rmode;
   let Inst{18-16} = opcode;
   let Inst{15-10} = 0;
   let Inst{9-5}   = Rn;
   let Inst{4-0}   = Rd;
 }
 
-let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
+let mayLoad = 0, mayStore = 0, hasSideEffects = 0, mayRaiseFPException = 1 in
 class BaseFPToInteger<bits<2> type, bits<2> rmode, bits<3> opcode,
                       RegisterClass srcType, RegisterClass dstType,
                       Operand immType, string asm, list<dag> pattern>
     : I<(outs dstType:$Rd), (ins srcType:$Rn, immType:$scale),
          asm, "\t$Rd, $Rn, $scale", "", pattern>,
       Sched<[WriteFCvt]> {
   bits<5> Rd;
   bits<5> Rn;
def SXDri : BaseFPToInteger<0b01, rmode, opcode, FPR64, GPR64,
     let Inst{31} = 1; // 64-bit GPR flag
   }
 }
 
 //---
 // Integer to floating point conversion
 //---
 
-let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
+let mayStore = 0, mayLoad = 0, hasSideEffects = 0, mayRaiseFPException = 1 in
 class BaseIntegerToFP<bit isUnsigned,
                       RegisterClass srcType, RegisterClass dstType,
                       Operand immType, string asm, list<dag> pattern>
     : I<(outs dstType:$Rd), (ins srcType:$Rn, immType:$scale),
          asm, "\t$Rd, $Rn, $scale", "", pattern>,
       Sched<[WriteFCvt]> {
   bits<5> Rd;
   bits<5> Rn;
   bits<6> scale;
   let Inst{30-24} = 0b0011110;
   let Inst{21-17} = 0b00001;
   let Inst{16}    = isUnsigned;
   let Inst{15-10} = scale;
   let Inst{9-5}   = Rn;
   let Inst{4-0}   = Rd;
 }
 
+let mayRaiseFPException = 1 in
 class BaseIntegerToFPUnscaled<bit isUnsigned,
                       RegisterClass srcType, RegisterClass dstType,
                       ValueType dvt, string asm, SDPatternOperator node>
     : I<(outs dstType:$Rd), (ins srcType:$Rn),
          asm, "\t$Rd, $Rn", "", [(set (dvt dstType:$Rd), (node srcType:$Rn))]>,
       Sched<[WriteFCvt]> {
   bits<5> Rd;
   bits<5> Rn;
def DXHighr : BaseUnscaledConversionFromHigh<0b01, 0b110, V128, GPR64,
     let Inst{22} = 0;
   }
 }
 
 //---
 // Floating point conversion
 //---
 
+let mayRaiseFPException = 1 in
 class BaseFPConversion<bits<2> type, bits<2> opcode, RegisterClass dstType,
                        RegisterClass srcType, string asm, list<dag> pattern>
     : I<(outs dstType:$Rd), (ins srcType:$Rn), asm, "\t$Rd, $Rn", "", pattern>,
       Sched<[WriteFCvt]> {
   bits<5> Rd;
   bits<5> Rn;
   let Inst{31-24} = 0b00011110;
   let Inst{23-22} = type;
class BaseSingleOperandFPData<bits<6> opcode, RegisterClass regtype,
   let Inst{21}    = 0b1;
   let Inst{20-15} = opcode;
   let Inst{14-10} = 0b10000;
   let Inst{9-5}   = Rn;
   let Inst{4-0}   = Rd;
 }
 
 multiclass SingleOperandFPData<bits<4> opcode, string asm,
-                               SDPatternOperator node = null_frag> {
-
+                               SDPatternOperator node = null_frag,
+                               int fpexceptions = 1> {
+  let mayRaiseFPException = fpexceptions in {
   def Hr : BaseSingleOperandFPData<{0b00,opcode}, FPR16, f16, asm, node> {
     let Inst{23-22} = 0b11; // 16-bit size flag
     let Predicates = [HasFullFP16];
   }
 
   def Sr : BaseSingleOperandFPData<{0b00,opcode}, FPR32, f32, asm, node> {
     let Inst{23-22} = 0b00; // 32-bit size flag
   }
 
   def Dr : BaseSingleOperandFPData<{0b00,opcode}, FPR64, f64, asm, node> {
     let Inst{23-22} = 0b01; // 64-bit size flag
   }
   }
+}
+
+multiclass SingleOperandFPDataNoException<bits<4> opcode, string asm,
+                                       SDPatternOperator node = null_frag>
+    : SingleOperandFPData<opcode, asm, node, 0>;
 
+let mayRaiseFPException = 1 in
 multiclass SingleOperandFPNo16<bits<6> opcode, string asm,
                   SDPatternOperator node = null_frag>{
 
   def Sr : BaseSingleOperandFPData<opcode, FPR32, f32, asm, node> {
     let Inst{23-22} = 0b00; // 32-bit registers
   }
 
   def Dr : BaseSingleOperandFPData<opcode, FPR64, f64, asm, node> {
     let Inst{23-22} = 0b01; // 64-bit registers
   }
 }
 
 // FRInt[32|64][Z|N] instructions
 multiclass FRIntNNT<bits<2> opcode, string asm, SDPatternOperator node = null_frag> :
       SingleOperandFPNo16<{0b0100,opcode}, asm, node>;
 
 //---
 // Two operand floating point data processing
 //---
 
-let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
+let mayLoad = 0, mayStore = 0, hasSideEffects = 0, mayRaiseFPException = 1 in
 class BaseTwoOperandFPData<bits<4> opcode, RegisterClass regtype,
                            string asm, list<dag> pat>
     : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
          asm, "\t$Rd, $Rn, $Rm", "", pat>,
       Sched<[WriteF]> {
   bits<5> Rd;
   bits<5> Rn;
   bits<5> Rm;
multiclass TwoOperandFPDataNeg<bits<4> opcode, string asm,
   }
 }
 
 
 //---
 // Three operand floating point data processing
 //---
 
+let mayRaiseFPException = 1 in
 class BaseThreeOperandFPData<bit isNegated, bit isSub,
                              RegisterClass regtype, string asm, list<dag> pat>
     : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, regtype: $Ra),
          asm, "\t$Rd, $Rn, $Rm, $Ra", "", pat>,
       Sched<[WriteFMul]> {
   bits<5> Rd;
   bits<5> Rn;
   bits<5> Rm;
def Drrr : BaseThreeOperandFPData<isNegated, isSub, FPR64, asm,
     let Inst{23-22} = 0b01; // 64-bit size flag
   }
 }
 
 //---
 // Floating point data comparisons
 //---
 
-let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
+let mayLoad = 0, mayStore = 0, hasSideEffects = 0, mayRaiseFPException = 1 in
 class BaseOneOperandFPComparison<bit signalAllNans,
                                  RegisterClass regtype, string asm,
                                  list<dag> pat>
     : I<(outs), (ins regtype:$Rn), asm, "\t$Rn, #0.0", "", pat>,
       Sched<[WriteFCmp]> {
   bits<5> Rn;
   let Inst{31-24} = 0b00011110;
   let Inst{21}    = 1;
 
   let Inst{15-10} = 0b001000;
   let Inst{9-5}   = Rn;
   let Inst{4}     = signalAllNans;
   let Inst{3-0}   = 0b1000;
 
   // Rm should be 0b00000 canonically, but we need to accept any value.
   let PostEncoderMethod = "fixOneOperandFPComparison";
 }
 
-let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
+let mayLoad = 0, mayStore = 0, hasSideEffects = 0, mayRaiseFPException = 1 in
 class BaseTwoOperandFPComparison<bit signalAllNans, RegisterClass regtype,
                                 string asm, list<dag> pat>
     : I<(outs), (ins regtype:$Rn, regtype:$Rm), asm, "\t$Rn, $Rm", "", pat>,
       Sched<[WriteFCmp]> {
   bits<5> Rm;
   bits<5> Rn;
   let Inst{31-24} = 0b00011110;
   let Inst{21}    = 1;
multiclass FPComparison<bit signalAllNans, string asm,
   }
   } // Defs = [NZCV]
 }
 
 //---
 // Floating point conditional comparisons
 //---
 
-let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
+let mayLoad = 0, mayStore = 0, hasSideEffects = 0, mayRaiseFPException = 1 in
 class BaseFPCondComparison<bit signalAllNans, RegisterClass regtype,
                            string mnemonic, list<dag> pat>
     : I<(outs), (ins regtype:$Rn, regtype:$Rm, imm32_0_15:$nzcv, ccode:$cond),
          mnemonic, "\t$Rn, $Rm, $nzcv, $cond", "", pat>,
       Sched<[WriteFCmp]> {
   let Uses = [NZCV];
   let Defs = [NZCV];
 
def v8i8  : BaseSIMDThreeSameVector<0, U, 0b001, opc, V64,
     [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
   def v16i8 : BaseSIMDThreeSameVector<1, U, 0b001, opc, V128,
                                       asm, ".16b",
     [(set (v16i8 V128:$Rd),
           (OpNode (v16i8 V128:$Rn), (v16i8 V128:$Rm)))]>;
 }
 
 // As above, but only floating point elements supported.
+let mayRaiseFPException = 1 in
 multiclass SIMDThreeSameVectorFP<bit U, bit S, bits<3> opc,
                                  string asm, SDPatternOperator OpNode> {
   let Predicates = [HasNEON, HasFullFP16] in {
   def v4f16 : BaseSIMDThreeSameVector<0, U, {S,0b10}, {0b00,opc}, V64,
                                       asm, ".4h",
         [(set (v4f16 V64:$Rd), (OpNode (v4f16 V64:$Rn), (v4f16 V64:$Rm)))]>;
   def v8f16 : BaseSIMDThreeSameVector<1, U, {S,0b10}, {0b00,opc}, V128,
                                       asm, ".8h",
         [(set (v8f16 V128:$Rd), (OpNode (v8f16 V128:$Rn), (v8f16 V128:$Rm)))]>;
   } // Predicates = [HasNEON, HasFullFP16]
   def v2f32 : BaseSIMDThreeSameVector<0, U, {S,0b01}, {0b11,opc}, V64,
                                       asm, ".2s",
         [(set (v2f32 V64:$Rd), (OpNode (v2f32 V64:$Rn), (v2f32 V64:$Rm)))]>;
   def v4f32 : BaseSIMDThreeSameVector<1, U, {S,0b01}, {0b11,opc}, V128,
                                       asm, ".4s",
         [(set (v4f32 V128:$Rd), (OpNode (v4f32 V128:$Rn), (v4f32 V128:$Rm)))]>;
   def v2f64 : BaseSIMDThreeSameVector<1, U, {S,0b11}, {0b11,opc}, V128,
                                       asm, ".2d",
         [(set (v2f64 V128:$Rd), (OpNode (v2f64 V128:$Rn), (v2f64 V128:$Rm)))]>;
 }
 
+let mayRaiseFPException = 1 in
 multiclass SIMDThreeSameVectorFPCmp<bit U, bit S, bits<3> opc,
                                     string asm,
                                     SDPatternOperator OpNode> {
   let Predicates = [HasNEON, HasFullFP16] in {
   def v4f16 : BaseSIMDThreeSameVector<0, U, {S,0b10}, {0b00,opc}, V64,
                                       asm, ".4h",
         [(set (v4i16 V64:$Rd), (OpNode (v4f16 V64:$Rn), (v4f16 V64:$Rm)))]>;
   def v8f16 : BaseSIMDThreeSameVector<1, U, {S,0b10}, {0b00,opc}, V128,
                                       asm, ".8h",
         [(set (v8i16 V128:$Rd), (OpNode (v8f16 V128:$Rn), (v8f16 V128:$Rm)))]>;
   } // Predicates = [HasNEON, HasFullFP16]
   def v2f32 : BaseSIMDThreeSameVector<0, U, {S,0b01}, {0b11,opc}, V64,
                                       asm, ".2s",
         [(set (v2i32 V64:$Rd), (OpNode (v2f32 V64:$Rn), (v2f32 V64:$Rm)))]>;
   def v4f32 : BaseSIMDThreeSameVector<1, U, {S,0b01}, {0b11,opc}, V128,
                                       asm, ".4s",
         [(set (v4i32 V128:$Rd), (OpNode (v4f32 V128:$Rn), (v4f32 V128:$Rm)))]>;
   def v2f64 : BaseSIMDThreeSameVector<1, U, {S,0b11}, {0b11,opc}, V128,
                                       asm, ".2d",
         [(set (v2i64 V128:$Rd), (OpNode (v2f64 V128:$Rn), (v2f64 V128:$Rm)))]>;
 }
 
+let mayRaiseFPException = 1 in
 multiclass SIMDThreeSameVectorFPTied<bit U, bit S, bits<3> opc,
                                  string asm, SDPatternOperator OpNode> {
   let Predicates = [HasNEON, HasFullFP16] in {
   def v4f16 : BaseSIMDThreeSameVectorTied<0, U, {S,0b10}, {0b00,opc}, V64,
                                       asm, ".4h",
      [(set (v4f16 V64:$dst),
            (OpNode (v4f16 V64:$Rd), (v4f16 V64:$Rn), (v4f16 V64:$Rm)))]>;
   def v8f16 : BaseSIMDThreeSameVectorTied<1, U, {S,0b10}, {0b00,opc}, V128,
[(set (v4f32 V128:$dst),
            (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn), (v4f32 V128:$Rm)))]>;
   def v2f64 : BaseSIMDThreeSameVectorTied<1, U, {S,0b11}, {0b11,opc}, V128,
                                       asm, ".2d",
      [(set (v2f64 V128:$dst),
            (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn), (v2f64 V128:$Rm)))]>;
 }
 
 // As above, but D and B sized elements unsupported.
+let mayRaiseFPException = 1 in
 multiclass SIMDThreeSameVectorHS<bit U, bits<5> opc, string asm,
                                 SDPatternOperator OpNode> {
   def v4i16 : BaseSIMDThreeSameVector<0, U, 0b011, opc, V64,
                                       asm, ".4h",
         [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
   def v8i16 : BaseSIMDThreeSameVector<1, U, 0b011, opc, V128,
                                       asm, ".8h",
         [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
def v8i8  : BaseSIMDThreeSameVectorDot<0, U, Mixed, asm, ".2s", ".8b", V64,
                                          v2i32, v8i8, OpNode>;
   def v16i8 : BaseSIMDThreeSameVectorDot<1, U, Mixed, asm, ".4s", ".16b", V128,
                                          v4i32, v16i8, OpNode>;
 }
 
 // ARMv8.2-A Fused Multiply Add-Long Instructions (Vector): These instructions
 // select inputs from 4H vectors and accumulate outputs to a 2S vector (or from
 // 8H to 4S, when Q=1).
+let mayRaiseFPException = 1 in
 class BaseSIMDThreeSameVectorFML<bit Q, bit U, bit b13, bits<3> size, string asm, string kind1,
                                  string kind2, RegisterOperand RegType,
                                  ValueType AccumType, ValueType InputType,
                                  SDPatternOperator OpNode> :
         BaseSIMDThreeSameVectorTied<Q, U, size, 0b11101, RegType, asm, kind1,
     [(set (AccumType RegType:$dst),
               (OpNode (AccumType RegType:$Rd),
                       (InputType RegType:$Rn),
multiclass SIMDTwoVectorBH<bit U, bits<5> opc, string asm,
   def v8i16 : BaseSIMDTwoSameVector<1, U, 0b01, opc, 0b00, V128,
                                 asm, ".8h", ".8h",
                     [(set (v8i16 V128:$Rd), (OpNode V128:$Rn))]>;
 }
 
 // Supports H, S and D element sizes, uses high bit of the size field
 // as an extra opcode bit.
 multiclass SIMDTwoVectorFP<bit U, bit S, bits<5> opc, string asm,
-                           SDPatternOperator OpNode> {
+                           SDPatternOperator OpNode,
+                           int fpexceptions = 1> {
+  let mayRaiseFPException = fpexceptions in {
   let Predicates = [HasNEON, HasFullFP16] in {
   def v4f16 : BaseSIMDTwoSameVector<0, U, {S,1}, opc, 0b11, V64,
                                 asm, ".4h", ".4h",
                           [(set (v4f16 V64:$Rd), (OpNode (v4f16 V64:$Rn)))]>;
   def v8f16 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, 0b11, V128,
                                 asm, ".8h", ".8h",
                           [(set (v8f16 V128:$Rd), (OpNode (v8f16 V128:$Rn)))]>;
   } // Predicates = [HasNEON, HasFullFP16]
   def v2f32 : BaseSIMDTwoSameVector<0, U, {S,0}, opc, 0b00, V64,
                                 asm, ".2s", ".2s",
                           [(set (v2f32 V64:$Rd), (OpNode (v2f32 V64:$Rn)))]>;
   def v4f32 : BaseSIMDTwoSameVector<1, U, {S,0}, opc, 0b00, V128,
                                 asm, ".4s", ".4s",
                           [(set (v4f32 V128:$Rd), (OpNode (v4f32 V128:$Rn)))]>;
   def v2f64 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, 0b00, V128,
                                 asm, ".2d", ".2d",
                           [(set (v2f64 V128:$Rd), (OpNode (v2f64 V128:$Rn)))]>;
   }
+}
+
+multiclass SIMDTwoVectorFPNoException<bit U, bit S, bits<5> opc, string asm,
+                                      SDPatternOperator OpNode>
+    : SIMDTwoVectorFP<U, S, opc, asm, OpNode, 0>;
 
 // Supports only S and D element sizes
+let mayRaiseFPException = 1 in
 multiclass SIMDTwoVectorSD<bit U, bits<5> opc, string asm,
                            SDPatternOperator OpNode = null_frag> {
 
   def v2f32 : BaseSIMDTwoSameVector<0, U, 00, opc, 0b00, V64,
                                 asm, ".2s", ".2s",
                           [(set (v2f32 V64:$Rd), (OpNode (v2f32 V64:$Rn)))]>;
   def v4f32 : BaseSIMDTwoSameVector<1, U, 00, opc, 0b00, V128,
                                 asm, ".4s", ".4s",
multiclass SIMDTwoVectorS<bit U, bit S, bits<5> opc, string asm,
   def v2i32 : BaseSIMDTwoSameVector<0, U, {S,0}, opc, 0b00, V64,
                                 asm, ".2s", ".2s",
                           [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
   def v4i32 : BaseSIMDTwoSameVector<1, U, {S,0}, opc, 0b00, V128,
                                 asm, ".4s", ".4s",
                           [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
 }
 
-
+let mayRaiseFPException = 1 in
 multiclass SIMDTwoVectorFPToInt<bit U, bit S, bits<5> opc, string asm,
                            SDPatternOperator OpNode> {
   let Predicates = [HasNEON, HasFullFP16] in {
   def v4f16 : BaseSIMDTwoSameVector<0, U, {S,1}, opc, 0b11, V64,
                                 asm, ".4h", ".4h",
                           [(set (v4i16 V64:$Rd), (OpNode (v4f16 V64:$Rn)))]>;
   def v8f16 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, 0b11, V128,
                                 asm, ".8h", ".8h",
                           [(set (v8i16 V128:$Rd), (OpNode (v8f16 V128:$Rn)))]>;
   } // Predicates = [HasNEON, HasFullFP16]
   def v2f32 : BaseSIMDTwoSameVector<0, U, {S,0}, opc, 0b00, V64,
                                 asm, ".2s", ".2s",
                           [(set (v2i32 V64:$Rd), (OpNode (v2f32 V64:$Rn)))]>;
   def v4f32 : BaseSIMDTwoSameVector<1, U, {S,0}, opc, 0b00, V128,
                                 asm, ".4s", ".4s",
                           [(set (v4i32 V128:$Rd), (OpNode (v4f32 V128:$Rn)))]>;
   def v2f64 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, 0b00, V128,
                                 asm, ".2d", ".2d",
                           [(set (v2i64 V128:$Rd), (OpNode (v2f64 V128:$Rn)))]>;
 }
 
+let mayRaiseFPException = 1 in
 multiclass SIMDTwoVectorIntToFP<bit U, bit S, bits<5> opc, string asm,
                            SDPatternOperator OpNode> {
   let Predicates = [HasNEON, HasFullFP16] in {
   def v4f16 : BaseSIMDTwoSameVector<0, U, {S,1}, opc, 0b11, V64,
                                 asm, ".4h", ".4h",
                           [(set (v4f16 V64:$Rd), (OpNode (v4i16 V64:$Rn)))]>;
   def v8f16 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, 0b11, V128,
                                 asm, ".8h", ".8h",
def v2i64rz : BaseSIMDCmpTwoVector<1, U, 0b11, 0b00, opc, V128,
                                      asm, ".2d", "0",
                                      v2i64, v2i64, OpNode>;
 }
 
 // FP Comparisons support only S and D element sizes (and H for v8.2a).
 multiclass SIMDFPCmpTwoVector<bit U, bit S, bits<5> opc,
                               string asm, SDNode OpNode> {
 
+  let mayRaiseFPException = 1 in {
   let Predicates = [HasNEON, HasFullFP16] in {
   def v4i16rz : BaseSIMDCmpTwoVector<0, U, {S,1}, 0b11, opc, V64,
                                      asm, ".4h", "0.0",
                                      v4i16, v4f16, OpNode>;
   def v8i16rz : BaseSIMDCmpTwoVector<1, U, {S,1}, 0b11, opc, V128,
                                      asm, ".8h", "0.0",
                                      v8i16, v8f16, OpNode>;
   } // Predicates = [HasNEON, HasFullFP16]
   def v2i32rz : BaseSIMDCmpTwoVector<0, U, {S,0}, 0b00, opc, V64,
                                      asm, ".2s", "0.0",
                                      v2i32, v2f32, OpNode>;
   def v4i32rz : BaseSIMDCmpTwoVector<1, U, {S,0}, 0b00, opc, V128,
                                      asm, ".4s", "0.0",
                                      v4i32, v4f32, OpNode>;
   def v2i64rz : BaseSIMDCmpTwoVector<1, U, {S,1}, 0b00, opc, V128,
                                      asm, ".2d", "0.0",
                                      v2i64, v2f64, OpNode>;
+  }
 
   let Predicates = [HasNEON, HasFullFP16] in {
   def : InstAlias<asm # "\t$Vd.4h, $Vn.4h, #0",
                   (!cast<Instruction>(NAME # v4i16rz) V64:$Vd, V64:$Vn), 0>;
   def : InstAlias<asm # "\t$Vd.8h, $Vn.8h, #0",
                   (!cast<Instruction>(NAME # v8i16rz) V128:$Vd, V128:$Vn), 0>;
   }
   def : InstAlias<asm # "\t$Vd.2s, $Vn.2s, #0",
multiclass SIMDFPCmpTwoVector<bit U, bit S, bits<5> opc,
   def : InstAlias<asm # ".2s\t$Vd, $Vn, #0",
                   (!cast<Instruction>(NAME # v2i32rz) V64:$Vd, V64:$Vn), 0>;
   def : InstAlias<asm # ".4s\t$Vd, $Vn, #0",
                   (!cast<Instruction>(NAME # v4i32rz) V128:$Vd, V128:$Vn), 0>;
   def : InstAlias<asm # ".2d\t$Vd, $Vn, #0",
                   (!cast<Instruction>(NAME # v2i64rz) V128:$Vd, V128:$Vn), 0>;
 }
 
-let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
+let mayLoad = 0, mayStore = 0, hasSideEffects = 0, mayRaiseFPException = 1 in
 class BaseSIMDFPCvtTwoVector<bit Q, bit U, bits<2> size, bits<5> opcode,
                              RegisterOperand outtype, RegisterOperand intype,
                              string asm, string VdTy, string VnTy,
                              list<dag> pattern>
   : I<(outs outtype:$Rd), (ins intype:$Rn), asm,
       !strconcat("\t$Rd", VdTy, ", $Rn", VnTy), "", pattern>,
     Sched<[WriteVq]> {
   bits<5> Rd;
   bits<5> Rn;
   let Inst{31}    = 0;
   let Inst{30}    = Q;
   let Inst{29}    = U;
   let Inst{28-24} = 0b01110;
   let Inst{23-22} = size;
   let Inst{21-17} = 0b10000;
   let Inst{16-12} = opcode;
   let Inst{11-10} = 0b10;
   let Inst{9-5}   = Rn;
   let Inst{4-0}   = Rd;
 }
 
-let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
+let mayLoad = 0, mayStore = 0, hasSideEffects = 0, mayRaiseFPException = 1 in
 class BaseSIMDFPCvtTwoVectorTied<bit Q, bit U, bits<2> size, bits<5> opcode,
                              RegisterOperand outtype, RegisterOperand intype,
                              string asm, string VdTy, string VnTy,
                              list<dag> pattern>
   : I<(outs outtype:$dst), (ins outtype:$Rd, intype:$Rn), asm,
       !strconcat("\t$Rd", VdTy, ", $Rn", VnTy), "$Rd = $dst", pattern>,
     Sched<[WriteVq]> {
   bits<5> Rd;
multiclass SIMDThreeScalarHSTied<bit U, bit R, bits<5> opc, string asm> {
   def v1i16: BaseSIMDThreeScalarTied<U, 0b01, R, opc, (outs FPR16:$dst),
                                      (ins FPR16:$Rd, FPR16:$Rn, FPR16:$Rm),
                                      asm, []>;
 }
 
 multiclass SIMDFPThreeScalar<bit U, bit S, bits<3> opc, string asm,
                              SDPatternOperator OpNode = null_frag,
                              Predicate pred = HasNEON> {
-  let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
+  let mayLoad = 0, mayStore = 0, hasSideEffects = 0, mayRaiseFPException = 1 in {
     let Predicates = [pred] in {
     def NAME#64 : BaseSIMDThreeScalar<U, {S,0b11}, {0b11,opc}, FPR64, asm,
       [(set (f64 FPR64:$Rd), (OpNode (f64 FPR64:$Rn), (f64 FPR64:$Rm)))]>;
     def NAME#32 : BaseSIMDThreeScalar<U, {S,0b01}, {0b11,opc}, FPR32, asm,
       [(set FPR32:$Rd, (OpNode FPR32:$Rn, FPR32:$Rm))]>;
     }
     let Predicates = [pred, HasFullFP16] in {
     def NAME#16 : BaseSIMDThreeScalar<U, {S,0b10}, {0b00,opc}, FPR16, asm,
       [(set (f16 FPR16:$Rd), (OpNode (f16 FPR16:$Rn), (f16 FPR16:$Rm)))]>;
     }
   }
 
   def : Pat<(v1f64 (OpNode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
             (!cast<Instruction>(NAME # "64") FPR64:$Rn, FPR64:$Rm)>;
 }
 
 multiclass SIMDThreeScalarFPCmp<bit U, bit S, bits<3> opc, string asm,
                                 SDPatternOperator OpNode = null_frag> {
-  let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
+  let mayLoad = 0, mayStore = 0, hasSideEffects = 0, mayRaiseFPException = 1 in {
     def NAME#64 : BaseSIMDThreeScalar<U, {S,0b11}, {0b11,opc}, FPR64, asm,
       [(set (i64 FPR64:$Rd), (OpNode (f64 FPR64:$Rn), (f64 FPR64:$Rm)))]>;
     def NAME#32 : BaseSIMDThreeScalar<U, {S,0b01}, {0b11,opc}, FPR32, asm,
       [(set (i32 FPR32:$Rd), (OpNode (f32 FPR32:$Rn), (f32 FPR32:$Rm)))]>;
     let Predicates = [HasNEON, HasFullFP16] in {
     def NAME#16 : BaseSIMDThreeScalar<U, {S,0b10}, {0b00,opc}, FPR16, asm,
       []>;
     } // Predicates = [HasNEON, HasFullFP16]
class BaseSIMDCmpTwoScalar<bit U, bits<2> size, bits<2> size2, bits<5> opcode,
   let Inst{20-19} = size2;
   let Inst{18-17} = 0b00;
   let Inst{16-12} = opcode;
   let Inst{11-10} = 0b10;
   let Inst{9-5}   = Rn;
   let Inst{4-0}   = Rd;
 }
 
+let mayRaiseFPException = 1 in
 class SIMDInexactCvtTwoScalar<bits<5> opcode, string asm>
   : I<(outs FPR32:$Rd), (ins FPR64:$Rn), asm, "\t$Rd, $Rn", "",
      [(set (f32 FPR32:$Rd), (int_aarch64_sisd_fcvtxn (f64 FPR64:$Rn)))]>,
     Sched<[WriteVd]> {
   bits<5> Rd;
   bits<5> Rn;
   let Inst{31-17} = 0b011111100110000;
   let Inst{16-12} = opcode;
   let Inst{11-10} = 0b10;
   let Inst{9-5}   = Rn;
   let Inst{4-0}   = Rd;
 }
 
 multiclass SIMDCmpTwoScalarD<bit U, bits<5> opc, string asm,
                              SDPatternOperator OpNode> {
   def v1i64rz  : BaseSIMDCmpTwoScalar<U, 0b11, 0b00, opc, FPR64, asm, "0">;
 
   def : Pat<(v1i64 (OpNode FPR64:$Rn)),
             (!cast<Instruction>(NAME # v1i64rz) FPR64:$Rn)>;
 }
 
 multiclass SIMDFPCmpTwoScalar<bit U, bit S, bits<5> opc, string asm,
                               SDPatternOperator OpNode> {
+  let mayRaiseFPException = 1 in {
   def v1i64rz  : BaseSIMDCmpTwoScalar<U, {S,1}, 0b00, opc, FPR64, asm, "0.0">;
   def v1i32rz  : BaseSIMDCmpTwoScalar<U, {S,0}, 0b00, opc, FPR32, asm, "0.0">;
   let Predicates = [HasNEON, HasFullFP16] in {
   def v1i16rz  : BaseSIMDCmpTwoScalar<U, {S,1}, 0b11, opc, FPR16, asm, "0.0">;
   }
+  }
 
   def : InstAlias<asm # "\t$Rd, $Rn, #0",
                   (!cast<Instruction>(NAME # v1i64rz) FPR64:$Rd, FPR64:$Rn), 0>;
   def : InstAlias<asm # "\t$Rd, $Rn, #0",
                   (!cast<Instruction>(NAME # v1i32rz) FPR32:$Rd, FPR32:$Rn), 0>;
   let Predicates = [HasNEON, HasFullFP16] in {
   def : InstAlias<asm # "\t$Rd, $Rn, #0",
                   (!cast<Instruction>(NAME # v1i16rz) FPR16:$Rd, FPR16:$Rn), 0>;
   }
 
   def : Pat<(v1i64 (OpNode (v1f64 FPR64:$Rn))),
             (!cast<Instruction>(NAME # v1i64rz) FPR64:$Rn)>;
 }
 
 multiclass SIMDTwoScalarD<bit U, bits<5> opc, string asm,
                           SDPatternOperator OpNode = null_frag> {
   def v1i64       : BaseSIMDTwoScalar<U, 0b11, 0b00, opc, FPR64, FPR64, asm,
     [(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn)))]>;
 
   def : Pat<(i64 (OpNode (i64 FPR64:$Rn))),
             (!cast<Instruction>(NAME # "v1i64") FPR64:$Rn)>;
 }
 
+let mayRaiseFPException = 1 in
 multiclass SIMDFPTwoScalar<bit U, bit S, bits<5> opc, string asm,
                            Predicate pred = HasNEON> {
   let Predicates = [pred] in {
   def v1i64       : BaseSIMDTwoScalar<U, {S,1}, 0b00, opc, FPR64, FPR64, asm,[]>;
   def v1i32       : BaseSIMDTwoScalar<U, {S,0}, 0b00, opc, FPR32, FPR32, asm,[]>;
   }
   let Predicates = [pred, HasFullFP16] in {
   def v1f16       : BaseSIMDTwoScalar<U, {S,1}, 0b11, opc, FPR16, FPR16, asm,[]>;
   }
 }
 
+let mayRaiseFPException = 1 in
 multiclass SIMDFPTwoScalarCVT<bit U, bit S, bits<5> opc, string asm,
                               SDPatternOperator OpNode> {
   def v1i64 : BaseSIMDTwoScalar<U, {S,1}, 0b00, opc, FPR64, FPR64, asm,
                                 [(set FPR64:$Rd, (OpNode (f64 FPR64:$Rn)))]>;
   def v1i32 : BaseSIMDTwoScalar<U, {S,0}, 0b00, opc, FPR32, FPR32, asm,
                                 [(set FPR32:$Rd, (OpNode (f32 FPR32:$Rn)))]>;
   let Predicates = [HasNEON, HasFullFP16] in {
   def v1i16 : BaseSIMDTwoScalar<U, {S,1}, 0b11, opc, FPR16, FPR16, asm,
class BaseSIMDPairwiseScalar<bit U, bits<2> size, bits<5> opcode,
   let Inst{4-0}   = Rd;
 }
 
 multiclass SIMDPairwiseScalarD<bit U, bits<5> opc, string asm> {
   def v2i64p : BaseSIMDPairwiseScalar<U, 0b11, opc, FPR64Op, V128,
                                       asm, ".2d">;
 }
 
+let mayRaiseFPException = 1 in
 multiclass SIMDFPPairwiseScalar<bit S, bits<5> opc, string asm> {
   let Predicates = [HasNEON, HasFullFP16] in {
   def v2i16p : BaseSIMDPairwiseScalar<0, {S,0}, opc, FPR16Op, V64,
                                       asm, ".2h">;
   }
   def v2i32p : BaseSIMDPairwiseScalar<1, {S,0}, opc, FPR32Op, V64,
                                       asm, ".2s">;
   def v2i64p : BaseSIMDPairwiseScalar<1, {S,1}, opc, FPR64Op, V128,
multiclass SIMDAcrossLanesHSD<bit U, bits<5> opcode, string asm> {
   def v4i16v : BaseSIMDAcrossLanes<0, U, 0b01, opcode, FPR32, V64,
                                    asm, ".4h", []>;
   def v8i16v : BaseSIMDAcrossLanes<1, U, 0b01, opcode, FPR32, V128,
                                    asm, ".8h", []>;
   def v4i32v : BaseSIMDAcrossLanes<1, U, 0b10, opcode, FPR64, V128,
                                    asm, ".4s", []>;
 }
 
+let mayRaiseFPException = 1 in
 multiclass SIMDFPAcrossLanes<bits<5> opcode, bit sz1, string asm,
                             Intrinsic intOp> {
   let Predicates = [HasNEON, HasFullFP16] in {
   def v4i16v : BaseSIMDAcrossLanes<0, 0, {sz1, 0}, opcode, FPR16, V64,
                                    asm, ".4h",
         [(set (f16 FPR16:$Rd), (intOp (v4f16 V64:$Rn)))]>;
   def v8i16v : BaseSIMDAcrossLanes<1, 0, {sz1, 0}, opcode, FPR16, V128,
                                    asm, ".8h",

 multiclass SIMDThreeSameVectorBF16DotI<bit U, string asm> {
 
   def v4bf16  : BaseSIMDThreeSameVectorBF16DotI<0, U, asm, ".2s", ".4h",
                                                ".2h", V64, v2f32, v4bf16>;
   def v8bf16 : BaseSIMDThreeSameVectorBF16DotI<1, U, asm, ".4s", ".8h",
                                               ".2h", V128, v4f32, v8bf16>;
 }
 
+let mayRaiseFPException = 1 in
 class SIMDBF16MLAL<bit Q, string asm, SDPatternOperator OpNode>
   : BaseSIMDThreeSameVectorTied<Q, 0b1, 0b110, 0b11111, V128, asm, ".4s",
               [(set (v4f32 V128:$dst), (OpNode (v4f32 V128:$Rd),
                                                (v8bf16 V128:$Rn),
                                                (v8bf16 V128:$Rm)))]> {
   let AsmString = !strconcat(asm, "{\t$Rd.4s, $Rn.8h, $Rm.8h}");
 }
 
+let mayRaiseFPException = 1 in
 class SIMDBF16MLALIndex<bit Q, string asm, SDPatternOperator OpNode>
   : I<(outs V128:$dst),
       (ins V128:$Rd, V128:$Rn, V128_lo:$Rm, VectorIndexH:$idx), asm,
       "{\t$Rd.4s, $Rn.8h, $Rm.h$idx}", "$Rd = $dst",
           [(set (v4f32 V128:$dst),
                 (v4f32 (OpNode (v4f32 V128:$Rd),
                                (v8bf16 V128:$Rn),
                                (v8bf16
: BaseSIMDThreeSameVectorTied<1, 1, 0b010, 0b11101,
                           [(set (v4f32 V128:$dst),
                                 (int_aarch64_neon_bfmmla (v4f32 V128:$Rd),
                                                          (v8bf16 V128:$Rn),
                                                          (v8bf16 V128:$Rm)))]> {
   let AsmString = !strconcat(asm, "{\t$Rd", ".4s", ", $Rn", ".8h",
                                     ", $Rm", ".8h", "}");
 }
 
+let mayRaiseFPException = 1 in
 class SIMD_BFCVTN
   : BaseSIMDMixedTwoVector<0, 0, 0b10, 0b10110, V128, V128,
                            "bfcvtn", ".4h", ".4s",
     [(set (v8bf16 V128:$Rd),
           (int_aarch64_neon_bfcvtn (v4f32 V128:$Rn)))]>;
 
+let mayRaiseFPException = 1 in
 class SIMD_BFCVTN2
   : BaseSIMDMixedTwoVectorTied<1, 0, 0b10, 0b10110, V128, V128,
                            "bfcvtn2", ".8h", ".4s",
     [(set (v8bf16 V128:$dst),
           (int_aarch64_neon_bfcvtn2 (v8bf16 V128:$Rd), (v4f32 V128:$Rn)))]>;
 
+let mayRaiseFPException = 1 in
 class BF16ToSinglePrecision<string asm>
   : I<(outs FPR16:$Rd), (ins FPR32:$Rn), asm, "\t$Rd, $Rn", "",
     [(set (bf16 FPR16:$Rd), (int_aarch64_neon_bfcvt (f32 FPR32:$Rn)))]>,
     Sched<[WriteFCvt]> {
   bits<5> Rd;
   bits<5> Rn;
   let Inst{31-10} = 0b0001111001100011010000;
   let Inst{9-5}   = Rn;
multiclass SIMDThreeSameVectorDotIndex<bit U, bit Mixed, bits<2> size, string asm,
                                        SDPatternOperator OpNode> {
   def v8i8  : BaseSIMDThreeSameVectorDotIndex<0, U, Mixed, size, asm, ".2s", ".8b", ".4b",
                                               V64, v2i32, v8i8, OpNode>;
   def v16i8 : BaseSIMDThreeSameVectorDotIndex<1, U, Mixed, size, asm, ".4s", ".16b", ".4b",
                                               V128, v4i32, v16i8, OpNode>;
 }
 
 // ARMv8.2-A Fused Multiply Add-Long Instructions (Indexed)
+let mayRaiseFPException = 1 in
 class BaseSIMDThreeSameVectorFMLIndex<bit Q, bit U, bits<4> opc, string asm,
                                       string dst_kind, string lhs_kind,
                                       string rhs_kind, RegisterOperand RegType,
                                       ValueType AccumType, ValueType InputType,
                                       SDPatternOperator OpNode> :
         BaseSIMDIndexedTied<Q, U, 0, 0b10, opc, RegType, RegType, V128,
                             VectorIndexH, asm, "", dst_kind, lhs_kind, rhs_kind,
           [(set (AccumType RegType:$dst),

 multiclass SIMDThreeSameVectorFMLIndex<bit U, bits<4> opc, string asm,
                                        SDPatternOperator OpNode> {
   def v4f16 : BaseSIMDThreeSameVectorFMLIndex<0, U, opc, asm, ".2s", ".2h", ".h",
                                               V64, v2f32, v4f16, OpNode>;
   def v8f16 : BaseSIMDThreeSameVectorFMLIndex<1, U, opc, asm, ".4s", ".4h", ".h",
                                               V128, v4f32, v8f16, OpNode>;
 }
 
+let mayRaiseFPException = 1 in
 multiclass SIMDFPIndexed<bit U, bits<4> opc, string asm,
                          SDPatternOperator OpNode> {
   let Predicates = [HasNEON, HasFullFP16] in {
   def v4i16_indexed : BaseSIMDIndexed<0, U, 0, 0b00, opc,
                                       V64, V64,
                                       V128_lo, VectorIndexH,
                                       asm, ".4h", ".4h", ".4h", ".h",
     [(set (v4f16 V64:$Rd),
multiclass SIMDFPIndexedTiedPatterns<string INST, SDPatternOperator OpNode> {
 
   // 1 variant for 64-bit scalar version: extract from .1d or from .2d
   def : Pat<(f64 (OpNode (f64 FPR64:$Rd), (f64 FPR64:$Rn),
                          (vector_extract (v2f64 V128:$Rm), VectorIndexD:$idx))),
             (!cast<Instruction>(INST # "v1i64_indexed") FPR64:$Rd, FPR64:$Rn,
                 V128:$Rm, VectorIndexD:$idx)>;
 }
 
+let mayRaiseFPException = 1 in
 multiclass SIMDFPIndexedTied<bit U, bits<4> opc, string asm> {
   let Predicates = [HasNEON, HasFullFP16] in {
   def v4i16_indexed : BaseSIMDIndexedTied<0, U, 0, 0b00, opc, V64, V64,
                                           V128_lo, VectorIndexH,
                                           asm, ".4h", ".4h", ".4h", ".h", []> {
     bits<3> idx;
     let Inst{11} = idx{2};
     let Inst{21} = idx{1};

 }
 def complexrotateopodd : Operand<i32>, TImmLeaf<i32, [{ return Imm >= 0 && Imm <= 270;  }],
                                                   SDNodeXForm<imm, [{
   return CurDAG->getTargetConstant(((N->getSExtValue() - 90) / 180), SDLoc(N), MVT::i32);
 }]>> {
   let ParserMatchClass = ComplexRotationOperand<180, 90, "Odd">;
   let PrintMethod = "printComplexRotationOp<180, 90>";
 }
-let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
+let mayLoad = 0, mayStore = 0, hasSideEffects = 0, mayRaiseFPException = 1 in
 class BaseSIMDThreeSameVectorComplex<bit Q, bit U, bits<2> size, bits<3> opcode,
                                      RegisterOperand regtype, Operand rottype,
                                      string asm, string kind, list<dag> pattern>
   : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, rottype:$rot), asm,
       "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind # ", $rot"
       "|" # kind # "\t$Rd, $Rn, $Rm, $rot}", "", pattern>,
     Sched<[!if(Q, WriteVq, WriteVd)]> {
   bits<5> Rd;
def v2f64 : BaseSIMDThreeSameVectorComplex<1, U, 0b11, opcode, V128, rottype,
               asm, ".2d",
               [(set (v2f64 V128:$dst), (OpNode (v2f64 V128:$Rd),
                                                (v2f64 V128:$Rn),
                                                (v2f64 V128:$Rm),
                                                (i32 rottype:$rot)))]>;
   }
 }
 
-let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
+let mayLoad = 0, mayStore = 0, hasSideEffects = 0, mayRaiseFPException = 1 in
 class BaseSIMDThreeSameVectorTiedComplex<bit Q, bit U, bits<2> size,
                                          bits<3> opcode,
                                          RegisterOperand regtype,
                                          Operand rottype, string asm,
                                          string kind, list<dag> pattern>
   : I<(outs regtype:$dst),
       (ins regtype:$Rd, regtype:$Rn, regtype:$Rm, rottype:$rot), asm,
       "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind # ", $rot"
def v2f64 : BaseSIMDThreeSameVectorTiedComplex<1, U, 0b11, opcode, V128,
               rottype, asm, ".2d",
               [(set (v2f64 V128:$dst), (OpNode (v2f64 V128:$Rd),
                                                (v2f64 V128:$Rn),
                                                (v2f64 V128:$Rm),
                                                (i32 rottype:$rot)))]>;
   }
 }
 
-let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
+let mayLoad = 0, mayStore = 0, hasSideEffects = 0, mayRaiseFPException = 1 in
 class BaseSIMDIndexedTiedComplex<bit Q, bit U, bit Scalar, bits<2> size,
                                  bit opc1, bit opc2, RegisterOperand dst_reg,
                                  RegisterOperand lhs_reg,
                                  RegisterOperand rhs_reg, Operand vec_idx,
                                  Operand rottype, string asm, string apple_kind,
                                  string dst_kind, string lhs_kind,
                                  string rhs_kind, list<dag> pattern>
   : I<(outs dst_reg:$dst),

llvm/lib/Target/AArch64/AArch64InstrInfo.td

 //===----------------------------------------------------------------------===//
 
 defm FCVT : FPConversion<"fcvt">;
 
 //===----------------------------------------------------------------------===//
 // Floating point single operand instructions.
 //===----------------------------------------------------------------------===//
 
-defm FABS   : SingleOperandFPData<0b0001, "fabs", fabs>;
-defm FMOV   : SingleOperandFPData<0b0000, "fmov">;
-defm FNEG   : SingleOperandFPData<0b0010, "fneg", fneg>;
+defm FABS   : SingleOperandFPDataNoException<0b0001, "fabs", fabs>;
+defm FMOV   : SingleOperandFPDataNoException<0b0000, "fmov">;
+defm FNEG   : SingleOperandFPDataNoException<0b0010, "fneg", fneg>;
 defm FRINTA : SingleOperandFPData<0b1100, "frinta", any_fround>;
 defm FRINTI : SingleOperandFPData<0b1111, "frinti", any_fnearbyint>;
 defm FRINTM : SingleOperandFPData<0b1010, "frintm", any_ffloor>;
 defm FRINTN : SingleOperandFPData<0b1000, "frintn", any_froundeven>;
 defm FRINTP : SingleOperandFPData<0b1001, "frintp", any_fceil>;
 
 defm FRINTX : SingleOperandFPData<0b1110, "frintx", any_frint>;
 defm FRINTZ : SingleOperandFPData<0b1011, "frintz", any_ftrunc>;

 defm CLS    : SIMDTwoVectorBHS<0, 0b00100, "cls", int_aarch64_neon_cls>;
 defm CLZ    : SIMDTwoVectorBHS<1, 0b00100, "clz", ctlz>;
 defm CMEQ   : SIMDCmpTwoVector<0, 0b01001, "cmeq", AArch64cmeqz>;
 defm CMGE   : SIMDCmpTwoVector<1, 0b01000, "cmge", AArch64cmgez>;
 defm CMGT   : SIMDCmpTwoVector<0, 0b01000, "cmgt", AArch64cmgtz>;
 defm CMLE   : SIMDCmpTwoVector<1, 0b01001, "cmle", AArch64cmlez>;
 defm CMLT   : SIMDCmpTwoVector<0, 0b01010, "cmlt", AArch64cmltz>;
 defm CNT    : SIMDTwoVectorB<0, 0b00, 0b00101, "cnt", ctpop>;
-defm FABS   : SIMDTwoVectorFP<0, 1, 0b01111, "fabs", fabs>;
+defm FABS   : SIMDTwoVectorFPNoException<0, 1, 0b01111, "fabs", fabs>;
 
 def : Pat<(v8i8 (AArch64vashr (v8i8 V64:$Rn), (i32 7))),
           (CMLTv8i8rz V64:$Rn)>;
 def : Pat<(v4i16 (AArch64vashr (v4i16 V64:$Rn), (i32 15))),
           (CMLTv4i16rz V64:$Rn)>;
 def : Pat<(v2i32 (AArch64vashr (v2i32 V64:$Rn), (i32 31))),
           (CMLTv2i32rz V64:$Rn)>;
 def : Pat<(v16i8 (AArch64vashr (v16i8 V128:$Rn), (i32 7))),

 def : Pat<(v2i64 (int_aarch64_neon_fcvtzs v2f64:$Rn)), (FCVTZSv2f64 $Rn)>;
 
 def : Pat<(v4i16 (int_aarch64_neon_fcvtzu v4f16:$Rn)), (FCVTZUv4f16 $Rn)>;
 def : Pat<(v8i16 (int_aarch64_neon_fcvtzu v8f16:$Rn)), (FCVTZUv8f16 $Rn)>;
 def : Pat<(v2i32 (int_aarch64_neon_fcvtzu v2f32:$Rn)), (FCVTZUv2f32 $Rn)>;
 def : Pat<(v4i32 (int_aarch64_neon_fcvtzu v4f32:$Rn)), (FCVTZUv4f32 $Rn)>;
 def : Pat<(v2i64 (int_aarch64_neon_fcvtzu v2f64:$Rn)), (FCVTZUv2f64 $Rn)>;
 
-defm FNEG   : SIMDTwoVectorFP<1, 1, 0b01111, "fneg", fneg>;
+defm FNEG   : SIMDTwoVectorFPNoException<1, 1, 0b01111, "fneg", fneg>;
 defm FRECPE : SIMDTwoVectorFP<0, 1, 0b11101, "frecpe", int_aarch64_neon_frecpe>;
 defm FRINTA : SIMDTwoVectorFP<1, 0, 0b11000, "frinta", any_fround>;
 defm FRINTI : SIMDTwoVectorFP<1, 1, 0b11001, "frinti", any_fnearbyint>;
 defm FRINTM : SIMDTwoVectorFP<0, 0, 0b11001, "frintm", any_ffloor>;
 defm FRINTN : SIMDTwoVectorFP<0, 0, 0b11000, "frintn", any_froundeven>;
 defm FRINTP : SIMDTwoVectorFP<0, 1, 0b11000, "frintp", any_fceil>;
 defm FRINTX : SIMDTwoVectorFP<1, 0, 0b11001, "frintx", any_frint>;
 defm FRINTZ : SIMDTwoVectorFP<0, 1, 0b11001, "frintz", any_ftrunc>;

llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp

// will have the same bit size.
         // Insert a subregister copy to implement a 64->32 trunc
         auto Trunc = MIB.buildInstr(TargetOpcode::COPY, {SrcTy}, {})
                          .addReg(ShiftReg, 0, AArch64::sub_32);
         MRI.setRegBank(Trunc.getReg(0), RBI.getRegBank(AArch64::GPRRegBankID));
         I.getOperand(2).setReg(Trunc.getReg(0));
       }
     }
     LLVM_FALLTHROUGH;
-  case TargetOpcode::G_FADD:
-  case TargetOpcode::G_FSUB:
-  case TargetOpcode::G_FMUL:
-  case TargetOpcode::G_FDIV:
   case TargetOpcode::G_OR: {
     // Reject the various things we don't support yet.
     if (unsupportedBinOp(I, RBI, MRI, TRI))
       return false;
 
     const unsigned OpSize = Ty.getSizeInBits();
 
     const Register DefReg = I.getOperand(0).getReg();
case TargetOpcode::G_FPTOUI: {
     const LLT DstTy = MRI.getType(I.getOperand(0).getReg()),
               SrcTy = MRI.getType(I.getOperand(1).getReg());
     const unsigned NewOpc = selectFPConvOpc(Opcode, DstTy, SrcTy);
     if (NewOpc == Opcode)
       return false;
 
     I.setDesc(TII.get(NewOpc));
     constrainSelectedInstRegOperands(I, TII, TRI, RBI);
+    I.setFlags(MachineInstr::NoFPExcept);
 
     return true;
   }
 
   case TargetOpcode::G_FREEZE:
     return selectCopy(I, TII, MRI, TRI, RBI);
 
   case TargetOpcode::G_INTTOPTR:
AArch64InstructionSelector::emitFPCompare(Register LHS, Register RHS,
   }
   unsigned CmpOpcTbl[2][2] = {{AArch64::FCMPSrr, AArch64::FCMPDrr},
                               {AArch64::FCMPSri, AArch64::FCMPDri}};
   unsigned CmpOpc = CmpOpcTbl[ShouldUseImm][OpSize == 64];
 
   // Partially build the compare. Decide if we need to add a use for the
   // third operand based off whether or not we're comparing against 0.0.
   auto CmpMI = MIRBuilder.buildInstr(CmpOpc).addUse(LHS);
+  CmpMI.setMIFlags(MachineInstr::NoFPExcept);
   if (!ShouldUseImm)
     CmpMI.addUse(RHS);
   constrainSelectedInstRegOperands(*CmpMI, TII, TRI, RBI);
   return &*CmpMI;
 }
 
 MachineInstr *AArch64InstructionSelector::emitVectorConcat(
     Optional<Register> Dst, Register Op1, Register Op2,

llvm/test/CodeGen/AArch64/GlobalISel/fold-brcond-fcmp.mir

 tracksRegLiveness: true
 body:             |
   ; CHECK-LABEL: name: oeq
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.1(0x50000000), %bb.2(0x30000000)
   ; CHECK:   liveins: $s0, $s1, $w0, $w1
   ; CHECK:   %cmp_lhs:fpr32 = COPY $s0
   ; CHECK:   %cmp_rhs:fpr32 = COPY $s1
-  ; CHECK:   FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
+  ; CHECK:   nofpexcept FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
   ; CHECK:   Bcc 0, %bb.2, implicit $nzcv
   ; CHECK:   B %bb.1
   ; CHECK: bb.1:
   ; CHECK:   $s0 = COPY %cmp_lhs
   ; CHECK:   RET_ReallyLR implicit $s0
   ; CHECK: bb.2:
   ; CHECK:   $s1 = COPY %cmp_rhs
   ; CHECK:   RET_ReallyLR implicit $s1

 tracksRegLiveness: true
 body:             |
   ; CHECK-LABEL: name: ogt
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.1(0x50000000), %bb.2(0x30000000)
   ; CHECK:   liveins: $s0, $s1, $w0, $w1
   ; CHECK:   %cmp_lhs:fpr32 = COPY $s0
   ; CHECK:   %cmp_rhs:fpr32 = COPY $s1
-  ; CHECK:   FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
+  ; CHECK:   nofpexcept FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
   ; CHECK:   Bcc 12, %bb.2, implicit $nzcv
   ; CHECK:   B %bb.1
   ; CHECK: bb.1:
   ; CHECK:   $s0 = COPY %cmp_lhs
   ; CHECK:   RET_ReallyLR implicit $s0
   ; CHECK: bb.2:
   ; CHECK:   $s1 = COPY %cmp_rhs
   ; CHECK:   RET_ReallyLR implicit $s1

 tracksRegLiveness: true
 body:             |
   ; CHECK-LABEL: name: oge
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.1(0x50000000), %bb.2(0x30000000)
   ; CHECK:   liveins: $s0, $s1, $w0, $w1
   ; CHECK:   %cmp_lhs:fpr32 = COPY $s0
   ; CHECK:   %cmp_rhs:fpr32 = COPY $s1
-  ; CHECK:   FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
+  ; CHECK:   nofpexcept FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
   ; CHECK:   Bcc 10, %bb.2, implicit $nzcv
   ; CHECK:   B %bb.1
   ; CHECK: bb.1:
   ; CHECK:   $s0 = COPY %cmp_lhs
   ; CHECK:   RET_ReallyLR implicit $s0
   ; CHECK: bb.2:
   ; CHECK:   $s1 = COPY %cmp_rhs
   ; CHECK:   RET_ReallyLR implicit $s1

 tracksRegLiveness: true
 body:             |
   ; CHECK-LABEL: name: olt
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.1(0x50000000), %bb.2(0x30000000)
   ; CHECK:   liveins: $s0, $s1, $w0, $w1
   ; CHECK:   %cmp_lhs:fpr32 = COPY $s0
   ; CHECK:   %cmp_rhs:fpr32 = COPY $s1
-  ; CHECK:   FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
+  ; CHECK:   nofpexcept FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
   ; CHECK:   Bcc 4, %bb.2, implicit $nzcv
   ; CHECK:   B %bb.1
   ; CHECK: bb.1:
   ; CHECK:   $s0 = COPY %cmp_lhs
   ; CHECK:   RET_ReallyLR implicit $s0
   ; CHECK: bb.2:
   ; CHECK:   $s1 = COPY %cmp_rhs
   ; CHECK:   RET_ReallyLR implicit $s1

 tracksRegLiveness: true
 body:             |
   ; CHECK-LABEL: name: ole
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.1(0x50000000), %bb.2(0x30000000)
   ; CHECK:   liveins: $s0, $s1, $w0, $w1
   ; CHECK:   %cmp_lhs:fpr32 = COPY $s0
   ; CHECK:   %cmp_rhs:fpr32 = COPY $s1
-  ; CHECK:   FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
+  ; CHECK:   nofpexcept FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
   ; CHECK:   Bcc 9, %bb.2, implicit $nzcv
   ; CHECK:   B %bb.1
   ; CHECK: bb.1:
   ; CHECK:   $s0 = COPY %cmp_lhs
   ; CHECK:   RET_ReallyLR implicit $s0
   ; CHECK: bb.2:
   ; CHECK:   $s1 = COPY %cmp_rhs
   ; CHECK:   RET_ReallyLR implicit $s1

 tracksRegLiveness: true
 body:             |
   ; CHECK-LABEL: name: one
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.1(0x50000000), %bb.2(0x30000000)
   ; CHECK:   liveins: $s0, $s1, $w0, $w1
   ; CHECK:   %cmp_lhs:fpr32 = COPY $s0
   ; CHECK:   %cmp_rhs:fpr32 = COPY $s1
-  ; CHECK:   FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
+  ; CHECK:   nofpexcept FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
   ; CHECK:   Bcc 4, %bb.2, implicit $nzcv
   ; CHECK:   Bcc 12, %bb.2, implicit $nzcv
   ; CHECK:   B %bb.1
   ; CHECK: bb.1:
   ; CHECK:   $s0 = COPY %cmp_lhs
   ; CHECK:   RET_ReallyLR implicit $s0
   ; CHECK: bb.2:
   ; CHECK:   $s1 = COPY %cmp_rhs

 tracksRegLiveness: true
 body:             |
   ; CHECK-LABEL: name: ord
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.1(0x50000000), %bb.2(0x30000000)
   ; CHECK:   liveins: $s0, $s1, $w0, $w1
   ; CHECK:   %cmp_lhs:fpr32 = COPY $s0
   ; CHECK:   %cmp_rhs:fpr32 = COPY $s1
-  ; CHECK:   FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
+  ; CHECK:   nofpexcept FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
   ; CHECK:   Bcc 7, %bb.2, implicit $nzcv
   ; CHECK:   B %bb.1
   ; CHECK: bb.1:
   ; CHECK:   $s0 = COPY %cmp_lhs
   ; CHECK:   RET_ReallyLR implicit $s0
   ; CHECK: bb.2:
   ; CHECK:   $s1 = COPY %cmp_rhs
   ; CHECK:   RET_ReallyLR implicit $s1

 tracksRegLiveness: true
 body:             |
   ; CHECK-LABEL: name: uno
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.1(0x50000000), %bb.2(0x30000000)
   ; CHECK:   liveins: $s0, $s1, $w0, $w1
   ; CHECK:   %cmp_lhs:fpr32 = COPY $s0
   ; CHECK:   %cmp_rhs:fpr32 = COPY $s1
-  ; CHECK:   FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
+  ; CHECK:   nofpexcept FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
   ; CHECK:   Bcc 6, %bb.2, implicit $nzcv
   ; CHECK:   B %bb.1
   ; CHECK: bb.1:
   ; CHECK:   $s0 = COPY %cmp_lhs
   ; CHECK:   RET_ReallyLR implicit $s0
   ; CHECK: bb.2:
   ; CHECK:   $s1 = COPY %cmp_rhs
   ; CHECK:   RET_ReallyLR implicit $s1

 tracksRegLiveness: true
 body:             |
   ; CHECK-LABEL: name: ueq
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.1(0x50000000), %bb.2(0x30000000)
   ; CHECK:   liveins: $s0, $s1, $w0, $w1
   ; CHECK:   %cmp_lhs:fpr32 = COPY $s0
   ; CHECK:   %cmp_rhs:fpr32 = COPY $s1
-  ; CHECK:   FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
+  ; CHECK:   nofpexcept FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
   ; CHECK:   Bcc 0, %bb.2, implicit $nzcv
   ; CHECK:   Bcc 6, %bb.2, implicit $nzcv
   ; CHECK:   B %bb.1
   ; CHECK: bb.1:
   ; CHECK:   $s0 = COPY %cmp_lhs
   ; CHECK:   RET_ReallyLR implicit $s0
   ; CHECK: bb.2:
   ; CHECK:   $s1 = COPY %cmp_rhs

 tracksRegLiveness: true
 body:             |
   ; CHECK-LABEL: name: ugt
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.1(0x50000000), %bb.2(0x30000000)
   ; CHECK:   liveins: $s0, $s1, $w0, $w1
   ; CHECK:   %cmp_lhs:fpr32 = COPY $s0
   ; CHECK:   %cmp_rhs:fpr32 = COPY $s1
-  ; CHECK:   FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
+  ; CHECK:   nofpexcept FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
   ; CHECK:   Bcc 8, %bb.2, implicit $nzcv
   ; CHECK:   B %bb.1
   ; CHECK: bb.1:
   ; CHECK:   $s0 = COPY %cmp_lhs
   ; CHECK:   RET_ReallyLR implicit $s0
   ; CHECK: bb.2:
   ; CHECK:   $s1 = COPY %cmp_rhs
   ; CHECK:   RET_ReallyLR implicit $s1

 tracksRegLiveness: true
 body:             |
   ; CHECK-LABEL: name: uge
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.1(0x50000000), %bb.2(0x30000000)
   ; CHECK:   liveins: $s0, $s1, $w0, $w1
   ; CHECK:   %cmp_lhs:fpr32 = COPY $s0
   ; CHECK:   %cmp_rhs:fpr32 = COPY $s1
-  ; CHECK:   FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
+  ; CHECK:   nofpexcept FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
   ; CHECK:   Bcc 5, %bb.2, implicit $nzcv
   ; CHECK:   B %bb.1
   ; CHECK: bb.1:
   ; CHECK:   $s0 = COPY %cmp_lhs
   ; CHECK:   RET_ReallyLR implicit $s0
   ; CHECK: bb.2:
   ; CHECK:   $s1 = COPY %cmp_rhs
   ; CHECK:   RET_ReallyLR implicit $s1

 tracksRegLiveness: true
 body:             |
   ; CHECK-LABEL: name: ult
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.1(0x50000000), %bb.2(0x30000000)
   ; CHECK:   liveins: $s0, $s1, $w0, $w1
   ; CHECK:   %cmp_lhs:fpr32 = COPY $s0
   ; CHECK:   %cmp_rhs:fpr32 = COPY $s1
-  ; CHECK:   FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
+  ; CHECK:   nofpexcept FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
   ; CHECK:   Bcc 11, %bb.2, implicit $nzcv
   ; CHECK:   B %bb.1
   ; CHECK: bb.1:
   ; CHECK:   $s0 = COPY %cmp_lhs
   ; CHECK:   RET_ReallyLR implicit $s0
   ; CHECK: bb.2:
   ; CHECK:   $s1 = COPY %cmp_rhs
   ; CHECK:   RET_ReallyLR implicit $s1

 tracksRegLiveness: true
 body:             |
   ; CHECK-LABEL: name: ule
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.1(0x50000000), %bb.2(0x30000000)
   ; CHECK:   liveins: $s0, $s1, $w0, $w1
   ; CHECK:   %cmp_lhs:fpr32 = COPY $s0
   ; CHECK:   %cmp_rhs:fpr32 = COPY $s1
-  ; CHECK:   FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
+  ; CHECK:   nofpexcept FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
   ; CHECK:   Bcc 13, %bb.2, implicit $nzcv
   ; CHECK:   B %bb.1
   ; CHECK: bb.1:
   ; CHECK:   $s0 = COPY %cmp_lhs
   ; CHECK:   RET_ReallyLR implicit $s0
   ; CHECK: bb.2:
   ; CHECK:   $s1 = COPY %cmp_rhs
   ; CHECK:   RET_ReallyLR implicit $s1

 tracksRegLiveness: true
 body:             |
   ; CHECK-LABEL: name: une
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.1(0x50000000), %bb.2(0x30000000)
   ; CHECK:   liveins: $s0, $s1, $w0, $w1
   ; CHECK:   %cmp_lhs:fpr32 = COPY $s0
   ; CHECK:   %cmp_rhs:fpr32 = COPY $s1
-  ; CHECK:   FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
+  ; CHECK:   nofpexcept FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
   ; CHECK:   Bcc 1, %bb.2, implicit $nzcv
   ; CHECK:   B %bb.1
   ; CHECK: bb.1:
   ; CHECK:   $s0 = COPY %cmp_lhs
   ; CHECK:   RET_ReallyLR implicit $s0
   ; CHECK: bb.2:
   ; CHECK:   $s1 = COPY %cmp_rhs
   ; CHECK:   RET_ReallyLR implicit $s1

llvm/test/CodeGen/AArch64/GlobalISel/fold-fp-select.mir

body:             |
   bb.0:
     liveins: $s0, $s1, $w1
 
     ; CHECK-LABEL: name: fcmp_more_than_one_user_no_fold
     ; CHECK: liveins: $s0, $s1, $w1
     ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
     ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
     ; CHECK: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
-    ; CHECK: FCMPSri [[COPY]], implicit-def $nzcv
+    ; CHECK: nofpexcept FCMPSri [[COPY]], implicit-def $nzcv
     ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
     ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY [[CSINCWr]]
     ; CHECK: [[COPY3:%[0-9]+]]:gpr32 = COPY [[COPY2]]
     ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY3]], 0, implicit-def $nzcv
     ; CHECK: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[FMOVS0_]], [[COPY1]], 1, implicit $nzcv
     ; CHECK: $w1 = COPY [[CSINCWr]]
     ; CHECK: $s0 = COPY [[FCSELSrrr]]
     ; CHECK: RET_ReallyLR implicit $s0
body:             |
   bb.0:
     liveins: $s0, $s1, $w1
 
     ; CHECK-LABEL: name: fcmp_more_than_one_select
     ; CHECK: liveins: $s0, $s1, $w1
     ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
     ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
     ; CHECK: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
-    ; CHECK: FCMPSri [[COPY]], implicit-def $nzcv
+    ; CHECK: nofpexcept FCMPSri [[COPY]], implicit-def $nzcv
     ; CHECK: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[FMOVS0_]], [[COPY1]], 0, implicit $nzcv
-    ; CHECK: FCMPSri [[COPY]], implicit-def $nzcv
+    ; CHECK: nofpexcept FCMPSri [[COPY]], implicit-def $nzcv
     ; CHECK: [[FCSELSrrr1:%[0-9]+]]:fpr32 = FCSELSrrr [[COPY1]], [[FMOVS0_]], 0, implicit $nzcv
     ; CHECK: $s0 = COPY [[FCSELSrrr]]
     ; CHECK: $s1 = COPY [[FCSELSrrr1]]
     ; CHECK: RET_ReallyLR implicit $s0
     %0:fpr(s32) = COPY $s0
     %1:fpr(s32) = COPY $s1
     %2:fpr(s32) = G_FCONSTANT float 0.000000e+00
     %5:gpr(s32) = G_FCMP floatpred(oeq), %0(s32), %2
body:             |
   bb.0:
     liveins: $s0, $s1
 
     ; CHECK-LABEL: name: foeq
     ; CHECK: liveins: $s0, $s1
     ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
     ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
     ; CHECK: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
-    ; CHECK: FCMPSri [[COPY]], implicit-def $nzcv
+    ; CHECK: nofpexcept FCMPSri [[COPY]], implicit-def $nzcv
     ; CHECK: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[FMOVS0_]], [[COPY1]], 0, implicit $nzcv
     ; CHECK: $s0 = COPY [[FCSELSrrr]]
     ; CHECK: RET_ReallyLR implicit $s0
     %0:fpr(s32) = COPY $s0
     %1:fpr(s32) = COPY $s1
     %2:fpr(s32) = G_FCONSTANT float 0.000000e+00
     %5:gpr(s32) = G_FCMP floatpred(oeq), %0(s32), %2
     %3:gpr(s1) = G_TRUNC %5(s32)
body:             |
   bb.0:
     liveins: $s0, $s1
 
     ; CHECK-LABEL: name: fueq
     ; CHECK: liveins: $s0, $s1
     ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
     ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
     ; CHECK: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
-    ; CHECK: FCMPSri [[COPY]], implicit-def $nzcv
+    ; CHECK: nofpexcept FCMPSri [[COPY]], implicit-def $nzcv
     ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
     ; CHECK: [[CSINCWr1:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
     ; CHECK: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr [[CSINCWr]], [[CSINCWr1]]
     ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY [[ORRWrr]]
     ; CHECK: [[COPY3:%[0-9]+]]:gpr32 = COPY [[COPY2]]
     ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY3]], 0, implicit-def $nzcv
     ; CHECK: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[FMOVS0_]], [[COPY1]], 1, implicit $nzcv
     ; CHECK: $s0 = COPY [[FCSELSrrr]]
body:             |
   bb.0:
     liveins: $s0, $s1
 
     ; CHECK-LABEL: name: fone
     ; CHECK: liveins: $s0, $s1
     ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
     ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
     ; CHECK: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
-    ; CHECK: FCMPSri [[COPY]], implicit-def $nzcv
+    ; CHECK: nofpexcept FCMPSri [[COPY]], implicit-def $nzcv
     ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 5, implicit $nzcv
     ; CHECK: [[CSINCWr1:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv
     ; CHECK: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr [[CSINCWr]], [[CSINCWr1]]
     ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY [[ORRWrr]]
     ; CHECK: [[COPY3:%[0-9]+]]:gpr32 = COPY [[COPY2]]
     ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY3]], 0, implicit-def $nzcv
     ; CHECK: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[COPY1]], [[FMOVS0_]], 1, implicit $nzcv
     ; CHECK: $s0 = COPY [[FCSELSrrr]]
body:             |
   bb.0:
     liveins: $s0, $s1
 
     ; CHECK-LABEL: name: fune
     ; CHECK: liveins: $s0, $s1
     ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
     ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
     ; CHECK: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
-    ; CHECK: FCMPSri [[COPY]], implicit-def $nzcv
+    ; CHECK: nofpexcept FCMPSri [[COPY]], implicit-def $nzcv
     ; CHECK: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[COPY1]], [[FMOVS0_]], 1, implicit $nzcv
     ; CHECK: $s0 = COPY [[FCSELSrrr]]
     ; CHECK: RET_ReallyLR implicit $s0
     %0:fpr(s32) = COPY $s0
     %1:fpr(s32) = COPY $s1
     %2:fpr(s32) = G_FCONSTANT float 0.000000e+00
     %5:gpr(s32) = G_FCMP floatpred(une), %0(s32), %2
     %3:gpr(s1) = G_TRUNC %5(s32)
body:             |
   bb.0:
     liveins: $d0, $d1
 
     ; CHECK-LABEL: name: doeq
     ; CHECK: liveins: $d0, $d1
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
     ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
     ; CHECK: [[FMOVD0_:%[0-9]+]]:fpr64 = FMOVD0
-    ; CHECK: FCMPDri [[COPY]], implicit-def $nzcv
+    ; CHECK: nofpexcept FCMPDri [[COPY]], implicit-def $nzcv
     ; CHECK: [[FCSELDrrr:%[0-9]+]]:fpr64 = FCSELDrrr [[FMOVD0_]], [[COPY1]], 0, implicit $nzcv
     ; CHECK: $d0 = COPY [[FCSELDrrr]]
     ; CHECK: RET_ReallyLR implicit $d0
     %0:fpr(s64) = COPY $d0
     %1:fpr(s64) = COPY $d1
     %2:fpr(s64) = G_FCONSTANT double 0.000000e+00
     %5:gpr(s32) = G_FCMP floatpred(oeq), %0(s64), %2
     %3:gpr(s1) = G_TRUNC %5(s32)
body:             |
   bb.0:
     liveins: $d0, $d1
 
     ; CHECK-LABEL: name: dueq
     ; CHECK: liveins: $d0, $d1
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
     ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
     ; CHECK: [[FMOVD0_:%[0-9]+]]:fpr64 = FMOVD0
-    ; CHECK: FCMPDri [[COPY]], implicit-def $nzcv
+    ; CHECK: nofpexcept FCMPDri [[COPY]], implicit-def $nzcv
     ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
     ; CHECK: [[CSINCWr1:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
     ; CHECK: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr [[CSINCWr]], [[CSINCWr1]]
     ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY [[ORRWrr]]
     ; CHECK: [[COPY3:%[0-9]+]]:gpr32 = COPY [[COPY2]]
     ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY3]], 0, implicit-def $nzcv
     ; CHECK: [[FCSELDrrr:%[0-9]+]]:fpr64 = FCSELDrrr [[FMOVD0_]], [[COPY1]], 1, implicit $nzcv
     ; CHECK: $d0 = COPY [[FCSELDrrr]]
body:             |
   bb.0:
     liveins: $d0, $d1
 
     ; CHECK-LABEL: name: done
     ; CHECK: liveins: $d0, $d1
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
     ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
     ; CHECK: [[FMOVD0_:%[0-9]+]]:fpr64 = FMOVD0
-    ; CHECK: FCMPDri [[COPY]], implicit-def $nzcv
+    ; CHECK: nofpexcept FCMPDri [[COPY]], implicit-def $nzcv
     ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 5, implicit $nzcv
     ; CHECK: [[CSINCWr1:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv
     ; CHECK: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr [[CSINCWr]], [[CSINCWr1]]
     ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY [[ORRWrr]]
     ; CHECK: [[COPY3:%[0-9]+]]:gpr32 = COPY [[COPY2]]
     ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY3]], 0, implicit-def $nzcv
     ; CHECK: [[FCSELDrrr:%[0-9]+]]:fpr64 = FCSELDrrr [[COPY1]], [[FMOVD0_]], 1, implicit $nzcv
     ; CHECK: $d0 = COPY [[FCSELDrrr]]
body:             |
   bb.0:
     liveins: $d0, $d1
 
     ; CHECK-LABEL: name: dune
     ; CHECK: liveins: $d0, $d1
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
     ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
     ; CHECK: [[FMOVD0_:%[0-9]+]]:fpr64 = FMOVD0
-    ; CHECK: FCMPDri [[COPY]], implicit-def $nzcv
+    ; CHECK: nofpexcept FCMPDri [[COPY]], implicit-def $nzcv
     ; CHECK: [[FCSELDrrr:%[0-9]+]]:fpr64 = FCSELDrrr [[COPY1]], [[FMOVD0_]], 1, implicit $nzcv
     ; CHECK: $d0 = COPY [[FCSELDrrr]]
     ; CHECK: RET_ReallyLR implicit $d0
     %0:fpr(s64) = COPY $d0
     %1:fpr(s64) = COPY $d1
     %2:fpr(s64) = G_FCONSTANT double 0.000000e+00
     %5:gpr(s32) = G_FCMP floatpred(une), %0(s64), %2
     %3:gpr(s1) = G_TRUNC %5(s32)

llvm/test/CodeGen/AArch64/GlobalISel/fold-select.mir

body:             |
   bb.0:
     liveins: $s0, $w0, $w1
 
     ; CHECK-LABEL: name: using_fcmp
     ; CHECK: liveins: $s0, $w0, $w1
     ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
     ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0
     ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr
-    ; CHECK: FCMPSri [[COPY1]], implicit-def $nzcv
+    ; CHECK: nofpexcept FCMPSri [[COPY1]], implicit-def $nzcv
     ; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[COPY2]], [[COPY]], 0, implicit $nzcv
     ; CHECK: $w0 = COPY [[CSELWr]]
     ; CHECK: RET_ReallyLR implicit $w0
     %1:gpr(s32) = COPY $w1
     %2:fpr(s32) = COPY $s0
     %3:fpr(s32) = G_FCONSTANT float 0.000000e+00
     %6:gpr(s32) = G_CONSTANT i32 0
     %7:gpr(s32) = G_FCMP floatpred(oeq), %2(s32), %3

llvm/test/CodeGen/AArch64/GlobalISel/preselect-process-phis.mir

body:             |
   ; CHECK: bb.1:
   ; CHECK:   successors: %bb.2(0x80000000)
   ; CHECK:   [[DEF2:%[0-9]+]]:gpr32 = IMPLICIT_DEF
   ; CHECK:   [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[DEF]], 0, implicit-def $nzcv
   ; CHECK:   [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[DEF2]], [[DEF2]], 1, implicit $nzcv
   ; CHECK: bb.2:
   ; CHECK:   successors: %bb.2(0x80000000)
   ; CHECK:   [[PHI:%[0-9]+]]:gpr32 = PHI [[CSELWr]], %bb.1, %8, %bb.2
-  ; CHECK:   [[FCVTHSr:%[0-9]+]]:fpr16 = FCVTHSr [[COPY]]
+  ; CHECK:   [[FCVTHSr:%[0-9]+]]:fpr16 = nofpexcept FCVTHSr [[COPY]]
   ; CHECK:   [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[FCVTHSr]], %subreg.hsub
   ; CHECK:   [[COPY1:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]]
   ; CHECK:   STRHHui [[PHI]], [[DEF1]], 0 :: (store (s16) into `half* undef`)
   ; CHECK:   B %bb.2
   bb.0:
     successors: %bb.1(0x80000000)
 
     %0:gpr(s1) = G_IMPLICIT_DEF
body:             |
   ; CHECK:   [[DEF2:%[0-9]+]]:gpr32 = IMPLICIT_DEF
   ; CHECK:   [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[DEF]], 0, implicit-def $nzcv
   ; CHECK:   [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[DEF2]], [[DEF2]], 1, implicit $nzcv
   ; CHECK:   [[COPY1:%[0-9]+]]:fpr32 = COPY [[CSELWr]]
   ; CHECK:   [[COPY2:%[0-9]+]]:fpr16 = COPY [[COPY1]].hsub
   ; CHECK: bb.2:
   ; CHECK:   successors: %bb.2(0x80000000)
   ; CHECK:   [[PHI:%[0-9]+]]:fpr16 = PHI %7, %bb.2, [[COPY2]], %bb.1
-  ; CHECK:   [[FCVTHSr:%[0-9]+]]:fpr16 = FCVTHSr [[COPY]]
+  ; CHECK:   [[FCVTHSr:%[0-9]+]]:fpr16 = nofpexcept FCVTHSr [[COPY]]
   ; CHECK:   STRHui [[PHI]], [[DEF1]], 0 :: (store (s16) into `half* undef`)
   ; CHECK:   B %bb.2
   bb.0:
     successors: %bb.1(0x80000000)
 
     %0:gpr(s1) = G_IMPLICIT_DEF
     %4:gpr(p0) = G_IMPLICIT_DEF
     %8:fpr(s32) = G_FCONSTANT float 0x7FF8000000000000

llvm/test/CodeGen/AArch64/GlobalISel/select-binop.mir

 
 body:             |
   bb.0:
     liveins: $s0, $s1
 
     ; CHECK-LABEL: name: fadd_s32_fpr
     ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
     ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
-    ; CHECK: [[FADDSrr:%[0-9]+]]:fpr32 = FADDSrr [[COPY]], [[COPY1]]
+    ; CHECK: [[FADDSrr:%[0-9]+]]:fpr32 = nofpexcept FADDSrr [[COPY]], [[COPY1]]
     ; CHECK: $s0 = COPY [[FADDSrr]]
     %0(s32) = COPY $s0
     %1(s32) = COPY $s1
     %2(s32) = G_FADD %0, %1
     $s0 = COPY %2(s32)
 ...
 
 ---
 name:            fadd_s64_fpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
   - { id: 2, class: fpr }
 
 body:             |
   bb.0:
     liveins: $d0, $d1
 
     ; CHECK-LABEL: name: fadd_s64_fpr
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
     ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
-    ; CHECK: [[FADDDrr:%[0-9]+]]:fpr64 = FADDDrr [[COPY]], [[COPY1]]
+    ; CHECK: [[FADDDrr:%[0-9]+]]:fpr64 = nofpexcept FADDDrr [[COPY]], [[COPY1]]
     ; CHECK: $d0 = COPY [[FADDDrr]]
     %0(s64) = COPY $d0
     %1(s64) = COPY $d1
     %2(s64) = G_FADD %0, %1
     $d0 = COPY %2(s64)
 ...
 
 ---
 name:            fsub_s32_fpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
   - { id: 2, class: fpr }
 
 body:             |
   bb.0:
     liveins: $s0, $s1
 
     ; CHECK-LABEL: name: fsub_s32_fpr
     ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
     ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
-    ; CHECK: [[FSUBSrr:%[0-9]+]]:fpr32 = FSUBSrr [[COPY]], [[COPY1]]
+    ; CHECK: [[FSUBSrr:%[0-9]+]]:fpr32 = nofpexcept FSUBSrr [[COPY]], [[COPY1]]
     ; CHECK: $s0 = COPY [[FSUBSrr]]
     %0(s32) = COPY $s0
     %1(s32) = COPY $s1
     %2(s32) = G_FSUB %0, %1
     $s0 = COPY %2(s32)
 ...
 
 ---
 name:            fsub_s64_fpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
   - { id: 2, class: fpr }
 
 body:             |
   bb.0:
     liveins: $d0, $d1
 
     ; CHECK-LABEL: name: fsub_s64_fpr
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
     ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
-    ; CHECK: [[FSUBDrr:%[0-9]+]]:fpr64 = FSUBDrr [[COPY]], [[COPY1]]
+    ; CHECK: [[FSUBDrr:%[0-9]+]]:fpr64 = nofpexcept FSUBDrr [[COPY]], [[COPY1]]
     ; CHECK: $d0 = COPY [[FSUBDrr]]
     %0(s64) = COPY $d0
     %1(s64) = COPY $d1
     %2(s64) = G_FSUB %0, %1
     $d0 = COPY %2(s64)
 ...
 
 ---
 name:            fmul_s32_fpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
   - { id: 2, class: fpr }
 
 body:             |
   bb.0:
     liveins: $s0, $s1
 
     ; CHECK-LABEL: name: fmul_s32_fpr
     ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
     ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
-    ; CHECK: [[FMULSrr:%[0-9]+]]:fpr32 = FMULSrr [[COPY]], [[COPY1]]
+    ; CHECK: [[FMULSrr:%[0-9]+]]:fpr32 = nofpexcept FMULSrr [[COPY]], [[COPY1]]
     ; CHECK: $s0 = COPY [[FMULSrr]]
     %0(s32) = COPY $s0
     %1(s32) = COPY $s1
     %2(s32) = G_FMUL %0, %1
     $s0 = COPY %2(s32)
 ...
 
 ---
 name:            fmul_s64_fpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
   - { id: 2, class: fpr }
 
 body:             |
   bb.0:
     liveins: $d0, $d1
 
     ; CHECK-LABEL: name: fmul_s64_fpr
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
     ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
-    ; CHECK: [[FMULDrr:%[0-9]+]]:fpr64 = FMULDrr [[COPY]], [[COPY1]]
+    ; CHECK: [[FMULDrr:%[0-9]+]]:fpr64 = nofpexcept FMULDrr [[COPY]], [[COPY1]]
     ; CHECK: $d0 = COPY [[FMULDrr]]
     %0(s64) = COPY $d0
     %1(s64) = COPY $d1
     %2(s64) = G_FMUL %0, %1
     $d0 = COPY %2(s64)
 ...
 
 ---
 name:            fdiv_s32_fpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
   - { id: 2, class: fpr }
 
 body:             |
   bb.0:
     liveins: $s0, $s1
 
     ; CHECK-LABEL: name: fdiv_s32_fpr
     ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
     ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
-    ; CHECK: [[FDIVSrr:%[0-9]+]]:fpr32 = FDIVSrr [[COPY]], [[COPY1]]
+    ; CHECK: [[FDIVSrr:%[0-9]+]]:fpr32 = nofpexcept FDIVSrr [[COPY]], [[COPY1]]
     ; CHECK: $s0 = COPY [[FDIVSrr]]
     %0(s32) = COPY $s0
     %1(s32) = COPY $s1
     %2(s32) = G_FDIV %0, %1
     $s0 = COPY %2(s32)
 ...
 
 ---
 name:            fdiv_s64_fpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
   - { id: 2, class: fpr }
 
 body:             |
   bb.0:
     liveins: $d0, $d1
 
     ; CHECK-LABEL: name: fdiv_s64_fpr
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
     ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
-    ; CHECK: [[FDIVDrr:%[0-9]+]]:fpr64 = FDIVDrr [[COPY]], [[COPY1]]
+    ; CHECK: [[FDIVDrr:%[0-9]+]]:fpr64 = nofpexcept FDIVDrr [[COPY]], [[COPY1]]
     ; CHECK: $d0 = COPY [[FDIVDrr]]
     %0(s64) = COPY $d0
     %1(s64) = COPY $d1
     %2(s64) = G_FDIV %0, %1
     $d0 = COPY %2(s64)
 ...
 ---
 name:            add_v8i16

llvm/test/CodeGen/AArch64/GlobalISel/select-ceil.mir

 # RUN: llc -verify-machineinstrs -mtriple aarch64--- \
 # RUN: -run-pass=instruction-select -mattr=+fullfp16 -global-isel %s -o - \
 # RUN: | FileCheck %s
 ...
 ---
 name:            ceil_float
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
 body:             |
   bb.0:
     ; CHECK-LABEL: name:            ceil_float
-    ; CHECK: %{{[0-9]+}}:fpr32 = FRINTPSr %{{[0-9]+}}
+    ; CHECK: %{{[0-9]+}}:fpr32 = nofpexcept FRINTPSr %{{[0-9]+}}
     liveins: $s0
     %0:fpr(s32) = COPY $s0
     %1:fpr(s32) = G_FCEIL %0
     $s0 = COPY %1(s32)
 
 ...
 ---
 name:            ceil_double
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
 body:             |
   bb.0:
     ; CHECK-LABEL: name:            ceil_double
-    ; CHECK: %{{[0-9]+}}:fpr64 = FRINTPDr %{{[0-9]+}}
+    ; CHECK: %{{[0-9]+}}:fpr64 = nofpexcept FRINTPDr %{{[0-9]+}}
     liveins: $d0
     %0:fpr(s64) = COPY $d0
     %1:fpr(s64) = G_FCEIL %0
     $d0 = COPY %1(s64)
 
 ...
 ---
 name:            ceil_v2f32
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
 body:             |
   bb.0:
     ; CHECK-LABEL: name:            ceil_v2f32
-    ; CHECK: %{{[0-9]+}}:fpr64 = FRINTPv2f32 %{{[0-9]+}}
+    ; CHECK: %{{[0-9]+}}:fpr64 = nofpexcept FRINTPv2f32 %{{[0-9]+}}
     liveins: $d0
     %0:fpr(<2 x s32>) = COPY $d0
     %1:fpr(<2 x s32>) = G_FCEIL %0
     $d0 = COPY %1(<2 x s32>)
 
 ...
 ---
 name:            ceil_v4f32
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
 body:             |
   bb.0:
     ; CHECK-LABEL: name:            ceil_v4f32
-    ; CHECK: %{{[0-9]+}}:fpr128 = FRINTPv4f32 %{{[0-9]+}}
+    ; CHECK: %{{[0-9]+}}:fpr128 = nofpexcept FRINTPv4f32 %{{[0-9]+}}
     liveins: $q0
     %0:fpr(<4 x s32>) = COPY $q0
     %1:fpr(<4 x s32>) = G_FCEIL %0
     $q0 = COPY %1(<4 x s32>)
 
 ...
 ---
 name:            ceil_v2f64
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
 body:             |
   bb.0:
     ; CHECK-LABEL: name:            ceil_v2f64
-    ; CHECK: %{{[0-9]+}}:fpr128 = FRINTPv2f64 %{{[0-9]+}}
+    ; CHECK: %{{[0-9]+}}:fpr128 = nofpexcept FRINTPv2f64 %{{[0-9]+}}
     liveins: $q0
     %0:fpr(<2 x s64>) = COPY $q0
     %1:fpr(<2 x s64>) = G_FCEIL %0
     $q0 = COPY %1(<2 x s64>)
 
 ...
 ---
 name:            ceil_v4f16
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
 body:             |
   bb.0:
     ; CHECK-LABEL: name:            ceil_v4f16
-    ; CHECK: %{{[0-9]+}}:fpr64 = FRINTPv4f16 %{{[0-9]+}}
+    ; CHECK: %{{[0-9]+}}:fpr64 = nofpexcept FRINTPv4f16 %{{[0-9]+}}
     liveins: $d0
     %0:fpr(<4 x s16>) = COPY $d0
     %1:fpr(<4 x s16>) = G_FCEIL %0
     $d0 = COPY %1(<4 x s16>)
 
 ...
 ---
 name:            ceil_v8f16
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
 body:             |
   bb.0:
     ; CHECK-LABEL: name:            ceil_v8f16
-    ; CHECK: %{{[0-9]+}}:fpr128 = FRINTPv8f16 %{{[0-9]+}}
+    ; CHECK: %{{[0-9]+}}:fpr128 = nofpexcept FRINTPv8f16 %{{[0-9]+}}
     liveins: $q0
     %0:fpr(<8 x s16>) = COPY $q0
     %1:fpr(<8 x s16>) = G_FCEIL %0
     $q0 = COPY %1(<8 x s16>)
 
 ...

llvm/test/CodeGen/AArch64/GlobalISel/select-faddp.mir

frameInfo:
   maxAlignment:    1
 body:             |
   bb.1:
     liveins: $q0
 
     ; CHECK-LABEL: name: f64_faddp
     ; CHECK: liveins: $q0
     ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[FADDPv2i64p:%[0-9]+]]:fpr64 = FADDPv2i64p [[COPY]]
+    ; CHECK: [[FADDPv2i64p:%[0-9]+]]:fpr64 = nofpexcept FADDPv2i64p [[COPY]]
     ; CHECK: $d0 = COPY [[FADDPv2i64p]]
     ; CHECK: RET_ReallyLR implicit $d0
     %0:fpr(<2 x s64>) = COPY $q0
     %6:gpr(s64) = G_CONSTANT i64 0
     %7:fpr(s64) = G_EXTRACT_VECTOR_ELT %0(<2 x s64>), %6(s64)
     %8:gpr(s64) = G_CONSTANT i64 1
     %9:fpr(s64) = G_EXTRACT_VECTOR_ELT %0(<2 x s64>), %8(s64)
     %4:fpr(s64) = G_FADD %7, %9
frameInfo:
   maxAlignment:    1
 body:             |
   bb.1:
     liveins: $d0
 
     ; CHECK-LABEL: name: f32_faddp
     ; CHECK: liveins: $d0
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[FADDPv2i32p:%[0-9]+]]:fpr32 = FADDPv2i32p [[COPY]]
+    ; CHECK: [[FADDPv2i32p:%[0-9]+]]:fpr32 = nofpexcept FADDPv2i32p [[COPY]]
     ; CHECK: $s0 = COPY [[FADDPv2i32p]]
     ; CHECK: RET_ReallyLR implicit $s0
     %0:fpr(<2 x s32>) = COPY $d0
     %6:gpr(s64) = G_CONSTANT i64 0
     %7:fpr(s32) = G_EXTRACT_VECTOR_ELT %0(<2 x s32>), %6(s64)
     %8:gpr(s64) = G_CONSTANT i64 1
     %9:fpr(s32) = G_EXTRACT_VECTOR_ELT %0(<2 x s32>), %8(s64)
     %4:fpr(s32) = G_FADD %7, %9
     $s0 = COPY %4(s32)
     RET_ReallyLR implicit $s0
 
 ...

llvm/test/CodeGen/AArch64/GlobalISel/select-fcmp.mir

 tracksRegLiveness: true
 body:             |
   bb.1:
     liveins: $s0, $s1
 
     ; CHECK-LABEL: name: zero
     ; CHECK: liveins: $s0, $s1
     ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
-    ; CHECK: FCMPSri [[COPY]], implicit-def $nzcv
+    ; CHECK: nofpexcept FCMPSri [[COPY]], implicit-def $nzcv
     ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
     ; CHECK: $s0 = COPY [[CSINCWr]]
     ; CHECK: RET_ReallyLR implicit $s0
     %0:fpr(s32) = COPY $s0
     %1:fpr(s32) = COPY $s1
     %2:fpr(s32) = G_FCONSTANT float 0.000000e+00
     %3:gpr(s32) = G_FCMP floatpred(oeq), %0(s32), %2
     $s0 = COPY %3(s32)

 body:             |
   bb.1:
     liveins: $s0, $s1
 
     ; CHECK-LABEL: name: notzero
     ; CHECK: liveins: $s0, $s1
     ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
     ; CHECK: [[FMOVSi:%[0-9]+]]:fpr32 = FMOVSi 112
-    ; CHECK: FCMPSrr [[COPY]], [[FMOVSi]], implicit-def $nzcv
+    ; CHECK: nofpexcept FCMPSrr [[COPY]], [[FMOVSi]], implicit-def $nzcv
     ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
     ; CHECK: $s0 = COPY [[CSINCWr]]
     ; CHECK: RET_ReallyLR implicit $s0
     %0:fpr(s32) = COPY $s0
     %1:fpr(s32) = COPY $s1
     %2:fpr(s32) = G_FCONSTANT float 1.000000e+00
     %3:gpr(s32) = G_FCMP floatpred(oeq), %0(s32), %2
     $s0 = COPY %3(s32)

 body:             |
   bb.1:
     liveins: $d0, $d1
 
     ; CHECK-LABEL: name: notzero_s64
     ; CHECK: liveins: $d0, $d1
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
     ; CHECK: [[FMOVDi:%[0-9]+]]:fpr64 = FMOVDi 112
-    ; CHECK: FCMPDrr [[COPY]], [[FMOVDi]], implicit-def $nzcv
+    ; CHECK: nofpexcept FCMPDrr [[COPY]], [[FMOVDi]], implicit-def $nzcv
     ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
     ; CHECK: $s0 = COPY [[CSINCWr]]
     ; CHECK: RET_ReallyLR implicit $s0
     %0:fpr(s64) = COPY $d0
     %1:fpr(s64) = COPY $d1
     %2:fpr(s64) = G_FCONSTANT double 1.000000e+00
     %3:gpr(s32) = G_FCMP floatpred(oeq), %0(s64), %2
     $s0 = COPY %3(s32)

 tracksRegLiveness: true
 body:             |
   bb.1:
     liveins: $d0, $d1, $s0
 
     ; CHECK-LABEL: name: zero_s64
     ; CHECK: liveins: $d0, $d1, $s0
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: FCMPDri [[COPY]], implicit-def $nzcv
+    ; CHECK: nofpexcept FCMPDri [[COPY]], implicit-def $nzcv
     ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
     ; CHECK: $s0 = COPY [[CSINCWr]]
     ; CHECK: RET_ReallyLR implicit $s0
     %0:fpr(s64) = COPY $d0
     %1:fpr(s64) = COPY $d1
     %2:fpr(s64) = G_FCONSTANT double 0.000000e+00
     %3:gpr(s32) = G_FCMP floatpred(oeq), %0(s64), %2
     $s0 = COPY %3(s32)
     RET_ReallyLR implicit $s0
 ...
 
 ---
 name:            zero_lhs
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.1:
     liveins: $s0, $s1
 
     ; CHECK-LABEL: name: zero_lhs
     ; CHECK: liveins: $s0, $s1
     ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
-    ; CHECK: FCMPSri [[COPY]], implicit-def $nzcv
+    ; CHECK: nofpexcept FCMPSri [[COPY]], implicit-def $nzcv
     ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
     ; CHECK: $s0 = COPY [[CSINCWr]]
     ; CHECK: RET_ReallyLR implicit $s0
     %0:fpr(s32) = COPY $s0
     %1:fpr(s32) = COPY $s1
     %2:fpr(s32) = G_FCONSTANT float 0.000000e+00
     %3:gpr(s32) = G_FCMP floatpred(oeq), %2(s32), %0
     $s0 = COPY %3(s32)

 body:             |
   bb.1:
     liveins: $s0, $s1
 
     ; CHECK-LABEL: name: zero_lhs_not_commutative_pred
     ; CHECK: liveins: $s0, $s1
     ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
     ; CHECK: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
-    ; CHECK: FCMPSrr [[FMOVS0_]], [[COPY]], implicit-def $nzcv
+    ; CHECK: nofpexcept FCMPSrr [[FMOVS0_]], [[COPY]], implicit-def $nzcv
     ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 5, implicit $nzcv
     ; CHECK: $s0 = COPY [[CSINCWr]]
     ; CHECK: RET_ReallyLR implicit $s0
     %0:fpr(s32) = COPY $s0
     %1:fpr(s32) = COPY $s1
     %2:fpr(s32) = G_FCONSTANT float 0.000000e+00
     %3:gpr(s32) = G_FCMP floatpred(olt), %2(s32), %0
     $s0 = COPY %3(s32)
     RET_ReallyLR implicit $s0
 
 ...

llvm/test/CodeGen/AArch64/GlobalISel/select-floor.mir

 # RUN: llc -verify-machineinstrs -mtriple aarch64--- \
 # RUN: -run-pass=instruction-select -mattr=+fullfp16 -global-isel %s -o - \
 # RUN: | FileCheck %s
 ...
 ---
 name:            floor_float
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
 body:             |
   bb.0:
     ; CHECK-LABEL: name:            floor_float
-    ; CHECK: %{{[0-9]+}}:fpr32 = FRINTMSr %{{[0-9]+}}
+    ; CHECK: %{{[0-9]+}}:fpr32 = nofpexcept FRINTMSr %{{[0-9]+}}
     liveins: $s0
     %0:fpr(s32) = COPY $s0
     %1:fpr(s32) = G_FFLOOR %0
     $s0 = COPY %1(s32)
 
 ...
 ---
 name:            floor_double
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
 body:             |
   bb.0:
     ; CHECK-LABEL: name:            floor_double
-    ; CHECK: %{{[0-9]+}}:fpr64 = FRINTMDr %{{[0-9]+}}
+    ; CHECK: %{{[0-9]+}}:fpr64 = nofpexcept FRINTMDr %{{[0-9]+}}
     liveins: $d0
     %0:fpr(s64) = COPY $d0
     %1:fpr(s64) = G_FFLOOR %0
     $d0 = COPY %1(s64)
 
 ...
 ---
 name:            floor_v2f32
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
 body:             |
   bb.0:
     ; CHECK-LABEL: name:            floor_v2f32
-    ; CHECK: %{{[0-9]+}}:fpr64 = FRINTMv2f32 %{{[0-9]+}}
+    ; CHECK: %{{[0-9]+}}:fpr64 = nofpexcept FRINTMv2f32 %{{[0-9]+}}
     liveins: $d0
     %0:fpr(<2 x s32>) = COPY $d0
     %1:fpr(<2 x s32>) = G_FFLOOR %0
     $d0 = COPY %1(<2 x s32>)
 
 ...
 ---
 name:            floor_v4f32
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
 body:             |
   bb.0:
     ; CHECK-LABEL: name:            floor_v4f32
-    ; CHECK: %{{[0-9]+}}:fpr128 = FRINTMv4f32 %{{[0-9]+}}
+    ; CHECK: %{{[0-9]+}}:fpr128 = nofpexcept FRINTMv4f32 %{{[0-9]+}}
     liveins: $q0
     %0:fpr(<4 x s32>) = COPY $q0
     %1:fpr(<4 x s32>) = G_FFLOOR %0
     $q0 = COPY %1(<4 x s32>)
 
 ...
 ---
 name:            floor_v2f64
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
 body:             |
   bb.0:
     ; CHECK-LABEL: name:            floor_v2f64
-    ; CHECK: %{{[0-9]+}}:fpr128 = FRINTMv2f64 %{{[0-9]+}}
+    ; CHECK: %{{[0-9]+}}:fpr128 = nofpexcept FRINTMv2f64 %{{[0-9]+}}
     liveins: $q0
     %0:fpr(<2 x s64>) = COPY $q0
     %1:fpr(<2 x s64>) = G_FFLOOR %0
     $q0 = COPY %1(<2 x s64>)
 
 ...
 ---
 name:            floor_v4f16
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
 body:             |
   bb.0:
     ; CHECK-LABEL: name:            floor_v4f16
-    ; CHECK: %{{[0-9]+}}:fpr64 = FRINTMv4f16 %{{[0-9]+}}
+    ; CHECK: %{{[0-9]+}}:fpr64 = nofpexcept FRINTMv4f16 %{{[0-9]+}}
     liveins: $d0
     %0:fpr(<4 x s16>) = COPY $d0
     %1:fpr(<4 x s16>) = G_FFLOOR %0
     $d0 = COPY %1(<4 x s16>)
 
 ...
 ---
 name:            floor_v8f16
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
 body:             |
   bb.0:
     ; CHECK-LABEL: name:            floor_v8f16
-    ; CHECK: %{{[0-9]+}}:fpr128 = FRINTMv8f16 %{{[0-9]+}}
+    ; CHECK: %{{[0-9]+}}:fpr128 = nofpexcept FRINTMv8f16 %{{[0-9]+}}
     liveins: $q0
     %0:fpr(<8 x s16>) = COPY $q0
     %1:fpr(<8 x s16>) = G_FFLOOR %0
     $q0 = COPY %1(<8 x s16>)
 
 ...

llvm/test/CodeGen/AArch64/GlobalISel/select-fma.mir

 body:             |
   bb.0:
     liveins: $w0, $w1, $w2
 
     ; CHECK-LABEL: name: FMADDSrrr_fpr
     ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $w0
     ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $w1
     ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $w2
-    ; CHECK: [[FMADDSrrr:%[0-9]+]]:fpr32 = FMADDSrrr [[COPY]], [[COPY1]], [[COPY2]]
+    ; CHECK: [[FMADDSrrr:%[0-9]+]]:fpr32 = nofpexcept FMADDSrrr [[COPY]], [[COPY1]], [[COPY2]]
     ; CHECK: $w0 = COPY [[FMADDSrrr]]
     %0(s32) = COPY $w0
     %1(s32) = COPY $w1
     %2(s32) = COPY $w2
     %3(s32) = G_FMA %0, %1, %2
     $w0 = COPY %3
 ...

llvm/test/CodeGen/AArch64/GlobalISel/select-fmul-indexed.mir

bb.1:
 
     ; CHECK-LABEL: name: v2s32_fmul_indexed
     ; CHECK: liveins: $d0, $x0
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
     ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x0
     ; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY1]], 0 :: (load (<2 x s32>), align 4)
     ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
     ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[LDRDui]], %subreg.dsub
-    ; CHECK: [[FMULv2i32_indexed:%[0-9]+]]:fpr64 = FMULv2i32_indexed [[COPY]], [[INSERT_SUBREG]], 0
+    ; CHECK: [[FMULv2i32_indexed:%[0-9]+]]:fpr64 = nofpexcept FMULv2i32_indexed [[COPY]], [[INSERT_SUBREG]], 0
     ; CHECK: $d0 = COPY [[FMULv2i32_indexed]]
     ; CHECK: RET_ReallyLR implicit $d0
     %0:fpr(<2 x s32>) = COPY $d0
     %1:gpr(p0) = COPY $x0
     %2:fpr(<2 x s32>) = G_LOAD %1(p0) :: (load (<2 x s32>), align 4)
     %9:fpr(<2 x s32>) = G_IMPLICIT_DEF
     %10:fpr(<4 x s32>) = G_CONCAT_VECTORS %2(<2 x s32>), %9(<2 x s32>)
     %8:gpr(s64) = G_CONSTANT i64 0
     %5:fpr(<2 x s32>) = G_DUPLANE32 %10, %8(s64)
     %7:fpr(<2 x s32>) = G_FMUL %0, %5
     $d0 = COPY %7(<2 x s32>)
     RET_ReallyLR implicit $d0
 
 ...

llvm/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir

registers:
   - { id: 1, class: fpr }
 
 body:             |
   bb.0:
     liveins: $s0
 
     ; CHECK-LABEL: name: fptrunc_s16_s32_fpr
     ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
-    ; CHECK: [[FCVTHSr:%[0-9]+]]:fpr16 = FCVTHSr [[COPY]]
+    ; CHECK: [[FCVTHSr:%[0-9]+]]:fpr16 = nofpexcept FCVTHSr [[COPY]]
     ; CHECK: $h0 = COPY [[FCVTHSr]]
     %0(s32) = COPY $s0
     %1(s16) = G_FPTRUNC %0
     $h0 = COPY %1(s16)
 ...
 
 ---
 name:            fptrunc_s16_s64_fpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
 
 body:             |
   bb.0:
     liveins: $d0
 
     ; CHECK-LABEL: name: fptrunc_s16_s64_fpr
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[FCVTHDr:%[0-9]+]]:fpr16 = FCVTHDr [[COPY]]
+    ; CHECK: [[FCVTHDr:%[0-9]+]]:fpr16 = nofpexcept FCVTHDr [[COPY]]
     ; CHECK: $h0 = COPY [[FCVTHDr]]
     %0(s64) = COPY $d0
     %1(s16) = G_FPTRUNC %0
     $h0 = COPY %1(s16)
 ...
 
 ---
 name:            fptrunc_s32_s64_fpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
 
 body:             |
   bb.0:
     liveins: $d0
 
     ; CHECK-LABEL: name: fptrunc_s32_s64_fpr
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[FCVTSDr:%[0-9]+]]:fpr32 = FCVTSDr [[COPY]]
+    ; CHECK: [[FCVTSDr:%[0-9]+]]:fpr32 = nofpexcept FCVTSDr [[COPY]]
     ; CHECK: $s0 = COPY [[FCVTSDr]]
     %0(s64) = COPY $d0
     %1(s32) = G_FPTRUNC %0
     $s0 = COPY %1(s32)
 ...
 
 ---
 name:            fptrunc_v4s16_v4s32_fpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
 
 body:             |
   bb.0:
     liveins: $d0
     ; CHECK-LABEL: name: fptrunc_v4s16_v4s32_fpr
     ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[FCVTNv4i16_:%[0-9]+]]:fpr64 = FCVTNv4i16 [[COPY]]
+    ; CHECK: [[FCVTNv4i16_:%[0-9]+]]:fpr64 = nofpexcept FCVTNv4i16 [[COPY]]
     ; CHECK: $d0 = COPY [[FCVTNv4i16_]]
     %0(<4 x s32>) = COPY $q0
     %1(<4 x s16>) = G_FPTRUNC %0
     $d0 = COPY %1(<4 x s16>)
 ...
 
 ---
 name:            fptrunc_v2s32_v2s64_fpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
 
 body:             |
   bb.0:
     liveins: $q0
     ; CHECK-LABEL: name: fptrunc_v2s32_v2s64_fpr
     ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[FCVTNv2i32_:%[0-9]+]]:fpr64 = FCVTNv2i32 [[COPY]]
+    ; CHECK: [[FCVTNv2i32_:%[0-9]+]]:fpr64 = nofpexcept FCVTNv2i32 [[COPY]]
     ; CHECK: $d0 = COPY [[FCVTNv2i32_]]
     %0(<2 x s64>) = COPY $q0
     %1(<2 x s32>) = G_FPTRUNC %0
     $d0 = COPY %1(<2 x s32>)
 ...
 
 ---
 name:            fpext_s32_s16_fpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
 
 body:             |
   bb.0:
     liveins: $h0
 
     ; CHECK-LABEL: name: fpext_s32_s16_fpr
     ; CHECK: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
-    ; CHECK: [[FCVTSHr:%[0-9]+]]:fpr32 = FCVTSHr [[COPY]]
+    ; CHECK: [[FCVTSHr:%[0-9]+]]:fpr32 = nofpexcept FCVTSHr [[COPY]]
     ; CHECK: $s0 = COPY [[FCVTSHr]]
     %0(s16) = COPY $h0
     %1(s32) = G_FPEXT %0
     $s0 = COPY %1(s32)
 ...
 
 ---
 name:            fpext_s64_s16_fpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
 
 body:             |
   bb.0:
     liveins: $h0
 
     ; CHECK-LABEL: name: fpext_s64_s16_fpr
     ; CHECK: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
-    ; CHECK: [[FCVTDHr:%[0-9]+]]:fpr64 = FCVTDHr [[COPY]]
+    ; CHECK: [[FCVTDHr:%[0-9]+]]:fpr64 = nofpexcept FCVTDHr [[COPY]]
     ; CHECK: $d0 = COPY [[FCVTDHr]]
     %0(s16) = COPY $h0
     %1(s64) = G_FPEXT %0
     $d0 = COPY %1(s64)
 ...
 
 ---
 name:            fpext_s64_s32_fpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
 
 body:             |
   bb.0:
     liveins: $d0
 
     ; CHECK-LABEL: name: fpext_s64_s32_fpr
     ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
-    ; CHECK: [[FCVTDSr:%[0-9]+]]:fpr64 = FCVTDSr [[COPY]]
+    ; CHECK: [[FCVTDSr:%[0-9]+]]:fpr64 = nofpexcept FCVTDSr [[COPY]]
     ; CHECK: $d0 = COPY [[FCVTDSr]]
     %0(s32) = COPY $s0
     %1(s64) = G_FPEXT %0
     $d0 = COPY %1(s64)
 ...
 
 ---
 name:            fpext_v4s32_v4s16_fpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
 
 body:             |
   bb.0:
     liveins: $d0
     ; CHECK-LABEL: name: fpext_v4s32_v4s16_fpr
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[FCVTLv4i16_:%[0-9]+]]:fpr128 = FCVTLv4i16 [[COPY]]
+    ; CHECK: [[FCVTLv4i16_:%[0-9]+]]:fpr128 = nofpexcept FCVTLv4i16 [[COPY]]
     ; CHECK: $q0 = COPY [[FCVTLv4i16_]]
     %0(<4 x s16>) = COPY $d0
     %1(<4 x s32>) = G_FPEXT %0
     $q0 = COPY %1(<4 x s32>)
 ...
 
 ---
 name:            fpext_v2s64_v2s32_fpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
 
 body:             |
   bb.0:
     liveins: $d0
     ; CHECK-LABEL: name: fpext_v2s64_v2s32_fpr
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[FCVTLv2i32_:%[0-9]+]]:fpr128 = FCVTLv2i32 [[COPY]]
+    ; CHECK: [[FCVTLv2i32_:%[0-9]+]]:fpr128 = nofpexcept FCVTLv2i32 [[COPY]]
     ; CHECK: $q0 = COPY [[FCVTLv2i32_]]
     %0(<2 x s32>) = COPY $d0
     %1(<2 x s64>) = G_FPEXT %0
     $q0 = COPY %1(<2 x s64>)
 ...
 
 ---
 name:            sitofp_s32_s32_fpr_gpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: fpr }
 
 body:             |
   bb.0:
     liveins: $w0
 
     ; CHECK-LABEL: name: sitofp_s32_s32_fpr_gpr
     ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
-    ; CHECK: [[SCVTFUWSri:%[0-9]+]]:fpr32 = SCVTFUWSri [[COPY]]
+    ; CHECK: [[SCVTFUWSri:%[0-9]+]]:fpr32 = nofpexcept SCVTFUWSri [[COPY]]
     ; CHECK: $s0 = COPY [[SCVTFUWSri]]
     %0(s32) = COPY $w0
     %1(s32) = G_SITOFP %0
     $s0 = COPY %1(s32)
 ...
 
 ---
 name:            sitofp_s32_s32_fpr_fpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
 
 body:             |
   bb.0:
     liveins: $s0
 
     ; CHECK-LABEL: name: sitofp_s32_s32_fpr_fpr
     ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
-    ; CHECK: [[SCVTFv1i32_:%[0-9]+]]:fpr32 = SCVTFv1i32 [[COPY]]
+    ; CHECK: [[SCVTFv1i32_:%[0-9]+]]:fpr32 = nofpexcept SCVTFv1i32 [[COPY]]
     ; CHECK: $s0 = COPY [[SCVTFv1i32_]]
     %0(s32) = COPY $s0
     %1(s32) = G_SITOFP %0
     $s0 = COPY %1(s32)
 ...
 
 ---
 name:            uitofp_s32_s32_fpr_fpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
 
 body:             |
   bb.0:
     liveins: $s0
 
     ; CHECK-LABEL: name: uitofp_s32_s32_fpr_fpr
     ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
-    ; CHECK: [[UCVTFv1i32_:%[0-9]+]]:fpr32 = UCVTFv1i32 [[COPY]]
+    ; CHECK: [[UCVTFv1i32_:%[0-9]+]]:fpr32 = nofpexcept UCVTFv1i32 [[COPY]]
     ; CHECK: $s0 = COPY [[UCVTFv1i32_]]
     %0(s32) = COPY $s0
     %1(s32) = G_UITOFP %0
     $s0 = COPY %1(s32)
 ...
 
 ---
 name:            sitofp_s32_s64_fpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: fpr }
 
 body:             |
   bb.0:
     liveins: $x0
 
     ; CHECK-LABEL: name: sitofp_s32_s64_fpr
     ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
-    ; CHECK: [[SCVTFUXSri:%[0-9]+]]:fpr32 = SCVTFUXSri [[COPY]]
+    ; CHECK: [[SCVTFUXSri:%[0-9]+]]:fpr32 = nofpexcept SCVTFUXSri [[COPY]]
     ; CHECK: $s0 = COPY [[SCVTFUXSri]]
     %0(s64) = COPY $x0
     %1(s32) = G_SITOFP %0
     $s0 = COPY %1(s32)
 ...
 
 ---
 name:            sitofp_s64_s32_fpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: fpr }
 
 body:             |
   bb.0:
     liveins: $w0
 
     ; CHECK-LABEL: name: sitofp_s64_s32_fpr
     ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
-    ; CHECK: [[SCVTFUWDri:%[0-9]+]]:fpr64 = SCVTFUWDri [[COPY]]
+    ; CHECK: [[SCVTFUWDri:%[0-9]+]]:fpr64 = nofpexcept SCVTFUWDri [[COPY]]
     ; CHECK: $d0 = COPY [[SCVTFUWDri]]
     %0(s32) = COPY $w0
     %1(s64) = G_SITOFP %0
     $d0 = COPY %1(s64)
 ...
 
 ---
 name:            sitofp_s64_s32_fpr_both
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
 
 body:             |
   bb.0:
     liveins: $s0
 
     ; CHECK-LABEL: name: sitofp_s64_s32_fpr_both
     ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
     ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
-    ; CHECK: [[SCVTFUWDri:%[0-9]+]]:fpr64 = SCVTFUWDri [[COPY1]]
+    ; CHECK: [[SCVTFUWDri:%[0-9]+]]:fpr64 = nofpexcept SCVTFUWDri [[COPY1]]
     ; CHECK: $d0 = COPY [[SCVTFUWDri]]
     %0(s32) = COPY $s0
     %1(s64) = G_SITOFP %0
     $d0 = COPY %1(s64)
 ...
 
 ---
 name:            sitofp_s64_s64_fpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: fpr }
 
 body:             |
   bb.0:
     liveins: $x0
 
     ; CHECK-LABEL: name: sitofp_s64_s64_fpr
     ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
-    ; CHECK: [[SCVTFUXDri:%[0-9]+]]:fpr64 = SCVTFUXDri [[COPY]]
+    ; CHECK: [[SCVTFUXDri:%[0-9]+]]:fpr64 = nofpexcept SCVTFUXDri [[COPY]]
     ; CHECK: $d0 = COPY [[SCVTFUXDri]]
     %0(s64) = COPY $x0
     %1(s64) = G_SITOFP %0
     $d0 = COPY %1(s64)
 ...
 
 ---
 name:            uitofp_s32_s32_fpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: fpr }
 
 body:             |
   bb.0:
     liveins: $w0
 
     ; CHECK-LABEL: name: uitofp_s32_s32_fpr
     ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
-    ; CHECK: [[UCVTFUWSri:%[0-9]+]]:fpr32 = UCVTFUWSri [[COPY]]
+    ; CHECK: [[UCVTFUWSri:%[0-9]+]]:fpr32 = nofpexcept UCVTFUWSri [[COPY]]
     ; CHECK: $s0 = COPY [[UCVTFUWSri]]
     %0(s32) = COPY $w0
     %1(s32) = G_UITOFP %0
     $s0 = COPY %1(s32)
 ...
 
 ---
 name:            uitofp_s32_s64_fpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: fpr }
 
 body:             |
   bb.0:
     liveins: $x0
 
     ; CHECK-LABEL: name: uitofp_s32_s64_fpr
     ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
-    ; CHECK: [[UCVTFUXSri:%[0-9]+]]:fpr32 = UCVTFUXSri [[COPY]]
+    ; CHECK: [[UCVTFUXSri:%[0-9]+]]:fpr32 = nofpexcept UCVTFUXSri [[COPY]]
     ; CHECK: $s0 = COPY [[UCVTFUXSri]]
     %0(s64) = COPY $x0
     %1(s32) = G_UITOFP %0
     $s0 = COPY %1(s32)
 ...
 
 ---
 name:            uitofp_s64_s32_fpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: fpr }
 
 body:             |
   bb.0:
     liveins: $w0
 
     ; CHECK-LABEL: name: uitofp_s64_s32_fpr
     ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
-    ; CHECK: [[UCVTFUWDri:%[0-9]+]]:fpr64 = UCVTFUWDri [[COPY]]
+    ; CHECK: [[UCVTFUWDri:%[0-9]+]]:fpr64 = nofpexcept UCVTFUWDri [[COPY]]
     ; CHECK: $d0 = COPY [[UCVTFUWDri]]
     %0(s32) = COPY $w0
     %1(s64) = G_UITOFP %0
     $d0 = COPY %1(s64)
 ...
 
 ---
 name:            uitofp_s64_s64_fpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: fpr }
 
 body:             |
   bb.0:
     liveins: $x0
 
     ; CHECK-LABEL: name: uitofp_s64_s64_fpr
     ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
-    ; CHECK: [[UCVTFUXDri:%[0-9]+]]:fpr64 = UCVTFUXDri [[COPY]]
+    ; CHECK: [[UCVTFUXDri:%[0-9]+]]:fpr64 = nofpexcept UCVTFUXDri [[COPY]]
     ; CHECK: $d0 = COPY [[UCVTFUXDri]]
     %0(s64) = COPY $x0
     %1(s64) = G_UITOFP %0
     $d0 = COPY %1(s64)
 ...
 
 ---
 name:            fptosi_s32_s32_gpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: gpr }
 
 body:             |
   bb.0:
     liveins: $s0
 
     ; CHECK-LABEL: name: fptosi_s32_s32_gpr
     ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
-    ; CHECK: [[FCVTZSUWSr:%[0-9]+]]:gpr32 = FCVTZSUWSr [[COPY]]
+    ; CHECK: [[FCVTZSUWSr:%[0-9]+]]:gpr32 = nofpexcept FCVTZSUWSr [[COPY]]
     ; CHECK: $w0 = COPY [[FCVTZSUWSr]]
     %0(s32) = COPY $s0
     %1(s32) = G_FPTOSI %0
     $w0 = COPY %1(s32)
 ...
 
 ---
 name:            fptosi_s32_s64_gpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: gpr }
 
 body:             |
   bb.0:
     liveins: $d0
 
     ; CHECK-LABEL: name: fptosi_s32_s64_gpr
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[FCVTZSUWDr:%[0-9]+]]:gpr32 = FCVTZSUWDr [[COPY]]
+    ; CHECK: [[FCVTZSUWDr:%[0-9]+]]:gpr32 = nofpexcept FCVTZSUWDr [[COPY]]
     ; CHECK: $w0 = COPY [[FCVTZSUWDr]]
     %0(s64) = COPY $d0
     %1(s32) = G_FPTOSI %0
     $w0 = COPY %1(s32)
 ...
 
 ---
 name:            fptosi_s64_s32_gpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: gpr }
 
 body:             |
   bb.0:
     liveins: $s0
 
     ; CHECK-LABEL: name: fptosi_s64_s32_gpr
     ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
-    ; CHECK: [[FCVTZSUXSr:%[0-9]+]]:gpr64 = FCVTZSUXSr [[COPY]]
+    ; CHECK: [[FCVTZSUXSr:%[0-9]+]]:gpr64 = nofpexcept FCVTZSUXSr [[COPY]]
     ; CHECK: $x0 = COPY [[FCVTZSUXSr]]
     %0(s32) = COPY $s0
     %1(s64) = G_FPTOSI %0
     $x0 = COPY %1(s64)
 ...
 
 ---
 name:            fptosi_s64_s64_gpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: gpr }
 
 body:             |
   bb.0:
     liveins: $d0
 
     ; CHECK-LABEL: name: fptosi_s64_s64_gpr
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[FCVTZSUXDr:%[0-9]+]]:gpr64 = FCVTZSUXDr [[COPY]]
+    ; CHECK: [[FCVTZSUXDr:%[0-9]+]]:gpr64 = nofpexcept FCVTZSUXDr [[COPY]]
     ; CHECK: $x0 = COPY [[FCVTZSUXDr]]
     %0(s64) = COPY $d0
     %1(s64) = G_FPTOSI %0
     $x0 = COPY %1(s64)
 ...
 
 ---
 name:            fptoui_s32_s32_gpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: gpr }
 
 body:             |
   bb.0:
     liveins: $s0
 
     ; CHECK-LABEL: name: fptoui_s32_s32_gpr
     ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
-    ; CHECK: [[FCVTZUUWSr:%[0-9]+]]:gpr32 = FCVTZUUWSr [[COPY]]
+    ; CHECK: [[FCVTZUUWSr:%[0-9]+]]:gpr32 = nofpexcept FCVTZUUWSr [[COPY]]
     ; CHECK: $w0 = COPY [[FCVTZUUWSr]]
     %0(s32) = COPY $s0
     %1(s32) = G_FPTOUI %0
     $w0 = COPY %1(s32)
 ...
 
 ---
 name:            fptoui_s32_s64_gpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: gpr }
 
 body:             |
   bb.0:
     liveins: $d0
 
     ; CHECK-LABEL: name: fptoui_s32_s64_gpr
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[FCVTZUUWDr:%[0-9]+]]:gpr32 = FCVTZUUWDr [[COPY]]
+    ; CHECK: [[FCVTZUUWDr:%[0-9]+]]:gpr32 = nofpexcept FCVTZUUWDr [[COPY]]
     ; CHECK: $w0 = COPY [[FCVTZUUWDr]]
     %0(s64) = COPY $d0
     %1(s32) = G_FPTOUI %0
     $w0 = COPY %1(s32)
 ...
 
 ---
 name:            fptoui_s64_s32_gpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: gpr }
 
 body:             |
   bb.0:
     liveins: $s0
 
     ; CHECK-LABEL: name: fptoui_s64_s32_gpr
     ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
-    ; CHECK: [[FCVTZUUXSr:%[0-9]+]]:gpr64 = FCVTZUUXSr [[COPY]]
+    ; CHECK: [[FCVTZUUXSr:%[0-9]+]]:gpr64 = nofpexcept FCVTZUUXSr [[COPY]]
     ; CHECK: $x0 = COPY [[FCVTZUUXSr]]
     %0(s32) = COPY $s0
     %1(s64) = G_FPTOUI %0
     $x0 = COPY %1(s64)
 ...
 
 ---
 name:            fptoui_s64_s64_gpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: gpr }
 
 body:             |
   bb.0:
     liveins: $d0
 
     ; CHECK-LABEL: name: fptoui_s64_s64_gpr
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[FCVTZUUXDr:%[0-9]+]]:gpr64 = FCVTZUUXDr [[COPY]]
+    ; CHECK: [[FCVTZUUXDr:%[0-9]+]]:gpr64 = nofpexcept FCVTZUUXDr [[COPY]]
     ; CHECK: $x0 = COPY [[FCVTZUUXDr]]
     %0(s64) = COPY $d0
     %1(s64) = G_FPTOUI %0
     $x0 = COPY %1(s64)
 ...
 
 ---
 name:            sitofp_v2s64_v2s32
 legalized:       true
 regBankSelected: true
 
 body:             |
   bb.0:
     liveins: $d0
 
     ; CHECK-LABEL: name: sitofp_v2s64_v2s32
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
     ; CHECK: [[SSHLLv2i32_shift:%[0-9]+]]:fpr128 = SSHLLv2i32_shift [[COPY]], 0
-    ; CHECK: [[SCVTFv2f64_:%[0-9]+]]:fpr128 = SCVTFv2f64 [[SSHLLv2i32_shift]]
+    ; CHECK: [[SCVTFv2f64_:%[0-9]+]]:fpr128 = nofpexcept SCVTFv2f64 [[SSHLLv2i32_shift]]
     ; CHECK: $q0 = COPY [[SCVTFv2f64_]]
     %0:fpr(<2 x s32>) = COPY $d0
     %1:fpr(<2 x s64>) = G_SITOFP %0
     $q0 = COPY %1(<2 x s64>)
 ...
 
 ---
 name:            uitofp_v2s64_v2s32
 legalized:       true
 regBankSelected: true
 
 body:             |
   bb.0:
     liveins: $d0
 
     ; CHECK-LABEL: name: uitofp_v2s64_v2s32
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
     ; CHECK: [[USHLLv2i32_shift:%[0-9]+]]:fpr128 = USHLLv2i32_shift [[COPY]], 0
-    ; CHECK: [[UCVTFv2f64_:%[0-9]+]]:fpr128 = UCVTFv2f64 [[USHLLv2i32_shift]]
+    ; CHECK: [[UCVTFv2f64_:%[0-9]+]]:fpr128 = nofpexcept UCVTFv2f64 [[USHLLv2i32_shift]]
     ; CHECK: $q0 = COPY [[UCVTFv2f64_]]
     %0:fpr(<2 x s32>) = COPY $d0
     %1:fpr(<2 x s64>) = G_UITOFP %0
     $q0 = COPY %1(<2 x s64>)
 ...
 
 ---
 name:            sitofp_v2s32_v2s64
 legalized:       true
 regBankSelected: true
 
 body:             |
   bb.0:
     liveins: $q0
 
     ; CHECK-LABEL: name: sitofp_v2s32_v2s64
     ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[SCVTFv2f64_:%[0-9]+]]:fpr128 = SCVTFv2f64 [[COPY]]
-    ; CHECK: [[FCVTNv2i32_:%[0-9]+]]:fpr64 = FCVTNv2i32 [[SCVTFv2f64_]]
+    ; CHECK: [[SCVTFv2f64_:%[0-9]+]]:fpr128 = nofpexcept SCVTFv2f64 [[COPY]]
+    ; CHECK: [[FCVTNv2i32_:%[0-9]+]]:fpr64 = nofpexcept FCVTNv2i32 [[SCVTFv2f64_]]
     ; CHECK: $d0 = COPY [[FCVTNv2i32_]]
     %0:fpr(<2 x s64>) = COPY $q0
     %1:fpr(<2 x s32>) = G_SITOFP %0
     $d0 = COPY %1(<2 x s32>)
 ...
 
 ---
 name:            uitofp_v2s32_v2s64
 legalized:       true
 regBankSelected: true
 
 body:             |
   bb.0:
     liveins: $q0
 
     ; CHECK-LABEL: name: uitofp_v2s32_v2s64
     ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[UCVTFv2f64_:%[0-9]+]]:fpr128 = UCVTFv2f64 [[COPY]]
-    ; CHECK: [[FCVTNv2i32_:%[0-9]+]]:fpr64 = FCVTNv2i32 [[UCVTFv2f64_]]
+    ; CHECK: [[UCVTFv2f64_:%[0-9]+]]:fpr128 = nofpexcept UCVTFv2f64 [[COPY]]
+    ; CHECK: [[FCVTNv2i32_:%[0-9]+]]:fpr64 = nofpexcept FCVTNv2i32 [[UCVTFv2f64_]]
     ; CHECK: $d0 = COPY [[FCVTNv2i32_]]
     %0:fpr(<2 x s64>) = COPY $q0
     %1:fpr(<2 x s32>) = G_UITOFP %0
     $d0 = COPY %1(<2 x s32>)
 ...
 
 ---
 name:            fptosi_v2s64_v2s32
 legalized:       true
 regBankSelected: true
 
 body:             |
   bb.0:
     liveins: $d0
 
     ; CHECK-LABEL: name: fptosi_v2s64_v2s32
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[FCVTLv2i32_:%[0-9]+]]:fpr128 = FCVTLv2i32 [[COPY]]
-    ; CHECK: [[FCVTZSv2f64_:%[0-9]+]]:fpr128 = FCVTZSv2f64 [[FCVTLv2i32_]]
+    ; CHECK: [[FCVTLv2i32_:%[0-9]+]]:fpr128 = nofpexcept FCVTLv2i32 [[COPY]]
+    ; CHECK: [[FCVTZSv2f64_:%[0-9]+]]:fpr128 = nofpexcept FCVTZSv2f64 [[FCVTLv2i32_]]
     ; CHECK: $q0 = COPY [[FCVTZSv2f64_]]
     %0:fpr(<2 x s32>) = COPY $d0
     %1:fpr(<2 x s64>) = G_FPTOSI %0
     $q0 = COPY %1(<2 x s64>)
 ...
 
 ---
 name:            fptoui_v2s64_v2s32
 legalized:       true
 regBankSelected: true
 
 body:             |
   bb.0:
     liveins: $d0
 
     ; CHECK-LABEL: name: fptoui_v2s64_v2s32
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[FCVTLv2i32_:%[0-9]+]]:fpr128 = FCVTLv2i32 [[COPY]]
-    ; CHECK: [[FCVTZUv2f64_:%[0-9]+]]:fpr128 = FCVTZUv2f64 [[FCVTLv2i32_]]
+    ; CHECK: [[FCVTLv2i32_:%[0-9]+]]:fpr128 = nofpexcept FCVTLv2i32 [[COPY]]
+    ; CHECK: [[FCVTZUv2f64_:%[0-9]+]]:fpr128 = nofpexcept FCVTZUv2f64 [[FCVTLv2i32_]]
     ; CHECK: $q0 = COPY [[FCVTZUv2f64_]]
     %0:fpr(<2 x s32>) = COPY $d0
     %1:fpr(<2 x s64>) = G_FPTOUI %0
     $q0 = COPY %1(<2 x s64>)
 ...
 
 ---
 name:            fptosi_v2s32_v2s64
 legalized:       true
 regBankSelected: true
 
 body:             |
   bb.0:
     liveins: $q0
 
     ; CHECK-LABEL: name: fptosi_v2s32_v2s64
     ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[FCVTZSv2f64_:%[0-9]+]]:fpr128 = FCVTZSv2f64 [[COPY]]
+    ; CHECK: [[FCVTZSv2f64_:%[0-9]+]]:fpr128 = nofpexcept FCVTZSv2f64 [[COPY]]
     ; CHECK: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[FCVTZSv2f64_]]
     ; CHECK: $d0 = COPY [[XTNv2i32_]]
     %0:fpr(<2 x s64>) = COPY $q0
     %1:fpr(<2 x s32>) = G_FPTOSI %0
     $d0 = COPY %1(<2 x s32>)
 ...
 
 ---
 name:            fptoui_v2s32_v2s64
 legalized:       true
 regBankSelected: true
 
 body:             |
   bb.0:
     liveins: $q0
 
     ; CHECK-LABEL: name: fptoui_v2s32_v2s64
     ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[FCVTZUv2f64_:%[0-9]+]]:fpr128 = FCVTZUv2f64 [[COPY]]
+    ; CHECK: [[FCVTZUv2f64_:%[0-9]+]]:fpr128 = nofpexcept FCVTZUv2f64 [[COPY]]
     ; CHECK: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[FCVTZUv2f64_]]
     ; CHECK: $d0 = COPY [[XTNv2i32_]]
     %0:fpr(<2 x s64>) = COPY $q0
     %1:fpr(<2 x s32>) = G_FPTOUI %0
     $d0 = COPY %1(<2 x s32>)
 ...

llvm/test/CodeGen/AArch64/GlobalISel/select-frint-nofp16.mir

 body:             |
   bb.0:
     liveins: $h0
 
     ; CHECK-LABEL: name: test_f16.rint
     ; CHECK: liveins: $h0
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
-    ; CHECK-NEXT: [[FCVTSHr:%[0-9]+]]:fpr32 = FCVTSHr [[COPY]]
-    ; CHECK-NEXT: [[FRINTXSr:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr]]
-    ; CHECK-NEXT: [[FCVTHSr:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr]]
-    ; CHECK-NEXT: $h0 = COPY [[FCVTHSr]]
+    ; CHECK-NEXT: %1:fpr32 = nofpexcept FCVTSHr [[COPY]]
+    ; CHECK-NEXT: %2:fpr32 = nofpexcept FRINTXSr %1
+    ; CHECK-NEXT: %3:fpr16 = nofpexcept FCVTHSr %2
+    ; CHECK-NEXT: $h0 = COPY %3
     ; CHECK-NEXT: RET_ReallyLR implicit $h0
     %0:fpr(s16) = COPY $h0
     %2:fpr(s32) = G_FPEXT %0(s16)
     %3:fpr(s32) = G_FRINT %2
     %1:fpr(s16) = G_FPTRUNC %3(s32)
     $h0 = COPY %1(s16)
     RET_ReallyLR implicit $h0
 
bb.0:
     ; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
     ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY]], %subreg.dsub
     ; CHECK-NEXT: [[DEF2:%[0-9]+]]:fpr128 = IMPLICIT_DEF
     ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF2]], [[COPY]], %subreg.dsub
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY [[INSERT_SUBREG]].hsub
     ; CHECK-NEXT: [[DUPi16_:%[0-9]+]]:fpr16 = DUPi16 [[INSERT_SUBREG]], 1
     ; CHECK-NEXT: [[DUPi16_1:%[0-9]+]]:fpr16 = DUPi16 [[INSERT_SUBREG1]], 2
     ; CHECK-NEXT: [[DUPi16_2:%[0-9]+]]:fpr16 = DUPi16 [[INSERT_SUBREG2]], 3
-    ; CHECK-NEXT: [[FCVTSHr:%[0-9]+]]:fpr32 = FCVTSHr [[COPY1]]
-    ; CHECK-NEXT: [[FRINTXSr:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr]]
-    ; CHECK-NEXT: [[FCVTHSr:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr]]
-    ; CHECK-NEXT: [[FCVTSHr1:%[0-9]+]]:fpr32 = FCVTSHr [[DUPi16_]]
-    ; CHECK-NEXT: [[FRINTXSr1:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr1]]
-    ; CHECK-NEXT: [[FCVTHSr1:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr1]]
-    ; CHECK-NEXT: [[FCVTSHr2:%[0-9]+]]:fpr32 = FCVTSHr [[DUPi16_1]]
-    ; CHECK-NEXT: [[FRINTXSr2:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr2]]
-    ; CHECK-NEXT: [[FCVTHSr2:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr2]]
-    ; CHECK-NEXT: [[FCVTSHr3:%[0-9]+]]:fpr32 = FCVTSHr [[DUPi16_2]]
-    ; CHECK-NEXT: [[FRINTXSr3:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr3]]
-    ; CHECK-NEXT: [[FCVTHSr3:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr3]]
+    ; CHECK-NEXT: %5:fpr32 = nofpexcept FCVTSHr [[COPY1]]
+    ; CHECK-NEXT: %6:fpr32 = nofpexcept FRINTXSr %5
+    ; CHECK-NEXT: %7:fpr16 = nofpexcept FCVTHSr %6
+    ; CHECK-NEXT: %8:fpr32 = nofpexcept FCVTSHr [[DUPi16_]]
+    ; CHECK-NEXT: %9:fpr32 = nofpexcept FRINTXSr %8
+    ; CHECK-NEXT: %10:fpr16 = nofpexcept FCVTHSr %9
+    ; CHECK-NEXT: %11:fpr32 = nofpexcept FCVTSHr [[DUPi16_1]]
+    ; CHECK-NEXT: %12:fpr32 = nofpexcept FRINTXSr %11
+    ; CHECK-NEXT: %13:fpr16 = nofpexcept FCVTHSr %12
+    ; CHECK-NEXT: %14:fpr32 = nofpexcept FCVTSHr [[DUPi16_2]]
+    ; CHECK-NEXT: %15:fpr32 = nofpexcept FRINTXSr %14
+    ; CHECK-NEXT: %16:fpr16 = nofpexcept FCVTHSr %15
     ; CHECK-NEXT: [[DEF3:%[0-9]+]]:fpr128 = IMPLICIT_DEF
-    ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF3]], [[FCVTHSr]], %subreg.hsub
+    ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF3]], %7, %subreg.hsub
     ; CHECK-NEXT: [[DEF4:%[0-9]+]]:fpr128 = IMPLICIT_DEF
-    ; CHECK-NEXT: [[INSERT_SUBREG4:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF4]], [[FCVTHSr1]], %subreg.hsub
+    ; CHECK-NEXT: [[INSERT_SUBREG4:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF4]], %10, %subreg.hsub
     ; CHECK-NEXT: [[INSvi16lane:%[0-9]+]]:fpr128 = INSvi16lane [[INSERT_SUBREG3]], 1, [[INSERT_SUBREG4]], 0
     ; CHECK-NEXT: [[DEF5:%[0-9]+]]:fpr128 = IMPLICIT_DEF
-    ; CHECK-NEXT: [[INSERT_SUBREG5:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF5]], [[FCVTHSr2]], %subreg.hsub
+    ; CHECK-NEXT: [[INSERT_SUBREG5:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF5]], %13, %subreg.hsub
     ; CHECK-NEXT: [[INSvi16lane1:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane]], 2, [[INSERT_SUBREG5]], 0
     ; CHECK-NEXT: [[DEF6:%[0-9]+]]:fpr128 = IMPLICIT_DEF
-    ; CHECK-NEXT: [[INSERT_SUBREG6:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF6]], [[FCVTHSr3]], %subreg.hsub
+    ; CHECK-NEXT: [[INSERT_SUBREG6:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF6]], %16, %subreg.hsub
     ; CHECK-NEXT: [[INSvi16lane2:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane1]], 3, [[INSERT_SUBREG6]], 0
     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi16lane2]].dsub
     ; CHECK-NEXT: $d0 = COPY [[COPY2]]
     ; CHECK-NEXT: RET_ReallyLR implicit $d0
     %0:fpr(<4 x s16>) = COPY $d0
     %2:fpr(s16), %3:fpr(s16), %4:fpr(s16), %5:fpr(s16) = G_UNMERGE_VALUES %0(<4 x s16>)
     %16:fpr(s32) = G_FPEXT %2(s16)
     %17:fpr(s32) = G_FRINT %16
bb.0:
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY [[COPY]].hsub
     ; CHECK-NEXT: [[DUPi16_:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 1
     ; CHECK-NEXT: [[DUPi16_1:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 2
     ; CHECK-NEXT: [[DUPi16_2:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 3
     ; CHECK-NEXT: [[DUPi16_3:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 4
     ; CHECK-NEXT: [[DUPi16_4:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 5
     ; CHECK-NEXT: [[DUPi16_5:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 6
     ; CHECK-NEXT: [[DUPi16_6:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 7
-    ; CHECK-NEXT: [[FCVTSHr:%[0-9]+]]:fpr32 = FCVTSHr [[COPY1]]
-    ; CHECK-NEXT: [[FRINTXSr:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr]]
-    ; CHECK-NEXT: [[FCVTHSr:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr]]
-    ; CHECK-NEXT: [[FCVTSHr1:%[0-9]+]]:fpr32 = FCVTSHr [[DUPi16_]]
-    ; CHECK-NEXT: [[FRINTXSr1:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr1]]
-    ; CHECK-NEXT: [[FCVTHSr1:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr1]]
-    ; CHECK-NEXT: [[FCVTSHr2:%[0-9]+]]:fpr32 = FCVTSHr [[DUPi16_1]]
-    ; CHECK-NEXT: [[FRINTXSr2:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr2]]
-    ; CHECK-NEXT: [[FCVTHSr2:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr2]]
-    ; CHECK-NEXT: [[FCVTSHr3:%[0-9]+]]:fpr32 = FCVTSHr [[DUPi16_2]]
-    ; CHECK-NEXT: [[FRINTXSr3:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr3]]
-    ; CHECK-NEXT: [[FCVTHSr3:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr3]]
-    ; CHECK-NEXT: [[FCVTSHr4:%[0-9]+]]:fpr32 = FCVTSHr [[DUPi16_3]]
-    ; CHECK-NEXT: [[FRINTXSr4:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr4]]
-    ; CHECK-NEXT: [[FCVTHSr4:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr4]]
-    ; CHECK-NEXT: [[FCVTSHr5:%[0-9]+]]:fpr32 = FCVTSHr [[DUPi16_4]]
-    ; CHECK-NEXT: [[FRINTXSr5:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr5]]
-    ; CHECK-NEXT: [[FCVTHSr5:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr5]]
-    ; CHECK-NEXT: [[FCVTSHr6:%[0-9]+]]:fpr32 = FCVTSHr [[DUPi16_5]]
-    ; CHECK-NEXT: [[FRINTXSr6:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr6]]
-    ; CHECK-NEXT: [[FCVTHSr6:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr6]]
-    ; CHECK-NEXT: [[FCVTSHr7:%[0-9]+]]:fpr32 = FCVTSHr [[DUPi16_6]]
-    ; CHECK-NEXT: [[FRINTXSr7:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr7]]
-    ; CHECK-NEXT: [[FCVTHSr7:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr7]]
+    ; CHECK-NEXT: %9:fpr32 = nofpexcept FCVTSHr [[COPY1]]
+    ; CHECK-NEXT: %10:fpr32 = nofpexcept FRINTXSr %9
+    ; CHECK-NEXT: %11:fpr16 = nofpexcept FCVTHSr %10
+    ; CHECK-NEXT: %12:fpr32 = nofpexcept FCVTSHr [[DUPi16_]]
+    ; CHECK-NEXT: %13:fpr32 = nofpexcept FRINTXSr %12
+    ; CHECK-NEXT: %14:fpr16 = nofpexcept FCVTHSr %13
+    ; CHECK-NEXT: %15:fpr32 = nofpexcept FCVTSHr [[DUPi16_1]]
+    ; CHECK-NEXT: %16:fpr32 = nofpexcept FRINTXSr %15
+    ; CHECK-NEXT: %17:fpr16 = nofpexcept FCVTHSr %16
+    ; CHECK-NEXT: %18:fpr32 = nofpexcept FCVTSHr [[DUPi16_2]]
+    ; CHECK-NEXT: %19:fpr32 = nofpexcept FRINTXSr %18
+    ; CHECK-NEXT: %20:fpr16 = nofpexcept FCVTHSr %19
+    ; CHECK-NEXT: %21:fpr32 = nofpexcept FCVTSHr [[DUPi16_3]]
+    ; CHECK-NEXT: %22:fpr32 = nofpexcept FRINTXSr %21
+    ; CHECK-NEXT: %23:fpr16 = nofpexcept FCVTHSr %22
+    ; CHECK-NEXT: %24:fpr32 = nofpexcept FCVTSHr [[DUPi16_4]]
+    ; CHECK-NEXT: %25:fpr32 = nofpexcept FRINTXSr %24
+    ; CHECK-NEXT: %26:fpr16 = nofpexcept FCVTHSr %25
+    ; CHECK-NEXT: %27:fpr32 = nofpexcept FCVTSHr [[DUPi16_5]]
+    ; CHECK-NEXT: %28:fpr32 = nofpexcept FRINTXSr %27
+    ; CHECK-NEXT: %29:fpr16 = nofpexcept FCVTHSr %28
+    ; CHECK-NEXT: %30:fpr32 = nofpexcept FCVTSHr [[DUPi16_6]]
+    ; CHECK-NEXT: %31:fpr32 = nofpexcept FRINTXSr %30
+    ; CHECK-NEXT: %32:fpr16 = nofpexcept FCVTHSr %31
     ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
-    ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[FCVTHSr]], %subreg.hsub
+    ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], %11, %subreg.hsub
     ; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
-    ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[FCVTHSr1]], %subreg.hsub
+    ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], %14, %subreg.hsub
     ; CHECK-NEXT: [[INSvi16lane:%[0-9]+]]:fpr128 = INSvi16lane [[INSERT_SUBREG]], 1, [[INSERT_SUBREG1]], 0
     ; CHECK-NEXT: [[DEF2:%[0-9]+]]:fpr128 = IMPLICIT_DEF
-    ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF2]], [[FCVTHSr2]], %subreg.hsub
+    ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF2]], %17, %subreg.hsub
     ; CHECK-NEXT: [[INSvi16lane1:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane]], 2, [[INSERT_SUBREG2]], 0
     ; CHECK-NEXT: [[DEF3:%[0-9]+]]:fpr128 = IMPLICIT_DEF
-    ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF3]], [[FCVTHSr3]], %subreg.hsub
+    ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF3]], %20, %subreg.hsub
     ; CHECK-NEXT: [[INSvi16lane2:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane1]], 3, [[INSERT_SUBREG3]], 0
     ; CHECK-NEXT: [[DEF4:%[0-9]+]]:fpr128 = IMPLICIT_DEF
-    ; CHECK-NEXT: [[INSERT_SUBREG4:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF4]], [[FCVTHSr4]], %subreg.hsub
+    ; CHECK-NEXT: [[INSERT_SUBREG4:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF4]], %23, %subreg.hsub
     ; CHECK-NEXT: [[INSvi16lane3:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane2]], 4, [[INSERT_SUBREG4]], 0
     ; CHECK-NEXT: [[DEF5:%[0-9]+]]:fpr128 = IMPLICIT_DEF
-    ; CHECK-NEXT: [[INSERT_SUBREG5:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF5]], [[FCVTHSr5]], %subreg.hsub
+    ; CHECK-NEXT: [[INSERT_SUBREG5:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF5]], %26, %subreg.hsub
     ; CHECK-NEXT: [[INSvi16lane4:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane3]], 5, [[INSERT_SUBREG5]], 0
     ; CHECK-NEXT: [[DEF6:%[0-9]+]]:fpr128 = IMPLICIT_DEF
-    ; CHECK-NEXT: [[INSERT_SUBREG6:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF6]], [[FCVTHSr6]], %subreg.hsub
+    ; CHECK-NEXT: [[INSERT_SUBREG6:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF6]], %29, %subreg.hsub
     ; CHECK-NEXT: [[INSvi16lane5:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane4]], 6, [[INSERT_SUBREG6]], 0
     ; CHECK-NEXT: [[DEF7:%[0-9]+]]:fpr128 = IMPLICIT_DEF
-    ; CHECK-NEXT: [[INSERT_SUBREG7:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF7]], [[FCVTHSr7]], %subreg.hsub
+    ; CHECK-NEXT: [[INSERT_SUBREG7:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF7]], %32, %subreg.hsub
     ; CHECK-NEXT: [[INSvi16lane6:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane5]], 7, [[INSERT_SUBREG7]], 0
     ; CHECK-NEXT: $q0 = COPY [[INSvi16lane6]]
     ; CHECK-NEXT: RET_ReallyLR implicit $q0
     %0:fpr(<8 x s16>) = COPY $q0
     %2:fpr(s16), %3:fpr(s16), %4:fpr(s16), %5:fpr(s16), %6:fpr(s16), %7:fpr(s16), %8:fpr(s16), %9:fpr(s16) = G_UNMERGE_VALUES %0(<8 x s16>)
     %32:fpr(s32) = G_FPEXT %2(s16)
     %33:fpr(s32) = G_FRINT %32
     %10:fpr(s16) = G_FPTRUNC %33(s32)

llvm/test/CodeGen/AArch64/GlobalISel/select-frint.mir

 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $h0
 
     ; CHECK-LABEL: name: test_f16.rint
     ; CHECK: liveins: $h0
     ; CHECK: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
-    ; CHECK: [[FRINTXHr:%[0-9]+]]:fpr16 = FRINTXHr [[COPY]]
+    ; CHECK: [[FRINTXHr:%[0-9]+]]:fpr16 = nofpexcept FRINTXHr [[COPY]]
     ; CHECK: $h0 = COPY [[FRINTXHr]]
     ; CHECK: RET_ReallyLR implicit $h0
     %0:fpr(s16) = COPY $h0
     %1:fpr(s16) = G_FRINT %0
     $h0 = COPY %1(s16)
     RET_ReallyLR implicit $h0
 
 ...
 ---
 name:            test_f32.rint
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $s0
 
     ; CHECK-LABEL: name: test_f32.rint
     ; CHECK: liveins: $s0
     ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
-    ; CHECK: [[FRINTXSr:%[0-9]+]]:fpr32 = FRINTXSr [[COPY]]
+    ; CHECK: [[FRINTXSr:%[0-9]+]]:fpr32 = nofpexcept FRINTXSr [[COPY]]
     ; CHECK: $s0 = COPY [[FRINTXSr]]
     ; CHECK: RET_ReallyLR implicit $s0
     %0:fpr(s32) = COPY $s0
     %1:fpr(s32) = G_FRINT %0
     $s0 = COPY %1(s32)
     RET_ReallyLR implicit $s0
 
 ...
 ---
 name:            test_f64.rint
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $d0
 
     ; CHECK-LABEL: name: test_f64.rint
     ; CHECK: liveins: $d0
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[FRINTXDr:%[0-9]+]]:fpr64 = FRINTXDr [[COPY]]
+    ; CHECK: [[FRINTXDr:%[0-9]+]]:fpr64 = nofpexcept FRINTXDr [[COPY]]
     ; CHECK: $d0 = COPY [[FRINTXDr]]
     ; CHECK: RET_ReallyLR implicit $d0
     %0:fpr(s64) = COPY $d0
     %1:fpr(s64) = G_FRINT %0
     $d0 = COPY %1(s64)
     RET_ReallyLR implicit $d0
 
 ...
 ---
 name:            test_v4f32.rint
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $q0
 
     ; CHECK-LABEL: name: test_v4f32.rint
     ; CHECK: liveins: $q0
     ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[FRINTXv4f32_:%[0-9]+]]:fpr128 = FRINTXv4f32 [[COPY]]
+    ; CHECK: [[FRINTXv4f32_:%[0-9]+]]:fpr128 = nofpexcept FRINTXv4f32 [[COPY]]
     ; CHECK: $q0 = COPY [[FRINTXv4f32_]]
     ; CHECK: RET_ReallyLR implicit $q0
     %0:fpr(<4 x s32>) = COPY $q0
     %1:fpr(<4 x s32>) = G_FRINT %0
     $q0 = COPY %1(<4 x s32>)
     RET_ReallyLR implicit $q0
 
 ...
 ---
 name:            test_v2f64.rint
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $q0
 
     ; CHECK-LABEL: name: test_v2f64.rint
     ; CHECK: liveins: $q0
     ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[FRINTXv2f64_:%[0-9]+]]:fpr128 = FRINTXv2f64 [[COPY]]
+    ; CHECK: [[FRINTXv2f64_:%[0-9]+]]:fpr128 = nofpexcept FRINTXv2f64 [[COPY]]
     ; CHECK: $q0 = COPY [[FRINTXv2f64_]]
     ; CHECK: RET_ReallyLR implicit $q0
     %0:fpr(<2 x s64>) = COPY $q0
     %1:fpr(<2 x s64>) = G_FRINT %0
     $q0 = COPY %1(<2 x s64>)
     RET_ReallyLR implicit $q0
 
 ...
 ---
 name:            test_v4f16.rint
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $d0
 
     ; CHECK-LABEL: name: test_v4f16.rint
     ; CHECK: liveins: $d0
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[FRINTXv4f16_:%[0-9]+]]:fpr64 = FRINTXv4f16 [[COPY]]
+    ; CHECK: [[FRINTXv4f16_:%[0-9]+]]:fpr64 = nofpexcept FRINTXv4f16 [[COPY]]
     ; CHECK: $d0 = COPY [[FRINTXv4f16_]]
     ; CHECK: RET_ReallyLR implicit $d0
     %0:fpr(<4 x s16>) = COPY $d0
     %1:fpr(<4 x s16>) = G_FRINT %0
     $d0 = COPY %1(<4 x s16>)
     RET_ReallyLR implicit $d0
 
 ...
 ---
 name:            test_v8f16.rint
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $q0
 
     ; CHECK-LABEL: name: test_v8f16.rint
     ; CHECK: liveins: $q0
     ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[FRINTXv8f16_:%[0-9]+]]:fpr128 = FRINTXv8f16 [[COPY]]
+    ; CHECK: [[FRINTXv8f16_:%[0-9]+]]:fpr128 = nofpexcept FRINTXv8f16 [[COPY]]
     ; CHECK: $q0 = COPY [[FRINTXv8f16_]]
     ; CHECK: RET_ReallyLR implicit $q0
     %0:fpr(<8 x s16>) = COPY $q0
     %1:fpr(<8 x s16>) = G_FRINT %0
     $q0 = COPY %1(<8 x s16>)
     RET_ReallyLR implicit $q0
 
 ...
 ---
 name:            test_v2f32.rint
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $d0
 
     ; CHECK-LABEL: name: test_v2f32.rint
     ; CHECK: liveins: $d0
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[FRINTXv2f32_:%[0-9]+]]:fpr64 = FRINTXv2f32 [[COPY]]
+    ; CHECK: [[FRINTXv2f32_:%[0-9]+]]:fpr64 = nofpexcept FRINTXv2f32 [[COPY]]
     ; CHECK: $d0 = COPY [[FRINTXv2f32_]]
     ; CHECK: RET_ReallyLR implicit $d0
     %0:fpr(<2 x s32>) = COPY $d0
     %1:fpr(<2 x s32>) = G_FRINT %0
     $d0 = COPY %1(<2 x s32>)
     RET_ReallyLR implicit $d0
 
 ...

llvm/test/CodeGen/AArch64/GlobalISel/select-imm.mir

 body:             |
   bb.1 (%ir-block.0):
     liveins: $d0
 
     ; CHECK-LABEL: name: test_f64_cp
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
     ; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
     ; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0
-    ; CHECK: [[FADDDrr:%[0-9]+]]:fpr64 = FADDDrr [[COPY]], [[LDRDui]]
+    ; CHECK: [[FADDDrr:%[0-9]+]]:fpr64 = nofpexcept FADDDrr [[COPY]], [[LDRDui]]
     ; CHECK: $d0 = COPY [[FADDDrr]]
     ; CHECK: RET_ReallyLR implicit $d0
     %0:fpr(s64) = COPY $d0
     %1:fpr(s64) = G_FCONSTANT double 0x3FEFF7CED916872B
     %2:fpr(s64) = G_FADD %0, %1
     $d0 = COPY %2(s64)
     RET_ReallyLR implicit $d0
 
 ...
 # 32b FP immediates need to be loaded if using optsize.
 ---
 name:            test_f32_cp_optsize
 legalized:       true
 regBankSelected: true
 liveins:
   - { reg: '$s0' }
 body:             |
   bb.1 (%ir-block.0):
     liveins: $s0
 
     ; CHECK-LABEL: name: test_f32_cp_optsize
     ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
     ; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
     ; CHECK: [[LDRSui:%[0-9]+]]:fpr32 = LDRSui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0
-    ; CHECK: [[FADDSrr:%[0-9]+]]:fpr32 = FADDSrr [[COPY]], [[LDRSui]]
+    ; CHECK: [[FADDSrr:%[0-9]+]]:fpr32 = nofpexcept FADDSrr [[COPY]], [[LDRSui]]
     ; CHECK: $s0 = COPY [[FADDSrr]]
     ; CHECK: RET_ReallyLR implicit $s0
     %0:fpr(s32) = COPY $s0
     %1:fpr(s32) = G_FCONSTANT float 0x3FDB267DE0000000
     %2:fpr(s32) = G_FADD %0, %1
     $s0 = COPY %2(s32)
     RET_ReallyLR implicit $s0
 
 ...
 # 32b FP immediates need to be loaded if using minsize.
 ---
 name:            test_f32_cp_minsize
 legalized:       true
 regBankSelected: true
 liveins:
   - { reg: '$s0' }
 body:             |
   bb.1 (%ir-block.0):
     liveins: $s0
 
     ; CHECK-LABEL: name: test_f32_cp_minsize
     ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
     ; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
     ; CHECK: [[LDRSui:%[0-9]+]]:fpr32 = LDRSui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0
-    ; CHECK: [[FADDSrr:%[0-9]+]]:fpr32 = FADDSrr [[COPY]], [[LDRSui]]
+    ; CHECK: [[FADDSrr:%[0-9]+]]:fpr32 = nofpexcept FADDSrr [[COPY]], [[LDRSui]]
     ; CHECK: $s0 = COPY [[FADDSrr]]
     ; CHECK: RET_ReallyLR implicit $s0
     %0:fpr(s32) = COPY $s0
     %1:fpr(s32) = G_FCONSTANT float 0x3FDB267DE0000000
     %2:fpr(s32) = G_FADD %0, %1
     $s0 = COPY %2(s32)
     RET_ReallyLR implicit $s0
 
 ...

llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-round.mir

 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $d0
 
     ; CHECK-LABEL: name: test_f64.intrinsic_round
     ; CHECK: liveins: $d0
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[FRINTADr:%[0-9]+]]:fpr64 = FRINTADr [[COPY]]
+    ; CHECK: [[FRINTADr:%[0-9]+]]:fpr64 = nofpexcept FRINTADr [[COPY]]
     ; CHECK: $d0 = COPY [[FRINTADr]]
     ; CHECK: RET_ReallyLR implicit $d0
     %0:fpr(s64) = COPY $d0
     %1:fpr(s64) = G_INTRINSIC_ROUND %0
     $d0 = COPY %1(s64)
     RET_ReallyLR implicit $d0
 
 ...
 ---
 name:            test_f32.intrinsic_round
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $s0
 
     ; CHECK-LABEL: name: test_f32.intrinsic_round
     ; CHECK: liveins: $s0
     ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
-    ; CHECK: [[FRINTASr:%[0-9]+]]:fpr32 = FRINTASr [[COPY]]
+    ; CHECK: [[FRINTASr:%[0-9]+]]:fpr32 = nofpexcept FRINTASr [[COPY]]
     ; CHECK: $s0 = COPY [[FRINTASr]]
     ; CHECK: RET_ReallyLR implicit $s0
     %0:fpr(s32) = COPY $s0
     %1:fpr(s32) = G_INTRINSIC_ROUND %0
     $s0 = COPY %1(s32)
     RET_ReallyLR implicit $s0
 
 ...
 ---
 name:            test_f16.intrinsic_round
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 frameInfo:
   maxCallFrameSize: 0
 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $h0
 
     ; CHECK-LABEL: name: test_f16.intrinsic_round
     ; CHECK: liveins: $h0
     ; CHECK: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
-    ; CHECK: [[FRINTAHr:%[0-9]+]]:fpr16 = FRINTAHr [[COPY]]
+    ; CHECK: [[FRINTAHr:%[0-9]+]]:fpr16 = nofpexcept FRINTAHr [[COPY]]
     ; CHECK: $h0 = COPY [[FRINTAHr]]
     ; CHECK: RET_ReallyLR implicit $h0
     %0:fpr(s16) = COPY $h0
     %1:fpr(s16) = G_INTRINSIC_ROUND %0
     $h0 = COPY %1(s16)
     RET_ReallyLR implicit $h0
 
 ...
 ---
 name:            test_v4f16.intrinsic_round
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 frameInfo:
   maxCallFrameSize: 0
 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $d0
 
     ; CHECK-LABEL: name: test_v4f16.intrinsic_round
     ; CHECK: liveins: $d0
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[FRINTAv4f16_:%[0-9]+]]:fpr64 = FRINTAv4f16 [[COPY]]
+    ; CHECK: [[FRINTAv4f16_:%[0-9]+]]:fpr64 = nofpexcept FRINTAv4f16 [[COPY]]
     ; CHECK: $d0 = COPY [[FRINTAv4f16_]]
     ; CHECK: RET_ReallyLR implicit $d0
     %0:fpr(<4 x s16>) = COPY $d0
     %1:fpr(<4 x s16>) = G_INTRINSIC_ROUND %0
     $d0 = COPY %1(<4 x s16>)
     RET_ReallyLR implicit $d0
 
 ...
 ---
 name:            test_v8f16.intrinsic_round
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 frameInfo:
   maxCallFrameSize: 0
 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $q0
 
     ; CHECK-LABEL: name: test_v8f16.intrinsic_round
     ; CHECK: liveins: $q0
     ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[FRINTAv8f16_:%[0-9]+]]:fpr128 = FRINTAv8f16 [[COPY]]
+    ; CHECK: [[FRINTAv8f16_:%[0-9]+]]:fpr128 = nofpexcept FRINTAv8f16 [[COPY]]
     ; CHECK: $q0 = COPY [[FRINTAv8f16_]]
     ; CHECK: RET_ReallyLR implicit $q0
     %0:fpr(<8 x s16>) = COPY $q0
     %1:fpr(<8 x s16>) = G_INTRINSIC_ROUND %0
     $q0 = COPY %1(<8 x s16>)
     RET_ReallyLR implicit $q0
 
 ...
 ---
 name:            test_v2f32.intrinsic_round
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 frameInfo:
   maxCallFrameSize: 0
 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $d0
 
     ; CHECK-LABEL: name: test_v2f32.intrinsic_round
     ; CHECK: liveins: $d0
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[FRINTAv2f32_:%[0-9]+]]:fpr64 = FRINTAv2f32 [[COPY]]
+    ; CHECK: [[FRINTAv2f32_:%[0-9]+]]:fpr64 = nofpexcept FRINTAv2f32 [[COPY]]
     ; CHECK: $d0 = COPY [[FRINTAv2f32_]]
     ; CHECK: RET_ReallyLR implicit $d0
     %0:fpr(<2 x s32>) = COPY $d0
     %1:fpr(<2 x s32>) = G_INTRINSIC_ROUND %0
     $d0 = COPY %1(<2 x s32>)
     RET_ReallyLR implicit $d0
 
 ...
 ---
 name:            test_v4f32.intrinsic_round
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 frameInfo:
   maxCallFrameSize: 0
 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $q0
 
     ; CHECK-LABEL: name: test_v4f32.intrinsic_round
     ; CHECK: liveins: $q0
     ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[FRINTAv4f32_:%[0-9]+]]:fpr128 = FRINTAv4f32 [[COPY]]
+    ; CHECK: [[FRINTAv4f32_:%[0-9]+]]:fpr128 = nofpexcept FRINTAv4f32 [[COPY]]
     ; CHECK: $q0 = COPY [[FRINTAv4f32_]]
     ; CHECK: RET_ReallyLR implicit $q0
     %0:fpr(<4 x s32>) = COPY $q0
     %1:fpr(<4 x s32>) = G_INTRINSIC_ROUND %0
     $q0 = COPY %1(<4 x s32>)
     RET_ReallyLR implicit $q0
 
 ...
 ---
 name:            test_v2f64.intrinsic_round
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 frameInfo:
   maxCallFrameSize: 0
 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $q0
 
     ; CHECK-LABEL: name: test_v2f64.intrinsic_round
     ; CHECK: liveins: $q0
     ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[FRINTAv2f64_:%[0-9]+]]:fpr128 = FRINTAv2f64 [[COPY]]
+    ; CHECK: [[FRINTAv2f64_:%[0-9]+]]:fpr128 = nofpexcept FRINTAv2f64 [[COPY]]
     ; CHECK: $q0 = COPY [[FRINTAv2f64_]]
     ; CHECK: RET_ReallyLR implicit $q0
     %0:fpr(<2 x s64>) = COPY $q0
     %1:fpr(<2 x s64>) = G_INTRINSIC_ROUND %0
     $q0 = COPY %1(<2 x s64>)
     RET_ReallyLR implicit $q0

llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-trunc.mir

 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $d0
 
     ; CHECK-LABEL: name: test_f64.intrinsic_trunc
     ; CHECK: liveins: $d0
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[FRINTZDr:%[0-9]+]]:fpr64 = FRINTZDr [[COPY]]
+    ; CHECK: [[FRINTZDr:%[0-9]+]]:fpr64 = nofpexcept FRINTZDr [[COPY]]
     ; CHECK: $d0 = COPY [[FRINTZDr]]
     ; CHECK: RET_ReallyLR implicit $d0
     %0:fpr(s64) = COPY $d0
     %1:fpr(s64) = G_INTRINSIC_TRUNC %0
     $d0 = COPY %1(s64)
     RET_ReallyLR implicit $d0
 
 ...
 ---
 name:            test_f32.intrinsic_trunc
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $s0
 
     ; CHECK-LABEL: name: test_f32.intrinsic_trunc
     ; CHECK: liveins: $s0
     ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
-    ; CHECK: [[FRINTZSr:%[0-9]+]]:fpr32 = FRINTZSr [[COPY]]
+    ; CHECK: [[FRINTZSr:%[0-9]+]]:fpr32 = nofpexcept FRINTZSr [[COPY]]
     ; CHECK: $s0 = COPY [[FRINTZSr]]
     ; CHECK: RET_ReallyLR implicit $s0
     %0:fpr(s32) = COPY $s0
     %1:fpr(s32) = G_INTRINSIC_TRUNC %0
     $s0 = COPY %1(s32)
     RET_ReallyLR implicit $s0
 
 ...
 ---
 name:            test_f16.intrinsic_trunc
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 frameInfo:
   maxCallFrameSize: 0
 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $h0
 
     ; CHECK-LABEL: name: test_f16.intrinsic_trunc
     ; CHECK: liveins: $h0
     ; CHECK: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
-    ; CHECK: [[FRINTZHr:%[0-9]+]]:fpr16 = FRINTZHr [[COPY]]
+    ; CHECK: [[FRINTZHr:%[0-9]+]]:fpr16 = nofpexcept FRINTZHr [[COPY]]
     ; CHECK: $h0 = COPY [[FRINTZHr]]
     ; CHECK: RET_ReallyLR implicit $h0
     %0:fpr(s16) = COPY $h0
     %1:fpr(s16) = G_INTRINSIC_TRUNC %0
     $h0 = COPY %1(s16)
     RET_ReallyLR implicit $h0
 
 ...
 ---
 name:            test_v4f16.intrinsic_trunc
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 frameInfo:
   maxCallFrameSize: 0
 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $d0
 
     ; CHECK-LABEL: name: test_v4f16.intrinsic_trunc
     ; CHECK: liveins: $d0
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[FRINTZv4f16_:%[0-9]+]]:fpr64 = FRINTZv4f16 [[COPY]]
+    ; CHECK: [[FRINTZv4f16_:%[0-9]+]]:fpr64 = nofpexcept FRINTZv4f16 [[COPY]]
     ; CHECK: $d0 = COPY [[FRINTZv4f16_]]
     ; CHECK: RET_ReallyLR implicit $d0
     %0:fpr(<4 x s16>) = COPY $d0
     %1:fpr(<4 x s16>) = G_INTRINSIC_TRUNC %0
     $d0 = COPY %1(<4 x s16>)
     RET_ReallyLR implicit $d0
 
 ...
 ---
 name:            test_v8f16.intrinsic_trunc
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 frameInfo:
   maxCallFrameSize: 0
 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $q0
 
     ; CHECK-LABEL: name: test_v8f16.intrinsic_trunc
     ; CHECK: liveins: $q0
     ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[FRINTZv8f16_:%[0-9]+]]:fpr128 = FRINTZv8f16 [[COPY]]
+    ; CHECK: [[FRINTZv8f16_:%[0-9]+]]:fpr128 = nofpexcept FRINTZv8f16 [[COPY]]
     ; CHECK: $q0 = COPY [[FRINTZv8f16_]]
     ; CHECK: RET_ReallyLR implicit $q0
     %0:fpr(<8 x s16>) = COPY $q0
     %1:fpr(<8 x s16>) = G_INTRINSIC_TRUNC %0
     $q0 = COPY %1(<8 x s16>)
     RET_ReallyLR implicit $q0
 
 ...
 ---
 name:            test_v2f32.intrinsic_trunc
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 frameInfo:
   maxCallFrameSize: 0
 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $d0
 
     ; CHECK-LABEL: name: test_v2f32.intrinsic_trunc
     ; CHECK: liveins: $d0
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[FRINTZv2f32_:%[0-9]+]]:fpr64 = FRINTZv2f32 [[COPY]]
+    ; CHECK: [[FRINTZv2f32_:%[0-9]+]]:fpr64 = nofpexcept FRINTZv2f32 [[COPY]]
     ; CHECK: $d0 = COPY [[FRINTZv2f32_]]
     ; CHECK: RET_ReallyLR implicit $d0
     %0:fpr(<2 x s32>) = COPY $d0
     %1:fpr(<2 x s32>) = G_INTRINSIC_TRUNC %0
     $d0 = COPY %1(<2 x s32>)
     RET_ReallyLR implicit $d0
 
 ...
 ---
 name:            test_v4f32.intrinsic_trunc
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 frameInfo:
   maxCallFrameSize: 0
 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $q0
 
     ; CHECK-LABEL: name: test_v4f32.intrinsic_trunc
     ; CHECK: liveins: $q0
     ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[FRINTZv4f32_:%[0-9]+]]:fpr128 = FRINTZv4f32 [[COPY]]
+    ; CHECK: [[FRINTZv4f32_:%[0-9]+]]:fpr128 = nofpexcept FRINTZv4f32 [[COPY]]
     ; CHECK: $q0 = COPY [[FRINTZv4f32_]]
     ; CHECK: RET_ReallyLR implicit $q0
     %0:fpr(<4 x s32>) = COPY $q0
     %1:fpr(<4 x s32>) = G_INTRINSIC_TRUNC %0
     $q0 = COPY %1(<4 x s32>)
     RET_ReallyLR implicit $q0
 
 ...
 ---
 name:            test_v2f64.intrinsic_trunc
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 frameInfo:
   maxCallFrameSize: 0
 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $q0
 
     ; CHECK-LABEL: name: test_v2f64.intrinsic_trunc
     ; CHECK: liveins: $q0
     ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[FRINTZv2f64_:%[0-9]+]]:fpr128 = FRINTZv2f64 [[COPY]]
+    ; CHECK: [[FRINTZv2f64_:%[0-9]+]]:fpr128 = nofpexcept FRINTZv2f64 [[COPY]]
     ; CHECK: $q0 = COPY [[FRINTZv2f64_]]
     ; CHECK: RET_ReallyLR implicit $q0
     %0:fpr(<2 x s64>) = COPY $q0
     %1:fpr(<2 x s64>) = G_INTRINSIC_TRUNC %0
     $q0 = COPY %1(<2 x s64>)
     RET_ReallyLR implicit $q0

llvm/test/CodeGen/AArch64/GlobalISel/select-nearbyint.mir

 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $d0
 
     ; CHECK-LABEL: name: test_v4f16.nearbyint
     ; CHECK: liveins: $d0
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[FRINTIv4f16_:%[0-9]+]]:fpr64 = FRINTIv4f16 [[COPY]]
+    ; CHECK: [[FRINTIv4f16_:%[0-9]+]]:fpr64 = nofpexcept FRINTIv4f16 [[COPY]]
     ; CHECK: $d0 = COPY [[FRINTIv4f16_]]
     ; CHECK: RET_ReallyLR implicit $d0
     %0:fpr(<4 x s16>) = COPY $d0
     %1:fpr(<4 x s16>) = G_FNEARBYINT %0
     $d0 = COPY %1(<4 x s16>)
     RET_ReallyLR implicit $d0
 
 ...
 ---
 name:            test_v8f16.nearbyint
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $q0
 
     ; CHECK-LABEL: name: test_v8f16.nearbyint
     ; CHECK: liveins: $q0
     ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[FRINTIv8f16_:%[0-9]+]]:fpr128 = FRINTIv8f16 [[COPY]]
+    ; CHECK: [[FRINTIv8f16_:%[0-9]+]]:fpr128 = nofpexcept FRINTIv8f16 [[COPY]]
     ; CHECK: $q0 = COPY [[FRINTIv8f16_]]
     ; CHECK: RET_ReallyLR implicit $q0
     %0:fpr(<8 x s16>) = COPY $q0
     %1:fpr(<8 x s16>) = G_FNEARBYINT %0
     $q0 = COPY %1(<8 x s16>)
     RET_ReallyLR implicit $q0
 
 ...
 ---
 name:            test_v2f32.nearbyint
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $d0
 
     ; CHECK-LABEL: name: test_v2f32.nearbyint
     ; CHECK: liveins: $d0
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[FRINTIv2f32_:%[0-9]+]]:fpr64 = FRINTIv2f32 [[COPY]]
+    ; CHECK: [[FRINTIv2f32_:%[0-9]+]]:fpr64 = nofpexcept FRINTIv2f32 [[COPY]]
     ; CHECK: $d0 = COPY [[FRINTIv2f32_]]
     ; CHECK: RET_ReallyLR implicit $d0
     %0:fpr(<2 x s32>) = COPY $d0
     %1:fpr(<2 x s32>) = G_FNEARBYINT %0
     $d0 = COPY %1(<2 x s32>)
     RET_ReallyLR implicit $d0
 
 ...
 ---
 name:            test_v2f64.nearbyint
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $q0
 
     ; CHECK-LABEL: name: test_v2f64.nearbyint
     ; CHECK: liveins: $q0
     ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[FRINTIv2f64_:%[0-9]+]]:fpr128 = FRINTIv2f64 [[COPY]]
+    ; CHECK: [[FRINTIv2f64_:%[0-9]+]]:fpr128 = nofpexcept FRINTIv2f64 [[COPY]]
     ; CHECK: $q0 = COPY [[FRINTIv2f64_]]
     ; CHECK: RET_ReallyLR implicit $q0
     %0:fpr(<2 x s64>) = COPY $q0
     %1:fpr(<2 x s64>) = G_FNEARBYINT %0
     $q0 = COPY %1(<2 x s64>)
     RET_ReallyLR implicit $q0
 
 ...
 ---
 name:            test_f32.nearbyint
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $s0
 
     ; CHECK-LABEL: name: test_f32.nearbyint
     ; CHECK: liveins: $s0
     ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
-    ; CHECK: [[FRINTISr:%[0-9]+]]:fpr32 = FRINTISr [[COPY]]
+    ; CHECK: [[FRINTISr:%[0-9]+]]:fpr32 = nofpexcept FRINTISr [[COPY]]
     ; CHECK: $s0 = COPY [[FRINTISr]]
     ; CHECK: RET_ReallyLR implicit $s0
     %0:fpr(s32) = COPY $s0
     %1:fpr(s32) = G_FNEARBYINT %0
     $s0 = COPY %1(s32)
     RET_ReallyLR implicit $s0
 
 ...
 ---
 name:            test_f64.nearbyint
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $d0
 
     ; CHECK-LABEL: name: test_f64.nearbyint
     ; CHECK: liveins: $d0
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[FRINTIDr:%[0-9]+]]:fpr64 = FRINTIDr [[COPY]]
+    ; CHECK: [[FRINTIDr:%[0-9]+]]:fpr64 = nofpexcept FRINTIDr [[COPY]]
     ; CHECK: $d0 = COPY [[FRINTIDr]]
     ; CHECK: RET_ReallyLR implicit $d0
     %0:fpr(s64) = COPY $d0
     %1:fpr(s64) = G_FNEARBYINT %0
     $d0 = COPY %1(s64)
     RET_ReallyLR implicit $d0
 
 ...
 ---
 name:            test_f16.nearbyint
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $h0
 
     ; CHECK-LABEL: name: test_f16.nearbyint
     ; CHECK: liveins: $h0
     ; CHECK: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
-    ; CHECK: [[FRINTIHr:%[0-9]+]]:fpr16 = FRINTIHr [[COPY]]
+    ; CHECK: [[FRINTIHr:%[0-9]+]]:fpr16 = nofpexcept FRINTIHr [[COPY]]
     ; CHECK: $h0 = COPY [[FRINTIHr]]
     ; CHECK: RET_ReallyLR implicit $h0
     %0:fpr(s16) = COPY $h0
     %1:fpr(s16) = G_FNEARBYINT %0
     $h0 = COPY %1(s16)
     RET_ReallyLR implicit $h0
 
 ...

llvm/test/CodeGen/AArch64/GlobalISel/select-neon-vector-fcmp.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=aarch64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
 
 ...
 ---
 name:            fcmeq
 alignment:       4
 legalized:       true
 regBankSelected: true
 body:             |
   bb.0:
     ; CHECK-LABEL: name: fcmeq
     ; CHECK: %lhs:fpr128 = COPY $q0
     ; CHECK: %rhs:fpr128 = COPY $q1
-    ; CHECK: %fcmp:fpr128 = FCMEQv2f64 %lhs, %rhs
+    ; CHECK: %fcmp:fpr128 = nofpexcept FCMEQv2f64 %lhs, %rhs
     ; CHECK: $q0 = COPY %fcmp
     ; CHECK: RET_ReallyLR implicit $q0
     %lhs:fpr(<2 x s64>) = COPY $q0
     %rhs:fpr(<2 x s64>) = COPY $q1
     %fcmp:fpr(<2 x s64>) = G_FCMEQ %lhs, %rhs(<2 x s64>)
     $q0 = COPY %fcmp(<2 x s64>)
     RET_ReallyLR implicit $q0
 
 ...
 ---
 name:            fcmge
 alignment:       4
 legalized:       true
 regBankSelected: true
 body:             |
   bb.0:
     ; CHECK-LABEL: name: fcmge
     ; CHECK: %lhs:fpr128 = COPY $q0
     ; CHECK: %rhs:fpr128 = COPY $q1
-    ; CHECK: %fcmp:fpr128 = FCMGEv2f64 %lhs, %rhs
+    ; CHECK: %fcmp:fpr128 = nofpexcept FCMGEv2f64 %lhs, %rhs
     ; CHECK: $q0 = COPY %fcmp
     ; CHECK: RET_ReallyLR implicit $q0
     %lhs:fpr(<2 x s64>) = COPY $q0
     %rhs:fpr(<2 x s64>) = COPY $q1
     %fcmp:fpr(<2 x s64>) = G_FCMGE %lhs, %rhs(<2 x s64>)
     $q0 = COPY %fcmp(<2 x s64>)
     RET_ReallyLR implicit $q0
 
 ...
 ---
 name:            fcmgt
 alignment:       4
 legalized:       true
 regBankSelected: true
 body:             |
   bb.0:
     ; CHECK-LABEL: name: fcmgt
     ; CHECK: %lhs:fpr128 = COPY $q0
     ; CHECK: %rhs:fpr128 = COPY $q1
-    ; CHECK: %fcmp:fpr128 = FCMGTv2f64 %lhs, %rhs
+    ; CHECK: %fcmp:fpr128 = nofpexcept FCMGTv2f64 %lhs, %rhs
     ; CHECK: $q0 = COPY %fcmp
     ; CHECK: RET_ReallyLR implicit $q0
     %lhs:fpr(<2 x s64>) = COPY $q0
     %rhs:fpr(<2 x s64>) = COPY $q1
     %fcmp:fpr(<2 x s64>) = G_FCMGT %lhs, %rhs(<2 x s64>)
     $q0 = COPY %fcmp(<2 x s64>)
     RET_ReallyLR implicit $q0
 
 ...
 ---
 name:            fcmeqz
 alignment:       4
 legalized:       true
 regBankSelected: true
 body:             |
   bb.0:
     ; CHECK-LABEL: name: fcmeqz
     ; CHECK: %lhs:fpr128 = COPY $q0
-    ; CHECK: %fcmp:fpr128 = FCMEQv2i64rz %lhs
+    ; CHECK: %fcmp:fpr128 = nofpexcept FCMEQv2i64rz %lhs
     ; CHECK: $q0 = COPY %fcmp
     ; CHECK: RET_ReallyLR implicit $q0
     %lhs:fpr(<2 x s64>) = COPY $q0
     %zero:gpr(s64) = G_CONSTANT i64 0
     %zero_vec:fpr(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
     %fcmp:fpr(<2 x s64>) = G_FCMEQZ %lhs
     $q0 = COPY %fcmp(<2 x s64>)
     RET_ReallyLR implicit $q0
 
 ...
 ---
 name:            fcmgez
 alignment:       4
 legalized:       true
 regBankSelected: true
 body:             |
   bb.0:
     ; CHECK-LABEL: name: fcmgez
     ; CHECK: %lhs:fpr128 = COPY $q0
-    ; CHECK: %fcmp:fpr128 = FCMGEv2i64rz %lhs
+    ; CHECK: %fcmp:fpr128 = nofpexcept FCMGEv2i64rz %lhs
     ; CHECK: $q0 = COPY %fcmp
     ; CHECK: RET_ReallyLR implicit $q0
     %lhs:fpr(<2 x s64>) = COPY $q0
     %zero:gpr(s64) = G_CONSTANT i64 0
     %zero_vec:fpr(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
     %fcmp:fpr(<2 x s64>) = G_FCMGEZ %lhs
     $q0 = COPY %fcmp(<2 x s64>)
     RET_ReallyLR implicit $q0
 
 ...
 ---
 name:            fcmgtz
 alignment:       4
 legalized:       true
 regBankSelected: true
 body:             |
   bb.0:
     ; CHECK-LABEL: name: fcmgtz
     ; CHECK: %lhs:fpr128 = COPY $q0
-    ; CHECK: %fcmp:fpr128 = FCMGTv2i64rz %lhs
+    ; CHECK: %fcmp:fpr128 = nofpexcept FCMGTv2i64rz %lhs
     ; CHECK: $q0 = COPY %fcmp
     ; CHECK: RET_ReallyLR implicit $q0
     %lhs:fpr(<2 x s64>) = COPY $q0
     %zero:gpr(s64) = G_CONSTANT i64 0
     %zero_vec:fpr(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
     %fcmp:fpr(<2 x s64>) = G_FCMGTZ %lhs
     $q0 = COPY %fcmp(<2 x s64>)
     RET_ReallyLR implicit $q0
 
 ...
 ---
 name:            fcmlez
 alignment:       4
 legalized:       true
 regBankSelected: true
 body:             |
   bb.0:
     ; CHECK-LABEL: name: fcmlez
     ; CHECK: %lhs:fpr128 = COPY $q0
-    ; CHECK: %fcmp:fpr128 = FCMLEv2i64rz %lhs
+    ; CHECK: %fcmp:fpr128 = nofpexcept FCMLEv2i64rz %lhs
     ; CHECK: $q0 = COPY %fcmp
     ; CHECK: RET_ReallyLR implicit $q0
     %lhs:fpr(<2 x s64>) = COPY $q0
     %zero:gpr(s64) = G_CONSTANT i64 0
     %zero_vec:fpr(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
     %fcmp:fpr(<2 x s64>) = G_FCMLEZ %lhs
     $q0 = COPY %fcmp(<2 x s64>)
     RET_ReallyLR implicit $q0
 
 ...
 ---
 name:            fcmltz
 alignment:       4
 legalized:       true
 regBankSelected: true
 body:             |
   bb.0:
     ; CHECK-LABEL: name: fcmltz
     ; CHECK: %lhs:fpr128 = COPY $q0
-    ; CHECK: %fcmp:fpr128 = FCMLTv2i64rz %lhs
+    ; CHECK: %fcmp:fpr128 = nofpexcept FCMLTv2i64rz %lhs
     ; CHECK: $q0 = COPY %fcmp
     ; CHECK: RET_ReallyLR implicit $q0
     %lhs:fpr(<2 x s64>) = COPY $q0
     %zero:gpr(s64) = G_CONSTANT i64 0
     %zero_vec:fpr(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
     %fcmp:fpr(<2 x s64>) = G_FCMLTZ %lhs
     $q0 = COPY %fcmp(<2 x s64>)
     RET_ReallyLR implicit $q0

llvm/test/CodeGen/AArch64/GlobalISel/select-sqrt.mir

 # RUN: llc -verify-machineinstrs -mtriple aarch64--- \
 # RUN: -run-pass=instruction-select -mattr=+fullfp16 -global-isel %s -o - \
 # RUN: | FileCheck %s
 ...
 ---
 name:            sqrt_float
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
 body:             |
   bb.0:
     ; CHECK-LABEL: name:            sqrt_float
-    ; CHECK: %{{[0-9]+}}:fpr32 = FSQRTSr %{{[0-9]+}}
+    ; CHECK: %{{[0-9]+}}:fpr32 = nofpexcept FSQRTSr %{{[0-9]+}}
     liveins: $s0
     %0:fpr(s32) = COPY $s0
     %1:fpr(s32) = G_FSQRT %0
     $s0 = COPY %1(s32)
 
 ...
 ---
 name:            sqrt_double
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
 body:             |
   bb.0:
     ; CHECK-LABEL: name:            sqrt_double
-    ; CHECK: %{{[0-9]+}}:fpr64 = FSQRTDr %{{[0-9]+}}
+    ; CHECK: %{{[0-9]+}}:fpr64 = nofpexcept FSQRTDr %{{[0-9]+}}
     liveins: $d0
     %0:fpr(s64) = COPY $d0
     %1:fpr(s64) = G_FSQRT %0
     $d0 = COPY %1(s64)
 
 ...
 ---
 name:            sqrt_v2f32
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
 body:             |
   bb.0:
     ; CHECK-LABEL: name:            sqrt_v2f32
-    ; CHECK: %{{[0-9]+}}:fpr64 = FSQRTv2f32 %{{[0-9]+}}
+    ; CHECK: %{{[0-9]+}}:fpr64 = nofpexcept FSQRTv2f32 %{{[0-9]+}}
     liveins: $d0
     %0:fpr(<2 x s32>) = COPY $d0
     %1:fpr(<2 x s32>) = G_FSQRT %0
     $d0 = COPY %1(<2 x s32>)
 
 ...
 ---
 name:            sqrt_v4f32
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
 body:             |
   bb.0:
     ; CHECK-LABEL: name:            sqrt_v4f32
-    ; CHECK: %{{[0-9]+}}:fpr128 = FSQRTv4f32 %{{[0-9]+}}
+    ; CHECK: %{{[0-9]+}}:fpr128 = nofpexcept FSQRTv4f32 %{{[0-9]+}}
     liveins: $q0
     %0:fpr(<4 x s32>) = COPY $q0
     %1:fpr(<4 x s32>) = G_FSQRT %0
     $q0 = COPY %1(<4 x s32>)
 
 ...
 ---
 name:            sqrt_v2f64
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
 body:             |
   bb.0:
     ; CHECK-LABEL: name:            sqrt_v2f64
-    ; CHECK: %{{[0-9]+}}:fpr128 = FSQRTv2f64 %{{[0-9]+}}
+    ; CHECK: %{{[0-9]+}}:fpr128 = nofpexcept FSQRTv2f64 %{{[0-9]+}}
     liveins: $q0
     %0:fpr(<2 x s64>) = COPY $q0
     %1:fpr(<2 x s64>) = G_FSQRT %0
     $q0 = COPY %1(<2 x s64>)
 
 ...
 ---
 name:            sqrt_v4f16
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
 body:             |
   bb.0:
     ; CHECK-LABEL: name:            sqrt_v4f16
-    ; CHECK: %{{[0-9]+}}:fpr64 = FSQRTv4f16 %{{[0-9]+}}
+    ; CHECK: %{{[0-9]+}}:fpr64 = nofpexcept FSQRTv4f16 %{{[0-9]+}}
     liveins: $d0
     %0:fpr(<4 x s16>) = COPY $d0
     %1:fpr(<4 x s16>) = G_FSQRT %0
     $d0 = COPY %1(<4 x s16>)
 
 ...
 ---
 name:            sqrt_v8f16
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
 body:             |
   bb.0:
     ; CHECK-LABEL: name:            sqrt_v8f16
-    ; CHECK: %{{[0-9]+}}:fpr128 = FSQRTv8f16 %{{[0-9]+}}
+    ; CHECK: %{{[0-9]+}}:fpr128 = nofpexcept FSQRTv8f16 %{{[0-9]+}}
     liveins: $q0
     %0:fpr(<8 x s16>) = COPY $q0
     %1:fpr(<8 x s16>) = G_FSQRT %0
     $q0 = COPY %1(<8 x s16>)
 
 ...

llvm/test/CodeGen/AArch64/GlobalISel/select-static.mir

registers:
   - { id: 2, class: fpr }
   - { id: 3, class: gpr }
   - { id: 4, class: gpr }
   - { id: 5, class: gpr }
   - { id: 6, class: gpr }
   - { id: 7, class: gpr }
 
 # CHECK:  body:
-# CHECK:    FCMPSrr %0, %0, implicit-def $nzcv
+# CHECK:    nofpexcept FCMPSrr %0, %0, implicit-def $nzcv
 # CHECK:    [[TST_MI:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 5, implicit $nzcv
 # CHECK:    [[TST_GT:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv
 # CHECK:    %1:gpr32 = ORRWrr [[TST_MI]], [[TST_GT]]
 
-# CHECK:    FCMPDrr %2, %2, implicit-def $nzcv
+# CHECK:    nofpexcept FCMPDrr %2, %2, implicit-def $nzcv
 # CHECK:    %3:gpr32 = CSINCWr $wzr, $wzr, 4, implicit $nzcv
 
 body:             |
   bb.0:
     liveins: $w0, $x0
 
     %0(s32) = COPY $s0
     %1(s32) = G_FCMP floatpred(one), %0, %0

llvm/test/CodeGen/AArch64/GlobalISel/select-with-no-legality-check.mir

body:             |
   bb.0.entry:
     liveins: $s0, $s1, $s2
 
     ; CHECK-LABEL: name: test_rule339_id2369_at_idx26608
     ; CHECK: liveins: $s0, $s1, $s2
     ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s2
     ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
     ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0
-    ; CHECK: [[FNMADDSrrr:%[0-9]+]]:fpr32 = FNMADDSrrr [[COPY1]], [[COPY2]], [[COPY]]
+    ; CHECK: [[FNMADDSrrr:%[0-9]+]]:fpr32 = nofpexcept FNMADDSrrr [[COPY1]], [[COPY2]], [[COPY]]
     ; CHECK: $noreg = PATCHABLE_RET [[FNMADDSrrr]]
     %5:fpr(s32) = COPY $s2
     %4:fpr(s32) = COPY $s1
     %3:fpr(s32) = COPY $s0
     %1:fpr(s32) = G_FNEG %5
     %0:fpr(s32) = G_FNEG %4
     %2:fpr(s32) = G_FMA %0, %3, %1
     $noreg = PATCHABLE_RET %2(s32)
body:             |
   bb.0.entry:
     liveins: $d0, $d1, $d2
 
     ; CHECK-LABEL: name: test_rule340_id2370_at_idx26714
     ; CHECK: liveins: $d0, $d1, $d2
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
     ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
     ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[FNMADDDrrr:%[0-9]+]]:fpr64 = FNMADDDrrr [[COPY1]], [[COPY2]], [[COPY]]
+    ; CHECK: [[FNMADDDrrr:%[0-9]+]]:fpr64 = nofpexcept FNMADDDrrr [[COPY1]], [[COPY2]], [[COPY]]
     ; CHECK: $noreg = PATCHABLE_RET [[FNMADDDrrr]]
     %5:fpr(s64) = COPY $d2
     %4:fpr(s64) = COPY $d1
     %3:fpr(s64) = COPY $d0
     %1:fpr(s64) = G_FNEG %5
     %0:fpr(s64) = G_FNEG %4
     %2:fpr(s64) = G_FMA %0, %3, %1
     $noreg = PATCHABLE_RET %2(s64)
body:             |
   bb.0.entry:
     liveins: $s0, $s1, $s2
 
     ; CHECK-LABEL: name: test_rule341_id2371_at_idx26820
     ; CHECK: liveins: $s0, $s1, $s2
     ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s2
     ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
     ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0
-    ; CHECK: [[FNMADDSrrr:%[0-9]+]]:fpr32 = FNMADDSrrr [[COPY1]], [[COPY2]], [[COPY]]
+    ; CHECK: [[FNMADDSrrr:%[0-9]+]]:fpr32 = nofpexcept FNMADDSrrr [[COPY1]], [[COPY2]], [[COPY]]
     ; CHECK: $noreg = PATCHABLE_RET [[FNMADDSrrr]]
     %5:fpr(s32) = COPY $s2
     %4:fpr(s32) = COPY $s1
     %3:fpr(s32) = COPY $s0
     %1:fpr(s32) = G_FNEG %5
     %0:fpr(s32) = G_FNEG %4
     %2:fpr(s32) = G_FMA %3, %0, %1
     $noreg = PATCHABLE_RET %2(s32)
body:             |
   bb.0.entry:
     liveins: $d0, $d1, $d2
 
     ; CHECK-LABEL: name: test_rule342_id2372_at_idx26926
     ; CHECK: liveins: $d0, $d1, $d2
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
     ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
     ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[FNMADDDrrr:%[0-9]+]]:fpr64 = FNMADDDrrr [[COPY1]], [[COPY2]], [[COPY]]
+    ; CHECK: [[FNMADDDrrr:%[0-9]+]]:fpr64 = nofpexcept FNMADDDrrr [[COPY1]], [[COPY2]], [[COPY]]
     ; CHECK: $noreg = PATCHABLE_RET [[FNMADDDrrr]]
     %5:fpr(s64) = COPY $d2
     %4:fpr(s64) = COPY $d1
     %3:fpr(s64) = COPY $d0
     %1:fpr(s64) = G_FNEG %5
     %0:fpr(s64) = G_FNEG %4
     %2:fpr(s64) = G_FMA %3, %0, %1
     $noreg = PATCHABLE_RET %2(s64)
body:             |
   bb.0.entry:
     liveins: $s0, $s1, $s2
 
     ; CHECK-LABEL: name: test_rule928_id2367_at_idx60019
     ; CHECK: liveins: $s0, $s1, $s2
     ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s2
     ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
     ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0
-    ; CHECK: [[FMSUBSrrr:%[0-9]+]]:fpr32 = FMSUBSrrr [[COPY]], [[COPY2]], [[COPY1]]
+    ; CHECK: [[FMSUBSrrr:%[0-9]+]]:fpr32 = nofpexcept FMSUBSrrr [[COPY]], [[COPY2]], [[COPY1]]
     ; CHECK: $noreg = PATCHABLE_RET [[FMSUBSrrr]]
     %4:fpr(s32) = COPY $s2
     %3:fpr(s32) = COPY $s1
     %2:fpr(s32) = COPY $s0
     %0:fpr(s32) = G_FNEG %4
     %1:fpr(s32) = G_FMA %0, %2, %3
     $noreg = PATCHABLE_RET %1(s32)
 
body:             |
   bb.0.entry:
     liveins: $d0, $d1, $d2
 
     ; CHECK-LABEL: name: test_rule929_id2368_at_idx60105
     ; CHECK: liveins: $d0, $d1, $d2
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
     ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
     ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[FMSUBDrrr:%[0-9]+]]:fpr64 = FMSUBDrrr [[COPY]], [[COPY2]], [[COPY1]]
+    ; CHECK: [[FMSUBDrrr:%[0-9]+]]:fpr64 = nofpexcept FMSUBDrrr [[COPY]], [[COPY2]], [[COPY1]]
     ; CHECK: $noreg = PATCHABLE_RET [[FMSUBDrrr]]
     %4:fpr(s64) = COPY $d2
     %3:fpr(s64) = COPY $d1
     %2:fpr(s64) = COPY $d0
     %0:fpr(s64) = G_FNEG %4
     %1:fpr(s64) = G_FMA %0, %2, %3
     $noreg = PATCHABLE_RET %1(s64)
 
body:             |
   bb.0.entry:
     liveins: $d0, $d1, $d2
 
     ; CHECK-LABEL: name: test_rule930_id2446_at_idx60191
     ; CHECK: liveins: $d0, $d1, $d2
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
     ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
     ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[FMLSv2f32_:%[0-9]+]]:fpr64 = FMLSv2f32 [[COPY1]], [[COPY2]], [[COPY]]
+    ; CHECK: [[FMLSv2f32_:%[0-9]+]]:fpr64 = nofpexcept FMLSv2f32 [[COPY1]], [[COPY2]], [[COPY]]
     ; CHECK: $noreg = PATCHABLE_RET [[FMLSv2f32_]]
     %4:fpr(<2 x s32>) = COPY $d2
     %3:fpr(<2 x s32>) = COPY $d1
     %2:fpr(<2 x s32>) = COPY $d0
     %0:fpr(<2 x s32>) = G_FNEG %4
     %1:fpr(<2 x s32>) = G_FMA %0, %2, %3
     $noreg = PATCHABLE_RET %1(<2 x s32>)
 
body:             |
   bb.0.entry:
     liveins: $q0, $q1, $q2
 
     ; CHECK-LABEL: name: test_rule931_id2447_at_idx60277
     ; CHECK: liveins: $q0, $q1, $q2
     ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
     ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
     ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[FMLSv4f32_:%[0-9]+]]:fpr128 = FMLSv4f32 [[COPY1]], [[COPY2]], [[COPY]]
+    ; CHECK: [[FMLSv4f32_:%[0-9]+]]:fpr128 = nofpexcept FMLSv4f32 [[COPY1]], [[COPY2]], [[COPY]]
     ; CHECK: $noreg = PATCHABLE_RET [[FMLSv4f32_]]
     %4:fpr(<4 x s32>) = COPY $q2
     %3:fpr(<4 x s32>) = COPY $q1
     %2:fpr(<4 x s32>) = COPY $q0
     %0:fpr(<4 x s32>) = G_FNEG %4
     %1:fpr(<4 x s32>) = G_FMA %0, %2, %3
     $noreg = PATCHABLE_RET %1(<4 x s32>)
 
body:             |
   bb.0.entry:
     liveins: $q0, $q1, $q2
 
     ; CHECK-LABEL: name: test_rule932_id2448_at_idx60363
     ; CHECK: liveins: $q0, $q1, $q2
     ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
     ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
     ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[FMLSv2f64_:%[0-9]+]]:fpr128 = FMLSv2f64 [[COPY1]], [[COPY2]], [[COPY]]
+    ; CHECK: [[FMLSv2f64_:%[0-9]+]]:fpr128 = nofpexcept FMLSv2f64 [[COPY1]], [[COPY2]], [[COPY]]
     ; CHECK: $noreg = PATCHABLE_RET [[FMLSv2f64_]]
     %4:fpr(<2 x s64>) = COPY $q2
     %3:fpr(<2 x s64>) = COPY $q1
     %2:fpr(<2 x s64>) = COPY $q0
     %0:fpr(<2 x s64>) = G_FNEG %4
     %1:fpr(<2 x s64>) = G_FMA %0, %2, %3
     $noreg = PATCHABLE_RET %1(<2 x s64>)
 
body:             |
   bb.0.entry:
     liveins: $s0, $s1, $s2
 
     ; CHECK-LABEL: name: test_rule934_id429_at_idx60537
     ; CHECK: liveins: $s0, $s1, $s2
     ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s2
     ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
     ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0
-    ; CHECK: [[FMSUBSrrr:%[0-9]+]]:fpr32 = FMSUBSrrr [[COPY2]], [[COPY]], [[COPY1]]
+    ; CHECK: [[FMSUBSrrr:%[0-9]+]]:fpr32 = nofpexcept FMSUBSrrr [[COPY2]], [[COPY]], [[COPY1]]
     ; CHECK: $noreg = PATCHABLE_RET [[FMSUBSrrr]]
     %4:fpr(s32) = COPY $s2
     %3:fpr(s32) = COPY $s1
     %2:fpr(s32) = COPY $s0
     %0:fpr(s32) = G_FNEG %4
     %1:fpr(s32) = G_FMA %2, %0, %3
     $noreg = PATCHABLE_RET %1(s32)
 
body:             |
   bb.0.entry:
     liveins: $d0, $d1, $d2
 
     ; CHECK-LABEL: name: test_rule935_id430_at_idx60625
     ; CHECK: liveins: $d0, $d1, $d2
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
     ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
     ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[FMSUBDrrr:%[0-9]+]]:fpr64 = FMSUBDrrr [[COPY2]], [[COPY]], [[COPY1]]
+    ; CHECK: [[FMSUBDrrr:%[0-9]+]]:fpr64 = nofpexcept FMSUBDrrr [[COPY2]], [[COPY]], [[COPY1]]
     ; CHECK: $noreg = PATCHABLE_RET [[FMSUBDrrr]]
     %4:fpr(s64) = COPY $d2
     %3:fpr(s64) = COPY $d1
     %2:fpr(s64) = COPY $d0
     %0:fpr(s64) = G_FNEG %4
     %1:fpr(s64) = G_FMA %2, %0, %3
     $noreg = PATCHABLE_RET %1(s64)
 
body:             |
   bb.0.entry:
     liveins: $d0, $d1, $d2
 
     ; CHECK-LABEL: name: test_rule938_id899_at_idx60889
     ; CHECK: liveins: $d0, $d1, $d2
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
     ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
     ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[FMLSv2f32_:%[0-9]+]]:fpr64 = FMLSv2f32 [[COPY1]], [[COPY2]], [[COPY]]
+    ; CHECK: [[FMLSv2f32_:%[0-9]+]]:fpr64 = nofpexcept FMLSv2f32 [[COPY1]], [[COPY2]], [[COPY]]
     ; CHECK: $noreg = PATCHABLE_RET [[FMLSv2f32_]]
     %4:fpr(<2 x s32>) = COPY $d2
     %3:fpr(<2 x s32>) = COPY $d1
     %2:fpr(<2 x s32>) = COPY $d0
     %0:fpr(<2 x s32>) = G_FNEG %4
     %1:fpr(<2 x s32>) = G_FMA %2, %0, %3
     $noreg = PATCHABLE_RET %1(<2 x s32>)
 
body:             |
   bb.0.entry:
     liveins: $q0, $q1, $q2
 
     ; CHECK-LABEL: name: test_rule939_id900_at_idx60977
     ; CHECK: liveins: $q0, $q1, $q2
     ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
     ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
     ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[FMLSv4f32_:%[0-9]+]]:fpr128 = FMLSv4f32 [[COPY1]], [[COPY2]], [[COPY]]
+    ; CHECK: [[FMLSv4f32_:%[0-9]+]]:fpr128 = nofpexcept FMLSv4f32 [[COPY1]], [[COPY2]], [[COPY]]
     ; CHECK: $noreg = PATCHABLE_RET [[FMLSv4f32_]]
     %4:fpr(<4 x s32>) = COPY $q2
     %3:fpr(<4 x s32>) = COPY $q1
     %2:fpr(<4 x s32>) = COPY $q0
     %0:fpr(<4 x s32>) = G_FNEG %4
     %1:fpr(<4 x s32>) = G_FMA %2, %0, %3
     $noreg = PATCHABLE_RET %1(<4 x s32>)
 
body:             |
   bb.0.entry:
     liveins: $q0, $q1, $q2
 
     ; CHECK-LABEL: name: test_rule940_id901_at_idx61065
     ; CHECK: liveins: $q0, $q1, $q2
     ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
     ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
     ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[FMLSv2f64_:%[0-9]+]]:fpr128 = FMLSv2f64 [[COPY1]], [[COPY2]], [[COPY]]
+    ; CHECK: [[FMLSv2f64_:%[0-9]+]]:fpr128 = nofpexcept FMLSv2f64 [[COPY1]], [[COPY2]], [[COPY]]
     ; CHECK: $noreg = PATCHABLE_RET [[FMLSv2f64_]]
     %4:fpr(<2 x s64>) = COPY $q2
     %3:fpr(<2 x s64>) = COPY $q1
     %2:fpr(<2 x s64>) = COPY $q0
     %0:fpr(<2 x s64>) = G_FNEG %4
     %1:fpr(<2 x s64>) = G_FMA %2, %0, %3
     $noreg = PATCHABLE_RET %1(<2 x s64>)
 
body:             |
   bb.0.entry:
     liveins: $s0, $s1, $s2
 
     ; CHECK-LABEL: name: test_rule942_id435_at_idx61241
     ; CHECK: liveins: $s0, $s1, $s2
     ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s2
     ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
     ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0
-    ; CHECK: [[FNMSUBSrrr:%[0-9]+]]:fpr32 = FNMSUBSrrr [[COPY2]], [[COPY1]], [[COPY]]
+    ; CHECK: [[FNMSUBSrrr:%[0-9]+]]:fpr32 = nofpexcept FNMSUBSrrr [[COPY2]], [[COPY1]], [[COPY]]
     ; CHECK: $noreg = PATCHABLE_RET [[FNMSUBSrrr]]
     %4:fpr(s32) = COPY $s2
     %3:fpr(s32) = COPY $s1
     %2:fpr(s32) = COPY $s0
     %0:fpr(s32) = G_FNEG %4
     %1:fpr(s32) = G_FMA %2, %3, %0
     $noreg = PATCHABLE_RET %1(s32)
 
body:             |
   bb.0.entry:
     liveins: $d0, $d1, $d2
 
     ; CHECK-LABEL: name: test_rule943_id436_at_idx61329
     ; CHECK: liveins: $d0, $d1, $d2
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
     ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
     ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[FNMSUBDrrr:%[0-9]+]]:fpr64 = FNMSUBDrrr [[COPY2]], [[COPY1]], [[COPY]]
+    ; CHECK: [[FNMSUBDrrr:%[0-9]+]]:fpr64 = nofpexcept FNMSUBDrrr [[COPY2]], [[COPY1]], [[COPY]]
     ; CHECK: $noreg = PATCHABLE_RET [[FNMSUBDrrr]]
     %4:fpr(s64) = COPY $d2
     %3:fpr(s64) = COPY $d1
     %2:fpr(s64) = COPY $d0
     %0:fpr(s64) = G_FNEG %4
     %1:fpr(s64) = G_FMA %2, %3, %0
     $noreg = PATCHABLE_RET %1(s64)
 
body:             |
   bb.0.entry:
     liveins: $s0, $s1, $s2
 
     ; CHECK-LABEL: name: test_rule990_id432_at_idx65123
     ; CHECK: liveins: $s0, $s1, $s2
     ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s2
     ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
     ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0
-    ; CHECK: [[FNMADDSrrr:%[0-9]+]]:fpr32 = FNMADDSrrr [[COPY2]], [[COPY1]], [[COPY]]
+    ; CHECK: [[FNMADDSrrr:%[0-9]+]]:fpr32 = nofpexcept FNMADDSrrr [[COPY2]], [[COPY1]], [[COPY]]
     ; CHECK: $noreg = PATCHABLE_RET [[FNMADDSrrr]]
     %4:fpr(s32) = COPY $s2
     %3:fpr(s32) = COPY $s1
     %2:fpr(s32) = COPY $s0
     %0:fpr(s32) = G_FMA %2, %3, %4
     %1:fpr(s32) = G_FNEG %0
     $noreg = PATCHABLE_RET %1(s32)
 
body:             |
   bb.0.entry:
     liveins: $d0, $d1, $d2
 
     ; CHECK-LABEL: name: test_rule991_id433_at_idx65211
     ; CHECK: liveins: $d0, $d1, $d2
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
     ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
     ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[FNMADDDrrr:%[0-9]+]]:fpr64 = FNMADDDrrr [[COPY2]], [[COPY1]], [[COPY]]
+    ; CHECK: [[FNMADDDrrr:%[0-9]+]]:fpr64 = nofpexcept FNMADDDrrr [[COPY2]], [[COPY1]], [[COPY]]
     ; CHECK: $noreg = PATCHABLE_RET [[FNMADDDrrr]]
     %4:fpr(s64) = COPY $d2
     %3:fpr(s64) = COPY $d1
     %2:fpr(s64) = COPY $d0
     %0:fpr(s64) = G_FMA %2, %3, %4
     %1:fpr(s64) = G_FNEG %0
     $noreg = PATCHABLE_RET %1(s64)
 

 body:             |
   bb.0.entry:
     liveins: $s0, $s1
 
     ; CHECK-LABEL: name: test_rule993_id420_at_idx65375
     ; CHECK: liveins: $s0, $s1
     ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s1
     ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0
-    ; CHECK: [[FNMULSrr:%[0-9]+]]:fpr32 = FNMULSrr [[COPY1]], [[COPY]]
+    ; CHECK: [[FNMULSrr:%[0-9]+]]:fpr32 = nofpexcept FNMULSrr [[COPY1]], [[COPY]]
     ; CHECK: $noreg = PATCHABLE_RET [[FNMULSrr]]
     %3:fpr(s32) = COPY $s1
     %2:fpr(s32) = COPY $s0
     %0:fpr(s32) = G_FMUL %2, %3
     %1:fpr(s32) = G_FNEG %0
     $noreg = PATCHABLE_RET %1(s32)
 
 ...

 body:             |
   bb.0.entry:
     liveins: $d0, $d1
 
     ; CHECK-LABEL: name: test_rule994_id421_at_idx65451
     ; CHECK: liveins: $d0, $d1
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
     ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[FNMULDrr:%[0-9]+]]:fpr64 = FNMULDrr [[COPY1]], [[COPY]]
+    ; CHECK: [[FNMULDrr:%[0-9]+]]:fpr64 = nofpexcept FNMULDrr [[COPY1]], [[COPY]]
     ; CHECK: $noreg = PATCHABLE_RET [[FNMULDrr]]
     %3:fpr(s64) = COPY $d1
     %2:fpr(s64) = COPY $d0
     %0:fpr(s64) = G_FMUL %2, %3
     %1:fpr(s64) = G_FNEG %0
     $noreg = PATCHABLE_RET %1(s64)
 
 ...
body:             |
   bb.0.entry:
     liveins: $d0, $d1, $d2
 
     ; CHECK-LABEL: name: test_rule1239_id894_at_idx82201
     ; CHECK: liveins: $d0, $d1, $d2
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
     ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
     ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[FMLAv2f32_:%[0-9]+]]:fpr64 = FMLAv2f32 [[COPY]], [[COPY1]], [[COPY2]]
+    ; CHECK: [[FMLAv2f32_:%[0-9]+]]:fpr64 = nofpexcept FMLAv2f32 [[COPY]], [[COPY1]], [[COPY2]]
     ; CHECK: $noreg = PATCHABLE_RET [[FMLAv2f32_]]
     %3:fpr(<2 x s32>) = COPY $d2
     %2:fpr(<2 x s32>) = COPY $d1
     %1:fpr(<2 x s32>) = COPY $d0
     %0:fpr(<2 x s32>) = G_FMA %1, %2, %3
     $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
body:             |
   bb.0.entry:
     liveins: $q0, $q1, $q2
 
     ; CHECK-LABEL: name: test_rule1240_id895_at_idx82269
     ; CHECK: liveins: $q0, $q1, $q2
     ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
     ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
     ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[FMLAv4f32_:%[0-9]+]]:fpr128 = FMLAv4f32 [[COPY]], [[COPY1]], [[COPY2]]
+    ; CHECK: [[FMLAv4f32_:%[0-9]+]]:fpr128 = nofpexcept FMLAv4f32 [[COPY]], [[COPY1]], [[COPY2]]
     ; CHECK: $noreg = PATCHABLE_RET [[FMLAv4f32_]]
     %3:fpr(<4 x s32>) = COPY $q2
     %2:fpr(<4 x s32>) = COPY $q1
     %1:fpr(<4 x s32>) = COPY $q0
     %0:fpr(<4 x s32>) = G_FMA %1, %2, %3
     $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
body:             |
   bb.0.entry:
     liveins: $q0, $q1, $q2
 
     ; CHECK-LABEL: name: test_rule1241_id896_at_idx82337
     ; CHECK: liveins: $q0, $q1, $q2
     ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
     ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
     ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[FMLAv2f64_:%[0-9]+]]:fpr128 = FMLAv2f64 [[COPY]], [[COPY1]], [[COPY2]]
+    ; CHECK: [[FMLAv2f64_:%[0-9]+]]:fpr128 = nofpexcept FMLAv2f64 [[COPY]], [[COPY1]], [[COPY2]]
     ; CHECK: $noreg = PATCHABLE_RET [[FMLAv2f64_]]
     %3:fpr(<2 x s64>) = COPY $q2
     %2:fpr(<2 x s64>) = COPY $q1
     %1:fpr(<2 x s64>) = COPY $q0
     %0:fpr(<2 x s64>) = G_FMA %1, %2, %3
     $noreg = PATCHABLE_RET %0(<2 x s64>)
 
 ...

 body:             |
   bb.0.entry:
     liveins: $d0, $d1
 
     ; CHECK-LABEL: name: test_rule1268_id829_at_idx83513
     ; CHECK: liveins: $d0, $d1
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
     ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[FADDv2f32_:%[0-9]+]]:fpr64 = FADDv2f32 [[COPY1]], [[COPY]]
+    ; CHECK: [[FADDv2f32_:%[0-9]+]]:fpr64 = nofpexcept FADDv2f32 [[COPY1]], [[COPY]]
     ; CHECK: $noreg = PATCHABLE_RET [[FADDv2f32_]]
     %2:fpr(<2 x s32>) = COPY $d1
     %1:fpr(<2 x s32>) = COPY $d0
     %0:fpr(<2 x s32>) = G_FADD %1, %2
     $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---

 body:             |
   bb.0.entry:
     liveins: $q0, $q1
 
     ; CHECK-LABEL: name: test_rule1269_id830_at_idx83556
     ; CHECK: liveins: $q0, $q1
     ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
     ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[FADDv4f32_:%[0-9]+]]:fpr128 = FADDv4f32 [[COPY1]], [[COPY]]
+    ; CHECK: [[FADDv4f32_:%[0-9]+]]:fpr128 = nofpexcept FADDv4f32 [[COPY1]], [[COPY]]
     ; CHECK: $noreg = PATCHABLE_RET [[FADDv4f32_]]
     %2:fpr(<4 x s32>) = COPY $q1
     %1:fpr(<4 x s32>) = COPY $q0
     %0:fpr(<4 x s32>) = G_FADD %1, %2
     $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---

 body:             |
   bb.0.entry:
     liveins: $q0, $q1
 
     ; CHECK-LABEL: name: test_rule1270_id831_at_idx83599
     ; CHECK: liveins: $q0, $q1
     ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
     ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[FADDv2f64_:%[0-9]+]]:fpr128 = FADDv2f64 [[COPY1]], [[COPY]]
+    ; CHECK: [[FADDv2f64_:%[0-9]+]]:fpr128 = nofpexcept FADDv2f64 [[COPY1]], [[COPY]]
     ; CHECK: $noreg = PATCHABLE_RET [[FADDv2f64_]]
     %2:fpr(<2 x s64>) = COPY $q1
     %1:fpr(<2 x s64>) = COPY $q0
     %0:fpr(<2 x s64>) = G_FADD %1, %2
     $noreg = PATCHABLE_RET %0(<2 x s64>)
 
 ...
 ---

 body:             |
   bb.0.entry:
     liveins: $d0, $d1
 
     ; CHECK-LABEL: name: test_rule1276_id849_at_idx83857
     ; CHECK: liveins: $d0, $d1
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
     ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[FDIVv2f32_:%[0-9]+]]:fpr64 = FDIVv2f32 [[COPY1]], [[COPY]]
+    ; CHECK: [[FDIVv2f32_:%[0-9]+]]:fpr64 = nofpexcept FDIVv2f32 [[COPY1]], [[COPY]]
     ; CHECK: $noreg = PATCHABLE_RET [[FDIVv2f32_]]
     %2:fpr(<2 x s32>) = COPY $d1
     %1:fpr(<2 x s32>) = COPY $d0
     %0:fpr(<2 x s32>) = G_FDIV %1, %2
     $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---

 body:             |
   bb.0.entry:
     liveins: $q0, $q1
 
     ; CHECK-LABEL: name: test_rule1277_id850_at_idx83900
     ; CHECK: liveins: $q0, $q1
     ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
     ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[FDIVv4f32_:%[0-9]+]]:fpr128 = FDIVv4f32 [[COPY1]], [[COPY]]
+    ; CHECK: [[FDIVv4f32_:%[0-9]+]]:fpr128 = nofpexcept FDIVv4f32 [[COPY1]], [[COPY]]
     ; CHECK: $noreg = PATCHABLE_RET [[FDIVv4f32_]]
     %2:fpr(<4 x s32>) = COPY $q1
     %1:fpr(<4 x s32>) = COPY $q0
     %0:fpr(<4 x s32>) = G_FDIV %1, %2
     $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---

 body:             |
   bb.0.entry:
     liveins: $q0, $q1
 
     ; CHECK-LABEL: name: test_rule1278_id851_at_idx83943
     ; CHECK: liveins: $q0, $q1
     ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
     ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[FDIVv2f64_:%[0-9]+]]:fpr128 = FDIVv2f64 [[COPY1]], [[COPY]]
+    ; CHECK: [[FDIVv2f64_:%[0-9]+]]:fpr128 = nofpexcept FDIVv2f64 [[COPY1]], [[COPY]]
     ; CHECK: $noreg = PATCHABLE_RET [[FDIVv2f64_]]
     %2:fpr(<2 x s64>) = COPY $q1
     %1:fpr(<2 x s64>) = COPY $q0
     %0:fpr(<2 x s64>) = G_FDIV %1, %2
     $noreg = PATCHABLE_RET %0(<2 x s64>)
 
 ...
 ---

 body:             |
   bb.0.entry:
     liveins: $d0, $d1
 
     ; CHECK-LABEL: name: test_rule1284_id909_at_idx84201
     ; CHECK: liveins: $d0, $d1
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
     ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[FMULv2f32_:%[0-9]+]]:fpr64 = FMULv2f32 [[COPY1]], [[COPY]]
+    ; CHECK: [[FMULv2f32_:%[0-9]+]]:fpr64 = nofpexcept FMULv2f32 [[COPY1]], [[COPY]]
     ; CHECK: $noreg = PATCHABLE_RET [[FMULv2f32_]]
     %2:fpr(<2 x s32>) = COPY $d1
     %1:fpr(<2 x s32>) = COPY $d0
     %0:fpr(<2 x s32>) = G_FMUL %1, %2
     $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---

 body:             |
   bb.0.entry:
     liveins: $q0, $q1
 
     ; CHECK-LABEL: name: test_rule1285_id910_at_idx84244
     ; CHECK: liveins: $q0, $q1
     ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
     ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[FMULv4f32_:%[0-9]+]]:fpr128 = FMULv4f32 [[COPY1]], [[COPY]]
+    ; CHECK: [[FMULv4f32_:%[0-9]+]]:fpr128 = nofpexcept FMULv4f32 [[COPY1]], [[COPY]]
     ; CHECK: $noreg = PATCHABLE_RET [[FMULv4f32_]]
     %2:fpr(<4 x s32>) = COPY $q1
     %1:fpr(<4 x s32>) = COPY $q0
     %0:fpr(<4 x s32>) = G_FMUL %1, %2
     $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---

 body:             |
   bb.0.entry:
     liveins: $q0, $q1
 
     ; CHECK-LABEL: name: test_rule1286_id911_at_idx84287
     ; CHECK: liveins: $q0, $q1
     ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
     ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[FMULv2f64_:%[0-9]+]]:fpr128 = FMULv2f64 [[COPY1]], [[COPY]]
+    ; CHECK: [[FMULv2f64_:%[0-9]+]]:fpr128 = nofpexcept FMULv2f64 [[COPY1]], [[COPY]]
     ; CHECK: $noreg = PATCHABLE_RET [[FMULv2f64_]]
     %2:fpr(<2 x s64>) = COPY $q1
     %1:fpr(<2 x s64>) = COPY $q0
     %0:fpr(<2 x s64>) = G_FMUL %1, %2
     $noreg = PATCHABLE_RET %0(<2 x s64>)
 
 ...
 ---

 body:             |
   bb.0.entry:
     liveins: $d0, $d1
 
     ; CHECK-LABEL: name: test_rule1292_id924_at_idx84545
     ; CHECK: liveins: $d0, $d1
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
     ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[FSUBv2f32_:%[0-9]+]]:fpr64 = FSUBv2f32 [[COPY1]], [[COPY]]
+    ; CHECK: [[FSUBv2f32_:%[0-9]+]]:fpr64 = nofpexcept FSUBv2f32 [[COPY1]], [[COPY]]
     ; CHECK: $noreg = PATCHABLE_RET [[FSUBv2f32_]]
     %2:fpr(<2 x s32>) = COPY $d1
     %1:fpr(<2 x s32>) = COPY $d0
     %0:fpr(<2 x s32>) = G_FSUB %1, %2
     $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---

 body:             |
   bb.0.entry:
     liveins: $q0, $q1
 
     ; CHECK-LABEL: name: test_rule1293_id925_at_idx84588
     ; CHECK: liveins: $q0, $q1
     ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
     ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[FSUBv4f32_:%[0-9]+]]:fpr128 = FSUBv4f32 [[COPY1]], [[COPY]]
+    ; CHECK: [[FSUBv4f32_:%[0-9]+]]:fpr128 = nofpexcept FSUBv4f32 [[COPY1]], [[COPY]]
     ; CHECK: $noreg = PATCHABLE_RET [[FSUBv4f32_]]
     %2:fpr(<4 x s32>) = COPY $q1
     %1:fpr(<4 x s32>) = COPY $q0
     %0:fpr(<4 x s32>) = G_FSUB %1, %2
     $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---

 body:             |
   bb.0.entry:
     liveins: $q0, $q1
 
     ; CHECK-LABEL: name: test_rule1294_id926_at_idx84631
     ; CHECK: liveins: $q0, $q1
     ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
     ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[FSUBv2f64_:%[0-9]+]]:fpr128 = FSUBv2f64 [[COPY1]], [[COPY]]
+    ; CHECK: [[FSUBv2f64_:%[0-9]+]]:fpr128 = nofpexcept FSUBv2f64 [[COPY1]], [[COPY]]
     ; CHECK: $noreg = PATCHABLE_RET [[FSUBv2f64_]]
     %2:fpr(<2 x s64>) = COPY $q1
     %1:fpr(<2 x s64>) = COPY $q0
     %0:fpr(<2 x s64>) = G_FSUB %1, %2
     $noreg = PATCHABLE_RET %0(<2 x s64>)
 
 ...
 ---
liveins:
   - { reg: '$d0', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
     liveins: $d0
 
     ; CHECK-LABEL: name: test_rule1592_id2383_at_idx97425
     ; CHECK: liveins: $d0
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[FCVTLv2i32_:%[0-9]+]]:fpr128 = FCVTLv2i32 [[COPY]]
+    ; CHECK: [[FCVTLv2i32_:%[0-9]+]]:fpr128 = nofpexcept FCVTLv2i32 [[COPY]]
     ; CHECK: $noreg = PATCHABLE_RET [[FCVTLv2i32_]]
     %1:fpr(<2 x s32>) = COPY $d0
     %0:fpr(<2 x s64>) = G_FPEXT %1(<2 x s32>)
     $noreg = PATCHABLE_RET %0(<2 x s64>)
 
 ...
 ---
 name:            test_rule1593_id2385_at_idx97458
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
 liveins:
   - { reg: '$d0', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
     liveins: $d0
 
     ; CHECK-LABEL: name: test_rule1593_id2385_at_idx97458
     ; CHECK: liveins: $d0
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[FCVTLv4i16_:%[0-9]+]]:fpr128 = FCVTLv4i16 [[COPY]]
+    ; CHECK: [[FCVTLv4i16_:%[0-9]+]]:fpr128 = nofpexcept FCVTLv4i16 [[COPY]]
     ; CHECK: $noreg = PATCHABLE_RET [[FCVTLv4i16_]]
     %1:fpr(<4 x s16>) = COPY $d0
     %0:fpr(<4 x s32>) = G_FPEXT %1(<4 x s16>)
     $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---
 name:            test_rule1602_id587_at_idx97771
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
 liveins:
   - { reg: '$d0', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
     liveins: $d0
 
     ; CHECK-LABEL: name: test_rule1602_id587_at_idx97771
     ; CHECK: liveins: $d0
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[FCVTZSv2f32_:%[0-9]+]]:fpr64 = FCVTZSv2f32 [[COPY]]
+    ; CHECK: [[FCVTZSv2f32_:%[0-9]+]]:fpr64 = nofpexcept FCVTZSv2f32 [[COPY]]
     ; CHECK: $noreg = PATCHABLE_RET [[FCVTZSv2f32_]]
     %1:fpr(<2 x s32>) = COPY $d0
     %0:fpr(<2 x s32>) = G_FPTOSI %1(<2 x s32>)
     $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
 name:            test_rule1603_id588_at_idx97806
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
 liveins:
   - { reg: '$q0', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
     liveins: $q0
 
     ; CHECK-LABEL: name: test_rule1603_id588_at_idx97806
     ; CHECK: liveins: $q0
     ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[FCVTZSv4f32_:%[0-9]+]]:fpr128 = FCVTZSv4f32 [[COPY]]
+    ; CHECK: [[FCVTZSv4f32_:%[0-9]+]]:fpr128 = nofpexcept FCVTZSv4f32 [[COPY]]
     ; CHECK: $noreg = PATCHABLE_RET [[FCVTZSv4f32_]]
     %1:fpr(<4 x s32>) = COPY $q0
     %0:fpr(<4 x s32>) = G_FPTOSI %1(<4 x s32>)
     $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---
 name:            test_rule1604_id589_at_idx97841
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
 liveins:
   - { reg: '$q0', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
     liveins: $q0
 
     ; CHECK-LABEL: name: test_rule1604_id589_at_idx97841
     ; CHECK: liveins: $q0
     ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[FCVTZSv2f64_:%[0-9]+]]:fpr128 = FCVTZSv2f64 [[COPY]]
+    ; CHECK: [[FCVTZSv2f64_:%[0-9]+]]:fpr128 = nofpexcept FCVTZSv2f64 [[COPY]]
     ; CHECK: $noreg = PATCHABLE_RET [[FCVTZSv2f64_]]
     %1:fpr(<2 x s64>) = COPY $q0
     %0:fpr(<2 x s64>) = G_FPTOSI %1(<2 x s64>)
     $noreg = PATCHABLE_RET %0(<2 x s64>)
 
 ...
 ---
 name:            test_rule1613_id592_at_idx98156
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
 liveins:
   - { reg: '$d0', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
     liveins: $d0
 
     ; CHECK-LABEL: name: test_rule1613_id592_at_idx98156
     ; CHECK: liveins: $d0
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[FCVTZUv2f32_:%[0-9]+]]:fpr64 = FCVTZUv2f32 [[COPY]]
+    ; CHECK: [[FCVTZUv2f32_:%[0-9]+]]:fpr64 = nofpexcept FCVTZUv2f32 [[COPY]]
     ; CHECK: $noreg = PATCHABLE_RET [[FCVTZUv2f32_]]
     %1:fpr(<2 x s32>) = COPY $d0
     %0:fpr(<2 x s32>) = G_FPTOUI %1(<2 x s32>)
     $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
 name:            test_rule1614_id593_at_idx98191
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
 liveins:
   - { reg: '$q0', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
     liveins: $q0
 
     ; CHECK-LABEL: name: test_rule1614_id593_at_idx98191
     ; CHECK: liveins: $q0
     ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[FCVTZUv4f32_:%[0-9]+]]:fpr128 = FCVTZUv4f32 [[COPY]]
+    ; CHECK: [[FCVTZUv4f32_:%[0-9]+]]:fpr128 = nofpexcept FCVTZUv4f32 [[COPY]]
     ; CHECK: $noreg = PATCHABLE_RET [[FCVTZUv4f32_]]
     %1:fpr(<4 x s32>) = COPY $q0
     %0:fpr(<4 x s32>) = G_FPTOUI %1(<4 x s32>)
     $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---
 name:            test_rule1615_id594_at_idx98226
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
 liveins:
   - { reg: '$q0', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
     liveins: $q0
 
     ; CHECK-LABEL: name: test_rule1615_id594_at_idx98226
     ; CHECK: liveins: $q0
     ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[FCVTZUv2f64_:%[0-9]+]]:fpr128 = FCVTZUv2f64 [[COPY]]
+    ; CHECK: [[FCVTZUv2f64_:%[0-9]+]]:fpr128 = nofpexcept FCVTZUv2f64 [[COPY]]
     ; CHECK: $noreg = PATCHABLE_RET [[FCVTZUv2f64_]]
     %1:fpr(<2 x s64>) = COPY $q0
     %0:fpr(<2 x s64>) = G_FPTOUI %1(<2 x s64>)
     $noreg = PATCHABLE_RET %0(<2 x s64>)
 
 ...
 ---
 name:            test_rule1619_id2389_at_idx98366
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
 liveins:
   - { reg: '$q0', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
     liveins: $q0
 
     ; CHECK-LABEL: name: test_rule1619_id2389_at_idx98366
     ; CHECK: liveins: $q0
     ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[FCVTNv2i32_:%[0-9]+]]:fpr64 = FCVTNv2i32 [[COPY]]
+    ; CHECK: [[FCVTNv2i32_:%[0-9]+]]:fpr64 = nofpexcept FCVTNv2i32 [[COPY]]
     ; CHECK: $noreg = PATCHABLE_RET [[FCVTNv2i32_]]
     %1:fpr(<2 x s64>) = COPY $q0
     %0:fpr(<2 x s32>) = G_FPTRUNC %1(<2 x s64>)
     $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
 name:            test_rule1620_id2390_at_idx98399
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
 liveins:
   - { reg: '$q0', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
     liveins: $q0
 
     ; CHECK-LABEL: name: test_rule1620_id2390_at_idx98399
     ; CHECK: liveins: $q0
     ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[FCVTNv4i16_:%[0-9]+]]:fpr64 = FCVTNv4i16 [[COPY]]
+    ; CHECK: [[FCVTNv4i16_:%[0-9]+]]:fpr64 = nofpexcept FCVTNv4i16 [[COPY]]
     ; CHECK: $noreg = PATCHABLE_RET [[FCVTNv4i16_]]
     %1:fpr(<4 x s32>) = COPY $q0
     %0:fpr(<4 x s16>) = G_FPTRUNC %1(<4 x s32>)
     $noreg = PATCHABLE_RET %0(<4 x s16>)
 
 ...
 ---
 name:            test_rule1621_id2923_at_idx98432
liveins:
   - { reg: '$d0', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
     liveins: $d0
 
     ; CHECK-LABEL: name: test_rule1632_id687_at_idx98847
     ; CHECK: liveins: $d0
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[SCVTFv2f32_:%[0-9]+]]:fpr64 = SCVTFv2f32 [[COPY]]
+    ; CHECK: [[SCVTFv2f32_:%[0-9]+]]:fpr64 = nofpexcept SCVTFv2f32 [[COPY]]
     ; CHECK: $noreg = PATCHABLE_RET [[SCVTFv2f32_]]
     %1:fpr(<2 x s32>) = COPY $d0
     %0:fpr(<2 x s32>) = G_SITOFP %1(<2 x s32>)
     $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
 name:            test_rule1633_id688_at_idx98882
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
 liveins:
   - { reg: '$q0', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
     liveins: $q0
 
     ; CHECK-LABEL: name: test_rule1633_id688_at_idx98882
     ; CHECK: liveins: $q0
     ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[SCVTFv4f32_:%[0-9]+]]:fpr128 = SCVTFv4f32 [[COPY]]
+    ; CHECK: [[SCVTFv4f32_:%[0-9]+]]:fpr128 = nofpexcept SCVTFv4f32 [[COPY]]
     ; CHECK: $noreg = PATCHABLE_RET [[SCVTFv4f32_]]
     %1:fpr(<4 x s32>) = COPY $q0
     %0:fpr(<4 x s32>) = G_SITOFP %1(<4 x s32>)
     $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---
 name:            test_rule1634_id689_at_idx98917
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
 liveins:
   - { reg: '$q0', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
     liveins: $q0
 
     ; CHECK-LABEL: name: test_rule1634_id689_at_idx98917
     ; CHECK: liveins: $q0
     ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[SCVTFv2f64_:%[0-9]+]]:fpr128 = SCVTFv2f64 [[COPY]]
+    ; CHECK: [[SCVTFv2f64_:%[0-9]+]]:fpr128 = nofpexcept SCVTFv2f64 [[COPY]]
     ; CHECK: $noreg = PATCHABLE_RET [[SCVTFv2f64_]]
     %1:fpr(<2 x s64>) = COPY $q0
     %0:fpr(<2 x s64>) = G_SITOFP %1(<2 x s64>)
     $noreg = PATCHABLE_RET %0(<2 x s64>)
 
 ...
 ---
 name:            test_rule1635_id748_at_idx98952
liveins:
   - { reg: '$d0', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
     liveins: $d0
 
     ; CHECK-LABEL: name: test_rule1647_id731_at_idx99386
     ; CHECK: liveins: $d0
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[UCVTFv2f32_:%[0-9]+]]:fpr64 = UCVTFv2f32 [[COPY]]
+    ; CHECK: [[UCVTFv2f32_:%[0-9]+]]:fpr64 = nofpexcept UCVTFv2f32 [[COPY]]
     ; CHECK: $noreg = PATCHABLE_RET [[UCVTFv2f32_]]
     %1:fpr(<2 x s32>) = COPY $d0
     %0:fpr(<2 x s32>) = G_UITOFP %1(<2 x s32>)
     $noreg = PATCHABLE_RET %0(<2 x s32>)
 
 ...
 ---
 name:            test_rule1648_id732_at_idx99421
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
 liveins:
   - { reg: '$q0', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
     liveins: $q0
 
     ; CHECK-LABEL: name: test_rule1648_id732_at_idx99421
     ; CHECK: liveins: $q0
     ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[UCVTFv4f32_:%[0-9]+]]:fpr128 = UCVTFv4f32 [[COPY]]
+    ; CHECK: [[UCVTFv4f32_:%[0-9]+]]:fpr128 = nofpexcept UCVTFv4f32 [[COPY]]
     ; CHECK: $noreg = PATCHABLE_RET [[UCVTFv4f32_]]
     %1:fpr(<4 x s32>) = COPY $q0
     %0:fpr(<4 x s32>) = G_UITOFP %1(<4 x s32>)
     $noreg = PATCHABLE_RET %0(<4 x s32>)
 
 ...
 ---
 name:            test_rule1649_id733_at_idx99456
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
 liveins:
   - { reg: '$q0', virtual-reg: '%1' }
 body:             |
   bb.0.entry:
     liveins: $q0
 
     ; CHECK-LABEL: name: test_rule1649_id733_at_idx99456
     ; CHECK: liveins: $q0
     ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[UCVTFv2f64_:%[0-9]+]]:fpr128 = UCVTFv2f64 [[COPY]]
+    ; CHECK: [[UCVTFv2f64_:%[0-9]+]]:fpr128 = nofpexcept UCVTFv2f64 [[COPY]]
     ; CHECK: $noreg = PATCHABLE_RET [[UCVTFv2f64_]]
     %1:fpr(<2 x s64>) = COPY $q0
     %0:fpr(<2 x s64>) = G_UITOFP %1(<2 x s64>)
     $noreg = PATCHABLE_RET %0(<2 x s64>)
 
 ...
 ---
 name:            test_rule1650_id2924_at_idx99491

llvm/test/CodeGen/AArch64/GlobalISel/select.mir

registers:
   - { id: 2, class: fpr }
   - { id: 3, class: gpr }
   - { id: 4, class: gpr }
   - { id: 5, class: gpr }
   - { id: 6, class: gpr }
   - { id: 7, class: gpr }
 
 # CHECK:  body:
-# CHECK:    FCMPSrr %0, %0, implicit-def $nzcv
+# CHECK:    nofpexcept FCMPSrr %0, %0, implicit-def $nzcv
 # CHECK:    [[TST_MI:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 5, implicit $nzcv
 # CHECK:    [[TST_GT:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv
 # CHECK:    %1:gpr32 = ORRWrr [[TST_MI]], [[TST_GT]]
 
-# CHECK:    FCMPDrr %2, %2, implicit-def $nzcv
+# CHECK:    nofpexcept FCMPDrr %2, %2, implicit-def $nzcv
 # CHECK:    %3:gpr32 = CSINCWr $wzr, $wzr, 4, implicit $nzcv
 
 body:             |
   bb.0:
     liveins: $w0, $x0
 
     %0(s32) = COPY $s0
     %1(s32) = G_FCMP floatpred(one), %0, %0

llvm/test/CodeGen/AArch64/strict-fp-opt.ll

+; RUN: llc -mtriple=aarch64-none-eabi %s -o - | FileCheck %s
+; RUN: llc -mtriple=aarch64-none-eabi -global-isel=true -global-isel-abort=2 %s -o - | FileCheck %s
+
+
+; Div whose result is unused should be removed unless we have strict exceptions
+
+; CHECK-LABEL: unused_div:
+; CHECK-NOT: fdiv
+; CHECK: ret
+define void @unused_div(float %x, float %y) #0 {
+entry:
+  %add = fdiv float %x, %y
+  ret void
+}
+
+; CHECK-LABEL: unused_div_fpexcept_strict:
+; CHECK: fdiv s0, s0, s1
+; CHECK-NEXT: ret
+define void @unused_div_fpexcept_strict(float %x, float %y) #0 {
+entry:
+  %add = call float @llvm.experimental.constrained.fdiv.f32(float %x, float %y, metadata !"round.tonearest", metadata !"fpexcept.strict") #0
+  ret void
+}
+
+
+; Machine CSE should eliminate the second add unless we have strict exceptions
+
+; CHECK-LABEL: add_twice:
+; CHECK: fadd [[ADD:s[0-9]+]], s0, s1
+; CHECK-NEXT: cmp w0, #0
+; CHECK-NEXT: fmul [[MUL:s[0-9]+]], [[ADD]], [[ADD]]
+; CHECK-NEXT: fcsel s0, [[ADD]], [[MUL]], eq
+; CHECK-NEXT: ret
+define float @add_twice(float %x, float %y, i32 %n) #0 {
+entry:
+  %add = fadd float %x, %y
+  %tobool.not = icmp eq i32 %n, 0
+  br i1 %tobool.not, label %if.end, label %if.then
+
+if.then:
+  %add1 = fadd float %x, %y
+  %mul = fmul float %add, %add1
+  br label %if.end
+
+if.end:
+  %a.0 = phi float [ %mul, %if.then ], [ %add, %entry ]
+  ret float %a.0
+}
+
+; CHECK-LABEL: add_twice_fpexcept_strict:
+; CHECK: fmov [[X:s[0-9]+]], s0
+; CHECK-NEXT: fadd s0, s0, s1
+; CHECK-NEXT: cbz w0, [[LABEL:.LBB[0-9_]+]]
+; CHECK: fadd [[ADD:s[0-9]+]], [[X]], s1
+; CHECK-NEXT: fmul s0, s0, [[ADD]]
+; CHECK: [[LABEL]]:
+; CHECK-NEXT: ret
+define float @add_twice_fpexcept_strict(float %x, float %y, i32 %n) #0 {
+entry:
+  %add = call float @llvm.experimental.constrained.fadd.f32(float %x, float %y, metadata !"round.tonearest", metadata !"fpexcept.strict") #0
+  %tobool.not = icmp eq i32 %n, 0
+  br i1 %tobool.not, label %if.end, label %if.then
+
+if.then:
+  %add1 = call float @llvm.experimental.constrained.fadd.f32(float %x, float %y, metadata !"round.tonearest", metadata !"fpexcept.strict") #0
+  %mul = call float @llvm.experimental.constrained.fmul.f32(float %add, float %add1, metadata !"round.tonearest", metadata !"fpexcept.strict") #0
+  br label %if.end
+
+if.end:
+  %a.0 = phi float [ %mul, %if.then ], [ %add, %entry ]
+  ret float %a.0
+}
+
+declare float @llvm.experimental.constrained.fadd.f32(float, float, metadata, metadata) #0
+declare float @llvm.experimental.constrained.fmul.f32(float, float, metadata, metadata) #0
+declare float @llvm.experimental.constrained.fdiv.f32(float, float, metadata, metadata) #0
+
+attributes #0 = { "strictfp" }