[AArch64] Mark all instructions that read/write FPCR as doing so

[john.brawn]

Summary

All instructions that can raise fp exceptions also read FPCR, with the only other instructions that interact with it being the MSR/MRS to write/read FPCR.

Introducing an FPCR register also requires adjusting invalidateWindowsRegisterPairing in AArch64FrameLowering.cpp to use the encoded value of registers instead of their enum value, as the enum value is based on the alphabetical order of register names and now FPCR is placed between FP and LR.

This change unfortunately means a large number of mir tests need to be adjusted due to instructions now requiring an implicit fpcr operand to be present.

[simon_tatham]

llvm/lib/Target/AArch64/AArch64FrameLowering.cpp

2473

I don't know this code well, but just looking at this if statement in isolation, in the case where Reg1==FP, the previous version of the condition would have required Reg2==LR, whereas this one will accept either Reg2==LR or Reg2=FPCR.

Or is there some condition at the call sites which means nothing but GPRs will ever be passed to this function in the first place, so that the (FP,FPCR) pair will never trigger that false positive?

[john.brawn]

This is interacting badly with MachineCSE, as the presence of a physical register prevents it from optimising in some cases. I think the fix is in MachineCSE, but removing this patch from review while I look at it.

[john.brawn]

Rebased. Also adjust invalidateWindowsRegisterPairing to use encoded register numbers which should be more robust.

[john.brawn]

Rebased again.

[john.brawn]

Ping.

llvm/lib/Target/AArch64/AArch64FrameLowering.cpp

static bool produceCompactUnwindFrame(MachineFunction &MF) {
   AttributeList Attrs = MF.getFunction().getAttributes();
   return Subtarget.isTargetMachO() &&
          !(Subtarget.getTargetLowering()->supportSwiftError() &&
            Attrs.hasAttrSomewhere(Attribute::SwiftError)) &&
          MF.getFunction().getCallingConv() != CallingConv::SwiftTail;
 }
 
 static bool invalidateWindowsRegisterPairing(unsigned Reg1, unsigned Reg2,
-                                             bool NeedsWinCFI, bool IsFirst) {
+                                             bool NeedsWinCFI, bool IsFirst,
+                                             const TargetRegisterInfo *TRI) {
   // If we are generating register pairs for a Windows function that requires
   // EH support, then pair consecutive registers only.  There are no unwind
   // opcodes for saves/restores of non-consectuve register pairs.
   // The unwind opcodes are save_regp, save_regp_x, save_fregp, save_frepg_x,
   // save_lrpair.
   // https://docs.microsoft.com/en-us/cpp/build/arm64-exception-handling
 
   if (Reg2 == AArch64::FP)
     return true;
   if (!NeedsWinCFI)
     return false;
-  if (Reg2 == Reg1 + 1)
+  if (TRI->getEncodingValue(Reg2) == TRI->getEncodingValue(Reg1) + 1)
     return false;
   // If pairing a GPR with LR, the pair can be described by the save_lrpair
   // opcode. If this is the first register pair, it would end up with a
   // predecrement, but there's no save_lrpair_x opcode, so we can only do this
   // if LR is paired with something else than the first register.
   // The save_lrpair opcode requires the first register to be an odd one.
   if (Reg1 >= AArch64::X19 && Reg1 <= AArch64::X27 &&
       (Reg1 - AArch64::X19) % 2 == 0 && Reg2 == AArch64::LR && !IsFirst)
     return false;
   return true;
 }
 
 /// Returns true if Reg1 and Reg2 cannot be paired using a ldp/stp instruction.
 /// WindowsCFI requires that only consecutive registers can be paired.
 /// LR and FP need to be allocated together when the frame needs to save
 /// the frame-record. This means any other register pairing with LR is invalid.
 static bool invalidateRegisterPairing(unsigned Reg1, unsigned Reg2,
                                       bool UsesWinAAPCS, bool NeedsWinCFI,
-                                      bool NeedsFrameRecord, bool IsFirst) {
+                                      bool NeedsFrameRecord, bool IsFirst,
+                                      const TargetRegisterInfo *TRI) {
   if (UsesWinAAPCS)
-    return invalidateWindowsRegisterPairing(Reg1, Reg2, NeedsWinCFI, IsFirst);
+    return invalidateWindowsRegisterPairing(Reg1, Reg2, NeedsWinCFI, IsFirst,
+                                            TRI);
 
   // If we need to store the frame record, don't pair any register
   // with LR other than FP.
   if (NeedsFrameRecord)
     return Reg2 == AArch64::LR;
 
   return false;
 }
for (unsigned i = FirstReg; i < Count; i += RegInc) {
     // Add the next reg to the pair if it is in the same register class.
     if (unsigned(i + RegInc) < Count) {
       Register NextReg = CSI[i + RegInc].getReg();
       bool IsFirst = i == FirstReg;
       switch (RPI.Type) {
       case RegPairInfo::GPR:
         if (AArch64::GPR64RegClass.contains(NextReg) &&
             !invalidateRegisterPairing(RPI.Reg1, NextReg, IsWindows,
-                                       NeedsWinCFI, NeedsFrameRecord, IsFirst))
+                                       NeedsWinCFI, NeedsFrameRecord, IsFirst,
+                                       TRI))
           RPI.Reg2 = NextReg;
         break;
       case RegPairInfo::FPR64:
         if (AArch64::FPR64RegClass.contains(NextReg) &&
             !invalidateWindowsRegisterPairing(RPI.Reg1, NextReg, NeedsWinCFI,
-                                              IsFirst))
+                                              IsFirst, TRI))
           RPI.Reg2 = NextReg;
         break;
       case RegPairInfo::FPR128:
         if (AArch64::FPR128RegClass.contains(NextReg))
           RPI.Reg2 = NextReg;
         break;
       case RegPairInfo::PPR:
       case RegPairInfo::ZPR:

llvm/lib/Target/AArch64/AArch64InstrFormats.td

 }
 }
 let Predicates = [HasFPARMv8] in {
 
 //---
 // Floating point to integer conversion
 //---
 
-let mayRaiseFPException = 1 in
+let mayRaiseFPException = 1, Uses = [FPCR] in
 class BaseFPToIntegerUnscaled<bits<2> type, bits<2> rmode, bits<3> opcode,
                       RegisterClass srcType, RegisterClass dstType,
                       string asm, list<dag> pattern>
     : I<(outs dstType:$Rd), (ins srcType:$Rn),
          asm, "\t$Rd, $Rn", "", pattern>,
       Sched<[WriteFCvt]> {
   bits<5> Rd;
   bits<5> Rn;
   let Inst{30-29} = 0b00;
   let Inst{28-24} = 0b11110;
   let Inst{23-22} = type;
   let Inst{21}    = 1;
   let Inst{20-19} = rmode;
   let Inst{18-16} = opcode;
   let Inst{15-10} = 0;
   let Inst{9-5}   = Rn;
   let Inst{4-0}   = Rd;
 }
 
-let mayLoad = 0, mayStore = 0, hasSideEffects = 0, mayRaiseFPException = 1 in
+let mayLoad = 0, mayStore = 0, hasSideEffects = 0, mayRaiseFPException = 1, Uses = [FPCR] in
 class BaseFPToInteger<bits<2> type, bits<2> rmode, bits<3> opcode,
                       RegisterClass srcType, RegisterClass dstType,
                       Operand immType, string asm, list<dag> pattern>
     : I<(outs dstType:$Rd), (ins srcType:$Rn, immType:$scale),
          asm, "\t$Rd, $Rn, $scale", "", pattern>,
       Sched<[WriteFCvt]> {
   bits<5> Rd;
   bits<5> Rn;
def SXDri : BaseFPToInteger<0b01, rmode, opcode, FPR64, GPR64,
     let Inst{31} = 1; // 64-bit GPR flag
   }
 }
 
 //---
 // Integer to floating point conversion
 //---
 
-let mayStore = 0, mayLoad = 0, hasSideEffects = 0, mayRaiseFPException = 1 in
+let mayStore = 0, mayLoad = 0, hasSideEffects = 0, mayRaiseFPException = 1, Uses = [FPCR] in
 class BaseIntegerToFP<bit isUnsigned,
                       RegisterClass srcType, RegisterClass dstType,
                       Operand immType, string asm, list<dag> pattern>
     : I<(outs dstType:$Rd), (ins srcType:$Rn, immType:$scale),
          asm, "\t$Rd, $Rn, $scale", "", pattern>,
       Sched<[WriteFCvt]> {
   bits<5> Rd;
   bits<5> Rn;
   bits<6> scale;
   let Inst{30-24} = 0b0011110;
   let Inst{21-17} = 0b00001;
   let Inst{16}    = isUnsigned;
   let Inst{15-10} = scale;
   let Inst{9-5}   = Rn;
   let Inst{4-0}   = Rd;
 }
 
-let mayRaiseFPException = 1 in
+let mayRaiseFPException = 1, Uses = [FPCR] in
 class BaseIntegerToFPUnscaled<bit isUnsigned,
                       RegisterClass srcType, RegisterClass dstType,
                       ValueType dvt, string asm, SDPatternOperator node>
     : I<(outs dstType:$Rd), (ins srcType:$Rn),
          asm, "\t$Rd, $Rn", "", [(set (dvt dstType:$Rd), (node srcType:$Rn))]>,
       Sched<[WriteFCvt]> {
   bits<5> Rd;
   bits<5> Rn;
def DXHighr : BaseUnscaledConversionFromHigh<0b01, 0b110, V128, GPR64,
     let Inst{22} = 0;
   }
 }
 
 //---
 // Floating point conversion
 //---
 
-let mayRaiseFPException = 1 in
+let mayRaiseFPException = 1, Uses = [FPCR] in
 class BaseFPConversion<bits<2> type, bits<2> opcode, RegisterClass dstType,
                        RegisterClass srcType, string asm, list<dag> pattern>
     : I<(outs dstType:$Rd), (ins srcType:$Rn), asm, "\t$Rd, $Rn", "", pattern>,
       Sched<[WriteFCvt]> {
   bits<5> Rd;
   bits<5> Rn;
   let Inst{31-24} = 0b00011110;
   let Inst{23-22} = type;
class BaseSingleOperandFPData<bits<6> opcode, RegisterClass regtype,
   let Inst{14-10} = 0b10000;
   let Inst{9-5}   = Rn;
   let Inst{4-0}   = Rd;
 }
 
 multiclass SingleOperandFPData<bits<4> opcode, string asm,
                                SDPatternOperator node = null_frag,
                                int fpexceptions = 1> {
-  let mayRaiseFPException = fpexceptions in {
+  let mayRaiseFPException = fpexceptions, Uses = !if(fpexceptions,[FPCR],[]<Register>) in {
   def Hr : BaseSingleOperandFPData<{0b00,opcode}, FPR16, f16, asm, node> {
     let Inst{23-22} = 0b11; // 16-bit size flag
     let Predicates = [HasFullFP16];
   }
 
   def Sr : BaseSingleOperandFPData<{0b00,opcode}, FPR32, f32, asm, node> {
     let Inst{23-22} = 0b00; // 32-bit size flag
   }
 
   def Dr : BaseSingleOperandFPData<{0b00,opcode}, FPR64, f64, asm, node> {
     let Inst{23-22} = 0b01; // 64-bit size flag
   }
   }
 }
 
 multiclass SingleOperandFPDataNoException<bits<4> opcode, string asm,
                                        SDPatternOperator node = null_frag>
     : SingleOperandFPData<opcode, asm, node, 0>;
 
-let mayRaiseFPException = 1 in
+let mayRaiseFPException = 1, Uses = [FPCR] in
 multiclass SingleOperandFPNo16<bits<6> opcode, string asm,
                   SDPatternOperator node = null_frag>{
 
   def Sr : BaseSingleOperandFPData<opcode, FPR32, f32, asm, node> {
     let Inst{23-22} = 0b00; // 32-bit registers
   }
 
   def Dr : BaseSingleOperandFPData<opcode, FPR64, f64, asm, node> {
     let Inst{23-22} = 0b01; // 64-bit registers
   }
 }
 
 // FRInt[32|64][Z|N] instructions
 multiclass FRIntNNT<bits<2> opcode, string asm, SDPatternOperator node = null_frag> :
       SingleOperandFPNo16<{0b0100,opcode}, asm, node>;
 
 //---
 // Two operand floating point data processing
 //---
 
-let mayLoad = 0, mayStore = 0, hasSideEffects = 0, mayRaiseFPException = 1 in
+let mayLoad = 0, mayStore = 0, hasSideEffects = 0, mayRaiseFPException = 1, Uses = [FPCR] in
 class BaseTwoOperandFPData<bits<4> opcode, RegisterClass regtype,
                            string asm, list<dag> pat>
     : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
          asm, "\t$Rd, $Rn, $Rm", "", pat>,
       Sched<[WriteF]> {
   bits<5> Rd;
   bits<5> Rn;
   bits<5> Rm;
multiclass TwoOperandFPDataNeg<bits<4> opcode, string asm,
   }
 }
 
 
 //---
 // Three operand floating point data processing
 //---
 
-let mayRaiseFPException = 1 in
+let mayRaiseFPException = 1, Uses = [FPCR] in
 class BaseThreeOperandFPData<bit isNegated, bit isSub,
                              RegisterClass regtype, string asm, list<dag> pat>
     : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, regtype: $Ra),
          asm, "\t$Rd, $Rn, $Rm, $Ra", "", pat>,
       Sched<[WriteFMul]> {
   bits<5> Rd;
   bits<5> Rn;
   bits<5> Rm;
def Drrr : BaseThreeOperandFPData<isNegated, isSub, FPR64, asm,
     let Inst{23-22} = 0b01; // 64-bit size flag
   }
 }
 
 //---
 // Floating point data comparisons
 //---
 
-let mayLoad = 0, mayStore = 0, hasSideEffects = 0, mayRaiseFPException = 1 in
+let mayLoad = 0, mayStore = 0, hasSideEffects = 0, mayRaiseFPException = 1, Uses = [FPCR] in
 class BaseOneOperandFPComparison<bit signalAllNans,
                                  RegisterClass regtype, string asm,
                                  list<dag> pat>
     : I<(outs), (ins regtype:$Rn), asm, "\t$Rn, #0.0", "", pat>,
       Sched<[WriteFCmp]> {
   bits<5> Rn;
   let Inst{31-24} = 0b00011110;
   let Inst{21}    = 1;
 
   let Inst{15-10} = 0b001000;
   let Inst{9-5}   = Rn;
   let Inst{4}     = signalAllNans;
   let Inst{3-0}   = 0b1000;
 
   // Rm should be 0b00000 canonically, but we need to accept any value.
   let PostEncoderMethod = "fixOneOperandFPComparison";
 }
 
-let mayLoad = 0, mayStore = 0, hasSideEffects = 0, mayRaiseFPException = 1 in
+let mayLoad = 0, mayStore = 0, hasSideEffects = 0, mayRaiseFPException = 1, Uses = [FPCR] in
 class BaseTwoOperandFPComparison<bit signalAllNans, RegisterClass regtype,
                                 string asm, list<dag> pat>
     : I<(outs), (ins regtype:$Rn, regtype:$Rm), asm, "\t$Rn, $Rm", "", pat>,
       Sched<[WriteFCmp]> {
   bits<5> Rm;
   bits<5> Rn;
   let Inst{31-24} = 0b00011110;
   let Inst{21}    = 1;
multiclass FPComparison<bit signalAllNans, string asm,
   }
   } // Defs = [NZCV]
 }
 
 //---
 // Floating point conditional comparisons
 //---
 
-let mayLoad = 0, mayStore = 0, hasSideEffects = 0, mayRaiseFPException = 1 in
+let mayLoad = 0, mayStore = 0, hasSideEffects = 0, mayRaiseFPException = 1, Uses = [FPCR] in
 class BaseFPCondComparison<bit signalAllNans, RegisterClass regtype,
                            string mnemonic, list<dag> pat>
     : I<(outs), (ins regtype:$Rn, regtype:$Rm, imm32_0_15:$nzcv, ccode:$cond),
          mnemonic, "\t$Rn, $Rm, $nzcv, $cond", "", pat>,
       Sched<[WriteFCmp]> {
   let Uses = [NZCV];
   let Defs = [NZCV];
 
def v8i8  : BaseSIMDThreeSameVector<0, U, 0b001, opc, V64,
     [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
   def v16i8 : BaseSIMDThreeSameVector<1, U, 0b001, opc, V128,
                                       asm, ".16b",
     [(set (v16i8 V128:$Rd),
           (OpNode (v16i8 V128:$Rn), (v16i8 V128:$Rm)))]>;
 }
 
 // As above, but only floating point elements supported.
-let mayRaiseFPException = 1 in
+let mayRaiseFPException = 1, Uses = [FPCR] in
 multiclass SIMDThreeSameVectorFP<bit U, bit S, bits<3> opc,
                                  string asm, SDPatternOperator OpNode> {
   let Predicates = [HasNEON, HasFullFP16] in {
   def v4f16 : BaseSIMDThreeSameVector<0, U, {S,0b10}, {0b00,opc}, V64,
                                       asm, ".4h",
         [(set (v4f16 V64:$Rd), (OpNode (v4f16 V64:$Rn), (v4f16 V64:$Rm)))]>;
   def v8f16 : BaseSIMDThreeSameVector<1, U, {S,0b10}, {0b00,opc}, V128,
                                       asm, ".8h",
         [(set (v8f16 V128:$Rd), (OpNode (v8f16 V128:$Rn), (v8f16 V128:$Rm)))]>;
   } // Predicates = [HasNEON, HasFullFP16]
   def v2f32 : BaseSIMDThreeSameVector<0, U, {S,0b01}, {0b11,opc}, V64,
                                       asm, ".2s",
         [(set (v2f32 V64:$Rd), (OpNode (v2f32 V64:$Rn), (v2f32 V64:$Rm)))]>;
   def v4f32 : BaseSIMDThreeSameVector<1, U, {S,0b01}, {0b11,opc}, V128,
                                       asm, ".4s",
         [(set (v4f32 V128:$Rd), (OpNode (v4f32 V128:$Rn), (v4f32 V128:$Rm)))]>;
   def v2f64 : BaseSIMDThreeSameVector<1, U, {S,0b11}, {0b11,opc}, V128,
                                       asm, ".2d",
         [(set (v2f64 V128:$Rd), (OpNode (v2f64 V128:$Rn), (v2f64 V128:$Rm)))]>;
 }
 
-let mayRaiseFPException = 1 in
+let mayRaiseFPException = 1, Uses = [FPCR] in
 multiclass SIMDThreeSameVectorFPCmp<bit U, bit S, bits<3> opc,
                                     string asm,
                                     SDPatternOperator OpNode> {
   let Predicates = [HasNEON, HasFullFP16] in {
   def v4f16 : BaseSIMDThreeSameVector<0, U, {S,0b10}, {0b00,opc}, V64,
                                       asm, ".4h",
         [(set (v4i16 V64:$Rd), (OpNode (v4f16 V64:$Rn), (v4f16 V64:$Rm)))]>;
   def v8f16 : BaseSIMDThreeSameVector<1, U, {S,0b10}, {0b00,opc}, V128,
                                       asm, ".8h",
         [(set (v8i16 V128:$Rd), (OpNode (v8f16 V128:$Rn), (v8f16 V128:$Rm)))]>;
   } // Predicates = [HasNEON, HasFullFP16]
   def v2f32 : BaseSIMDThreeSameVector<0, U, {S,0b01}, {0b11,opc}, V64,
                                       asm, ".2s",
         [(set (v2i32 V64:$Rd), (OpNode (v2f32 V64:$Rn), (v2f32 V64:$Rm)))]>;
   def v4f32 : BaseSIMDThreeSameVector<1, U, {S,0b01}, {0b11,opc}, V128,
                                       asm, ".4s",
         [(set (v4i32 V128:$Rd), (OpNode (v4f32 V128:$Rn), (v4f32 V128:$Rm)))]>;
   def v2f64 : BaseSIMDThreeSameVector<1, U, {S,0b11}, {0b11,opc}, V128,
                                       asm, ".2d",
         [(set (v2i64 V128:$Rd), (OpNode (v2f64 V128:$Rn), (v2f64 V128:$Rm)))]>;
 }
 
-let mayRaiseFPException = 1 in
+let mayRaiseFPException = 1, Uses = [FPCR] in
 multiclass SIMDThreeSameVectorFPTied<bit U, bit S, bits<3> opc,
                                  string asm, SDPatternOperator OpNode> {
   let Predicates = [HasNEON, HasFullFP16] in {
   def v4f16 : BaseSIMDThreeSameVectorTied<0, U, {S,0b10}, {0b00,opc}, V64,
                                       asm, ".4h",
      [(set (v4f16 V64:$dst),
            (OpNode (v4f16 V64:$Rd), (v4f16 V64:$Rn), (v4f16 V64:$Rm)))]>;
   def v8f16 : BaseSIMDThreeSameVectorTied<1, U, {S,0b10}, {0b00,opc}, V128,
[(set (v4f32 V128:$dst),
            (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn), (v4f32 V128:$Rm)))]>;
   def v2f64 : BaseSIMDThreeSameVectorTied<1, U, {S,0b11}, {0b11,opc}, V128,
                                       asm, ".2d",
      [(set (v2f64 V128:$dst),
            (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn), (v2f64 V128:$Rm)))]>;
 }
 
 // As above, but D and B sized elements unsupported.
-let mayRaiseFPException = 1 in
+let mayRaiseFPException = 1, Uses = [FPCR] in
 multiclass SIMDThreeSameVectorHS<bit U, bits<5> opc, string asm,
                                 SDPatternOperator OpNode> {
   def v4i16 : BaseSIMDThreeSameVector<0, U, 0b011, opc, V64,
                                       asm, ".4h",
         [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
   def v8i16 : BaseSIMDThreeSameVector<1, U, 0b011, opc, V128,
                                       asm, ".8h",
         [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
def v8i8  : BaseSIMDThreeSameVectorDot<0, U, Mixed, asm, ".2s", ".8b", V64,
                                          v2i32, v8i8, OpNode>;
   def v16i8 : BaseSIMDThreeSameVectorDot<1, U, Mixed, asm, ".4s", ".16b", V128,
                                          v4i32, v16i8, OpNode>;
 }
 
 // ARMv8.2-A Fused Multiply Add-Long Instructions (Vector): These instructions
 // select inputs from 4H vectors and accumulate outputs to a 2S vector (or from
 // 8H to 4S, when Q=1).
-let mayRaiseFPException = 1 in
+let mayRaiseFPException = 1, Uses = [FPCR] in
 class BaseSIMDThreeSameVectorFML<bit Q, bit U, bit b13, bits<3> size, string asm, string kind1,
                                  string kind2, RegisterOperand RegType,
                                  ValueType AccumType, ValueType InputType,
                                  SDPatternOperator OpNode> :
         BaseSIMDThreeSameVectorTied<Q, U, size, 0b11101, RegType, asm, kind1,
     [(set (AccumType RegType:$dst),
               (OpNode (AccumType RegType:$Rd),
                       (InputType RegType:$Rn),
def v8i16 : BaseSIMDTwoSameVector<1, U, 0b01, opc, 0b00, V128,
                     [(set (v8i16 V128:$Rd), (OpNode V128:$Rn))]>;
 }
 
 // Supports H, S and D element sizes, uses high bit of the size field
 // as an extra opcode bit.
 multiclass SIMDTwoVectorFP<bit U, bit S, bits<5> opc, string asm,
                            SDPatternOperator OpNode,
                            int fpexceptions = 1> {
-  let mayRaiseFPException = fpexceptions in {
+  let mayRaiseFPException = fpexceptions, Uses = !if(fpexceptions,[FPCR],[]<Register>) in {
   let Predicates = [HasNEON, HasFullFP16] in {
   def v4f16 : BaseSIMDTwoSameVector<0, U, {S,1}, opc, 0b11, V64,
                                 asm, ".4h", ".4h",
                           [(set (v4f16 V64:$Rd), (OpNode (v4f16 V64:$Rn)))]>;
   def v8f16 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, 0b11, V128,
                                 asm, ".8h", ".8h",
                           [(set (v8f16 V128:$Rd), (OpNode (v8f16 V128:$Rn)))]>;
   } // Predicates = [HasNEON, HasFullFP16]
multiclass SIMDTwoVectorFP<bit U, bit S, bits<5> opc, string asm,
   }
 }
 
 multiclass SIMDTwoVectorFPNoException<bit U, bit S, bits<5> opc, string asm,
                                       SDPatternOperator OpNode>
     : SIMDTwoVectorFP<U, S, opc, asm, OpNode, 0>;
 
 // Supports only S and D element sizes
-let mayRaiseFPException = 1 in
+let mayRaiseFPException = 1, Uses = [FPCR] in
 multiclass SIMDTwoVectorSD<bit U, bits<5> opc, string asm,
                            SDPatternOperator OpNode = null_frag> {
 
   def v2f32 : BaseSIMDTwoSameVector<0, U, 00, opc, 0b00, V64,
                                 asm, ".2s", ".2s",
                           [(set (v2f32 V64:$Rd), (OpNode (v2f32 V64:$Rn)))]>;
   def v4f32 : BaseSIMDTwoSameVector<1, U, 00, opc, 0b00, V128,
                                 asm, ".4s", ".4s",
multiclass SIMDTwoVectorS<bit U, bit S, bits<5> opc, string asm,
   def v2i32 : BaseSIMDTwoSameVector<0, U, {S,0}, opc, 0b00, V64,
                                 asm, ".2s", ".2s",
                           [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
   def v4i32 : BaseSIMDTwoSameVector<1, U, {S,0}, opc, 0b00, V128,
                                 asm, ".4s", ".4s",
                           [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
 }
 
-let mayRaiseFPException = 1 in
+let mayRaiseFPException = 1, Uses = [FPCR] in
 multiclass SIMDTwoVectorFPToInt<bit U, bit S, bits<5> opc, string asm,
                            SDPatternOperator OpNode> {
   let Predicates = [HasNEON, HasFullFP16] in {
   def v4f16 : BaseSIMDTwoSameVector<0, U, {S,1}, opc, 0b11, V64,
                                 asm, ".4h", ".4h",
                           [(set (v4i16 V64:$Rd), (OpNode (v4f16 V64:$Rn)))]>;
   def v8f16 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, 0b11, V128,
                                 asm, ".8h", ".8h",
                           [(set (v8i16 V128:$Rd), (OpNode (v8f16 V128:$Rn)))]>;
   } // Predicates = [HasNEON, HasFullFP16]
   def v2f32 : BaseSIMDTwoSameVector<0, U, {S,0}, opc, 0b00, V64,
                                 asm, ".2s", ".2s",
                           [(set (v2i32 V64:$Rd), (OpNode (v2f32 V64:$Rn)))]>;
   def v4f32 : BaseSIMDTwoSameVector<1, U, {S,0}, opc, 0b00, V128,
                                 asm, ".4s", ".4s",
                           [(set (v4i32 V128:$Rd), (OpNode (v4f32 V128:$Rn)))]>;
   def v2f64 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, 0b00, V128,
                                 asm, ".2d", ".2d",
                           [(set (v2i64 V128:$Rd), (OpNode (v2f64 V128:$Rn)))]>;
 }
 
-let mayRaiseFPException = 1 in
+let mayRaiseFPException = 1, Uses = [FPCR] in
 multiclass SIMDTwoVectorIntToFP<bit U, bit S, bits<5> opc, string asm,
                            SDPatternOperator OpNode> {
   let Predicates = [HasNEON, HasFullFP16] in {
   def v4f16 : BaseSIMDTwoSameVector<0, U, {S,1}, opc, 0b11, V64,
                                 asm, ".4h", ".4h",
                           [(set (v4f16 V64:$Rd), (OpNode (v4i16 V64:$Rn)))]>;
   def v8f16 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, 0b11, V128,
                                 asm, ".8h", ".8h",
def v2i64rz : BaseSIMDCmpTwoVector<1, U, 0b11, 0b00, opc, V128,
                                      asm, ".2d", "0",
                                      v2i64, v2i64, OpNode>;
 }
 
 // FP Comparisons support only S and D element sizes (and H for v8.2a).
 multiclass SIMDFPCmpTwoVector<bit U, bit S, bits<5> opc,
                               string asm, SDNode OpNode> {
 
-  let mayRaiseFPException = 1 in {
+  let mayRaiseFPException = 1, Uses = [FPCR] in {
   let Predicates = [HasNEON, HasFullFP16] in {
   def v4i16rz : BaseSIMDCmpTwoVector<0, U, {S,1}, 0b11, opc, V64,
                                      asm, ".4h", "0.0",
                                      v4i16, v4f16, OpNode>;
   def v8i16rz : BaseSIMDCmpTwoVector<1, U, {S,1}, 0b11, opc, V128,
                                      asm, ".8h", "0.0",
                                      v8i16, v8f16, OpNode>;
   } // Predicates = [HasNEON, HasFullFP16]
multiclass SIMDFPCmpTwoVector<bit U, bit S, bits<5> opc,
   def : InstAlias<asm # ".2s\t$Vd, $Vn, #0",
                   (!cast<Instruction>(NAME # v2i32rz) V64:$Vd, V64:$Vn), 0>;
   def : InstAlias<asm # ".4s\t$Vd, $Vn, #0",
                   (!cast<Instruction>(NAME # v4i32rz) V128:$Vd, V128:$Vn), 0>;
   def : InstAlias<asm # ".2d\t$Vd, $Vn, #0",
                   (!cast<Instruction>(NAME # v2i64rz) V128:$Vd, V128:$Vn), 0>;
 }
 
-let mayLoad = 0, mayStore = 0, hasSideEffects = 0, mayRaiseFPException = 1 in
+let mayLoad = 0, mayStore = 0, hasSideEffects = 0, mayRaiseFPException = 1, Uses = [FPCR] in
 class BaseSIMDFPCvtTwoVector<bit Q, bit U, bits<2> size, bits<5> opcode,
                              RegisterOperand outtype, RegisterOperand intype,
                              string asm, string VdTy, string VnTy,
                              list<dag> pattern>
   : I<(outs outtype:$Rd), (ins intype:$Rn), asm,
       !strconcat("\t$Rd", VdTy, ", $Rn", VnTy), "", pattern>,
     Sched<[WriteVq]> {
   bits<5> Rd;
   bits<5> Rn;
   let Inst{31}    = 0;
   let Inst{30}    = Q;
   let Inst{29}    = U;
   let Inst{28-24} = 0b01110;
   let Inst{23-22} = size;
   let Inst{21-17} = 0b10000;
   let Inst{16-12} = opcode;
   let Inst{11-10} = 0b10;
   let Inst{9-5}   = Rn;
   let Inst{4-0}   = Rd;
 }
 
-let mayLoad = 0, mayStore = 0, hasSideEffects = 0, mayRaiseFPException = 1 in
+let mayLoad = 0, mayStore = 0, hasSideEffects = 0, mayRaiseFPException = 1, Uses = [FPCR] in
 class BaseSIMDFPCvtTwoVectorTied<bit Q, bit U, bits<2> size, bits<5> opcode,
                              RegisterOperand outtype, RegisterOperand intype,
                              string asm, string VdTy, string VnTy,
                              list<dag> pattern>
   : I<(outs outtype:$dst), (ins outtype:$Rd, intype:$Rn), asm,
       !strconcat("\t$Rd", VdTy, ", $Rn", VnTy), "$Rd = $dst", pattern>,
     Sched<[WriteVq]> {
   bits<5> Rd;
multiclass SIMDThreeScalarHSTied<bit U, bit R, bits<5> opc, string asm> {
   def v1i16: BaseSIMDThreeScalarTied<U, 0b01, R, opc, (outs FPR16:$dst),
                                      (ins FPR16:$Rd, FPR16:$Rn, FPR16:$Rm),
                                      asm, []>;
 }
 
 multiclass SIMDFPThreeScalar<bit U, bit S, bits<3> opc, string asm,
                              SDPatternOperator OpNode = null_frag,
                              Predicate pred = HasNEON> {
-  let mayLoad = 0, mayStore = 0, hasSideEffects = 0, mayRaiseFPException = 1 in {
+  let mayLoad = 0, mayStore = 0, hasSideEffects = 0, mayRaiseFPException = 1, Uses = [FPCR] in {
     let Predicates = [pred] in {
     def NAME#64 : BaseSIMDThreeScalar<U, {S,0b11}, {0b11,opc}, FPR64, asm,
       [(set (f64 FPR64:$Rd), (OpNode (f64 FPR64:$Rn), (f64 FPR64:$Rm)))]>;
     def NAME#32 : BaseSIMDThreeScalar<U, {S,0b01}, {0b11,opc}, FPR32, asm,
       [(set FPR32:$Rd, (OpNode FPR32:$Rn, FPR32:$Rm))]>;
     }
     let Predicates = [pred, HasFullFP16] in {
     def NAME#16 : BaseSIMDThreeScalar<U, {S,0b10}, {0b00,opc}, FPR16, asm,
       [(set (f16 FPR16:$Rd), (OpNode (f16 FPR16:$Rn), (f16 FPR16:$Rm)))]>;
     }
   }
 
   def : Pat<(v1f64 (OpNode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
             (!cast<Instruction>(NAME # "64") FPR64:$Rn, FPR64:$Rm)>;
 }
 
 multiclass SIMDThreeScalarFPCmp<bit U, bit S, bits<3> opc, string asm,
                                 SDPatternOperator OpNode = null_frag> {
-  let mayLoad = 0, mayStore = 0, hasSideEffects = 0, mayRaiseFPException = 1 in {
+  let mayLoad = 0, mayStore = 0, hasSideEffects = 0, mayRaiseFPException = 1, Uses = [FPCR] in {
     def NAME#64 : BaseSIMDThreeScalar<U, {S,0b11}, {0b11,opc}, FPR64, asm,
       [(set (i64 FPR64:$Rd), (OpNode (f64 FPR64:$Rn), (f64 FPR64:$Rm)))]>;
     def NAME#32 : BaseSIMDThreeScalar<U, {S,0b01}, {0b11,opc}, FPR32, asm,
       [(set (i32 FPR32:$Rd), (OpNode (f32 FPR32:$Rn), (f32 FPR32:$Rm)))]>;
     let Predicates = [HasNEON, HasFullFP16] in {
     def NAME#16 : BaseSIMDThreeScalar<U, {S,0b10}, {0b00,opc}, FPR16, asm,
       []>;
     } // Predicates = [HasNEON, HasFullFP16]
class BaseSIMDCmpTwoScalar<bit U, bits<2> size, bits<2> size2, bits<5> opcode,
   let Inst{20-19} = size2;
   let Inst{18-17} = 0b00;
   let Inst{16-12} = opcode;
   let Inst{11-10} = 0b10;
   let Inst{9-5}   = Rn;
   let Inst{4-0}   = Rd;
 }
 
-let mayRaiseFPException = 1 in
+let mayRaiseFPException = 1, Uses = [FPCR] in
 class SIMDInexactCvtTwoScalar<bits<5> opcode, string asm>
   : I<(outs FPR32:$Rd), (ins FPR64:$Rn), asm, "\t$Rd, $Rn", "",
      [(set (f32 FPR32:$Rd), (int_aarch64_sisd_fcvtxn (f64 FPR64:$Rn)))]>,
     Sched<[WriteVd]> {
   bits<5> Rd;
   bits<5> Rn;
   let Inst{31-17} = 0b011111100110000;
   let Inst{16-12} = opcode;
   let Inst{11-10} = 0b10;
   let Inst{9-5}   = Rn;
   let Inst{4-0}   = Rd;
 }
 
 multiclass SIMDCmpTwoScalarD<bit U, bits<5> opc, string asm,
                              SDPatternOperator OpNode> {
   def v1i64rz  : BaseSIMDCmpTwoScalar<U, 0b11, 0b00, opc, FPR64, asm, "0">;
 
   def : Pat<(v1i64 (OpNode FPR64:$Rn)),
             (!cast<Instruction>(NAME # v1i64rz) FPR64:$Rn)>;
 }
 
 multiclass SIMDFPCmpTwoScalar<bit U, bit S, bits<5> opc, string asm,
                               SDPatternOperator OpNode> {
-  let mayRaiseFPException = 1 in {
+  let mayRaiseFPException = 1, Uses = [FPCR] in {
   def v1i64rz  : BaseSIMDCmpTwoScalar<U, {S,1}, 0b00, opc, FPR64, asm, "0.0">;
   def v1i32rz  : BaseSIMDCmpTwoScalar<U, {S,0}, 0b00, opc, FPR32, asm, "0.0">;
   let Predicates = [HasNEON, HasFullFP16] in {
   def v1i16rz  : BaseSIMDCmpTwoScalar<U, {S,1}, 0b11, opc, FPR16, asm, "0.0">;
   }
   }
 
   def : InstAlias<asm # "\t$Rd, $Rn, #0",
multiclass SIMDTwoScalarD<bit U, bits<5> opc, string asm,
                           SDPatternOperator OpNode = null_frag> {
   def v1i64       : BaseSIMDTwoScalar<U, 0b11, 0b00, opc, FPR64, FPR64, asm,
     [(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn)))]>;
 
   def : Pat<(i64 (OpNode (i64 FPR64:$Rn))),
             (!cast<Instruction>(NAME # "v1i64") FPR64:$Rn)>;
 }
 
-let mayRaiseFPException = 1 in
+let mayRaiseFPException = 1, Uses = [FPCR] in
 multiclass SIMDFPTwoScalar<bit U, bit S, bits<5> opc, string asm,
                            Predicate pred = HasNEON> {
   let Predicates = [pred] in {
   def v1i64       : BaseSIMDTwoScalar<U, {S,1}, 0b00, opc, FPR64, FPR64, asm,[]>;
   def v1i32       : BaseSIMDTwoScalar<U, {S,0}, 0b00, opc, FPR32, FPR32, asm,[]>;
   }
   let Predicates = [pred, HasFullFP16] in {
   def v1f16       : BaseSIMDTwoScalar<U, {S,1}, 0b11, opc, FPR16, FPR16, asm,[]>;
   }
 }
 
-let mayRaiseFPException = 1 in
+let mayRaiseFPException = 1, Uses = [FPCR] in
 multiclass SIMDFPTwoScalarCVT<bit U, bit S, bits<5> opc, string asm,
                               SDPatternOperator OpNode> {
   def v1i64 : BaseSIMDTwoScalar<U, {S,1}, 0b00, opc, FPR64, FPR64, asm,
                                 [(set FPR64:$Rd, (OpNode (f64 FPR64:$Rn)))]>;
   def v1i32 : BaseSIMDTwoScalar<U, {S,0}, 0b00, opc, FPR32, FPR32, asm,
                                 [(set FPR32:$Rd, (OpNode (f32 FPR32:$Rn)))]>;
   let Predicates = [HasNEON, HasFullFP16] in {
   def v1i16 : BaseSIMDTwoScalar<U, {S,1}, 0b11, opc, FPR16, FPR16, asm,
class BaseSIMDPairwiseScalar<bit U, bits<2> size, bits<5> opcode,
   let Inst{4-0}   = Rd;
 }
 
 multiclass SIMDPairwiseScalarD<bit U, bits<5> opc, string asm> {
   def v2i64p : BaseSIMDPairwiseScalar<U, 0b11, opc, FPR64Op, V128,
                                       asm, ".2d">;
 }
 
-let mayRaiseFPException = 1 in
+let mayRaiseFPException = 1, Uses = [FPCR] in
 multiclass SIMDFPPairwiseScalar<bit S, bits<5> opc, string asm> {
   let Predicates = [HasNEON, HasFullFP16] in {
   def v2i16p : BaseSIMDPairwiseScalar<0, {S,0}, opc, FPR16Op, V64,
                                       asm, ".2h">;
   }
   def v2i32p : BaseSIMDPairwiseScalar<1, {S,0}, opc, FPR32Op, V64,
                                       asm, ".2s">;
   def v2i64p : BaseSIMDPairwiseScalar<1, {S,1}, opc, FPR64Op, V128,
multiclass SIMDAcrossLanesHSD<bit U, bits<5> opcode, string asm> {
   def v4i16v : BaseSIMDAcrossLanes<0, U, 0b01, opcode, FPR32, V64,
                                    asm, ".4h", []>;
   def v8i16v : BaseSIMDAcrossLanes<1, U, 0b01, opcode, FPR32, V128,
                                    asm, ".8h", []>;
   def v4i32v : BaseSIMDAcrossLanes<1, U, 0b10, opcode, FPR64, V128,
                                    asm, ".4s", []>;
 }
 
-let mayRaiseFPException = 1 in
+let mayRaiseFPException = 1, Uses = [FPCR] in
 multiclass SIMDFPAcrossLanes<bits<5> opcode, bit sz1, string asm,
                             Intrinsic intOp> {
   let Predicates = [HasNEON, HasFullFP16] in {
   def v4i16v : BaseSIMDAcrossLanes<0, 0, {sz1, 0}, opcode, FPR16, V64,
                                    asm, ".4h",
         [(set (f16 FPR16:$Rd), (intOp (v4f16 V64:$Rn)))]>;
   def v8i16v : BaseSIMDAcrossLanes<1, 0, {sz1, 0}, opcode, FPR16, V128,
                                    asm, ".8h",

 multiclass SIMDThreeSameVectorBF16DotI<bit U, string asm> {
 
   def v4bf16  : BaseSIMDThreeSameVectorBF16DotI<0, U, asm, ".2s", ".4h",
                                                ".2h", V64, v2f32, v4bf16>;
   def v8bf16 : BaseSIMDThreeSameVectorBF16DotI<1, U, asm, ".4s", ".8h",
                                               ".2h", V128, v4f32, v8bf16>;
 }
 
-let mayRaiseFPException = 1 in
+let mayRaiseFPException = 1, Uses = [FPCR] in
 class SIMDBF16MLAL<bit Q, string asm, SDPatternOperator OpNode>
   : BaseSIMDThreeSameVectorTied<Q, 0b1, 0b110, 0b11111, V128, asm, ".4s",
               [(set (v4f32 V128:$dst), (OpNode (v4f32 V128:$Rd),
                                                (v8bf16 V128:$Rn),
                                                (v8bf16 V128:$Rm)))]> {
   let AsmString = !strconcat(asm, "{\t$Rd.4s, $Rn.8h, $Rm.8h}");
 }
 
-let mayRaiseFPException = 1 in
+let mayRaiseFPException = 1, Uses = [FPCR] in
 class SIMDBF16MLALIndex<bit Q, string asm, SDPatternOperator OpNode>
   : I<(outs V128:$dst),
       (ins V128:$Rd, V128:$Rn, V128_lo:$Rm, VectorIndexH:$idx), asm,
       "{\t$Rd.4s, $Rn.8h, $Rm.h$idx}", "$Rd = $dst",
           [(set (v4f32 V128:$dst),
                 (v4f32 (OpNode (v4f32 V128:$Rd),
                                (v8bf16 V128:$Rn),
                                (v8bf16
: BaseSIMDThreeSameVectorTied<1, 1, 0b010, 0b11101,
                           [(set (v4f32 V128:$dst),
                                 (int_aarch64_neon_bfmmla (v4f32 V128:$Rd),
                                                          (v8bf16 V128:$Rn),
                                                          (v8bf16 V128:$Rm)))]> {
   let AsmString = !strconcat(asm, "{\t$Rd", ".4s", ", $Rn", ".8h",
                                     ", $Rm", ".8h", "}");
 }
 
-let mayRaiseFPException = 1 in
+let mayRaiseFPException = 1, Uses = [FPCR] in
 class SIMD_BFCVTN
   : BaseSIMDMixedTwoVector<0, 0, 0b10, 0b10110, V128, V128,
                            "bfcvtn", ".4h", ".4s",
     [(set (v8bf16 V128:$Rd),
           (int_aarch64_neon_bfcvtn (v4f32 V128:$Rn)))]>;
 
-let mayRaiseFPException = 1 in
+let mayRaiseFPException = 1, Uses = [FPCR] in
 class SIMD_BFCVTN2
   : BaseSIMDMixedTwoVectorTied<1, 0, 0b10, 0b10110, V128, V128,
                            "bfcvtn2", ".8h", ".4s",
     [(set (v8bf16 V128:$dst),
           (int_aarch64_neon_bfcvtn2 (v8bf16 V128:$Rd), (v4f32 V128:$Rn)))]>;
 
-let mayRaiseFPException = 1 in
+let mayRaiseFPException = 1, Uses = [FPCR] in
 class BF16ToSinglePrecision<string asm>
   : I<(outs FPR16:$Rd), (ins FPR32:$Rn), asm, "\t$Rd, $Rn", "",
     [(set (bf16 FPR16:$Rd), (int_aarch64_neon_bfcvt (f32 FPR32:$Rn)))]>,
     Sched<[WriteFCvt]> {
   bits<5> Rd;
   bits<5> Rn;
   let Inst{31-10} = 0b0001111001100011010000;
   let Inst{9-5}   = Rn;
multiclass SIMDThreeSameVectorDotIndex<bit U, bit Mixed, bits<2> size, string asm,
                                        SDPatternOperator OpNode> {
   def v8i8  : BaseSIMDThreeSameVectorDotIndex<0, U, Mixed, size, asm, ".2s", ".8b", ".4b",
                                               V64, v2i32, v8i8, OpNode>;
   def v16i8 : BaseSIMDThreeSameVectorDotIndex<1, U, Mixed, size, asm, ".4s", ".16b", ".4b",
                                               V128, v4i32, v16i8, OpNode>;
 }
 
 // ARMv8.2-A Fused Multiply Add-Long Instructions (Indexed)
-let mayRaiseFPException = 1 in
+let mayRaiseFPException = 1, Uses = [FPCR] in
 class BaseSIMDThreeSameVectorFMLIndex<bit Q, bit U, bits<4> opc, string asm,
                                       string dst_kind, string lhs_kind,
                                       string rhs_kind, RegisterOperand RegType,
                                       ValueType AccumType, ValueType InputType,
                                       SDPatternOperator OpNode> :
         BaseSIMDIndexedTied<Q, U, 0, 0b10, opc, RegType, RegType, V128,
                             VectorIndexH, asm, "", dst_kind, lhs_kind, rhs_kind,
           [(set (AccumType RegType:$dst),

 multiclass SIMDThreeSameVectorFMLIndex<bit U, bits<4> opc, string asm,
                                        SDPatternOperator OpNode> {
   def v4f16 : BaseSIMDThreeSameVectorFMLIndex<0, U, opc, asm, ".2s", ".2h", ".h",
                                               V64, v2f32, v4f16, OpNode>;
   def v8f16 : BaseSIMDThreeSameVectorFMLIndex<1, U, opc, asm, ".4s", ".4h", ".h",
                                               V128, v4f32, v8f16, OpNode>;
 }
 
-let mayRaiseFPException = 1 in
+let mayRaiseFPException = 1, Uses = [FPCR] in
 multiclass SIMDFPIndexed<bit U, bits<4> opc, string asm,
                          SDPatternOperator OpNode> {
   let Predicates = [HasNEON, HasFullFP16] in {
   def v4i16_indexed : BaseSIMDIndexed<0, U, 0, 0b00, opc,
                                       V64, V64,
                                       V128_lo, VectorIndexH,
                                       asm, ".4h", ".4h", ".4h", ".h",
     [(set (v4f16 V64:$Rd),
multiclass SIMDFPIndexedTiedPatterns<string INST, SDPatternOperator OpNode> {
 
   // 1 variant for 64-bit scalar version: extract from .1d or from .2d
   def : Pat<(f64 (OpNode (f64 FPR64:$Rd), (f64 FPR64:$Rn),
                          (vector_extract (v2f64 V128:$Rm), VectorIndexD:$idx))),
             (!cast<Instruction>(INST # "v1i64_indexed") FPR64:$Rd, FPR64:$Rn,
                 V128:$Rm, VectorIndexD:$idx)>;
 }
 
-let mayRaiseFPException = 1 in
+let mayRaiseFPException = 1, Uses = [FPCR] in
 multiclass SIMDFPIndexedTied<bit U, bits<4> opc, string asm> {
   let Predicates = [HasNEON, HasFullFP16] in {
   def v4i16_indexed : BaseSIMDIndexedTied<0, U, 0, 0b00, opc, V64, V64,
                                           V128_lo, VectorIndexH,
                                           asm, ".4h", ".4h", ".4h", ".h", []> {
     bits<3> idx;
     let Inst{11} = idx{2};
     let Inst{21} = idx{1};

 }
 def complexrotateopodd : Operand<i32>, TImmLeaf<i32, [{ return Imm >= 0 && Imm <= 270;  }],
                                                   SDNodeXForm<imm, [{
   return CurDAG->getTargetConstant(((N->getSExtValue() - 90) / 180), SDLoc(N), MVT::i32);
 }]>> {
   let ParserMatchClass = ComplexRotationOperand<180, 90, "Odd">;
   let PrintMethod = "printComplexRotationOp<180, 90>";
 }
-let mayLoad = 0, mayStore = 0, hasSideEffects = 0, mayRaiseFPException = 1 in
+let mayLoad = 0, mayStore = 0, hasSideEffects = 0, mayRaiseFPException = 1, Uses = [FPCR] in
 class BaseSIMDThreeSameVectorComplex<bit Q, bit U, bits<2> size, bits<3> opcode,
                                      RegisterOperand regtype, Operand rottype,
                                      string asm, string kind, list<dag> pattern>
   : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, rottype:$rot), asm,
       "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind # ", $rot"
       "|" # kind # "\t$Rd, $Rn, $Rm, $rot}", "", pattern>,
     Sched<[!if(Q, WriteVq, WriteVd)]> {
   bits<5> Rd;
def v2f64 : BaseSIMDThreeSameVectorComplex<1, U, 0b11, opcode, V128, rottype,
               asm, ".2d",
               [(set (v2f64 V128:$dst), (OpNode (v2f64 V128:$Rd),
                                                (v2f64 V128:$Rn),
                                                (v2f64 V128:$Rm),
                                                (i32 rottype:$rot)))]>;
   }
 }
 
-let mayLoad = 0, mayStore = 0, hasSideEffects = 0, mayRaiseFPException = 1 in
+let mayLoad = 0, mayStore = 0, hasSideEffects = 0, mayRaiseFPException = 1, Uses = [FPCR] in
 class BaseSIMDThreeSameVectorTiedComplex<bit Q, bit U, bits<2> size,
                                          bits<3> opcode,
                                          RegisterOperand regtype,
                                          Operand rottype, string asm,
                                          string kind, list<dag> pattern>
   : I<(outs regtype:$dst),
       (ins regtype:$Rd, regtype:$Rn, regtype:$Rm, rottype:$rot), asm,
       "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind # ", $rot"
def v2f64 : BaseSIMDThreeSameVectorTiedComplex<1, U, 0b11, opcode, V128,
               rottype, asm, ".2d",
               [(set (v2f64 V128:$dst), (OpNode (v2f64 V128:$Rd),
                                                (v2f64 V128:$Rn),
                                                (v2f64 V128:$Rm),
                                                (i32 rottype:$rot)))]>;
   }
 }
 
-let mayLoad = 0, mayStore = 0, hasSideEffects = 0, mayRaiseFPException = 1 in
+let mayLoad = 0, mayStore = 0, hasSideEffects = 0, mayRaiseFPException = 1, Uses = [FPCR] in
 class BaseSIMDIndexedTiedComplex<bit Q, bit U, bit Scalar, bits<2> size,
                                  bit opc1, bit opc2, RegisterOperand dst_reg,
                                  RegisterOperand lhs_reg,
                                  RegisterOperand rhs_reg, Operand vec_idx,
                                  Operand rottype, string asm, string apple_kind,
                                  string dst_kind, string lhs_kind,
                                  string rhs_kind, list<dag> pattern>
   : I<(outs dst_reg:$dst),

llvm/lib/Target/AArch64/AArch64InstrInfo.td

def HWASAN_CHECK_MEMACCESS_SHORTGRANULES : Pseudo<
   Sched<[]>;
 }
 
 // The cycle counter PMC register is PMCCNTR_EL0.
 let Predicates = [HasPerfMon] in
 def : Pat<(readcyclecounter), (MRS 0xdce8)>;
 
 // FPCR register
-def : Pat<(i64 (int_aarch64_get_fpcr)), (MRS 0xda20)>;
-def : Pat<(int_aarch64_set_fpcr i64:$val), (MSR 0xda20, GPR64:$val)>;
+let Uses = [FPCR] in
+def MRS_FPCR : Pseudo<(outs GPR64:$dst), (ins),
+                      [(set GPR64:$dst, (int_aarch64_get_fpcr))]>,
+               PseudoInstExpansion<(MRS GPR64:$dst, 0xda20)>,
+               Sched<[WriteSys]>;
+let Defs = [FPCR] in
+def MSR_FPCR : Pseudo<(outs), (ins GPR64:$val),
+                      [(int_aarch64_set_fpcr i64:$val)]>,
+               PseudoInstExpansion<(MSR 0xda20, GPR64:$val)>,
+               Sched<[WriteSys]>;
 
 // Generic system instructions
 def SYSxt  : SystemXtI<0, "sys">;
 def SYSLxt : SystemLXtI<1, "sysl">;
 
 def : InstAlias<"sys $op1, $Cn, $Cm, $op2",
                 (SYSxt imm0_7:$op1, sys_cr_op:$Cn,
                  sys_cr_op:$Cm, imm0_7:$op2, XZR)>;

llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp

AArch64RegisterInfo::getStrictlyReservedRegs(const MachineFunction &MF) const {
 
   // SME tiles are not allocatable.
   if (MF.getSubtarget<AArch64Subtarget>().hasSME()) {
     for (MCSubRegIterator SubReg(AArch64::ZA, this, /*self=*/true);
          SubReg.isValid(); ++SubReg)
       Reserved.set(*SubReg);
   }
 
+  markSuperRegs(Reserved, AArch64::FPCR);
+
   assert(checkAllSuperRegsMarked(Reserved));
   return Reserved;
 }
 
 BitVector
 AArch64RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
   BitVector Reserved = getStrictlyReservedRegs(MF);
 

llvm/lib/Target/AArch64/AArch64RegisterInfo.td

 def NZCV  : AArch64Reg<0, "nzcv">;
 
 // First fault status register
 def FFR : AArch64Reg<0, "ffr">, DwarfRegNum<[47]>;
 
 // Purely virtual Vector Granule (VG) Dwarf register
 def VG : AArch64Reg<0, "vg">, DwarfRegNum<[46]>;
 
+// Floating-point control register
+def FPCR : AArch64Reg<0, "fpcr">;
+
 // GPR register classes with the intersections of GPR32/GPR32sp and
 // GPR64/GPR64sp for use by the coalescer.
 def GPR32common : RegisterClass<"AArch64", [i32], 32, (sequence "W%u", 0, 30)> {
   let AltOrders = [(rotl GPR32common, 8)];
   let AltOrderSelect = [{ return 1; }];
 }
 def GPR64common : RegisterClass<"AArch64", [i64], 64,
                                 (add (sequence "X%u", 0, 28), FP, LR)> {

llvm/test/CodeGen/AArch64/GlobalISel/postselectopt-constrain-new-regop.mir

body:             |
   ; CHECK:   liveins: $w1, $x0, $x2
   ; CHECK:   [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
   ; CHECK:   [[COPY1:%[0-9]+]]:gpr32sp = COPY $w1
   ; CHECK:   [[COPY2:%[0-9]+]]:gpr64sp = COPY $x2
   ; CHECK:   [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF
   ; CHECK:   [[COPY3:%[0-9]+]]:fpr32 = COPY [[DEF]]
   ; CHECK:   [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 872415232
   ; CHECK:   [[COPY4:%[0-9]+]]:fpr32 = COPY [[MOVi32imm]]
-  ; CHECK:   FCMPSrr [[COPY3]], [[COPY4]], implicit-def $nzcv
+  ; CHECK:   FCMPSrr [[COPY3]], [[COPY4]], implicit-def $nzcv, implicit $fpcr
   ; CHECK:   [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv
   ; CHECK:   [[SUBWri:%[0-9]+]]:gpr32common = SUBWri [[COPY1]], 1, 0
   ; CHECK:   [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[SUBWri]], %subreg.sub_32
   ; CHECK:   [[COPY5:%[0-9]+]]:fpr32 = COPY [[DEF]]
-  ; CHECK:   FCMPSrr [[COPY5]], [[COPY4]], implicit-def $nzcv
+  ; CHECK:   FCMPSrr [[COPY5]], [[COPY4]], implicit-def $nzcv, implicit $fpcr
   ; CHECK:   [[CSINCWr1:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv
   ; CHECK:   [[EORWrr:%[0-9]+]]:gpr32 = EORWrr [[CSINCWr]], [[CSINCWr1]]
   ; CHECK:   TBNZW [[EORWrr]], 0, %bb.2
   ; CHECK:   B %bb.1
   ; CHECK: bb.1:
   ; CHECK:   successors: %bb.2(0x80000000)
   ; CHECK:   [[UBFMXri:%[0-9]+]]:gpr64 = UBFMXri [[SUBREG_TO_REG]], 60, 59
   ; CHECK:   [[LDRSroX:%[0-9]+]]:fpr32 = LDRSroX [[COPY]], [[UBFMXri]], 0, 0 :: (load (s32))
   ; CHECK:   [[COPY6:%[0-9]+]]:fpr32 = COPY [[DEF]]
-  ; CHECK:   [[FMULSrr:%[0-9]+]]:fpr32 = FMULSrr [[COPY6]], [[LDRSroX]]
+  ; CHECK:   [[FMULSrr:%[0-9]+]]:fpr32 = FMULSrr [[COPY6]], [[LDRSroX]], implicit $fpcr
   ; CHECK:   [[COPY7:%[0-9]+]]:fpr32 = COPY [[DEF]]
-  ; CHECK:   [[FADDSrr:%[0-9]+]]:fpr32 = FADDSrr [[FMULSrr]], [[COPY7]]
+  ; CHECK:   [[FADDSrr:%[0-9]+]]:fpr32 = FADDSrr [[FMULSrr]], [[COPY7]], implicit $fpcr
   ; CHECK:   STRSui [[FADDSrr]], [[COPY2]], 0 :: (store (s32))
   ; CHECK: bb.2:
   ; CHECK:   RET_ReallyLR
   bb.1:
     liveins: $w1, $x0, $x2
 
     %0:gpr64sp = COPY $x0
     %1:gpr32sp = COPY $w1
     %2:gpr64sp = COPY $x2
     %3:gpr32 = IMPLICIT_DEF
     %29:fpr32 = COPY %3
     %33:gpr32 = MOVi32imm 872415232
     %4:fpr32 = COPY %33
-    FCMPSrr %29, %4, implicit-def $nzcv
+    FCMPSrr %29, %4, implicit-def $nzcv, implicit $fpcr
     %28:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv
     %7:gpr32 = SUBSWri %1, 1, 0, implicit-def $nzcv
     %8:gpr64 = SUBREG_TO_REG 0, %7, %subreg.sub_32
     %30:fpr32 = COPY %3
-    FCMPSrr %30, %4, implicit-def $nzcv
+    FCMPSrr %30, %4, implicit-def $nzcv, implicit $fpcr
     %27:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv
     %26:gpr32 = EORWrr %28, %27
     TBNZW %26, 0, %bb.3
     B %bb.2
 
   bb.2:
     %12:gpr64 = UBFMXri %8, 60, 59
     %15:fpr32 = LDRSroX %0, %12, 0, 0 :: (load (s32))
     %31:fpr32 = COPY %3
-    %16:fpr32 = FMULSrr %31, %15
+    %16:fpr32 = FMULSrr %31, %15, implicit $fpcr
     %32:fpr32 = COPY %3
-    %17:fpr32 = FADDSrr %16, %32
+    %17:fpr32 = FADDSrr %16, %32, implicit $fpcr
     STRSui %17, %2, 0 :: (store (s32))
 
   bb.3:
     RET_ReallyLR
 
 ...

llvm/test/CodeGen/AArch64/GlobalISel/postselectopt-dead-cc-defs-in-fcmp.mir

bb.1:
 
     ; CHECK-LABEL: name: test_fcmp_dead_cc
     ; CHECK: liveins: $w1, $x0, $s0, $s1
     ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
     ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
     ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0
     ; CHECK: [[COPY3:%[0-9]+]]:fpr32 = COPY $s1
     ; CHECK: [[COPY4:%[0-9]+]]:gpr32 = COPY $wzr
-    ; CHECK: FCMPSrr [[COPY2]], [[COPY3]], implicit-def dead $nzcv
+    ; CHECK: FCMPSrr [[COPY2]], [[COPY3]], implicit-def dead $nzcv, implicit $fpcr
     ; CHECK: [[SUBWrr:%[0-9]+]]:gpr32 = SUBWrr [[COPY1]], [[COPY4]]
-    ; CHECK: FCMPSrr [[COPY2]], [[COPY3]], implicit-def $nzcv
+    ; CHECK: FCMPSrr [[COPY2]], [[COPY3]], implicit-def $nzcv, implicit $fpcr
     ; CHECK: [[UBFMWri:%[0-9]+]]:gpr32common = UBFMWri [[SUBWrr]], 1, 31
     ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
     ; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[UBFMWri]], [[MOVi32imm]], 8, implicit $nzcv
     ; CHECK: $w0 = COPY [[CSELWr]]
     ; CHECK: RET_ReallyLR implicit $w0
     %1:gpr64 = COPY $x0
     %2:gpr32 = COPY $w1
     %3:fpr32 = COPY $s0
     %4:fpr32 = COPY $s1
     %26:gpr32 = COPY $wzr
-    FCMPSrr %3, %4, implicit-def $nzcv
+    FCMPSrr %3, %4, implicit-def $nzcv, implicit $fpcr
     %12:gpr32 = SUBSWrr %2, %26, implicit-def $nzcv
-    FCMPSrr %3, %4, implicit-def $nzcv
+    FCMPSrr %3, %4, implicit-def $nzcv, implicit $fpcr
     %14:gpr32common = UBFMWri %12, 1, 31
     %60:gpr32 = MOVi32imm 1
     %16:gpr32 = CSELWr %14, %60, 8, implicit $nzcv
     $w0 = COPY %16
     RET_ReallyLR implicit $w0
 
 ...
 ---
bb.1:
 
     ; CHECK-LABEL: name: test_fcmp_64_dead_cc
     ; CHECK: liveins: $w1, $x0, $d0, $d1
     ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
     ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
     ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
     ; CHECK: [[COPY3:%[0-9]+]]:fpr64 = COPY $d1
     ; CHECK: [[COPY4:%[0-9]+]]:gpr32 = COPY $wzr
-    ; CHECK: FCMPDrr [[COPY2]], [[COPY3]], implicit-def dead $nzcv
+    ; CHECK: FCMPDrr [[COPY2]], [[COPY3]], implicit-def dead $nzcv, implicit $fpcr
     ; CHECK: [[SUBWrr:%[0-9]+]]:gpr32 = SUBWrr [[COPY1]], [[COPY4]]
-    ; CHECK: FCMPDrr [[COPY2]], [[COPY3]], implicit-def $nzcv
+    ; CHECK: FCMPDrr [[COPY2]], [[COPY3]], implicit-def $nzcv, implicit $fpcr
     ; CHECK: [[UBFMWri:%[0-9]+]]:gpr32common = UBFMWri [[SUBWrr]], 1, 31
     ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
     ; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[UBFMWri]], [[MOVi32imm]], 8, implicit $nzcv
     ; CHECK: $w0 = COPY [[CSELWr]]
     ; CHECK: RET_ReallyLR implicit $w0
     %1:gpr64 = COPY $x0
     %2:gpr32 = COPY $w1
     %3:fpr64 = COPY $d0
     %4:fpr64 = COPY $d1
     %26:gpr32 = COPY $wzr
-    FCMPDrr %3, %4, implicit-def $nzcv
+    FCMPDrr %3, %4, implicit-def $nzcv, implicit $fpcr
     %12:gpr32 = SUBSWrr %2, %26, implicit-def $nzcv
-    FCMPDrr %3, %4, implicit-def $nzcv
+    FCMPDrr %3, %4, implicit-def $nzcv, implicit $fpcr
     %14:gpr32common = UBFMWri %12, 1, 31
     %60:gpr32 = MOVi32imm 1
     %16:gpr32 = CSELWr %14, %60, 8, implicit $nzcv
     $w0 = COPY %16
     RET_ReallyLR implicit $w0
 
 ...
 ---
bb.1:
 
     ; CHECK-LABEL: name: test_fcmp_dead_cc_3_fcmps
     ; CHECK: liveins: $w1, $x0, $s0, $s1
     ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
     ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
     ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0
     ; CHECK: [[COPY3:%[0-9]+]]:fpr32 = COPY $s1
     ; CHECK: [[COPY4:%[0-9]+]]:gpr32 = COPY $wzr
-    ; CHECK: FCMPSrr [[COPY2]], [[COPY3]], implicit-def dead $nzcv
+    ; CHECK: FCMPSrr [[COPY2]], [[COPY3]], implicit-def dead $nzcv, implicit $fpcr
     ; CHECK: [[SUBWrr:%[0-9]+]]:gpr32 = SUBWrr [[COPY1]], [[COPY4]]
-    ; CHECK: FCMPSrr [[COPY2]], [[COPY3]], implicit-def dead $nzcv
+    ; CHECK: FCMPSrr [[COPY2]], [[COPY3]], implicit-def dead $nzcv, implicit $fpcr
     ; CHECK: [[SUBWrr1:%[0-9]+]]:gpr32 = SUBWrr [[COPY1]], [[COPY4]]
-    ; CHECK: FCMPSrr [[COPY2]], [[COPY3]], implicit-def $nzcv
+    ; CHECK: FCMPSrr [[COPY2]], [[COPY3]], implicit-def $nzcv, implicit $fpcr
     ; CHECK: [[UBFMWri:%[0-9]+]]:gpr32common = UBFMWri [[SUBWrr1]], 1, 31
     ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
     ; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[UBFMWri]], [[MOVi32imm]], 8, implicit $nzcv
     ; CHECK: $w0 = COPY [[CSELWr]]
     ; CHECK: RET_ReallyLR implicit $w0
     %1:gpr64 = COPY $x0
     %2:gpr32 = COPY $w1
     %3:fpr32 = COPY $s0
     %4:fpr32 = COPY $s1
     %26:gpr32 = COPY $wzr
-    FCMPSrr %3, %4, implicit-def $nzcv
+    FCMPSrr %3, %4, implicit-def $nzcv, implicit $fpcr
     %12:gpr32 = SUBSWrr %2, %26, implicit-def $nzcv
-    FCMPSrr %3, %4, implicit-def $nzcv
+    FCMPSrr %3, %4, implicit-def $nzcv, implicit $fpcr
     %12:gpr32 = SUBSWrr %2, %26, implicit-def $nzcv
-    FCMPSrr %3, %4, implicit-def $nzcv
+    FCMPSrr %3, %4, implicit-def $nzcv, implicit $fpcr
     %14:gpr32common = UBFMWri %12, 1, 31
     %60:gpr32 = MOVi32imm 1
     %16:gpr32 = CSELWr %14, %60, 8, implicit $nzcv
     $w0 = COPY %16
     RET_ReallyLR implicit $w0
 
 ...
 ---
bb.1:
     ; CHECK-LABEL: name: test_impdef_made_dead
     ; CHECK: liveins: $w1, $x0, $s0, $s1
     ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
     ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
     ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0
     ; CHECK: [[COPY3:%[0-9]+]]:fpr32 = COPY $s1
     ; CHECK: [[COPY4:%[0-9]+]]:gpr32 = COPY $wzr
     ; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[COPY1]], [[COPY4]], implicit-def dead $nzcv
-    ; CHECK: FCMPSrr [[COPY2]], [[COPY3]], implicit-def $nzcv
+    ; CHECK: FCMPSrr [[COPY2]], [[COPY3]], implicit-def $nzcv, implicit $fpcr
     ; CHECK: [[UBFMWri:%[0-9]+]]:gpr32common = UBFMWri [[SUBSWrr]], 1, 31
     ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
     ; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[UBFMWri]], [[MOVi32imm]], 8, implicit $nzcv
     ; CHECK: %ret:gpr32 = SUBSWrr [[CSELWr]], [[SUBSWrr]], implicit-def dead $nzcv
     ; CHECK: $w0 = COPY [[CSELWr]]
     ; CHECK: RET_ReallyLR implicit $w0
     %1:gpr64 = COPY $x0
     %2:gpr32 = COPY $w1
     %3:fpr32 = COPY $s0
     %4:fpr32 = COPY $s1
     %26:gpr32 = COPY $wzr
     %12:gpr32 = SUBSWrr %2, %26, implicit-def $nzcv
-    FCMPSrr %3, %4, implicit-def $nzcv
+    FCMPSrr %3, %4, implicit-def $nzcv, implicit $fpcr
     %14:gpr32common = UBFMWri %12, 1, 31
     %60:gpr32 = MOVi32imm 1
     %16:gpr32 = CSELWr %14, %60, 8, implicit $nzcv
     %ret:gpr32 = SUBSWrr %16, %12, implicit-def $nzcv
     $w0 = COPY %16
     RET_ReallyLR implicit $w0
 ...

llvm/test/CodeGen/AArch64/GlobalISel/select-frint-nofp16.mir

 body:             |
   bb.0:
     liveins: $h0
 
     ; CHECK-LABEL: name: test_f16.rint
     ; CHECK: liveins: $h0
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
-    ; CHECK-NEXT: %1:fpr32 = nofpexcept FCVTSHr [[COPY]]
-    ; CHECK-NEXT: %2:fpr32 = nofpexcept FRINTXSr %1
-    ; CHECK-NEXT: %3:fpr16 = nofpexcept FCVTHSr %2
+    ; CHECK-NEXT: %1:fpr32 = nofpexcept FCVTSHr [[COPY]], implicit $fpcr
+    ; CHECK-NEXT: %2:fpr32 = nofpexcept FRINTXSr %1, implicit $fpcr
+    ; CHECK-NEXT: %3:fpr16 = nofpexcept FCVTHSr %2, implicit $fpcr
     ; CHECK-NEXT: $h0 = COPY %3
     ; CHECK-NEXT: RET_ReallyLR implicit $h0
     %0:fpr(s16) = COPY $h0
     %2:fpr(s32) = G_FPEXT %0(s16)
     %3:fpr(s32) = G_FRINT %2
     %1:fpr(s16) = G_FPTRUNC %3(s32)
     $h0 = COPY %1(s16)
     RET_ReallyLR implicit $h0
bb.0:
     ; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
     ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY]], %subreg.dsub
     ; CHECK-NEXT: [[DEF2:%[0-9]+]]:fpr128 = IMPLICIT_DEF
     ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF2]], [[COPY]], %subreg.dsub
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY [[INSERT_SUBREG]].hsub
     ; CHECK-NEXT: [[DUPi16_:%[0-9]+]]:fpr16 = DUPi16 [[INSERT_SUBREG]], 1
     ; CHECK-NEXT: [[DUPi16_1:%[0-9]+]]:fpr16 = DUPi16 [[INSERT_SUBREG1]], 2
     ; CHECK-NEXT: [[DUPi16_2:%[0-9]+]]:fpr16 = DUPi16 [[INSERT_SUBREG2]], 3
-    ; CHECK-NEXT: %5:fpr32 = nofpexcept FCVTSHr [[COPY1]]
-    ; CHECK-NEXT: %6:fpr32 = nofpexcept FRINTXSr %5
-    ; CHECK-NEXT: %7:fpr16 = nofpexcept FCVTHSr %6
-    ; CHECK-NEXT: %8:fpr32 = nofpexcept FCVTSHr [[DUPi16_]]
-    ; CHECK-NEXT: %9:fpr32 = nofpexcept FRINTXSr %8
-    ; CHECK-NEXT: %10:fpr16 = nofpexcept FCVTHSr %9
-    ; CHECK-NEXT: %11:fpr32 = nofpexcept FCVTSHr [[DUPi16_1]]
-    ; CHECK-NEXT: %12:fpr32 = nofpexcept FRINTXSr %11
-    ; CHECK-NEXT: %13:fpr16 = nofpexcept FCVTHSr %12
-    ; CHECK-NEXT: %14:fpr32 = nofpexcept FCVTSHr [[DUPi16_2]]
-    ; CHECK-NEXT: %15:fpr32 = nofpexcept FRINTXSr %14
-    ; CHECK-NEXT: %16:fpr16 = nofpexcept FCVTHSr %15
+    ; CHECK-NEXT: %5:fpr32 = nofpexcept FCVTSHr [[COPY1]], implicit $fpcr
+    ; CHECK-NEXT: %6:fpr32 = nofpexcept FRINTXSr %5, implicit $fpcr
+    ; CHECK-NEXT: %7:fpr16 = nofpexcept FCVTHSr %6, implicit $fpcr
+    ; CHECK-NEXT: %8:fpr32 = nofpexcept FCVTSHr [[DUPi16_]], implicit $fpcr
+    ; CHECK-NEXT: %9:fpr32 = nofpexcept FRINTXSr %8, implicit $fpcr
+    ; CHECK-NEXT: %10:fpr16 = nofpexcept FCVTHSr %9, implicit $fpcr
+    ; CHECK-NEXT: %11:fpr32 = nofpexcept FCVTSHr [[DUPi16_1]], implicit $fpcr
+    ; CHECK-NEXT: %12:fpr32 = nofpexcept FRINTXSr %11, implicit $fpcr
+    ; CHECK-NEXT: %13:fpr16 = nofpexcept FCVTHSr %12, implicit $fpcr
+    ; CHECK-NEXT: %14:fpr32 = nofpexcept FCVTSHr [[DUPi16_2]], implicit $fpcr
+    ; CHECK-NEXT: %15:fpr32 = nofpexcept FRINTXSr %14, implicit $fpcr
+    ; CHECK-NEXT: %16:fpr16 = nofpexcept FCVTHSr %15, implicit $fpcr
     ; CHECK-NEXT: [[DEF3:%[0-9]+]]:fpr128 = IMPLICIT_DEF
     ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF3]], %7, %subreg.hsub
     ; CHECK-NEXT: [[DEF4:%[0-9]+]]:fpr128 = IMPLICIT_DEF
     ; CHECK-NEXT: [[INSERT_SUBREG4:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF4]], %10, %subreg.hsub
     ; CHECK-NEXT: [[INSvi16lane:%[0-9]+]]:fpr128 = INSvi16lane [[INSERT_SUBREG3]], 1, [[INSERT_SUBREG4]], 0
     ; CHECK-NEXT: [[DEF5:%[0-9]+]]:fpr128 = IMPLICIT_DEF
     ; CHECK-NEXT: [[INSERT_SUBREG5:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF5]], %13, %subreg.hsub
     ; CHECK-NEXT: [[INSvi16lane1:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane]], 2, [[INSERT_SUBREG5]], 0
bb.0:
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY [[COPY]].hsub
     ; CHECK-NEXT: [[DUPi16_:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 1
     ; CHECK-NEXT: [[DUPi16_1:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 2
     ; CHECK-NEXT: [[DUPi16_2:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 3
     ; CHECK-NEXT: [[DUPi16_3:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 4
     ; CHECK-NEXT: [[DUPi16_4:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 5
     ; CHECK-NEXT: [[DUPi16_5:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 6
     ; CHECK-NEXT: [[DUPi16_6:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 7
-    ; CHECK-NEXT: %9:fpr32 = nofpexcept FCVTSHr [[COPY1]]
-    ; CHECK-NEXT: %10:fpr32 = nofpexcept FRINTXSr %9
-    ; CHECK-NEXT: %11:fpr16 = nofpexcept FCVTHSr %10
-    ; CHECK-NEXT: %12:fpr32 = nofpexcept FCVTSHr [[DUPi16_]]
-    ; CHECK-NEXT: %13:fpr32 = nofpexcept FRINTXSr %12
-    ; CHECK-NEXT: %14:fpr16 = nofpexcept FCVTHSr %13
-    ; CHECK-NEXT: %15:fpr32 = nofpexcept FCVTSHr [[DUPi16_1]]
-    ; CHECK-NEXT: %16:fpr32 = nofpexcept FRINTXSr %15
-    ; CHECK-NEXT: %17:fpr16 = nofpexcept FCVTHSr %16
-    ; CHECK-NEXT: %18:fpr32 = nofpexcept FCVTSHr [[DUPi16_2]]
-    ; CHECK-NEXT: %19:fpr32 = nofpexcept FRINTXSr %18
-    ; CHECK-NEXT: %20:fpr16 = nofpexcept FCVTHSr %19
-    ; CHECK-NEXT: %21:fpr32 = nofpexcept FCVTSHr [[DUPi16_3]]
-    ; CHECK-NEXT: %22:fpr32 = nofpexcept FRINTXSr %21
-    ; CHECK-NEXT: %23:fpr16 = nofpexcept FCVTHSr %22
-    ; CHECK-NEXT: %24:fpr32 = nofpexcept FCVTSHr [[DUPi16_4]]
-    ; CHECK-NEXT: %25:fpr32 = nofpexcept FRINTXSr %24
-    ; CHECK-NEXT: %26:fpr16 = nofpexcept FCVTHSr %25
-    ; CHECK-NEXT: %27:fpr32 = nofpexcept FCVTSHr [[DUPi16_5]]
-    ; CHECK-NEXT: %28:fpr32 = nofpexcept FRINTXSr %27
-    ; CHECK-NEXT: %29:fpr16 = nofpexcept FCVTHSr %28
-    ; CHECK-NEXT: %30:fpr32 = nofpexcept FCVTSHr [[DUPi16_6]]
-    ; CHECK-NEXT: %31:fpr32 = nofpexcept FRINTXSr %30
-    ; CHECK-NEXT: %32:fpr16 = nofpexcept FCVTHSr %31
+    ; CHECK-NEXT: %9:fpr32 = nofpexcept FCVTSHr [[COPY1]], implicit $fpcr
+    ; CHECK-NEXT: %10:fpr32 = nofpexcept FRINTXSr %9, implicit $fpcr
+    ; CHECK-NEXT: %11:fpr16 = nofpexcept FCVTHSr %10, implicit $fpcr
+    ; CHECK-NEXT: %12:fpr32 = nofpexcept FCVTSHr [[DUPi16_]], implicit $fpcr
+    ; CHECK-NEXT: %13:fpr32 = nofpexcept FRINTXSr %12, implicit $fpcr
+    ; CHECK-NEXT: %14:fpr16 = nofpexcept FCVTHSr %13, implicit $fpcr
+    ; CHECK-NEXT: %15:fpr32 = nofpexcept FCVTSHr [[DUPi16_1]], implicit $fpcr
+    ; CHECK-NEXT: %16:fpr32 = nofpexcept FRINTXSr %15, implicit $fpcr
+    ; CHECK-NEXT: %17:fpr16 = nofpexcept FCVTHSr %16, implicit $fpcr
+    ; CHECK-NEXT: %18:fpr32 = nofpexcept FCVTSHr [[DUPi16_2]], implicit $fpcr
+    ; CHECK-NEXT: %19:fpr32 = nofpexcept FRINTXSr %18, implicit $fpcr
+    ; CHECK-NEXT: %20:fpr16 = nofpexcept FCVTHSr %19, implicit $fpcr
+    ; CHECK-NEXT: %21:fpr32 = nofpexcept FCVTSHr [[DUPi16_3]], implicit $fpcr
+    ; CHECK-NEXT: %22:fpr32 = nofpexcept FRINTXSr %21, implicit $fpcr
+    ; CHECK-NEXT: %23:fpr16 = nofpexcept FCVTHSr %22, implicit $fpcr
+    ; CHECK-NEXT: %24:fpr32 = nofpexcept FCVTSHr [[DUPi16_4]], implicit $fpcr
+    ; CHECK-NEXT: %25:fpr32 = nofpexcept FRINTXSr %24, implicit $fpcr
+    ; CHECK-NEXT: %26:fpr16 = nofpexcept FCVTHSr %25, implicit $fpcr
+    ; CHECK-NEXT: %27:fpr32 = nofpexcept FCVTSHr [[DUPi16_5]], implicit $fpcr
+    ; CHECK-NEXT: %28:fpr32 = nofpexcept FRINTXSr %27, implicit $fpcr
+    ; CHECK-NEXT: %29:fpr16 = nofpexcept FCVTHSr %28, implicit $fpcr
+    ; CHECK-NEXT: %30:fpr32 = nofpexcept FCVTSHr [[DUPi16_6]], implicit $fpcr
+    ; CHECK-NEXT: %31:fpr32 = nofpexcept FRINTXSr %30, implicit $fpcr
+    ; CHECK-NEXT: %32:fpr16 = nofpexcept FCVTHSr %31, implicit $fpcr
     ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
     ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], %11, %subreg.hsub
     ; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
     ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], %14, %subreg.hsub
     ; CHECK-NEXT: [[INSvi16lane:%[0-9]+]]:fpr128 = INSvi16lane [[INSERT_SUBREG]], 1, [[INSERT_SUBREG1]], 0
     ; CHECK-NEXT: [[DEF2:%[0-9]+]]:fpr128 = IMPLICIT_DEF
     ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF2]], %17, %subreg.hsub
     ; CHECK-NEXT: [[INSvi16lane1:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane]], 2, [[INSERT_SUBREG2]], 0

llvm/test/CodeGen/AArch64/aarch64-combine-fmul-fsub.mir

registers:
   - { id: 2, class: fpr64 }
   - { id: 3, class: fpr64 }
   - { id: 4, class: fpr64 }
 body:             |
   bb.0.entry:
     %2:fpr64 = COPY $d2
     %1:fpr64 = COPY $d1
     %0:fpr64 = COPY $d0
-    %3:fpr64 = FMULv2f32 %0, %1
-    %4:fpr64 = FSUBv2f32 killed %3, %2
+    %3:fpr64 = FMULv2f32 %0, %1, implicit $fpcr
+    %4:fpr64 = FSUBv2f32 killed %3, %2, implicit $fpcr
     $d0 = COPY %4
     RET_ReallyLR implicit $d0
 
 ...
 # UNPROFITABLE-LABEL: name: f1_2s
 # UNPROFITABLE: [[R1:%[0-9]+]]:fpr64 = FNEGv2f32 %2
-# UNPROFITABLE-NEXT: FMLAv2f32 killed [[R1]], %0, %1
+# UNPROFITABLE-NEXT: FMLAv2f32 killed [[R1]], %0, %1, implicit $fpcr
 #
 # PROFITABLE-LABEL: name: f1_2s
 # PROFITABLE: [[R1:%[0-9]+]]:fpr64 = FNEGv2f32 %2
-# PROFITABLE-NEXT: FMLAv2f32 killed [[R1]], %0, %1
+# PROFITABLE-NEXT: FMLAv2f32 killed [[R1]], %0, %1, implicit $fpcr
 ---
 name:            f1_4s
 registers:
   - { id: 0, class: fpr128 }
   - { id: 1, class: fpr128 }
   - { id: 2, class: fpr128 }
   - { id: 3, class: fpr128 }
   - { id: 4, class: fpr128 }
 body:             |
   bb.0.entry:
     %2:fpr128 = COPY $q2
     %1:fpr128 = COPY $q1
     %0:fpr128 = COPY $q0
-    %3:fpr128 = FMULv4f32 %0, %1
-    %4:fpr128 = FSUBv4f32 killed %3, %2
+    %3:fpr128 = FMULv4f32 %0, %1, implicit $fpcr
+    %4:fpr128 = FSUBv4f32 killed %3, %2, implicit $fpcr
     $q0 = COPY %4
     RET_ReallyLR implicit $q0
 
 ...
 # UNPROFITABLE-LABEL: name: f1_4s
-# UNPROFITABLE: [[R1:%[0-9]+]]:fpr128 = FMULv4f32 %0, %1
-# UNPROFITABLE-NEXT: FSUBv4f32 killed [[R1]], %2
+# UNPROFITABLE: [[R1:%[0-9]+]]:fpr128 = FMULv4f32 %0, %1, implicit $fpcr
+# UNPROFITABLE-NEXT: FSUBv4f32 killed [[R1]], %2, implicit $fpcr
 #
 # PROFITABLE-LABEL: name: f1_4s
 # PROFITABLE: [[R1:%[0-9]+]]:fpr128 = FNEGv4f32 %2
-# PROFITABLE-NEXT: FMLAv4f32 killed [[R1]], %0, %1
+# PROFITABLE-NEXT: FMLAv4f32 killed [[R1]], %0, %1, implicit $fpcr
 ---
 name:            f1_2d
 registers:
   - { id: 0, class: fpr128 }
   - { id: 1, class: fpr128 }
   - { id: 2, class: fpr128 }
   - { id: 3, class: fpr128 }
   - { id: 4, class: fpr128 }
 body:             |
   bb.0.entry:
     %2:fpr128 = COPY $q2
     %1:fpr128 = COPY $q1
     %0:fpr128 = COPY $q0
-    %3:fpr128 = FMULv2f64 %0, %1
-    %4:fpr128 = FSUBv2f64 killed %3, %2
+    %3:fpr128 = FMULv2f64 %0, %1, implicit $fpcr
+    %4:fpr128 = FSUBv2f64 killed %3, %2, implicit $fpcr
     $q0 = COPY %4
     RET_ReallyLR implicit $q0
 
 ...
 # UNPROFITABLE-LABEL: name: f1_2d
-# UNPROFITABLE: %3:fpr128 = FMULv2f64 %0, %1
-# UNPROFITABLE-NEXT: FSUBv2f64 killed %3, %2
+# UNPROFITABLE: %3:fpr128 = FMULv2f64 %0, %1, implicit $fpcr
+# UNPROFITABLE-NEXT: FSUBv2f64 killed %3, %2, implicit $fpcr
 #
 # PROFITABLE-LABEL: name: f1_2d
 # PROFITABLE: [[R1:%[0-9]+]]:fpr128 = FNEGv2f64 %2
-# PROFITABLE-NEXT: FMLAv2f64 killed [[R1]], %0, %1
+# PROFITABLE-NEXT: FMLAv2f64 killed [[R1]], %0, %1, implicit $fpcr
 ---
 name:            f1_both_fmul_2s
 registers:
   - { id: 0, class: fpr64 }
   - { id: 1, class: fpr64 }
   - { id: 2, class: fpr64 }
   - { id: 3, class: fpr64 }
   - { id: 4, class: fpr64 }
   - { id: 5, class: fpr64 }
   - { id: 6, class: fpr64 }
 body:             |
   bb.0.entry:
     %3:fpr64 = COPY $q3
     %2:fpr64 = COPY $q2
     %1:fpr64 = COPY $q1
     %0:fpr64 = COPY $q0
-    %4:fpr64 = FMULv2f32 %0, %1
-    %5:fpr64 = FMULv2f32 %2, %3
-    %6:fpr64 = FSUBv2f32 killed %4, %5
+    %4:fpr64 = FMULv2f32 %0, %1, implicit $fpcr
+    %5:fpr64 = FMULv2f32 %2, %3, implicit $fpcr
+    %6:fpr64 = FSUBv2f32 killed %4, %5, implicit $fpcr
     $q0 = COPY %6
     RET_ReallyLR implicit $q0
 
 ...
 # ALL-LABEL: name: f1_both_fmul_2s
-# ALL: %4:fpr64 = FMULv2f32 %0, %1
-# ALL-NEXT: FMLSv2f32 killed %4, %2, %3
+# ALL: %4:fpr64 = FMULv2f32 %0, %1, implicit $fpcr
+# ALL-NEXT: FMLSv2f32 killed %4, %2, %3, implicit $fpcr
 ---
 name:            f1_both_fmul_4s
 registers:
   - { id: 0, class: fpr128 }
   - { id: 1, class: fpr128 }
   - { id: 2, class: fpr128 }
   - { id: 3, class: fpr128 }
   - { id: 4, class: fpr128 }
   - { id: 5, class: fpr128 }
   - { id: 6, class: fpr128 }
 body:             |
   bb.0.entry:
     %3:fpr128 = COPY $q3
     %2:fpr128 = COPY $q2
     %1:fpr128 = COPY $q1
     %0:fpr128 = COPY $q0
-    %4:fpr128 = FMULv4f32 %0, %1
-    %5:fpr128 = FMULv4f32 %2, %3
-    %6:fpr128 = FSUBv4f32 killed %4, %5
+    %4:fpr128 = FMULv4f32 %0, %1, implicit $fpcr
+    %5:fpr128 = FMULv4f32 %2, %3, implicit $fpcr
+    %6:fpr128 = FSUBv4f32 killed %4, %5, implicit $fpcr
     $q0 = COPY %6
     RET_ReallyLR implicit $q0
 
 ...
 # ALL-LABEL: name: f1_both_fmul_4s
-# ALL: %4:fpr128 = FMULv4f32 %0, %1
-# ALL-NEXT: FMLSv4f32 killed %4, %2, %3
+# ALL: %4:fpr128 = FMULv4f32 %0, %1, implicit $fpcr
+# ALL-NEXT: FMLSv4f32 killed %4, %2, %3, implicit $fpcr
 ---
 name:            f1_both_fmul_2d
 registers:
   - { id: 0, class: fpr128 }
   - { id: 1, class: fpr128 }
   - { id: 2, class: fpr128 }
   - { id: 3, class: fpr128 }
   - { id: 4, class: fpr128 }
   - { id: 5, class: fpr128 }
   - { id: 6, class: fpr128 }
 body:             |
   bb.0.entry:
     %3:fpr128 = COPY $q3
     %2:fpr128 = COPY $q2
     %1:fpr128 = COPY $q1
     %0:fpr128 = COPY $q0
-    %4:fpr128 = FMULv2f64 %0, %1
-    %5:fpr128 = FMULv2f64 %2, %3
-    %6:fpr128 = FSUBv2f64 killed %4, %5
+    %4:fpr128 = FMULv2f64 %0, %1, implicit $fpcr
+    %5:fpr128 = FMULv2f64 %2, %3, implicit $fpcr
+    %6:fpr128 = FSUBv2f64 killed %4, %5, implicit $fpcr
     $q0 = COPY %6
     RET_ReallyLR implicit $q0
 
 ...
 # ALL-LABEL: name: f1_both_fmul_2d
-# ALL: %4:fpr128 = FMULv2f64 %0, %1
-# ALL-NEXT: FMLSv2f64 killed %4, %2, %3
+# ALL: %4:fpr128 = FMULv2f64 %0, %1, implicit $fpcr
+# ALL-NEXT: FMLSv2f64 killed %4, %2, %3, implicit $fpcr
 

llvm/test/CodeGen/AArch64/early-ifcvt-regclass-mismatch.mir

bb.4.if.then155.i:
     %27:fpr64 = FMOVD0
 
   bb.5.if.end161.i:
     successors: %bb.6(0x40000000), %bb.7(0x40000000)
 
     %9:gpr64 = PHI %7, %bb.2, %26, %bb.3, %27, %bb.4
     %21:fpr64 = COPY %9
     %25:fpr64 = FMOVD0
-    %10:fpr64 = FADDDrr %25, %21
+    %10:fpr64 = FADDDrr %25, %21, implicit $fpcr
     %22:fpr64 = COPY %4
-    %11:fpr64 = FMULDrr %22, %10
+    %11:fpr64 = FMULDrr %22, %10, implicit $fpcr
     %23:fpr64 = COPY %4
-    %13:fpr64 = FABD64 %23, %11
+    %13:fpr64 = FABD64 %23, %11, implicit $fpcr
     %28:gpr64 = MOVi64imm 4307583784117748259
     %24:fpr64 = COPY %28
-    FCMPDrr %13, %24, implicit-def $nzcv
+    FCMPDrr %13, %24, implicit-def $nzcv, implicit $fpcr
     %17:gpr32 = CSINCWr $wzr, $wzr, 5, implicit $nzcv
     TBNZW %17, 0, %bb.6
     B %bb.7
 
   bb.6.if.then.i.i:
     successors:
 
 
   bb.7.if.end9.i.i:
     RET_ReallyLR
 
 ...

llvm/test/CodeGen/AArch64/machine-combiner-fmul-dup.mir

body:             |
   ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:fpr64 = COPY $d0
   ; CHECK-NEXT:   [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
   ; CHECK-NEXT:   [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY3]], %subreg.dsub
   ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:fpr64 = COPY [[COPY1]]
   ; CHECK-NEXT:   [[COPY5:%[0-9]+]]:fpr64 = COPY [[COPY2]]
   ; CHECK-NEXT:   [[DUPv2i32lane:%[0-9]+]]:fpr64 = DUPv2i32lane [[INSERT_SUBREG]], 0
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1.for.cond:
-  ; CHECK-NEXT:   [[FMULv2i32_indexed:%[0-9]+]]:fpr64 = FMULv2i32_indexed [[COPY5]], [[INSERT_SUBREG]], 0
-  ; CHECK-NEXT:   [[FADDv2f32_:%[0-9]+]]:fpr64 = FADDv2f32 killed [[FMULv2i32_indexed]], [[COPY4]]
+  ; CHECK-NEXT:   [[FMULv2i32_indexed:%[0-9]+]]:fpr64 = FMULv2i32_indexed [[COPY5]], [[INSERT_SUBREG]], 0, implicit $fpcr
+  ; CHECK-NEXT:   [[FADDv2f32_:%[0-9]+]]:fpr64 = FADDv2f32 killed [[FMULv2i32_indexed]], [[COPY4]], implicit $fpcr
   ; CHECK-NEXT:   STRDui killed [[FADDv2f32_]], [[COPY]], 0 :: (store (s64) into %ir.ret, align 16)
   ; CHECK-NEXT:   B %bb.1
   bb.0.entry:
     liveins: $d0, $d1, $d2, $x0
 
     %4:gpr64common = COPY $x0
     %3:fpr64 = COPY $d2
     %2:fpr64 = COPY $d1
     %1:fpr64 = COPY $d0
     %8:fpr128 = IMPLICIT_DEF
     %7:fpr128 = INSERT_SUBREG %8, %1, %subreg.dsub
     %6:fpr64 = COPY %3
     %5:fpr64 = COPY %2
     %0:fpr64 = DUPv2i32lane killed %7, 0
 
   bb.1.for.cond:
-    %9:fpr64 = FMULv2f32 %5, %0
-    %10:fpr64 = FADDv2f32 killed %9, %6
+    %9:fpr64 = FMULv2f32 %5, %0, implicit $fpcr
+    %10:fpr64 = FADDv2f32 killed %9, %6, implicit $fpcr
     STRDui killed %10, %4, 0 :: (store 8 into %ir.ret, align 16)
     B %bb.1
 
 ...
 ---
 name:            indexed_2s_rev
 alignment:       16
 tracksRegLiveness: true
body:             |
   ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:fpr64 = COPY $d0
   ; CHECK-NEXT:   [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
   ; CHECK-NEXT:   [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY3]], %subreg.dsub
   ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:fpr64 = COPY [[COPY1]]
   ; CHECK-NEXT:   [[COPY5:%[0-9]+]]:fpr64 = COPY [[COPY2]]
   ; CHECK-NEXT:   [[DUPv2i32lane:%[0-9]+]]:fpr64 = DUPv2i32lane [[INSERT_SUBREG]], 0
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1.for.cond:
-  ; CHECK-NEXT:   [[FMULv2i32_indexed:%[0-9]+]]:fpr64 = FMULv2i32_indexed [[COPY5]], [[INSERT_SUBREG]], 0
-  ; CHECK-NEXT:   [[FADDv2f32_:%[0-9]+]]:fpr64 = FADDv2f32 killed [[FMULv2i32_indexed]], [[COPY4]]
+  ; CHECK-NEXT:   [[FMULv2i32_indexed:%[0-9]+]]:fpr64 = FMULv2i32_indexed [[COPY5]], [[INSERT_SUBREG]], 0, implicit $fpcr
+  ; CHECK-NEXT:   [[FADDv2f32_:%[0-9]+]]:fpr64 = FADDv2f32 killed [[FMULv2i32_indexed]], [[COPY4]], implicit $fpcr
   ; CHECK-NEXT:   STRDui killed [[FADDv2f32_]], [[COPY]], 0 :: (store (s64) into %ir.ret, align 16)
   ; CHECK-NEXT:   B %bb.1
   bb.0.entry:
     liveins: $d0, $d1, $d2, $x0
 
     %4:gpr64common = COPY $x0
     %3:fpr64 = COPY $d2
     %2:fpr64 = COPY $d1
     %1:fpr64 = COPY $d0
     %8:fpr128 = IMPLICIT_DEF
     %7:fpr128 = INSERT_SUBREG %8, %1, %subreg.dsub
     %6:fpr64 = COPY %3
     %5:fpr64 = COPY %2
     %0:fpr64 = DUPv2i32lane killed %7, 0
 
   bb.1.for.cond:
-    %9:fpr64 = FMULv2f32 %0, %5
-    %10:fpr64 = FADDv2f32 killed %9, %6
+    %9:fpr64 = FMULv2f32 %0, %5, implicit $fpcr
+    %10:fpr64 = FADDv2f32 killed %9, %6, implicit $fpcr
     STRDui killed %10, %4, 0 :: (store 8 into %ir.ret, align 16)
     B %bb.1
 
 ...
 ---
 name:            indexed_2d
 alignment:       16
 tracksRegLiveness: true
body:             |
   ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:fpr128 = COPY $q2
   ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:fpr128 = COPY $q1
   ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:fpr128 = COPY $q0
   ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:fpr128 = COPY [[COPY1]]
   ; CHECK-NEXT:   [[COPY5:%[0-9]+]]:fpr128 = COPY [[COPY2]]
   ; CHECK-NEXT:   [[DUPv2i64lane:%[0-9]+]]:fpr128 = DUPv2i64lane [[COPY3]], 0
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1.for.cond:
-  ; CHECK-NEXT:   [[FMULv2i64_indexed:%[0-9]+]]:fpr128 = FMULv2i64_indexed [[COPY5]], [[COPY3]], 0
-  ; CHECK-NEXT:   [[FADDv2f64_:%[0-9]+]]:fpr128 = FADDv2f64 killed [[FMULv2i64_indexed]], [[COPY4]]
+  ; CHECK-NEXT:   [[FMULv2i64_indexed:%[0-9]+]]:fpr128 = FMULv2i64_indexed [[COPY5]], [[COPY3]], 0, implicit $fpcr
+  ; CHECK-NEXT:   [[FADDv2f64_:%[0-9]+]]:fpr128 = FADDv2f64 killed [[FMULv2i64_indexed]], [[COPY4]], implicit $fpcr
   ; CHECK-NEXT:   STRQui killed [[FADDv2f64_]], [[COPY]], 0 :: (store (s128) into %ir.ret)
   ; CHECK-NEXT:   B %bb.1
   bb.0.entry:
     liveins: $q0, $q1, $q2, $x0
 
     %4:gpr64common = COPY $x0
     %3:fpr128 = COPY $q2
     %2:fpr128 = COPY $q1
     %1:fpr128 = COPY $q0
     %6:fpr128 = COPY %3
     %5:fpr128 = COPY %2
     %0:fpr128 = DUPv2i64lane %1, 0
 
   bb.1.for.cond:
-    %7:fpr128 = FMULv2f64 %5, %0
-    %8:fpr128 = FADDv2f64 killed %7, %6
+    %7:fpr128 = FMULv2f64 %5, %0, implicit $fpcr
+    %8:fpr128 = FADDv2f64 killed %7, %6, implicit $fpcr
     STRQui killed %8, %4, 0 :: (store 16 into %ir.ret)
     B %bb.1
 
 ...
 ---
 name:            indexed_4s
 alignment:       16
 tracksRegLiveness: true
body:             |
   ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:fpr128 = COPY $q2
   ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:fpr128 = COPY $q1
   ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:fpr128 = COPY $q0
   ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:fpr128 = COPY [[COPY1]]
   ; CHECK-NEXT:   [[COPY5:%[0-9]+]]:fpr128 = COPY [[COPY2]]
   ; CHECK-NEXT:   [[DUPv4i32lane:%[0-9]+]]:fpr128 = DUPv4i32lane [[COPY3]], 0
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1.for.cond:
-  ; CHECK-NEXT:   [[FMULv4i32_indexed:%[0-9]+]]:fpr128 = FMULv4i32_indexed [[COPY5]], [[COPY3]], 0
-  ; CHECK-NEXT:   [[FADDv4f32_:%[0-9]+]]:fpr128 = FADDv4f32 killed [[FMULv4i32_indexed]], [[COPY4]]
+  ; CHECK-NEXT:   [[FMULv4i32_indexed:%[0-9]+]]:fpr128 = FMULv4i32_indexed [[COPY5]], [[COPY3]], 0, implicit $fpcr
+  ; CHECK-NEXT:   [[FADDv4f32_:%[0-9]+]]:fpr128 = FADDv4f32 killed [[FMULv4i32_indexed]], [[COPY4]], implicit $fpcr
   ; CHECK-NEXT:   STRQui killed [[FADDv4f32_]], [[COPY]], 0 :: (store (s128) into %ir.ret)
   ; CHECK-NEXT:   B %bb.1
   bb.0.entry:
     liveins: $q0, $q1, $q2, $x0
 
     %4:gpr64common = COPY $x0
     %3:fpr128 = COPY $q2
     %2:fpr128 = COPY $q1
     %1:fpr128 = COPY $q0
     %6:fpr128 = COPY %3
     %5:fpr128 = COPY %2
     %0:fpr128 = DUPv4i32lane %1, 0
 
   bb.1.for.cond:
-    %7:fpr128 = FMULv4f32 %5, %0
-    %8:fpr128 = FADDv4f32 killed %7, %6
+    %7:fpr128 = FMULv4f32 %5, %0, implicit $fpcr
+    %8:fpr128 = FADDv4f32 killed %7, %6, implicit $fpcr
     STRQui killed %8, %4, 0 :: (store 16 into %ir.ret)
     B %bb.1
 
 ...
 ---
 name:            indexed_4h
 alignment:       16
 tracksRegLiveness: true
body:             |
   ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:fpr64 = COPY $d2
   ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:fpr64 = COPY $d1
   ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:fpr64 = COPY $d0
   ; CHECK-NEXT:   [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
   ; CHECK-NEXT:   [[INSERT_SUBREG:%[0-9]+]]:fpr128_lo = INSERT_SUBREG [[DEF]], [[COPY3]], %subreg.dsub
   ; CHECK-NEXT:   [[DUPv4i16lane:%[0-9]+]]:fpr64 = DUPv4i16lane [[INSERT_SUBREG]], 0
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1.for.cond:
-  ; CHECK-NEXT:   [[FMULv4i16_indexed:%[0-9]+]]:fpr64 = FMULv4i16_indexed [[COPY2]], [[INSERT_SUBREG]], 0
-  ; CHECK-NEXT:   [[FADDv4f16_:%[0-9]+]]:fpr64 = FADDv4f16 killed [[FMULv4i16_indexed]], [[COPY1]]
+  ; CHECK-NEXT:   [[FMULv4i16_indexed:%[0-9]+]]:fpr64 = FMULv4i16_indexed [[COPY2]], [[INSERT_SUBREG]], 0, implicit $fpcr
+  ; CHECK-NEXT:   [[FADDv4f16_:%[0-9]+]]:fpr64 = FADDv4f16 killed [[FMULv4i16_indexed]], [[COPY1]], implicit $fpcr
   ; CHECK-NEXT:   STRDui killed [[FADDv4f16_]], [[COPY]], 0 :: (store (s64) into %ir.ret, align 16)
   ; CHECK-NEXT:   B %bb.1
   bb.0.entry:
     liveins: $d0, $d1, $d2, $x0
 
     %4:gpr64common = COPY $x0
     %3:fpr64 = COPY $d2
     %2:fpr64 = COPY $d1
     %1:fpr64 = COPY $d0
     %6:fpr128 = IMPLICIT_DEF
     %5:fpr128 = INSERT_SUBREG %6, %1, %subreg.dsub
     %0:fpr64 = DUPv4i16lane killed %5, 0
 
   bb.1.for.cond:
-    %7:fpr64 = FMULv4f16 %2, %0
-    %8:fpr64 = FADDv4f16 killed %7, %3
+    %7:fpr64 = FMULv4f16 %2, %0, implicit $fpcr
+    %8:fpr64 = FADDv4f16 killed %7, %3, implicit $fpcr
     STRDui killed %8, %4, 0 :: (store 8 into %ir.ret, align 16)
     B %bb.1
 
 ...
 ---
 name:            indexed_8h
 alignment:       16
 tracksRegLiveness: true
body:             |
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr64common = COPY $x0
   ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:fpr128 = COPY $q2
   ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:fpr128 = COPY $q1
   ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:fpr128_lo = COPY $q0
   ; CHECK-NEXT:   [[DUPv8i16lane:%[0-9]+]]:fpr128 = DUPv8i16lane [[COPY3]], 0
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1.for.cond:
-  ; CHECK-NEXT:   [[FMULv8i16_indexed:%[0-9]+]]:fpr128 = FMULv8i16_indexed [[COPY2]], [[COPY3]], 0
-  ; CHECK-NEXT:   [[FADDv8f16_:%[0-9]+]]:fpr128 = FADDv8f16 killed [[FMULv8i16_indexed]], [[COPY1]]
+  ; CHECK-NEXT:   [[FMULv8i16_indexed:%[0-9]+]]:fpr128 = FMULv8i16_indexed [[COPY2]], [[COPY3]], 0, implicit $fpcr
+  ; CHECK-NEXT:   [[FADDv8f16_:%[0-9]+]]:fpr128 = FADDv8f16 killed [[FMULv8i16_indexed]], [[COPY1]], implicit $fpcr
   ; CHECK-NEXT:   STRQui killed [[FADDv8f16_]], [[COPY]], 0 :: (store (s128) into %ir.ret)
   ; CHECK-NEXT:   B %bb.1
   bb.0.entry:
     liveins: $q0, $q1, $q2, $x0
 
     %4:gpr64common = COPY $x0
     %3:fpr128 = COPY $q2
     %2:fpr128 = COPY $q1
     %1:fpr128 = COPY $q0
     %0:fpr128 = DUPv8i16lane %1, 0
 
   bb.1.for.cond:
-    %5:fpr128 = FMULv8f16 %2, %0
-    %6:fpr128 = FADDv8f16 killed %5, %3
+    %5:fpr128 = FMULv8f16 %2, %0, implicit $fpcr
+    %6:fpr128 = FADDv8f16 killed %5, %3, implicit $fpcr
     STRQui killed %6, %4, 0 :: (store 16 into %ir.ret)
     B %bb.1
 
 ...
 ---
 name:            kill_state
 alignment:       16
 tracksRegLiveness: true
body:             |
   ; CHECK-NEXT:   [[DUPv2i32lane:%[0-9]+]]:fpr64 = DUPv2i32lane [[INSERT_SUBREG]], 0
   ; CHECK-NEXT:   [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
   ; CHECK-NEXT:   [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY]], %subreg.ssub
   ; CHECK-NEXT:   [[INSvi32lane:%[0-9]+]]:fpr128 = INSvi32lane [[INSERT_SUBREG]], 1, killed [[INSERT_SUBREG1]], 0
   ; CHECK-NEXT:   [[COPY8:%[0-9]+]]:fpr64 = COPY [[INSvi32lane]].dsub
   ; CHECK-NEXT:   STRDui killed [[COPY8]], [[COPY1]], 0 :: (store (s64) into %ir.ret2)
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1.for.cond:
-  ; CHECK-NEXT:   [[FMULv2i32_indexed:%[0-9]+]]:fpr64 = FMULv2i32_indexed [[COPY7]], [[INSERT_SUBREG]], 0
-  ; CHECK-NEXT:   [[FADDv2f32_:%[0-9]+]]:fpr64 = FADDv2f32 killed [[FMULv2i32_indexed]], [[COPY6]]
+  ; CHECK-NEXT:   [[FMULv2i32_indexed:%[0-9]+]]:fpr64 = FMULv2i32_indexed [[COPY7]], [[INSERT_SUBREG]], 0, implicit $fpcr
+  ; CHECK-NEXT:   [[FADDv2f32_:%[0-9]+]]:fpr64 = FADDv2f32 killed [[FMULv2i32_indexed]], [[COPY6]], implicit $fpcr
   ; CHECK-NEXT:   STRDui killed [[FADDv2f32_]], [[COPY2]], 0 :: (store (s64) into %ir.ret, align 16)
   ; CHECK-NEXT:   B %bb.1
   bb.0.entry:
     liveins: $d0, $d1, $d2, $x0, $x1, $s3
 
     %6:fpr32 = COPY $s3
     %5:gpr64common = COPY $x1
     %4:gpr64common = COPY $x0
     %3:fpr64 = COPY $d2
     %2:fpr64 = COPY $d1
     %1:fpr64 = COPY $d0
     %10:fpr128 = IMPLICIT_DEF
     %9:fpr128 = INSERT_SUBREG %10, %1, %subreg.dsub
     %8:fpr64 = COPY %3
     %7:fpr64 = COPY %2
     %0:fpr64 = DUPv2i32lane %9, 0
     %12:fpr128 = IMPLICIT_DEF
     %11:fpr128 = INSERT_SUBREG %12, %6, %subreg.ssub
     %13:fpr128 = INSvi32lane killed %9, 1, killed %11, 0
     %14:fpr64 = COPY %13.dsub
     STRDui killed %14, %5, 0 :: (store (s64) into %ir.ret2)
 
   bb.1.for.cond:
-    %15:fpr64 = FMULv2f32 %7, %0
-    %16:fpr64 = FADDv2f32 killed %15, %8
+    %15:fpr64 = FMULv2f32 %7, %0, implicit $fpcr
+    %16:fpr64 = FADDv2f32 killed %15, %8, implicit $fpcr
     STRDui killed %16, %4, 0 :: (store (s64) into %ir.ret, align 16)
     B %bb.1
 
 ...
 ---
 name:            extracopy
 alignment:       16
 tracksRegLiveness: true
body:             |
   ; CHECK-NEXT:   [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
   ; CHECK-NEXT:   [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY3]], %subreg.dsub
   ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:fpr64 = COPY [[COPY1]]
   ; CHECK-NEXT:   [[COPY5:%[0-9]+]]:fpr64 = COPY [[COPY2]]
   ; CHECK-NEXT:   [[DUPv2i32lane:%[0-9]+]]:fpr64 = DUPv2i32lane [[INSERT_SUBREG]], 0
   ; CHECK-NEXT:   [[COPY6:%[0-9]+]]:fpr64 = COPY [[DUPv2i32lane]]
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1:
-  ; CHECK-NEXT:   [[FMULv2i32_indexed:%[0-9]+]]:fpr64 = FMULv2i32_indexed [[COPY5]], [[INSERT_SUBREG]], 0
-  ; CHECK-NEXT:   [[FADDv2f32_:%[0-9]+]]:fpr64 = FADDv2f32 killed [[FMULv2i32_indexed]], [[COPY4]]
+  ; CHECK-NEXT:   [[FMULv2i32_indexed:%[0-9]+]]:fpr64 = FMULv2i32_indexed [[COPY5]], [[INSERT_SUBREG]], 0, implicit $fpcr
+  ; CHECK-NEXT:   [[FADDv2f32_:%[0-9]+]]:fpr64 = FADDv2f32 killed [[FMULv2i32_indexed]], [[COPY4]], implicit $fpcr
   ; CHECK-NEXT:   STRDui killed [[FADDv2f32_]], [[COPY]], 0 :: (store (s64), align 16)
   ; CHECK-NEXT:   B %bb.1
   bb.0:
     liveins: $d0, $d1, $d2, $x0
 
     %4:gpr64common = COPY $x0
     %3:fpr64 = COPY $d2
     %2:fpr64 = COPY $d1
     %1:fpr64 = COPY $d0
     %8:fpr128 = IMPLICIT_DEF
     %7:fpr128 = INSERT_SUBREG %8, %1, %subreg.dsub
     %6:fpr64 = COPY %3
     %5:fpr64 = COPY %2
     %11:fpr64 = DUPv2i32lane killed %7, 0
     %0:fpr64 = COPY %11
 
   bb.1:
-    %9:fpr64 = FMULv2f32 %5, %0
-    %10:fpr64 = FADDv2f32 killed %9, %6
+    %9:fpr64 = FMULv2f32 %5, %0, implicit $fpcr
+    %10:fpr64 = FADDv2f32 killed %9, %6, implicit $fpcr
     STRDui killed %10, %4, 0 :: (store 8, align 16)
     B %bb.1
 
 ...

llvm/test/CodeGen/AArch64/machine-combiner-instr-fmf.mir

 # RUN: llc -run-pass=machine-combiner -o - -simplify-mir -mtriple=arm64-apple-iphoneos %s | FileCheck %s
 
 # Can create FMADD, because both the fmul and fadd have all fast-math flags.
 #
 # CHECK-LABEL: name: scalar_fmadd_fast
 # CHECK:        [[C:%.*]]:fpr32 = COPY $s2
 # CHECK-NEXT:   [[B:%.*]]:fpr32 = COPY $s1
 # CHECK-NEXT:   [[A:%.*]]:fpr32 = COPY $s0
-# CHECK-NEXT:   :fpr32 = nnan ninf nsz arcp contract afn reassoc FMADDSrrr [[B]], [[A]], [[C]]
+# CHECK-NEXT:   :fpr32 = nnan ninf nsz arcp contract afn reassoc FMADDSrrr [[B]], [[A]], [[C]], implicit $fpcr
 ---
 name:            scalar_fmadd_fast
 alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fpr32 }
   - { id: 1, class: fpr32 }
   - { id: 2, class: fpr32 }

 machineFunctionInfo: {}
 body:             |
   bb.0.entry:
     liveins: $s0, $s1, $s2
 
     %2:fpr32 = COPY $s2
     %1:fpr32 = COPY $s1
     %0:fpr32 = COPY $s0
-    %3:fpr32 = nnan ninf nsz arcp contract afn reassoc FMULSrr %1, %0
-    %4:fpr32 = nnan ninf nsz arcp contract afn reassoc FADDSrr killed %3, %2
+    %3:fpr32 = nnan ninf nsz arcp contract afn reassoc FMULSrr %1, %0, implicit $fpcr
+    %4:fpr32 = nnan ninf nsz arcp contract afn reassoc FADDSrr killed %3, %2, implicit $fpcr
     $s0 = COPY %4
     RET_ReallyLR implicit $s0
 
 ...
 
 # Can create FMADD, because both the fmul and fadd have the contract fast-math flag.
 #
 # CHECK-LABEL: name: scalar_fmadd_contract
 # CHECK:        [[C:%.*]]:fpr32 = COPY $s2
 # CHECK-NEXT:   [[B:%.*]]:fpr32 = COPY $s1
 # CHECK-NEXT:   [[A:%.*]]:fpr32 = COPY $s0
-# CHECK-NEXT:   :fpr32 = contract FMADDSrrr [[B]], [[A]], [[C]]
+# CHECK-NEXT:   :fpr32 = contract FMADDSrrr [[B]], [[A]], [[C]], implicit $fpcr
 
 ---
 name:            scalar_fmadd_contract
 alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fpr32 }
   - { id: 1, class: fpr32 }

 machineFunctionInfo: {}
 body:             |
   bb.0.entry:
     liveins: $s0, $s1, $s2
 
     %2:fpr32 = COPY $s2
     %1:fpr32 = COPY $s1
     %0:fpr32 = COPY $s0
-    %3:fpr32 = contract FMULSrr %1, %0
-    %4:fpr32 = contract FADDSrr killed %3, %2
+    %3:fpr32 = contract FMULSrr %1, %0, implicit $fpcr
+    %4:fpr32 = contract FADDSrr killed %3, %2, implicit $fpcr
     $s0 = COPY %4
     RET_ReallyLR implicit $s0
 
 ...
 
 # Do not create FMADD, because we don't have the contract flag on the FADD.
 
 # CHECK-LABEL: name: scalar_fmadd_contract_op0
 # CHECK:        [[C:%.*]]:fpr32 = COPY $s2
 # CHECK-NEXT:   [[B:%.*]]:fpr32 = COPY $s1
 # CHECK-NEXT:   [[A:%.*]]:fpr32 = COPY $s0
-# CHECK-NEXT:   [[MUL:%.*]]:fpr32 = contract FMULSrr [[B]], [[A]]
-# CHECK-NEXT:   fpr32 = FADDSrr killed [[MUL]], [[C]]
+# CHECK-NEXT:   [[MUL:%.*]]:fpr32 = contract FMULSrr [[B]], [[A]], implicit $fpcr
+# CHECK-NEXT:   fpr32 = FADDSrr killed [[MUL]], [[C]], implicit $fpcr
 ---
 name:            scalar_fmadd_contract_op0
 alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fpr32 }
   - { id: 1, class: fpr32 }
   - { id: 2, class: fpr32 }

 machineFunctionInfo: {}
 body:             |
   bb.0.entry:
     liveins: $s0, $s1, $s2
 
     %2:fpr32 = COPY $s2
     %1:fpr32 = COPY $s1
     %0:fpr32 = COPY $s0
-    %3:fpr32 = contract FMULSrr %1, %0
-    %4:fpr32 = FADDSrr killed %3, %2
+    %3:fpr32 = contract FMULSrr %1, %0, implicit $fpcr
+    %4:fpr32 = FADDSrr killed %3, %2, implicit $fpcr
     $s0 = COPY %4
     RET_ReallyLR implicit $s0
 
 ...
 
 # Do create FMADD, because we have the contract flag on the FADD.
 #
 # CHECK-LABEL: name: scalar_fmadd_contract_op1
 # CHECK:        [[C:%.*]]:fpr32 = COPY $s2
 # CHECK-NEXT:   [[B:%.*]]:fpr32 = COPY $s1
 # CHECK-NEXT:   [[A:%.*]]:fpr32 = COPY $s0
-# CHECK-NEXT:   :fpr32 = contract FMADDSrrr [[B]], [[A]], [[C]]
+# CHECK-NEXT:   :fpr32 = contract FMADDSrrr [[B]], [[A]], [[C]], implicit $fpcr
 
 ---
 name:            scalar_fmadd_contract_op1
 alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fpr32 }
   - { id: 1, class: fpr32 }

 machineFunctionInfo: {}
 body:             |
   bb.0.entry:
     liveins: $s0, $s1, $s2
 
     %2:fpr32 = COPY $s2
     %1:fpr32 = COPY $s1
     %0:fpr32 = COPY $s0
-    %3:fpr32 = FMULSrr %1, %0
-    %4:fpr32 = contract FADDSrr killed %3, %2
+    %3:fpr32 = FMULSrr %1, %0, implicit $fpcr
+    %4:fpr32 = contract FADDSrr killed %3, %2, implicit $fpcr
     $s0 = COPY %4
     RET_ReallyLR implicit $s0
 
 ...
 
 # Do not create FMADD, as nsz flag does not allow it.
 #
 # CHECK-LABEL: name: scalar_fmadd_nsz
 # CHECK:        [[C:%.*]]:fpr32 = COPY $s2
 # CHECK-NEXT:   [[B:%.*]]:fpr32 = COPY $s1
 # CHECK-NEXT:   [[A:%.*]]:fpr32 = COPY $s0
-# CHECK-NEXT:   [[MUL:%.*]]:fpr32 = nsz FMULSrr [[B]], [[A]]
-# CHECK-NEXT:   fpr32 = nsz FADDSrr killed [[MUL]], [[C]]
+# CHECK-NEXT:   [[MUL:%.*]]:fpr32 = nsz FMULSrr [[B]], [[A]], implicit $fpcr
+# CHECK-NEXT:   fpr32 = nsz FADDSrr killed [[MUL]], [[C]], implicit $fpcr
 
 ---
 name:            scalar_fmadd_nsz
 alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fpr32 }
   - { id: 1, class: fpr32 }

 machineFunctionInfo: {}
 body:             |
   bb.0.entry:
     liveins: $s0, $s1, $s2
 
     %2:fpr32 = COPY $s2
     %1:fpr32 = COPY $s1
     %0:fpr32 = COPY $s0
-    %3:fpr32 = nsz FMULSrr %1, %0
-    %4:fpr32 = nsz FADDSrr killed %3, %2
+    %3:fpr32 = nsz FMULSrr %1, %0, implicit $fpcr
+    %4:fpr32 = nsz FADDSrr killed %3, %2, implicit $fpcr
     $s0 = COPY %4
     RET_ReallyLR implicit $s0
 
 ...
 
 # Can create FMLA, because both the fmul and fadd have all fast-math flags.
 #
 # CHECK-LABEL: name: vector_fmadd_fast
 # CHECK:       [[C:%.*]]:fpr128 = COPY $q2
 # CHECK-NEXT:  [[B:%.*]]:fpr128 = COPY $q1
 # CHECK-NEXT:  [[A:%.*]]:fpr128 = COPY $q0
-# CHECK-NEXT:  fpr128 = nnan ninf nsz arcp contract afn reassoc FMLAv2f64 [[C]], [[B]], [[A]]
+# CHECK-NEXT:  fpr128 = nnan ninf nsz arcp contract afn reassoc FMLAv2f64 [[C]], [[B]], [[A]], implicit $fpcr
 ---
 name:            vector_fmadd_fast
 alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fpr128 }
   - { id: 1, class: fpr128 }
   - { id: 2, class: fpr128 }

 machineFunctionInfo: {}
 body:             |
   bb.0.entry:
     liveins: $q0, $q1, $q2
 
     %2:fpr128 = COPY $q2
     %1:fpr128 = COPY $q1
     %0:fpr128 = COPY $q0
-    %3:fpr128 = nnan ninf nsz arcp contract afn reassoc FMULv2f64 %1, %0
-    %4:fpr128 = nnan ninf nsz arcp contract afn reassoc FADDv2f64 killed %3, %2
+    %3:fpr128 = nnan ninf nsz arcp contract afn reassoc FMULv2f64 %1, %0, implicit $fpcr
+    %4:fpr128 = nnan ninf nsz arcp contract afn reassoc FADDv2f64 killed %3, %2, implicit $fpcr
     $q0 = COPY %4
     RET_ReallyLR implicit $q0
 
 ...
 
 # Can create FMLA, because both the fmul and fadd have the contract fast-math flag.
 #
 # CHECK-LABEL: name: vector_fmadd_contract
 # CHECK:       [[C:%.*]]:fpr128 = COPY $q2
 # CHECK-NEXT:  [[B:%.*]]:fpr128 = COPY $q1
 # CHECK-NEXT:  [[A:%.*]]:fpr128 = COPY $q0
-# CHECK-NEXT:  fpr128 = contract FMLAv2f64 [[C]], [[B]], [[A]]
+# CHECK-NEXT:  fpr128 = contract FMLAv2f64 [[C]], [[B]], [[A]], implicit $fpcr
 ---
 name:            vector_fmadd_contract
 alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fpr128 }
   - { id: 1, class: fpr128 }
   - { id: 2, class: fpr128 }

 machineFunctionInfo: {}
 body:             |
   bb.0.entry:
     liveins: $q0, $q1, $q2
 
     %2:fpr128 = COPY $q2
     %1:fpr128 = COPY $q1
     %0:fpr128 = COPY $q0
-    %3:fpr128 = contract FMULv2f64 %1, %0
-    %4:fpr128 = contract FADDv2f64 killed %3, %2
+    %3:fpr128 = contract FMULv2f64 %1, %0, implicit $fpcr
+    %4:fpr128 = contract FADDv2f64 killed %3, %2, implicit $fpcr
     $q0 = COPY %4
     RET_ReallyLR implicit $q0
 
 ...
 
 # Do not create FMLA, because we don't have the contract flag on the FADD.
 #
 # CHECK-LABEL: name: vector_fmadd_contract_op0
 # CHECK:       [[C:%.*]]:fpr128 = COPY $q2
 # CHECK-NEXT:  [[B:%.*]]:fpr128 = COPY $q1
 # CHECK-NEXT:  [[A:%.*]]:fpr128 = COPY $q0
-# CHECK-NEXT:  [[MUL:%.*]]:fpr128 = contract FMULv2f64 [[B]], [[A]]
-# CHECK-NEXT:  fpr128 = FADDv2f64 killed [[MUL]], [[C]]
+# CHECK-NEXT:  [[MUL:%.*]]:fpr128 = contract FMULv2f64 [[B]], [[A]], implicit $fpcr
+# CHECK-NEXT:  fpr128 = FADDv2f64 killed [[MUL]], [[C]], implicit $fpcr
 ---
 name:            vector_fmadd_contract_op0
 alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fpr128 }
   - { id: 1, class: fpr128 }
   - { id: 2, class: fpr128 }

 machineFunctionInfo: {}
 body:             |
   bb.0.entry:
     liveins: $q0, $q1, $q2
 
     %2:fpr128 = COPY $q2
     %1:fpr128 = COPY $q1
     %0:fpr128 = COPY $q0
-    %3:fpr128 = contract FMULv2f64 %1, %0
-    %4:fpr128 = FADDv2f64 killed %3, %2
+    %3:fpr128 = contract FMULv2f64 %1, %0, implicit $fpcr
+    %4:fpr128 = FADDv2f64 killed %3, %2, implicit $fpcr
     $q0 = COPY %4
     RET_ReallyLR implicit $q0
 
 ...
 
 # Do create FMLA, because we have the contract flag on the FADD.
 #
 # CHECK-LABEL: name: vector_fmadd_contract_op1
 # CHECK:       [[C:%.*]]:fpr128 = COPY $q2
 # CHECK-NEXT:  [[B:%.*]]:fpr128 = COPY $q1
 # CHECK-NEXT:  [[A:%.*]]:fpr128 = COPY $q0
-# CHECK-NEXT:  fpr128 = contract FMLAv2f64 [[C]], [[B]], [[A]]
+# CHECK-NEXT:  fpr128 = contract FMLAv2f64 [[C]], [[B]], [[A]], implicit $fpcr
 
 ---
 name:            vector_fmadd_contract_op1
 alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fpr128 }
   - { id: 1, class: fpr128 }

 machineFunctionInfo: {}
 body:             |
   bb.0.entry:
     liveins: $q0, $q1, $q2
 
     %2:fpr128 = COPY $q2
     %1:fpr128 = COPY $q1
     %0:fpr128 = COPY $q0
-    %3:fpr128 = FMULv2f64 %1, %0
-    %4:fpr128 = contract FADDv2f64 killed %3, %2
+    %3:fpr128 = FMULv2f64 %1, %0, implicit $fpcr
+    %4:fpr128 = contract FADDv2f64 killed %3, %2, implicit $fpcr
     $q0 = COPY %4
     RET_ReallyLR implicit $q0
 
 ...
 
 # Do not create FMLA, as nsz flag does not allow it.
 #
 # CHECK-LABEL: name: vector_fmadd_nsz
 # CHECK:       [[C:%.*]]:fpr128 = COPY $q2
 # CHECK-NEXT:  [[B:%.*]]:fpr128 = COPY $q1
 # CHECK-NEXT:  [[A:%.*]]:fpr128 = COPY $q0
-# CHECK-NEXT:  [[MUL:%.*]]:fpr128 = nsz FMULv2f64 [[B]], [[A]]
-# CHECK-NEXT:  fpr128 = nsz FADDv2f64 killed [[MUL]], [[C]]
+# CHECK-NEXT:  [[MUL:%.*]]:fpr128 = nsz FMULv2f64 [[B]], [[A]], implicit $fpcr
+# CHECK-NEXT:  fpr128 = nsz FADDv2f64 killed [[MUL]], [[C]], implicit $fpcr
 ---
 name:            vector_fmadd_nsz
 alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fpr128 }
   - { id: 1, class: fpr128 }
   - { id: 2, class: fpr128 }

 machineFunctionInfo: {}
 body:             |
   bb.0.entry:
     liveins: $q0, $q1, $q2
 
     %2:fpr128 = COPY $q2
     %1:fpr128 = COPY $q1
     %0:fpr128 = COPY $q0
-    %3:fpr128 = nsz FMULv2f64 %1, %0
-    %4:fpr128 = nsz FADDv2f64 killed %3, %2
+    %3:fpr128 = nsz FMULv2f64 %1, %0, implicit $fpcr
+    %4:fpr128 = nsz FADDv2f64 killed %3, %2, implicit $fpcr
     $q0 = COPY %4
     RET_ReallyLR implicit $q0
 
 ...

llvm/test/CodeGen/AArch64/machine-combiner-reassociate.mir

 # RUN: llc -run-pass=machine-combiner -mtriple=aarch64-unknown-linux-gnu %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SAFE
 # RUN: llc -run-pass=machine-combiner -mtriple=aarch64-unknown-linux-gnu -enable-unsafe-fp-math %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-UNSAFE
 
 # fadd without the reassoc flags can be reassociate only when unsafe fp math is
 # enabled.
 # CHECK-LABEL: name: fadd_no_reassoc
-# CHECK:             [[ADD1:%[0-9]+]]:fpr32 = FADDSrr %0, %1
-# CHECK-SAFE-NEXT:   [[ADD2:%[0-9]+]]:fpr32 = FADDSrr killed [[ADD1]], %2
-# CHECK-SAFE-NEXT:   [[ADD3:%[0-9]+]]:fpr32 = FADDSrr killed [[ADD2]], %3
-# CHECK-UNSAFE-NEXT: [[ADD2:%[0-9]+]]:fpr32 = FADDSrr %2, %3
-# CHECK-UNSAFE-NEXT: [[ADD3:%[0-9]+]]:fpr32 = FADDSrr killed [[ADD1]], killed [[ADD2]]
+# CHECK:             [[ADD1:%[0-9]+]]:fpr32 = FADDSrr %0, %1, implicit $fpcr
+# CHECK-SAFE-NEXT:   [[ADD2:%[0-9]+]]:fpr32 = FADDSrr killed [[ADD1]], %2, implicit $fpcr
+# CHECK-SAFE-NEXT:   [[ADD3:%[0-9]+]]:fpr32 = FADDSrr killed [[ADD2]], %3, implicit $fpcr
+# CHECK-UNSAFE-NEXT: [[ADD2:%[0-9]+]]:fpr32 = FADDSrr %2, %3, implicit $fpcr
+# CHECK-UNSAFE-NEXT: [[ADD3:%[0-9]+]]:fpr32 = FADDSrr killed [[ADD1]], killed [[ADD2]], implicit $fpcr
 ---
 name:            fadd_no_reassoc
 alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fpr32 }
   - { id: 1, class: fpr32 }
   - { id: 2, class: fpr32 }

 body:             |
   bb.0.entry:
     liveins: $s0, $s1, $s2, $s3
 
     %3:fpr32 = COPY $s3
     %2:fpr32 = COPY $s2
     %1:fpr32 = COPY $s1
     %0:fpr32 = COPY $s0
-    %4:fpr32 = FADDSrr %0, %1
-    %5:fpr32 = FADDSrr killed %4, %2
-    %6:fpr32 = FADDSrr killed %5, %3
+    %4:fpr32 = FADDSrr %0, %1, implicit $fpcr
+    %5:fpr32 = FADDSrr killed %4, %2, implicit $fpcr
+    %6:fpr32 = FADDSrr killed %5, %3, implicit $fpcr
     $s0 = COPY %6
     RET_ReallyLR implicit $s0
 
 
 # FIXME: We should be able to reassociate without unsafe fp math, but currently
 # the reassoc flag is ignored.
 # CHECK-LABEL: name: fadd_reassoc
-# CHECK:             [[ADD1:%[0-9]+]]:fpr32 = reassoc FADDSrr %0, %1
-# CHECK-SAFE-NEXT:   [[ADD2:%[0-9]+]]:fpr32 = reassoc FADDSrr killed [[ADD1]], %2
-# CHECK-SAFE-NEXT:   [[ADD3:%[0-9]+]]:fpr32 = reassoc FADDSrr killed [[ADD2]], %3
-# CHECK-UNSAFE-NEXT: [[ADD2:%[0-9]+]]:fpr32 = reassoc FADDSrr %2, %3
-# CHECK-UNSAFE-NEXT: [[ADD3:%[0-9]+]]:fpr32 = reassoc FADDSrr killed [[ADD1]], killed [[ADD2]]
+# CHECK:             [[ADD1:%[0-9]+]]:fpr32 = reassoc FADDSrr %0, %1, implicit $fpcr
+# CHECK-SAFE-NEXT:   [[ADD2:%[0-9]+]]:fpr32 = reassoc FADDSrr killed [[ADD1]], %2, implicit $fpcr
+# CHECK-SAFE-NEXT:   [[ADD3:%[0-9]+]]:fpr32 = reassoc FADDSrr killed [[ADD2]], %3, implicit $fpcr
+# CHECK-UNSAFE-NEXT: [[ADD2:%[0-9]+]]:fpr32 = reassoc FADDSrr %2, %3, implicit $fpcr
+# CHECK-UNSAFE-NEXT: [[ADD3:%[0-9]+]]:fpr32 = reassoc FADDSrr killed [[ADD1]], killed [[ADD2]], implicit $fpcr
 ---
 name:            fadd_reassoc
 alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fpr32 }
   - { id: 1, class: fpr32 }
   - { id: 2, class: fpr32 }

 body:             |
   bb.0.entry:
     liveins: $s0, $s1, $s2, $s3
 
     %3:fpr32 = COPY $s3
     %2:fpr32 = COPY $s2
     %1:fpr32 = COPY $s1
     %0:fpr32 = COPY $s0
-    %4:fpr32 = reassoc FADDSrr %0, %1
-    %5:fpr32 = reassoc FADDSrr killed %4, %2
-    %6:fpr32 = reassoc FADDSrr killed %5, %3
+    %4:fpr32 = reassoc FADDSrr %0, %1, implicit $fpcr
+    %5:fpr32 = reassoc FADDSrr killed %4, %2, implicit $fpcr
+    %6:fpr32 = reassoc FADDSrr killed %5, %3, implicit $fpcr
     $s0 = COPY %6
     RET_ReallyLR implicit $s0
 
 
 # Check that flags on the instructions are preserved after reassociation.
 # CHECK-LABEL: name: fadd_flags
-# CHECK:             [[ADD1:%[0-9]+]]:fpr32 = nsz FADDSrr %0, %1
-# CHECK-SAFE-NEXT:   [[ADD2:%[0-9]+]]:fpr32 = nnan FADDSrr killed [[ADD1]], %2
-# CHECK-SAFE-NEXT:   [[ADD3:%[0-9]+]]:fpr32 = ninf FADDSrr killed [[ADD2]], %3
-# CHECK-UNSAFE-NEXT: [[ADD2:%[0-9]+]]:fpr32 = nnan FADDSrr %2, %3
-# CHECK-UNSAFE-NEXT: [[ADD3:%[0-9]+]]:fpr32 = ninf FADDSrr killed [[ADD1]], killed [[ADD2]]
+# CHECK:             [[ADD1:%[0-9]+]]:fpr32 = nsz FADDSrr %0, %1, implicit $fpcr
+# CHECK-SAFE-NEXT:   [[ADD2:%[0-9]+]]:fpr32 = nnan FADDSrr killed [[ADD1]], %2, implicit $fpcr
+# CHECK-SAFE-NEXT:   [[ADD3:%[0-9]+]]:fpr32 = ninf FADDSrr killed [[ADD2]], %3, implicit $fpcr
+# CHECK-UNSAFE-NEXT: [[ADD2:%[0-9]+]]:fpr32 = nnan FADDSrr %2, %3, implicit $fpcr
+# CHECK-UNSAFE-NEXT: [[ADD3:%[0-9]+]]:fpr32 = ninf FADDSrr killed [[ADD1]], killed [[ADD2]], implicit $fpcr
 ---
 name:            fadd_flags
 alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fpr32 }
   - { id: 1, class: fpr32 }
   - { id: 2, class: fpr32 }

 body:             |
   bb.0.entry:
     liveins: $s0, $s1, $s2, $s3
 
     %3:fpr32 = COPY $s3
     %2:fpr32 = COPY $s2
     %1:fpr32 = COPY $s1
     %0:fpr32 = COPY $s0
-    %4:fpr32 = nsz FADDSrr %0, %1
-    %5:fpr32 = nnan FADDSrr killed %4, %2
-    %6:fpr32 = ninf FADDSrr killed %5, %3
+    %4:fpr32 = nsz FADDSrr %0, %1, implicit $fpcr
+    %5:fpr32 = nnan FADDSrr killed %4, %2, implicit $fpcr
+    %6:fpr32 = ninf FADDSrr killed %5, %3, implicit $fpcr
     $s0 = COPY %6
     RET_ReallyLR implicit $s0

llvm/test/CodeGen/AArch64/machine-combiner.mir

bb.0:
     %4 = SUBSWrr %1, %2, implicit-def $nzcv
     Bcc 13, %bb.2, implicit $nzcv
     B %bb.1
 
   bb.1:
     ; CHECK: MADDWrrr %1, %2, %3
     %5 = MADDWrrr %1, %2, $wzr
     %6 = ADDWrr %3, killed %5
-    %7 = SCVTFUWDri killed %6
-    ; CHECK: FMADDDrrr %7, %7, %0
-    %8 = FMULDrr %7, %7
-    %9 = FADDDrr %0, killed %8
+    %7 = SCVTFUWDri killed %6, implicit $fpcr
+    ; CHECK: FMADDDrrr %7, %7, %0, implicit $fpcr
+    %8 = FMULDrr %7, %7, implicit $fpcr
+    %9 = FADDDrr %0, killed %8, implicit $fpcr
     $d0 = COPY %9
     RET_ReallyLR implicit $d0
 
   bb.2:
     $d0 = COPY %0
     RET_ReallyLR implicit $d0
 
 ...

llvm/test/CodeGen/AArch64/misched-predicate-virtreg.mir

 # RUN: llc -mcpu=exynos-m5 -mtriple=aarch64 -enable-misched -run-pass=machine-scheduler -debug-only=machine-scheduler %s -o /dev/null 2>&1 | FileCheck %s
 # REQUIRES: asserts
 
 # CHECK-LABEL: ********** MI Scheduling **********
 # CHECK:       SU(0):   %0:fpr128 = COPY $q1
 # CHECK-NEXT:    # preds left       : 0
 # CHECK-NEXT:    # succs left       : 1
 # CHECK-NEXT:    # rdefs left       : 0
 # CHECK-NEXT:    Latency            : 2
 # CHECK-NEXT:    Depth              : 0
 # CHECK-NEXT:    Height             : 12
 # CHECK-NEXT:    Successors:
 # CHECK-NEXT:      SU(1): Data Latency=2 Reg=%0
 # CHECK-NEXT:    Single Issue       : false;
-# CHECK-NEXT:  SU(1):   %1:fpr32 = FMINVv4i32v %0:fpr128
+# CHECK-NEXT:  SU(1):   %1:fpr32 = FMINVv4i32v %0:fpr128, implicit $fpcr
 # CHECK-NEXT:    # preds left       : 1
 # CHECK-NEXT:    # succs left       : 1
 # CHECK-NEXT:    # rdefs left       : 0
 # CHECK-NEXT:    Latency            : 8
 # CHECK-NEXT:    Depth              : 2
 # CHECK-NEXT:    Height             : 10
 # CHECK-NEXT:    Predecessors:
 # CHECK-NEXT:      SU(0): Data Latency=2 Reg=%0
 # CHECK-NEXT:    Successors:
 # CHECK-NEXT:      SU(2): Data Latency=8 Reg=%1
 # CHECK-NEXT:    Single Issue       : false;
 
 name: test_qform_virtreg
 tracksRegLiveness: true
 body: |
   bb.0:
     liveins: $s0, $q1
     %0:fpr128 = COPY $q1
-    %1:fpr32 = FMINVv4i32v %0:fpr128
+    %1:fpr32 = FMINVv4i32v %0:fpr128, implicit $fpcr
     $s0 = COPY %1
     RET_ReallyLR implicit $s0
 

llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir

 ---
 # CHECK-LABEL: name: test6
 # CHECK-LABEL: bb.0:
 # CHECK:    liveins: $x0, $x1, $q3
 
 # CHECK:         renamable $q9 = LDRQui $x0, 0 :: (load (s128))
 # CHECK-NEXT:    renamable $q9 = XTNv8i16 renamable $q9, killed renamable $q3
 # CHECK-NEXT:    STRQui renamable $q9, renamable $x0, 11 :: (store (s128), align 4)
-# CHECK-NEXT:    renamable $q9 = FADDv2f64 renamable $q9, renamable $q9
+# CHECK-NEXT:    renamable $q9 = FADDv2f64 renamable $q9, renamable $q9, implicit $fpcr
 # CHECK-NEXT:    STRQui renamable $q9, renamable $x0, 10 :: (store (s128), align 4)
 # CHECK-NEXT:    RET undef $lr
 
 # XTN has a tied use-def.
 name:            test6
 alignment:       4
 tracksRegLiveness: true
 liveins:
   - { reg: '$x0' }
   - { reg: '$x1' }
   - { reg: '$x8' }
   - { reg: '$q3' }
 frameInfo:
   maxAlignment:    1
   maxCallFrameSize: 0
 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $x0, $x1, $q3
     renamable $q9 = LDRQui $x0, 0 :: (load (s128))
     renamable $q9 = XTNv8i16 renamable $q9, killed renamable $q3
     STRQui renamable $q9, renamable $x0, 11 :: (store (s128), align 4)
-    renamable $q9 = FADDv2f64 renamable $q9, renamable $q9
+    renamable $q9 = FADDv2f64 renamable $q9, renamable $q9, implicit $fpcr
     STRQui renamable $q9, renamable $x0, 10 :: (store (s128), align 4)
     RET undef $lr
 
 ...
 ---
 # Currently we do not rename across frame-setup instructions.
 # CHECK-LABEL: name: test7
 # CHECK-LABEL: bb.0:

 
 ...
 ---
 # The livein $q7 is killed early, so we can re-use it for renaming.
 # CHECK-LABEL: name: test10
 # CHECK-LABEL: bb.0:
 # CHECK:    liveins: $x0, $x1, $q0, $q1, $q2, $q3, $q4, $q5, $q6, $q7
 
-# CHECK:         renamable $q7 = FADDv2f64 renamable $q7, renamable $q7
+# CHECK:         renamable $q7 = FADDv2f64 renamable $q7, renamable $q7, implicit $fpcr
 # CHECK-NEXT:    STRQui killed renamable $q7, renamable $x0, 100 :: (store (s128), align 4)
 # CHECK-NEXT:    $q7 = LDRQui $x0, 0 :: (load (s128))
 # CHECK-NEXT:    renamable $q9 = LDRQui $x0, 1 :: (load (s128))
 # CHECK-NEXT:    STPQi killed renamable $q9, killed $q7, renamable $x0, 10 :: (store (s128), align 4)
 # CHECK-NEXT:    RET undef $lr
 
 name:            test10
 alignment:       4
 tracksRegLiveness: true
 liveins:
   - { reg: '$x0' }
   - { reg: '$x1' }
   - { reg: '$x8' }
   - { reg: '$q3' }
 frameInfo:
   maxAlignment:    1
   maxCallFrameSize: 0
 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $x0, $x1, $q0, $q1, $q2, $q3, $q4, $q5, $q6, $q7
-    renamable $q7 = FADDv2f64 renamable $q7, renamable $q7
+    renamable $q7 = FADDv2f64 renamable $q7, renamable $q7, implicit $fpcr
     STRQui renamable killed $q7, renamable $x0, 100 :: (store (s128), align 4)
     renamable $q9 = LDRQui $x0, 0 :: (load (s128))
     STRQui renamable killed $q9, renamable $x0, 11 :: (store (s128), align 4)
     renamable $q9 = LDRQui $x0, 1 :: (load (s128))
     STRQui renamable killed $q9, renamable $x0, 10 :: (store (s128), align 4)
     RET undef $lr
 
 ...

llvm/test/CodeGen/AArch64/strict-fp-opt.ll

 ; CHECK: fdiv s0, s0, s1
 ; CHECK-NEXT: ret
 define void @unused_div_fpexcept_strict(float %x, float %y) #0 {
 entry:
   %add = call float @llvm.experimental.constrained.fdiv.f32(float %x, float %y, metadata !"round.tonearest", metadata !"fpexcept.strict") #0
   ret void
 }
 
+; CHECK-LABEL: unused_div_round_dynamic:
+; CHECK-NOT: fdiv
+; CHECK: ret
+define void @unused_div_round_dynamic(float %x, float %y) #0 {
+entry:
+  %add = call float @llvm.experimental.constrained.fdiv.f32(float %x, float %y, metadata !"round.dynamic", metadata !"fpexcept.ignore") #0
+  ret void
+}
+
 
 ; Machine CSE should eliminate the second add unless we have strict exceptions
 
 ; CHECK-LABEL: add_twice:
 ; CHECK: fadd [[ADD:s[0-9]+]], s0, s1
 ; CHECK-NEXT: cmp w0, #0
 ; CHECK-NEXT: fmul [[MUL:s[0-9]+]], [[ADD]], [[ADD]]
 ; CHECK-NEXT: fcsel s0, [[ADD]], [[MUL]], eq
if.then:
   %mul = call float @llvm.experimental.constrained.fmul.f32(float %add, float %add1, metadata !"round.tonearest", metadata !"fpexcept.strict") #0
   br label %if.end
 
 if.end:
   %a.0 = phi float [ %mul, %if.then ], [ %add, %entry ]
   ret float %a.0
 }
 
+; CHECK-LABEL: add_twice_round_dynamic:
+; CHECK: fadd s0, s0, s1
+; CHECK-NEXT: cbz w0, [[LABEL:.LBB[0-9_]+]]
+; CHECK-NOT: fadd
+; CHECK: fmul s0, s0, s0
+; CHECK: [[LABEL]]:
+; CHECK-NEXT: ret
+define float @add_twice_round_dynamic(float %x, float %y, i32 %n) #0 {
+entry:
+  %add = call float @llvm.experimental.constrained.fadd.f32(float %x, float %y, metadata !"round.dynamic", metadata !"fpexcept.ignore") #0
+  %tobool.not = icmp eq i32 %n, 0
+  br i1 %tobool.not, label %if.end, label %if.then
+
+if.then:
+  %add1 = call float @llvm.experimental.constrained.fadd.f32(float %x, float %y, metadata !"round.dynamic", metadata !"fpexcept.ignore") #0
+  %mul = call float @llvm.experimental.constrained.fmul.f32(float %add, float %add1, metadata !"round.dynamic", metadata !"fpexcept.ignore") #0
+  br label %if.end
+
+if.end:
+  %a.0 = phi float [ %mul, %if.then ], [ %add, %entry ]
+  ret float %a.0
+}
+
+
+; Two adds separated by llvm.set.rounding should be preserved when rounding is
+; dynamic (as they may give different results) or when we have strict exceptions
+; (the llvm.set.rounding is irrelevant, but both could trap).
+
+; CHECK-LABEL: set_rounding:
+; CHECK-DAG: fadd [[SREG:s[0-9]+]], s0, s1
+; CHECK-DAG: mrs [[XREG1:x[0-9]+]], FPCR
+; CHECK-DAG: orr [[XREG2:x[0-9]+]], [[XREG1]], #0xc00000
+; CHECK: msr FPCR, [[XREG2]]
+; CHECK-NEXT: mrs [[XREG3:x[0-9]+]], FPCR
+; CHECK-NEXT: and [[XREG4:x[0-9]+]], [[XREG3]], #0xffffffffff3fffff
+; CHECK-NEXT: msr FPCR, [[XREG4]]
+; CHECK-NEXT: fsub s0, [[SREG]], [[SREG]]
+; CHECK-NEXT: ret
+define float @set_rounding(float %x, float %y) #0 {
+entry:
+  %add1 = fadd float %x, %y
+  call void @llvm.set.rounding(i32 0)
+  %add2 = fadd float %x, %y
+  call void @llvm.set.rounding(i32 1)
+  %sub = fsub float %add1, %add2
+  ret float %sub
+}
+
+; CHECK-LABEL: set_rounding_fpexcept_strict:
+; CHECK-DAG: fadd [[SREG1:s[0-9]+]], s0, s1
+; CHECK-DAG: mrs [[XREG1:x[0-9]+]], FPCR
+; CHECK-DAG: orr [[XREG2:x[0-9]+]], [[XREG1]], #0xc00000
+; CHECK: msr FPCR, [[XREG2]]
+; CHECK-DAG: fadd [[SREG2:s[0-9]+]], s0, s1
+; CHECK-DAG: mrs [[XREG3:x[0-9]+]], FPCR
+; CHECK-DAG: and [[XREG4:x[0-9]+]], [[XREG3]], #0xffffffffff3fffff
+; CHECK-NEXT: msr FPCR, [[XREG4]]
+; CHECK-NEXT: fsub s0, [[SREG1]], [[SREG2]]
+; CHECK-NEXT: ret
+define float @set_rounding_fpexcept_strict(float %x, float %y) #0 {
+entry:
+  %add1 = call float @llvm.experimental.constrained.fadd.f32(float %x, float %y, metadata !"round.tonearest", metadata !"fpexcept.strict") #0
+  call void @llvm.set.rounding(i32 0)
+  %add2 = call float @llvm.experimental.constrained.fadd.f32(float %x, float %y, metadata !"round.tonearest", metadata !"fpexcept.strict") #0
+  call void @llvm.set.rounding(i32 1)
+  %sub = call float @llvm.experimental.constrained.fsub.f32(float %add1, float %add2, metadata !"round.tonearest", metadata !"fpexcept.strict") #0
+  ret float %sub
+}
+
+; CHECK-LABEL: set_rounding_round_dynamic:
+; CHECK-DAG: fadd [[SREG1:s[0-9]+]], s0, s1
+; CHECK-DAG: mrs [[XREG1:x[0-9]+]], FPCR
+; CHECK-DAG: orr [[XREG2:x[0-9]+]], [[XREG1]], #0xc00000
+; CHECK: msr FPCR, [[XREG2]]
+; CHECK-DAG: fadd [[SREG2:s[0-9]+]], s0, s1
+; CHECK-DAG: mrs [[XREG3:x[0-9]+]], FPCR
+; CHECK-DAG: and [[XREG4:x[0-9]+]], [[XREG3]], #0xffffffffff3fffff
+; CHECK-NEXT: msr FPCR, [[XREG4]]
+; CHECK-NEXT: fsub s0, [[SREG1]], [[SREG2]]
+; CHECK-NEXT: ret
+define float @set_rounding_round_dynamic(float %x, float %y) #0 {
+entry:
+  %add1 = call float @llvm.experimental.constrained.fadd.f32(float %x, float %y, metadata !"round.dynamic", metadata !"fpexcept.ignore") #0
+  call void @llvm.set.rounding(i32 0)
+  %add2 = call float @llvm.experimental.constrained.fadd.f32(float %x, float %y, metadata !"round.dynamic", metadata !"fpexcept.ignore") #0
+  call void @llvm.set.rounding(i32 1)
+  %sub = call float @llvm.experimental.constrained.fsub.f32(float %add1, float %add2, metadata !"round.dynamic", metadata !"fpexcept.ignore") #0
+  ret float %sub
+}
+
 declare float @llvm.experimental.constrained.fadd.f32(float, float, metadata, metadata) #0
+declare float @llvm.experimental.constrained.fsub.f32(float, float, metadata, metadata) #0
 declare float @llvm.experimental.constrained.fmul.f32(float, float, metadata, metadata) #0
 declare float @llvm.experimental.constrained.fdiv.f32(float, float, metadata, metadata) #0
+declare i32 @llvm.flt.rounds()
+declare void @llvm.set.rounding(i32)
 
 attributes #0 = { "strictfp" }

llvm/test/CodeGen/AArch64/taildup-inst-dup-loc.mir

body:             |
   ; CHECK: bb.2:
   ; CHECK:   successors: %bb.3(0x40000000), %bb.4(0x40000000)
   ; CHECK:   $wzr = SUBSWri [[DEF1]], 19, 0, implicit-def $nzcv
   ; CHECK:   [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
   ; CHECK:   TBNZW [[CSINCWr]], 0, %bb.3
   ; CHECK:   B %bb.4
   ; CHECK: bb.3:
   ; CHECK:   successors: %bb.9(0x80000000)
-  ; CHECK:   [[SCVTFUXDri:%[0-9]+]]:fpr64 = SCVTFUXDri [[DEF2]]
+  ; CHECK:   [[SCVTFUXDri:%[0-9]+]]:fpr64 = SCVTFUXDri [[DEF2]], implicit $fpcr
   ; CHECK:   [[COPY:%[0-9]+]]:gpr64 = COPY [[SCVTFUXDri]]
   ; CHECK:   [[COPY1:%[0-9]+]]:fpr64 = COPY [[SCVTFUXDri]]
   ; CHECK:   B %bb.9
   ; CHECK: bb.4:
   ; CHECK:   successors: %bb.5(0x40000000), %bb.8(0x40000000)
   ; CHECK:   TBNZW [[DEF]], 0, %bb.5
   ; CHECK:   B %bb.8
   ; CHECK: bb.5:
bb.3:
     $wzr = SUBSWri %2, 19, 0, implicit-def $nzcv
     %15:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
     TBNZW %15, 0, %bb.4
     B %bb.5
 
   bb.4:
     successors: %bb.7(0x80000000)
 
-    %6:fpr64 = SCVTFUXDri %5
+    %6:fpr64 = SCVTFUXDri %5, implicit $fpcr
     B %bb.7
 
   bb.5:
     successors: %bb.6(0x40000000), %bb.9(0x40000000)
 
     TBNZW %1, 0, %bb.6
     B %bb.9
 

llvm/test/CodeGen/AArch64/wineh-frame1.mir

 fixedStack:
 stack:
 constants:
 body:             |
   bb.0.entry:
     liveins: $x0, $x1, $d0, $d1, $d10, $d11, $d8, $d9, $x27, $x28, $x25, $x26, $x23, $x24, $x21, $x22, $x19, $x20
 
     $x19 = ADDXrr $x0, killed $x1
-    $d8 = FADDDrr killed $d0, $d1
-    $d9 = FADDDrr $d8, $d1
-    $d10 = FADDDrr $d9, $d8
-    $d11 = FADDDrr killed $d9, $d10
+    $d8 = FADDDrr killed $d0, $d1, implicit $fpcr
+    $d9 = FADDDrr $d8, $d1, implicit $fpcr
+    $d10 = FADDDrr $d9, $d8, implicit $fpcr
+    $d11 = FADDDrr killed $d9, $d10, implicit $fpcr
     $x20 = ADDXrr $x19, killed $x0
     $x21 = ADDXrr $x20, killed $x19
     $x22 = ADDXrr $x21, killed $x20
     $x23 = ADDXrr $x22, killed $x21
     $x24 = ADDXrr $x23, killed $x22
     $x25 = ADDXrr $x24, killed $x23
     $x26 = ADDXrr $x25, killed $x24
     $x27 = ADDXrr $x26, killed $x25
     $x28 = ADDXrr $x27, killed $x26
     $x0 = COPY $d11
     $x0 = ADDXrr $x0, killed $x28
     RET_ReallyLR implicit $x0
 
 ...

llvm/test/CodeGen/AArch64/wineh-frame2.mir

frameInfo:
   restorePoint:    ''
 fixedStack:
 stack:
 constants:
 body:             |
   bb.0.entry:
     liveins: $x0, $x1, $d0, $d1, $d10, $d11, $d8, $d9
     $x19 = ADDXrr $x0, killed $x1
-    $d8 = FADDDrr killed $d0, $d1
-    $d9 = FADDDrr $d8, $d1
-    $d10 = FADDDrr $d9, $d8
-    $d11 = FADDDrr killed $d9, $d10
-    $d12 = FADDDrr $d11, killed $d11
+    $d8 = FADDDrr killed $d0, $d1, implicit $fpcr
+    $d9 = FADDDrr $d8, $d1, implicit $fpcr
+    $d10 = FADDDrr $d9, $d8, implicit $fpcr
+    $d11 = FADDDrr killed $d9, $d10, implicit $fpcr
+    $d12 = FADDDrr $d11, killed $d11, implicit $fpcr
     $x0 = COPY $d12
     RET_ReallyLR implicit $x0
 
 ...

llvm/test/CodeGen/AArch64/wineh-frame4.mir

frameInfo:
   savePoint:       ''
   restorePoint:    ''
 fixedStack:
 stack:
 constants:
 body:             |
   bb.0.entry:
     liveins: $d0, $d1
-    $d8 = FADDDrr $d0, killed $d1
-    $d10 = FADDDrr killed $d8, $d0
+    $d8 = FADDDrr $d0, killed $d1, implicit $fpcr
+    $d10 = FADDDrr killed $d8, $d0, implicit $fpcr
     $x0 = COPY killed $d10
     RET_ReallyLR implicit $x0
 ...

llvm/test/CodeGen/AArch64/wineh2.mir

bb.0.entry:
     frame-setup STPXi killed $x23, killed $x24, $sp, 10 :: (store (s64) into %stack.4), (store (s64) into %stack.5)
     frame-setup SEH_SaveRegP 23, 24, 80
     frame-setup STPXi killed $x21, killed $x22, $sp, 12 :: (store (s64) into %stack.2), (store (s64) into %stack.3)
     frame-setup SEH_SaveRegP 21, 22, 96
     frame-setup STPXi killed $x19, killed $x20, $sp, 14 :: (store (s64) into %stack.0), (store (s64) into %stack.1)
     frame-setup SEH_SaveRegP 19, 20, 112
     frame-setup SEH_PrologEnd
     $x19 = ADDXrr $x0, killed $x1
-    $d8 = FADDDrr killed $d0, $d1
-    $d9 = FADDDrr $d8, $d1
-    $d10 = FADDDrr $d9, $d8
-    $d11 = FADDDrr killed $d9, $d10
-    $d12 = FADDDrr killed $d10, killed $d11
+    $d8 = FADDDrr killed $d0, $d1, implicit $fpcr
+    $d9 = FADDDrr $d8, $d1, implicit $fpcr
+    $d10 = FADDDrr $d9, $d8, implicit $fpcr
+    $d11 = FADDDrr killed $d9, $d10, implicit $fpcr
+    $d12 = FADDDrr killed $d10, killed $d11, implicit $fpcr
     $x20 = ADDXrr $x19, killed $x0
     $x21 = ADDXrr $x20, killed $x19
     $x22 = ADDXrr $x21, killed $x20
     $x23 = ADDXrr $x22, killed $x21
     $x24 = ADDXrr $x23, killed $x22
     $x25 = ADDXrr $x24, killed $x23
     $x26 = ADDXrr $x25, killed $x24
     $x27 = ADDXrr $x26, killed $x25

llvm/test/CodeGen/AArch64/wineh3.mir

bb.0.entry:
     frame-setup STPXi killed $x23, killed $x24, $sp, 8 :: (store (s64) into %stack.4), (store (s64) into %stack.5)
     frame-setup SEH_SaveRegP 23, 24, 64
     frame-setup STPXi killed $x21, killed $x22, $sp, 10 :: (store (s64) into %stack.2), (store (s64) into %stack.3)
     frame-setup SEH_SaveRegP 21, 22, 80
     frame-setup STPXi killed $x19, killed $x20, $sp, 12 :: (store (s64) into %stack.0), (store (s64) into %stack.1)
     frame-setup SEH_SaveRegP 19, 20, 96
     frame-setup SEH_PrologEnd
     $x19 = ADDXrr $x0, killed $x1
-    $d8 = FADDDrr killed $d0, $d1
-    $d9 = FADDDrr $d8, $d1
-    $d10 = FADDDrr $d9, $d8
-    $d11 = FADDDrr killed $d9, $d10
+    $d8 = FADDDrr killed $d0, $d1, implicit $fpcr
+    $d9 = FADDDrr $d8, $d1, implicit $fpcr
+    $d10 = FADDDrr $d9, $d8, implicit $fpcr
+    $d11 = FADDDrr killed $d9, $d10, implicit $fpcr
     $x20 = ADDXrr $x19, killed $x0
     $x21 = ADDXrr $x20, killed $x19
     $x22 = ADDXrr $x21, killed $x20
     $x23 = ADDXrr $x22, killed $x21
     $x24 = ADDXrr $x23, killed $x22
     $x25 = ADDXrr $x24, killed $x23
     $x26 = ADDXrr $x25, killed $x24
     $x27 = ADDXrr $x26, killed $x25

llvm/test/CodeGen/AArch64/wineh4.mir

bb.0.entry:
     frame-setup CFI_INSTRUCTION offset $w26, -64
     frame-setup CFI_INSTRUCTION offset $w27, -72
     frame-setup CFI_INSTRUCTION offset $w28, -80
     frame-setup CFI_INSTRUCTION offset $b8, -88
     frame-setup CFI_INSTRUCTION offset $b9, -96
     frame-setup CFI_INSTRUCTION offset $b10, -104
     frame-setup CFI_INSTRUCTION offset $b11, -112
     $x19 = ADDXrr $x0, killed $x1
-    $d8 = FADDDrr killed $d0, $d1
-    $d9 = FADDDrr $d8, $d1
-    $d10 = FADDDrr $d9, $d8
-    $d11 = FADDDrr killed $d9, $d10
+    $d8 = FADDDrr killed $d0, $d1, implicit $fpcr
+    $d9 = FADDDrr $d8, $d1, implicit $fpcr
+    $d10 = FADDDrr $d9, $d8, implicit $fpcr
+    $d11 = FADDDrr killed $d9, $d10, implicit $fpcr
     $x20 = SUBSXrr $x19, killed $x0, implicit-def $nzcv
     Bcc 1, %bb.2, implicit killed $nzcv
     B %bb.1
 
   bb.1:
     liveins: $x19, $x20
 
     $x21 = ADDXrr $x20, killed $x19

llvm/test/CodeGen/AArch64/wineh8.mir

bb.0.entry:
     frame-setup CFI_INSTRUCTION offset $w26, -64
     frame-setup CFI_INSTRUCTION offset $w27, -72
     frame-setup CFI_INSTRUCTION offset $w28, -80
     frame-setup CFI_INSTRUCTION offset $b8, -88
     frame-setup CFI_INSTRUCTION offset $b9, -96
     frame-setup CFI_INSTRUCTION offset $b10, -104
     frame-setup CFI_INSTRUCTION offset $b11, -112
     $x19 = ADDXrr $x0, killed $x1
-    $d8 = FADDDrr killed $d0, $d1
-    $d9 = FADDDrr $d8, $d1
-    $d10 = FADDDrr $d9, $d8
-    $d11 = FADDDrr killed $d9, $d10
+    $d8 = FADDDrr killed $d0, $d1, implicit $fpcr
+    $d9 = FADDDrr $d8, $d1, implicit $fpcr
+    $d10 = FADDDrr $d9, $d8, implicit $fpcr
+    $d11 = FADDDrr killed $d9, $d10, implicit $fpcr
     $x20 = SUBSXrr $x19, killed $x0, implicit-def $nzcv
     Bcc 1, %bb.2, implicit killed $nzcv
     B %bb.1
 
   bb.1:
     liveins: $x19, $x20
 
     $x21 = ADDXrr $x20, killed $x19

llvm/test/CodeGen/MIR/AArch64/mirCanonIdempotent.mir

bb.0:
     %1:gpr64 = COPY $x1
     %0:gpr64common = COPY $x0
     STRXui %0, %stack.1, 0 :: (store (s64))
     STRXui %1, %stack.2, 0 :: (store (s64))
     STRDui %2, %stack.3, 0 :: (store (s64))
     STRDui %3, %stack.4, 0 :: (store (s64))
 
     %4:fpr64 = FMOVDi 20
-    %5:fpr64 = FADDDrr %2, killed %4
+    %5:fpr64 = FADDDrr %2, killed %4, implicit $fpcr
     STRDui %5, %stack.5, 0 :: (store (s64))
 
-    %6:gpr32 = FCVTZSUWDr %5
+    %6:gpr32 = FCVTZSUWDr %5, implicit $fpcr
     STRDroW %3, %0, killed %6, 1, 1
 
     %7:gpr64common = LDRXui %stack.1, 0 :: (dereferenceable load (s64))
     %8:fpr64 = LDRDui %stack.5, 0 :: (dereferenceable load (s64))
 
-    %9:gpr32common = FCVTZSUWDr killed %8
+    %9:gpr32common = FCVTZSUWDr killed %8, implicit $fpcr
     %10:fpr64 = LDRDroW %7, %9, 1, 1
 
     %11:gpr32common = ADDWri %9, 1, 0
     STRDroW killed %10, %7, killed %11, 1, 1
 
     %12:fpr64 = LDRDui %stack.5, 0 :: (dereferenceable load (s64))
     %13:gpr64common = LDRXui %stack.1, 0 :: (dereferenceable load (s64))
 
-    %14:gpr32common = FCVTZSUWDr %12
+    %14:gpr32common = FCVTZSUWDr %12, implicit $fpcr
     %15:gpr32common = ADDWri killed %14, 30, 0
     STRDroW %12, killed %13, killed %15, 1, 1
 
     %16:fpr64 = LDRDui %stack.5, 0 :: (dereferenceable load (s64))
     STRDui killed %16, %stack.6, 0 :: (store (s64))
 
     %19:fpr64 = FMOVDi 112
     %46:gpr32 = MOVi32imm 408
     %43:fpr64 = LDRDui %stack.5, 0 :: (dereferenceable load (s64))
     %44:gpr64 = LDRXui %stack.2, 0 :: (dereferenceable load (s64))
 
-    %45:gpr32 = FCVTZSUWDr %43
+    %45:gpr32 = FCVTZSUWDr %43, implicit $fpcr
     %47:gpr64common = SMADDLrrr killed %45, %46, killed %44
     %48:fpr64 = LDRDui %stack.6, 0 :: (dereferenceable load (s64))
 
-    %49:gpr32 = FCVTZSUWDr killed %48
+    %49:gpr32 = FCVTZSUWDr killed %48, implicit $fpcr
     STRDroW %43, killed %47, killed %49, 1, 1
 
     %21:gpr64 = LDRXui %stack.2, 0 :: (dereferenceable load (s64))
     %22:fpr64 = LDRDui %stack.5, 0 :: (dereferenceable load (s64))
 
-    %23:gpr32 = FCVTZSUWDr killed %22
+    %23:gpr32 = FCVTZSUWDr killed %22, implicit $fpcr
     %24:gpr32 = MOVi32imm 408
     %25:gpr64common = SMADDLrrr %23, %24, killed %21
     %26:gpr64sp = ADDXrx killed %25, %23, 51
     %27:fpr64 = LDURDi %26, -8
-    %29:fpr64 = FADDDrr killed %27, %19
+    %29:fpr64 = FADDDrr killed %27, %19, implicit $fpcr
     STURDi killed %29, %26, -8
 
     %30:gpr64common = LDRXui %stack.1, 0 :: (dereferenceable load (s64))
     %31:fpr64 = LDRDui %stack.5, 0 :: (dereferenceable load (s64))
 
-    %32:gpr32common = FCVTZSUWDr killed %31
+    %32:gpr32common = FCVTZSUWDr killed %31, implicit $fpcr
     %34:gpr64all = IMPLICIT_DEF
     %33:gpr64 = INSERT_SUBREG %34, %32, %subreg.sub_32
     %35:gpr64 = SBFMXri killed %33, 61, 31
     %36:fpr64 = LDRDroX killed %30, %35, 0, 0
     %37:gpr64 = LDRXui %stack.2, 0 :: (dereferenceable load (s64))
 
     %38:gpr32common = ADDWri %32, 20, 0
     %39:gpr64common = SMADDLrrr killed %38, %24, killed %37

llvm/test/DebugInfo/COFF/AArch64/codeview-b-register.mir

--- |
   !15 = distinct !DILexicalBlock(scope: !12, file: !5)
 ...
 ---
 name: test.fn
 body: |
   bb.0:
   liveins: $b0
   DBG_VALUE $b0, $noreg, !11, !DIExpression(), debug-location !13
-  renamable $s0 = nofpexcept FCVTSHr killed renamable $h0, debug-location !14
+  renamable $s0 = nofpexcept FCVTSHr killed renamable $h0, implicit $fpcr, debug-location !14
   DBG_VALUE $b0, $noreg, !11, !DIExpression(DW_OP_LLVM_entry_value, 1), debug-location !13
-  nofpexcept FCMPSri killed renamable $s0, implicit-def $nzcv, debug-location !14
+  nofpexcept FCMPSri killed renamable $s0, implicit-def $nzcv, implicit $fpcr, debug-location !14
   renamable $w0 = CSINCWr $wzr, $wzr, 0, implicit killed $nzcv, debug-location !14
   RET undef $lr, implicit killed $w0
 ...

llvm/test/DebugInfo/COFF/AArch64/codeview-h-register.mir

--- |
   !15 = distinct !DILexicalBlock(scope: !12, file: !5)
 ...
 ---
 name: test.fn
 body: |
   bb.0:
   liveins: $h0
   DBG_VALUE $h0, $noreg, !11, !DIExpression(), debug-location !13
-  renamable $s0 = nofpexcept FCVTSHr killed renamable $h0, debug-location !14
+  renamable $s0 = nofpexcept FCVTSHr killed renamable $h0, implicit $fpcr, debug-location !14
   DBG_VALUE $h0, $noreg, !11, !DIExpression(DW_OP_LLVM_entry_value, 1), debug-location !13
-  nofpexcept FCMPSri killed renamable $s0, implicit-def $nzcv, debug-location !14
+  nofpexcept FCMPSri killed renamable $s0, implicit-def $nzcv, implicit $fpcr, debug-location !14
   renamable $w0 = CSINCWr $wzr, $wzr, 0, implicit killed $nzcv, debug-location !14
   RET undef $lr, implicit killed $w0
 ...