[CodeGen] Track physical register liveness in ExpandPostRAPseudos
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Authored by foad on Nov 2 2021, 6:56 AM.

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Reviewers: None

Summary

Track physical register liveness in ExpandPostRAPseudos and pass the
LivePhysRegs info into the copyPhysReg target hook.

Diff Detail

Repository: rG LLVM Github Monorepo

Event Timeline

foad created this revision.Nov 2 2021, 6:56 AM

Herald added subscribers: asavonic, frasercrmck, kerbowa and 36 others. · View Herald TranscriptNov 2 2021, 6:56 AM

foad requested review of this revision.Nov 2 2021, 6:56 AM

Herald added a project: Restricted Project. · View Herald TranscriptNov 2 2021, 6:56 AM

Herald added subscribers: llvm-commits, MaskRay, aheejin. · View Herald Transcript

foad added a parent revision: D113015: [CodeGen] Handle dead defs in LivePhysRegs::stepForward.Nov 2 2021, 6:58 AM

foad added a child revision: D113017: [AMDGPU] Avoid copying dead subregisters in copyPhysReg.

Harbormaster completed remote builds in B131964: Diff 384080.Nov 2 2021, 7:33 AM

kito-cheng added a subscriber: kito-cheng.Jun 28 2022, 3:25 AM

Herald added a project: Restricted Project. · View Herald TranscriptJun 28 2022, 3:25 AM

Herald added subscribers: jsji, kosarev, jsilvanus and 5 others. · View Herald Transcript

Revision Contents
Changeset List

Path

Size

llvm/

include/

llvm/

CodeGen/

TargetInstrInfo.h

12 lines

lib/

CodeGen/

ExpandPostRAPseudos.cpp

78 lines

Target/

AArch64/

AArch64InstrInfo.h

8 lines

AArch64InstrInfo.cpp

3 lines

AMDGPU/

8 lines

3 lines

8 lines

5 lines

ARC/

ARCInstrInfo.h

8 lines

ARCInstrInfo.cpp

3 lines

ARM/

8 lines

3 lines

8 lines

3 lines

8 lines

3 lines

AVR/

AVRInstrInfo.h

8 lines

AVRInstrInfo.cpp

3 lines

BPF/

BPFInstrInfo.h

8 lines

BPFInstrInfo.cpp

3 lines

Hexagon/

HexagonInstrInfo.h

8 lines

HexagonInstrInfo.cpp

3 lines

Lanai/

LanaiInstrInfo.h

8 lines

LanaiInstrInfo.cpp

4 lines

M68k/

M68kInstrInfo.h

8 lines

M68kInstrInfo.cpp

3 lines

MSP430/

MSP430InstrInfo.h

8 lines

MSP430InstrInfo.cpp

3 lines

Mips/

8 lines

3 lines

8 lines

3 lines

NVPTX/

NVPTXInstrInfo.h

8 lines

NVPTXInstrInfo.cpp

3 lines

PowerPC/

PPCInstrInfo.h

8 lines

PPCInstrInfo.cpp

3 lines

RISCV/

RISCVInstrInfo.h

8 lines

RISCVInstrInfo.cpp

3 lines

Sparc/

SparcInstrInfo.h

8 lines

SparcInstrInfo.cpp

3 lines

SystemZ/

SystemZInstrInfo.h

8 lines

SystemZInstrInfo.cpp

3 lines

VE/

VEInstrInfo.h

8 lines

VEInstrInfo.cpp

3 lines

WebAssembly/

WebAssemblyInstrInfo.h

8 lines

WebAssemblyInstrInfo.cpp

3 lines

X86/

X86InstrInfo.h

8 lines

X86InstrInfo.cpp

3 lines

XCore/

XCoreInstrInfo.h

8 lines

XCoreInstrInfo.cpp

3 lines

Diff 384080

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llvm/include/llvm/CodeGen/TargetInstrInfo.h

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llvm/lib/CodeGen/ExpandPostRAPseudos.cpp

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llvm/lib/Target/AArch64/AArch64InstrInfo.h

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llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

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llvm/lib/Target/AMDGPU/R600InstrInfo.h

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llvm/lib/Target/AMDGPU/R600InstrInfo.cpp

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llvm/lib/Target/AMDGPU/SIInstrInfo.h

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llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

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llvm/lib/Target/ARC/ARCInstrInfo.h

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llvm/lib/Target/ARC/ARCInstrInfo.cpp

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llvm/lib/Target/ARM/ARMBaseInstrInfo.h

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llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp

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llvm/lib/Target/ARM/Thumb1InstrInfo.h

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llvm/lib/Target/ARM/Thumb1InstrInfo.cpp

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llvm/lib/Target/ARM/Thumb2InstrInfo.h

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llvm/lib/Target/ARM/Thumb2InstrInfo.cpp

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llvm/lib/Target/AVR/AVRInstrInfo.h

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llvm/lib/Target/AVR/AVRInstrInfo.cpp

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llvm/lib/Target/BPF/BPFInstrInfo.h

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llvm/lib/Target/BPF/BPFInstrInfo.cpp

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llvm/lib/Target/Hexagon/HexagonInstrInfo.h

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llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp

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llvm/lib/Target/Lanai/LanaiInstrInfo.h

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llvm/lib/Target/Lanai/LanaiInstrInfo.cpp

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llvm/lib/Target/M68k/M68kInstrInfo.h

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llvm/lib/Target/M68k/M68kInstrInfo.cpp

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llvm/lib/Target/MSP430/MSP430InstrInfo.h

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llvm/lib/Target/MSP430/MSP430InstrInfo.cpp

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llvm/lib/Target/Mips/Mips16InstrInfo.h

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llvm/lib/Target/Mips/Mips16InstrInfo.cpp

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llvm/lib/Target/Mips/MipsSEInstrInfo.h

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llvm/lib/Target/Mips/MipsSEInstrInfo.cpp

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llvm/lib/Target/NVPTX/NVPTXInstrInfo.h

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llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp

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llvm/lib/Target/PowerPC/PPCInstrInfo.h

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llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

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llvm/lib/Target/RISCV/RISCVInstrInfo.h

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llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

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llvm/lib/Target/Sparc/SparcInstrInfo.h

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llvm/lib/Target/Sparc/SparcInstrInfo.cpp

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llvm/lib/Target/SystemZ/SystemZInstrInfo.h

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llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp

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llvm/lib/Target/VE/VEInstrInfo.h

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llvm/lib/Target/VE/VEInstrInfo.cpp

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llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.h

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llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp

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llvm/lib/Target/X86/X86InstrInfo.h

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llvm/lib/Target/X86/X86InstrInfo.cpp

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llvm/lib/Target/XCore/XCoreInstrInfo.h

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llvm/lib/Target/XCore/XCoreInstrInfo.cpp

[CodeGen] Track physical register liveness in ExpandPostRAPseudosNeeds ReviewPublicActions

Details

Diff Detail

Event Timeline

Revision ContentsChangeset List

Diff 384080

llvm/include/llvm/CodeGen/TargetInstrInfo.h

llvm/lib/CodeGen/ExpandPostRAPseudos.cpp

llvm/lib/Target/AArch64/AArch64InstrInfo.h

llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

llvm/lib/Target/AMDGPU/R600InstrInfo.h

llvm/lib/Target/AMDGPU/R600InstrInfo.cpp

llvm/lib/Target/AMDGPU/SIInstrInfo.h

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

llvm/lib/Target/ARC/ARCInstrInfo.h

llvm/lib/Target/ARC/ARCInstrInfo.cpp

llvm/lib/Target/ARM/ARMBaseInstrInfo.h

llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp

llvm/lib/Target/ARM/Thumb1InstrInfo.h

llvm/lib/Target/ARM/Thumb1InstrInfo.cpp

llvm/lib/Target/ARM/Thumb2InstrInfo.h

llvm/lib/Target/ARM/Thumb2InstrInfo.cpp

llvm/lib/Target/AVR/AVRInstrInfo.h

llvm/lib/Target/AVR/AVRInstrInfo.cpp

llvm/lib/Target/BPF/BPFInstrInfo.h

llvm/lib/Target/BPF/BPFInstrInfo.cpp

llvm/lib/Target/Hexagon/HexagonInstrInfo.h

llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp

llvm/lib/Target/Lanai/LanaiInstrInfo.h

llvm/lib/Target/Lanai/LanaiInstrInfo.cpp

llvm/lib/Target/M68k/M68kInstrInfo.h

llvm/lib/Target/M68k/M68kInstrInfo.cpp

llvm/lib/Target/MSP430/MSP430InstrInfo.h

llvm/lib/Target/MSP430/MSP430InstrInfo.cpp

llvm/lib/Target/Mips/Mips16InstrInfo.h

llvm/lib/Target/Mips/Mips16InstrInfo.cpp

llvm/lib/Target/Mips/MipsSEInstrInfo.h

llvm/lib/Target/Mips/MipsSEInstrInfo.cpp

llvm/lib/Target/NVPTX/NVPTXInstrInfo.h

llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp

llvm/lib/Target/PowerPC/PPCInstrInfo.h

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

llvm/lib/Target/RISCV/RISCVInstrInfo.h

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

llvm/lib/Target/Sparc/SparcInstrInfo.h

llvm/lib/Target/Sparc/SparcInstrInfo.cpp

llvm/lib/Target/SystemZ/SystemZInstrInfo.h

llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp

llvm/lib/Target/VE/VEInstrInfo.h

llvm/lib/Target/VE/VEInstrInfo.cpp

llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.h

llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp

llvm/lib/Target/X86/X86InstrInfo.h

llvm/lib/Target/X86/X86InstrInfo.cpp

llvm/lib/Target/XCore/XCoreInstrInfo.h

llvm/lib/Target/XCore/XCoreInstrInfo.cpp

[CodeGen] Track physical register liveness in ExpandPostRAPseudos
Needs ReviewPublic
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Revision Contents
Changeset List