[CodeGen] Track physical register liveness in ExpandPostRAPseudos

[foad]

Summary

Track physical register liveness in ExpandPostRAPseudos and pass the
LivePhysRegs info into the copyPhysReg target hook.

llvm/include/llvm/CodeGen/TargetInstrInfo.h

public:
   /// Emit instructions to copy a pair of physical registers.
   ///
   /// This function should support copies within any legal register class as
   /// well as any cross-class copies created during instruction selection.
   ///
   /// The source and destination registers may overlap, which may require a
   /// careful implementation when multiple copy instructions are required for
   /// large registers. See for example the ARM target.
-  virtual void copyPhysReg(MachineBasicBlock &MBB,
-                           MachineBasicBlock::iterator MI, const DebugLoc &DL,
-                           MCRegister DestReg, MCRegister SrcReg,
-                           bool KillSrc) const {
+  ///
+  /// LiveRegs represents the physical registers that are live immediately
+  /// before the copy.
+  virtual void
+  copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
+              const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
+              bool KillSrc,
+              const LivePhysRegs &LiveRegs = LivePhysRegs()) const {
     llvm_unreachable("Target didn't implement TargetInstrInfo::copyPhysReg!");
   }
 
   /// Allow targets to tell MachineVerifier whether a specific register
   /// MachineOperand can be used as part of PC-relative addressing.
   /// PC-relative addressing modes in many CISC architectures contain
   /// (non-PC) registers as offsets or scaling values, which inherently
   /// tags the corresponding MachineOperand with OPERAND_PCREL.

llvm/lib/CodeGen/ExpandPostRAPseudos.cpp

 //===-- ExpandPostRAPseudos.cpp - Pseudo instruction expansion pass -------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file defines a pass that expands COPY and SUBREG_TO_REG pseudo
 // instructions after register allocation.
 //
 //===----------------------------------------------------------------------===//
 
+#include "llvm/CodeGen/LivePhysRegs.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/Passes.h"
 #include "llvm/CodeGen/TargetInstrInfo.h"
 #include "llvm/CodeGen/TargetRegisterInfo.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
void getAnalysisUsage(AnalysisUsage &AU) const override {
     AU.addPreservedID(MachineDominatorsID);
     MachineFunctionPass::getAnalysisUsage(AU);
   }
 
   /// runOnMachineFunction - pass entry point
   bool runOnMachineFunction(MachineFunction&) override;
 
 private:
-  bool LowerSubregToReg(MachineInstr *MI);
-  bool LowerCopy(MachineInstr *MI);
+  bool LowerSubregToReg(MachineInstr *MI, const LivePhysRegs &LiveRegs);
+  bool LowerCopy(MachineInstr *MI, const LivePhysRegs &LiveRegs);
 
   void TransferImplicitOperands(MachineInstr *MI);
 };
 } // end anonymous namespace
 
 char ExpandPostRA::ID = 0;
 char &llvm::ExpandPostRAPseudosID = ExpandPostRA::ID;
 
 INITIALIZE_PASS(ExpandPostRA, DEBUG_TYPE,
                 "Post-RA pseudo instruction expansion pass", false, false)
 
 /// TransferImplicitOperands - MI is a pseudo-instruction, and the lowered
 /// replacement instructions immediately precede it.  Copy any implicit
 /// operands from MI to the replacement instruction.
 void ExpandPostRA::TransferImplicitOperands(MachineInstr *MI) {
   MachineBasicBlock::iterator CopyMI = MI;
   --CopyMI;
 
   for (const MachineOperand &MO : MI->implicit_operands())
     if (MO.isReg())
       CopyMI->addOperand(MO);
 }
 
-bool ExpandPostRA::LowerSubregToReg(MachineInstr *MI) {
+bool ExpandPostRA::LowerSubregToReg(MachineInstr *MI,
+                                    const LivePhysRegs &LiveRegs) {
   MachineBasicBlock *MBB = MI->getParent();
   assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
          MI->getOperand(1).isImm() &&
          (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
           MI->getOperand(3).isImm() && "Invalid subreg_to_reg");
 
   Register DstReg = MI->getOperand(0).getReg();
   Register InsReg = MI->getOperand(2).getReg();
if (DstReg != InsReg) {
       MI->RemoveOperand(3);     // SubIdx
       MI->RemoveOperand(1);     // Imm
       LLVM_DEBUG(dbgs() << "subreg: replace by: " << *MI);
       return true;
     }
     LLVM_DEBUG(dbgs() << "subreg: eliminated!");
   } else {
     TII->copyPhysReg(*MBB, MI, MI->getDebugLoc(), DstSubReg, InsReg,
-                     MI->getOperand(2).isKill());
+                     MI->getOperand(2).isKill(), LiveRegs);
 
     // Implicitly define DstReg for subsequent uses.
     MachineBasicBlock::iterator CopyMI = MI;
     --CopyMI;
     CopyMI->addRegisterDefined(DstReg);
     LLVM_DEBUG(dbgs() << "subreg: " << *CopyMI);
   }
 
   LLVM_DEBUG(dbgs() << '\n');
   MBB->erase(MI);
   return true;
 }
 
-bool ExpandPostRA::LowerCopy(MachineInstr *MI) {
+bool ExpandPostRA::LowerCopy(MachineInstr *MI, const LivePhysRegs &LiveRegs) {
 
   if (MI->allDefsAreDead()) {
     LLVM_DEBUG(dbgs() << "dead copy: " << *MI);
     MI->setDesc(TII->get(TargetOpcode::KILL));
     LLVM_DEBUG(dbgs() << "replaced by: " << *MI);
     return true;
   }
 
if (SrcMO.isUndef() || MI->getNumOperands() > 2) {
       return true;
     }
     // Vanilla identity copy.
     MI->eraseFromParent();
     return true;
   }
 
   LLVM_DEBUG(dbgs() << "real copy:   " << *MI);
-  TII->copyPhysReg(*MI->getParent(), MI, MI->getDebugLoc(),
-                   DstMO.getReg(), SrcMO.getReg(), SrcMO.isKill());
+  TII->copyPhysReg(*MI->getParent(), MI, MI->getDebugLoc(), DstMO.getReg(),
+                   SrcMO.getReg(), SrcMO.isKill(), LiveRegs);
 
   if (MI->getNumOperands() > 2)
     TransferImplicitOperands(MI);
   LLVM_DEBUG({
     MachineBasicBlock::iterator dMI = MI;
     dbgs() << "replaced by: " << *(--dMI);
   });
   MI->eraseFromParent();
   return true;
 }
 
 /// runOnMachineFunction - Reduce subregister inserts and extracts to register
 /// copies.
 ///
 bool ExpandPostRA::runOnMachineFunction(MachineFunction &MF) {
   LLVM_DEBUG(dbgs() << "Machine Function\n"
                     << "********** EXPANDING POST-RA PSEUDO INSTRS **********\n"
                     << "********** Function: " << MF.getName() << '\n');
   TRI = MF.getSubtarget().getRegisterInfo();
   TII = MF.getSubtarget().getInstrInfo();
 
+  LivePhysRegs LiveRegs(*TRI);
+  SmallVector<std::pair<MCPhysReg, const MachineOperand *>, 4> Dummy;
+  bool TracksRegLiveness = MF.getProperties().hasProperty(
+      MachineFunctionProperties::Property::TracksLiveness);
+
   bool MadeChange = false;
 
   for (MachineBasicBlock &MBB : MF) {
-    for (MachineBasicBlock::iterator mi = MBB.begin(), me = MBB.end();
-         mi != me;) {
-      MachineInstr &MI = *mi;
-      // Advance iterator here because MI may be erased.
-      ++mi;
+    if (TracksRegLiveness)
+      LiveRegs.addLiveIns(MBB);
 
-      // Only expand pseudos.
-      if (!MI.isPseudo())
-        continue;
+    for (auto &MI : make_early_inc_range(MBB)) {
+      MachineInstrSpan MIS(MI, &MBB);
 
+      // Only expand pseudos.
+      if (MI.isPseudo()) {
         // Give targets a chance to expand even standard pseudos.
         if (TII->expandPostRAPseudo(MI)) {
           MadeChange = true;
-        continue;
-      }
-
+        } else {
           // Expand standard pseudos.
           switch (MI.getOpcode()) {
           case TargetOpcode::SUBREG_TO_REG:
-        MadeChange |= LowerSubregToReg(&MI);
+            MadeChange |= LowerSubregToReg(&MI, LiveRegs);
             break;
           case TargetOpcode::COPY:
-        MadeChange |= LowerCopy(&MI);
+            MadeChange |= LowerCopy(&MI, LiveRegs);
             break;
           case TargetOpcode::DBG_VALUE:
             continue;
           case TargetOpcode::INSERT_SUBREG:
           case TargetOpcode::EXTRACT_SUBREG:
-        llvm_unreachable("Sub-register pseudos should have been eliminated.");
+            llvm_unreachable(
+                "Sub-register pseudos should have been eliminated.");
+          }
+        }
+      }
+
+      if (TracksRegLiveness) {
+        for (auto &MI2 : MIS) {
+          LiveRegs.stepForward(MI2, Dummy);
+          Dummy.clear();
+        }
       }
     }
+    LiveRegs.clear();
   }
 
   return MadeChange;
 }

llvm/lib/Target/AArch64/AArch64InstrInfo.h

public:
   void copyPhysRegTuple(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
                         const DebugLoc &DL, MCRegister DestReg,
                         MCRegister SrcReg, bool KillSrc, unsigned Opcode,
                         llvm::ArrayRef<unsigned> Indices) const;
   void copyGPRRegTuple(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
                        DebugLoc DL, unsigned DestReg, unsigned SrcReg,
                        bool KillSrc, unsigned Opcode, unsigned ZeroReg,
                        llvm::ArrayRef<unsigned> Indices) const;
-  void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
-                   const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
-                   bool KillSrc) const override;
+  void
+  copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
+              bool KillSrc,
+              const LivePhysRegs &LiveRegs = LivePhysRegs()) const override;
 
   void storeRegToStackSlot(MachineBasicBlock &MBB,
                            MachineBasicBlock::iterator MBBI, Register SrcReg,
                            bool isKill, int FrameIndex,
                            const TargetRegisterClass *RC,
                            const TargetRegisterInfo *TRI) const override;
 
   void loadRegFromStackSlot(MachineBasicBlock &MBB,

llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

for (unsigned SubReg = 0; SubReg != NumRegs; ++SubReg) {
     AddSubReg(MIB, SrcReg, Indices[SubReg], getKillRegState(KillSrc), TRI);
     MIB.addImm(0);
   }
 }
 
 void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
                                    MachineBasicBlock::iterator I,
                                    const DebugLoc &DL, MCRegister DestReg,
-                                   MCRegister SrcReg, bool KillSrc) const {
+                                   MCRegister SrcReg, bool KillSrc,
+                                   const LivePhysRegs &LiveRegs) const {
   if (AArch64::GPR32spRegClass.contains(DestReg) &&
       (AArch64::GPR32spRegClass.contains(SrcReg) || SrcReg == AArch64::WZR)) {
     const TargetRegisterInfo *TRI = &getRegisterInfo();
 
     if (DestReg == AArch64::WSP || SrcReg == AArch64::WSP) {
       // If either operand is WSP, expand to ADD #0.
       if (Subtarget.hasZeroCycleRegMove()) {
         // Cyclone recognizes "ADD Xd, Xn, #0" as a zero-cycle register move.

llvm/lib/Target/AMDGPU/R600InstrInfo.h

public:
   };
 
   explicit R600InstrInfo(const R600Subtarget &);
 
   const R600RegisterInfo &getRegisterInfo() const {
     return RI;
   }
 
-  void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
-                   const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
-                   bool KillSrc) const override;
+  void
+  copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
+              bool KillSrc,
+              const LivePhysRegs &LiveRegs = LivePhysRegs()) const override;
   bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
                            MachineBasicBlock::iterator MBBI) const override;
 
   bool isReductionOp(unsigned opcode) const;
   bool isCubeOp(unsigned opcode) const;
 
   /// \returns true if this \p Opcode represents an ALU instruction.
   bool isALUInstr(unsigned Opcode) const;

llvm/lib/Target/AMDGPU/R600InstrInfo.cpp

 
 bool R600InstrInfo::isVector(const MachineInstr &MI) const {
   return get(MI.getOpcode()).TSFlags & R600_InstFlag::VECTOR;
 }
 
 void R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
                                 MachineBasicBlock::iterator MI,
                                 const DebugLoc &DL, MCRegister DestReg,
-                                MCRegister SrcReg, bool KillSrc) const {
+                                MCRegister SrcReg, bool KillSrc,
+                                const LivePhysRegs &LiveRegs) const {
   unsigned VectorComponents = 0;
   if ((R600::R600_Reg128RegClass.contains(DestReg) ||
       R600::R600_Reg128VerticalRegClass.contains(DestReg)) &&
       (R600::R600_Reg128RegClass.contains(SrcReg) ||
        R600::R600_Reg128VerticalRegClass.contains(SrcReg))) {
     VectorComponents = 4;
   } else if((R600::R600_Reg64RegClass.contains(DestReg) ||
             R600::R600_Reg64VerticalRegClass.contains(DestReg)) &&

llvm/lib/Target/AMDGPU/SIInstrInfo.h

public:
 
   bool shouldClusterMemOps(ArrayRef<const MachineOperand *> BaseOps1,
                            ArrayRef<const MachineOperand *> BaseOps2,
                            unsigned NumLoads, unsigned NumBytes) const override;
 
   bool shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1, int64_t Offset0,
                                int64_t Offset1, unsigned NumLoads) const override;
 
-  void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
-                   const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
-                   bool KillSrc) const override;
+  void
+  copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
+              bool KillSrc,
+              const LivePhysRegs &LiveRegs = LivePhysRegs()) const override;
 
   void materializeImmediate(MachineBasicBlock &MBB,
                             MachineBasicBlock::iterator MI,
                             const DebugLoc &DL,
                             unsigned DestReg,
                             int64_t Value) const;
 
   const TargetRegisterClass *getPreferredSelectRegClass(

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

static void expandSGPRCopy(const SIInstrInfo &TII, MachineBasicBlock &MBB,
 
   if (KillSrc)
     LastMI->addRegisterKilled(SrcReg, &RI);
 }
 
 void SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
                               MachineBasicBlock::iterator MI,
                               const DebugLoc &DL, MCRegister DestReg,
-                              MCRegister SrcReg, bool KillSrc) const {
+                              MCRegister SrcReg, bool KillSrc,
+                              const LivePhysRegs &LiveRegs) const {
   const TargetRegisterClass *RC = RI.getPhysRegClass(DestReg);
 
   // FIXME: This is hack to resolve copies between 16 bit and 32 bit
   // registers until all patterns are fixed.
   if (Fix16BitCopies &&
       ((RI.getRegSizeInBits(*RC) == 16) ^
        (RI.getRegSizeInBits(*RI.getPhysRegClass(SrcReg)) == 16))) {
     MCRegister &RegToFix = (RI.getRegSizeInBits(*RC) == 16) ? DestReg : SrcReg;
if (Size == 16) {
     }
 
     if (IsAGPRDst || IsAGPRSrc) {
       if (!DstLow || !SrcLow) {
         reportIllegalCopy(this, MBB, MI, DL, DestReg, SrcReg, KillSrc,
                           "Cannot use hi16 subreg with an AGPR!");
       }
 
-      copyPhysReg(MBB, MI, DL, NewDestReg, NewSrcReg, KillSrc);
+      copyPhysReg(MBB, MI, DL, NewDestReg, NewSrcReg, KillSrc, LiveRegs);
       return;
     }
 
     if (IsSGPRSrc && !ST.hasSDWAScalar()) {
       if (!DstLow || !SrcLow) {
         reportIllegalCopy(this, MBB, MI, DL, DestReg, SrcReg, KillSrc,
                           "Cannot use hi16 subreg on VI!");
       }

llvm/lib/Target/ARC/ARCInstrInfo.h

public:
   unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
                         MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
                         const DebugLoc &,
                         int *BytesAdded = nullptr) const override;
 
   unsigned removeBranch(MachineBasicBlock &MBB,
                         int *BytesRemoved = nullptr) const override;
 
-  void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
-                   const DebugLoc &, MCRegister DestReg, MCRegister SrcReg,
-                   bool KillSrc) const override;
+  void
+  copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
+              bool KillSrc,
+              const LivePhysRegs &LiveRegs = LivePhysRegs()) const override;
 
   void storeRegToStackSlot(MachineBasicBlock &MBB,
                            MachineBasicBlock::iterator MI, Register SrcReg,
                            bool IsKill, int FrameIndex,
                            const TargetRegisterClass *RC,
                            const TargetRegisterInfo *TRI) const override;
 
   void loadRegFromStackSlot(MachineBasicBlock &MBB,

llvm/lib/Target/ARC/ARCInstrInfo.cpp

unsigned ARCInstrInfo::removeBranch(MachineBasicBlock &MBB,
   // Remove the branch.
   I->eraseFromParent();
   return 2;
 }
 
 void ARCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
                                MachineBasicBlock::iterator I,
                                const DebugLoc &DL, MCRegister DestReg,
-                               MCRegister SrcReg, bool KillSrc) const {
+                               MCRegister SrcReg, bool KillSrc,
+                               const LivePhysRegs &LiveRegs) const {
   assert(ARC::GPR32RegClass.contains(SrcReg) &&
          "Only GPR32 src copy supported.");
   assert(ARC::GPR32RegClass.contains(DestReg) &&
          "Only GPR32 dest copy supported.");
   BuildMI(MBB, I, DL, get(ARC::MOV_rr), DestReg)
       .addReg(SrcReg, getKillRegState(KillSrc));
 }
 

llvm/lib/Target/ARM/ARMBaseInstrInfo.h

public:
 
   void copyToCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
                   unsigned SrcReg, bool KillSrc,
                   const ARMSubtarget &Subtarget) const;
   void copyFromCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
                     unsigned DestReg, bool KillSrc,
                     const ARMSubtarget &Subtarget) const;
 
-  void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
-                   const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
-                   bool KillSrc) const override;
+  void
+  copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
+              bool KillSrc,
+              const LivePhysRegs &LiveRegs = LivePhysRegs()) const override;
 
   void storeRegToStackSlot(MachineBasicBlock &MBB,
                            MachineBasicBlock::iterator MBBI,
                            Register SrcReg, bool isKill, int FrameIndex,
                            const TargetRegisterClass *RC,
                            const TargetRegisterInfo *TRI) const override;
 
   void loadRegFromStackSlot(MachineBasicBlock &MBB,

llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp

void llvm::addPredicatedMveVpredROp(MachineInstrBuilder &MIB,
                                     unsigned Cond, unsigned Inactive) {
   addPredicatedMveVpredNOp(MIB, Cond);
   MIB.addReg(Inactive);
 }
 
 void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
                                    MachineBasicBlock::iterator I,
                                    const DebugLoc &DL, MCRegister DestReg,
-                                   MCRegister SrcReg, bool KillSrc) const {
+                                   MCRegister SrcReg, bool KillSrc,
+                                   const LivePhysRegs &LiveRegs) const {
   bool GPRDest = ARM::GPRRegClass.contains(DestReg);
   bool GPRSrc = ARM::GPRRegClass.contains(SrcReg);
 
   if (GPRDest && GPRSrc) {
     BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
         .addReg(SrcReg, getKillRegState(KillSrc))
         .add(predOps(ARMCC::AL))
         .add(condCodeOp());

llvm/lib/Target/ARM/Thumb1InstrInfo.h

public:
   unsigned getUnindexedOpcode(unsigned Opc) const override;
 
   /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
   /// such, whenever a client has an instance of instruction info, it should
   /// always be able to get register info as well (through this method).
   ///
   const ThumbRegisterInfo &getRegisterInfo() const override { return RI; }
 
-  void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
-                   const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
-                   bool KillSrc) const override;
+  void
+  copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
+              bool KillSrc,
+              const LivePhysRegs &LiveRegs = LivePhysRegs()) const override;
   void storeRegToStackSlot(MachineBasicBlock &MBB,
                            MachineBasicBlock::iterator MBBI,
                            Register SrcReg, bool isKill, int FrameIndex,
                            const TargetRegisterClass *RC,
                            const TargetRegisterInfo *TRI) const override;
 
   void loadRegFromStackSlot(MachineBasicBlock &MBB,
                             MachineBasicBlock::iterator MBBI,

llvm/lib/Target/ARM/Thumb1InstrInfo.cpp

 
 unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {
   return 0;
 }
 
 void Thumb1InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
                                   MachineBasicBlock::iterator I,
                                   const DebugLoc &DL, MCRegister DestReg,
-                                  MCRegister SrcReg, bool KillSrc) const {
+                                  MCRegister SrcReg, bool KillSrc,
+                                  const LivePhysRegs &LiveRegs) const {
   // Need to check the arch.
   MachineFunction &MF = *MBB.getParent();
   const ARMSubtarget &st = MF.getSubtarget<ARMSubtarget>();
 
   assert(ARM::GPRRegClass.contains(DestReg, SrcReg) &&
          "Thumb1 can only copy GPR registers");
 
   if (st.hasV6Ops() || ARM::hGPRRegClass.contains(SrcReg)

llvm/lib/Target/ARM/Thumb2InstrInfo.h

public:
   unsigned getUnindexedOpcode(unsigned Opc) const override;
 
   void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
                                MachineBasicBlock *NewDest) const override;
 
   bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
                            MachineBasicBlock::iterator MBBI) const override;
 
-  void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
-                   const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
-                   bool KillSrc) const override;
+  void
+  copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
+              bool KillSrc,
+              const LivePhysRegs &LiveRegs = LivePhysRegs()) const override;
 
   void storeRegToStackSlot(MachineBasicBlock &MBB,
                            MachineBasicBlock::iterator MBBI,
                            Register SrcReg, bool isKill, int FrameIndex,
                            const TargetRegisterClass *RC,
                            const TargetRegisterInfo *TRI) const override;
 
   void loadRegFromStackSlot(MachineBasicBlock &MBB,

llvm/lib/Target/ARM/Thumb2InstrInfo.cpp

if (!RV && getSubtarget().hasV8_1MMainlineOps() && !PreferNoCSEL) {
     return NewMI;
   }
   return RV;
 }
 
 void Thumb2InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
                                   MachineBasicBlock::iterator I,
                                   const DebugLoc &DL, MCRegister DestReg,
-                                  MCRegister SrcReg, bool KillSrc) const {
+                                  MCRegister SrcReg, bool KillSrc,
+                                  const LivePhysRegs &LiveRegs) const {
   // Handle SPR, DPR, and QPR copies.
   if (!ARM::GPRRegClass.contains(DestReg, SrcReg))
     return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc);
 
   BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
       .addReg(SrcReg, getKillRegState(KillSrc))
       .add(predOps(ARMCC::AL));
 }

llvm/lib/Target/AVR/AVRInstrInfo.h

public:
   explicit AVRInstrInfo();
 
   const AVRRegisterInfo &getRegisterInfo() const { return RI; }
   const MCInstrDesc &getBrCond(AVRCC::CondCodes CC) const;
   AVRCC::CondCodes getCondFromBranchOpc(unsigned Opc) const;
   AVRCC::CondCodes getOppositeCondition(AVRCC::CondCodes CC) const;
   unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
 
-  void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
-                   const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
-                   bool KillSrc) const override;
+  void
+  copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
+              bool KillSrc,
+              const LivePhysRegs &LiveRegs = LivePhysRegs()) const override;
   void storeRegToStackSlot(MachineBasicBlock &MBB,
                            MachineBasicBlock::iterator MI, Register SrcReg,
                            bool isKill, int FrameIndex,
                            const TargetRegisterClass *RC,
                            const TargetRegisterInfo *TRI) const override;
   void loadRegFromStackSlot(MachineBasicBlock &MBB,
                             MachineBasicBlock::iterator MI, Register DestReg,
                             int FrameIndex, const TargetRegisterClass *RC,

llvm/lib/Target/AVR/AVRInstrInfo.cpp

 namespace llvm {
 
 AVRInstrInfo::AVRInstrInfo()
     : AVRGenInstrInfo(AVR::ADJCALLSTACKDOWN, AVR::ADJCALLSTACKUP), RI() {}
 
 void AVRInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
                                MachineBasicBlock::iterator MI,
                                const DebugLoc &DL, MCRegister DestReg,
-                               MCRegister SrcReg, bool KillSrc) const {
+                               MCRegister SrcReg, bool KillSrc,
+                               const LivePhysRegs &LiveRegs) const {
   const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
   const AVRRegisterInfo &TRI = *STI.getRegisterInfo();
   unsigned Opc;
 
   // Not all AVR devices support the 16-bit `MOVW` instruction.
   if (AVR::DREGSRegClass.contains(DestReg, SrcReg)) {
     if (STI.hasMOVW() && AVR::DREGSMOVWRegClass.contains(DestReg, SrcReg)) {
       BuildMI(MBB, MI, DL, get(AVR::MOVWRdRr), DestReg)

llvm/lib/Target/BPF/BPFInstrInfo.h

 class BPFInstrInfo : public BPFGenInstrInfo {
   const BPFRegisterInfo RI;
 
 public:
   BPFInstrInfo();
 
   const BPFRegisterInfo &getRegisterInfo() const { return RI; }
 
-  void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
-                   const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
-                   bool KillSrc) const override;
+  void
+  copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
+              bool KillSrc,
+              const LivePhysRegs &LiveRegs = LivePhysRegs()) const override;
 
   bool expandPostRAPseudo(MachineInstr &MI) const override;
 
   void storeRegToStackSlot(MachineBasicBlock &MBB,
                            MachineBasicBlock::iterator MBBI, Register SrcReg,
                            bool isKill, int FrameIndex,
                            const TargetRegisterClass *RC,
                            const TargetRegisterInfo *TRI) const override;

llvm/lib/Target/BPF/BPFInstrInfo.cpp

 using namespace llvm;
 
 BPFInstrInfo::BPFInstrInfo()
     : BPFGenInstrInfo(BPF::ADJCALLSTACKDOWN, BPF::ADJCALLSTACKUP) {}
 
 void BPFInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
                                MachineBasicBlock::iterator I,
                                const DebugLoc &DL, MCRegister DestReg,
-                               MCRegister SrcReg, bool KillSrc) const {
+                               MCRegister SrcReg, bool KillSrc,
+                               const LivePhysRegs &LiveRegs) const {
   if (BPF::GPRRegClass.contains(DestReg, SrcReg))
     BuildMI(MBB, I, DL, get(BPF::MOV_rr), DestReg)
         .addReg(SrcReg, getKillRegState(KillSrc));
   else if (BPF::GPR32RegClass.contains(DestReg, SrcReg))
     BuildMI(MBB, I, DL, get(BPF::MOV_rr_32), DestReg)
         .addReg(SrcReg, getKillRegState(KillSrc));
   else
     llvm_unreachable("Impossible reg-to-reg copy");

llvm/lib/Target/Hexagon/HexagonInstrInfo.h

public:
   /// Emit instructions to copy a pair of physical registers.
   ///
   /// This function should support copies within any legal register class as
   /// well as any cross-class copies created during instruction selection.
   ///
   /// The source and destination registers may overlap, which may require a
   /// careful implementation when multiple copy instructions are required for
   /// large registers. See for example the ARM target.
-  void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
-                   const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
-                   bool KillSrc) const override;
+  void
+  copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
+              bool KillSrc,
+              const LivePhysRegs &LiveRegs = LivePhysRegs()) const override;
 
   /// Store the specified register of the given register class to the specified
   /// stack frame index. The store instruction is to be added to the given
   /// machine basic block before the specified machine instruction. If isKill
   /// is true, the register operand is the last use and must be marked kill.
   void storeRegToStackSlot(MachineBasicBlock &MBB,
                            MachineBasicBlock::iterator MBBI,
                            Register SrcReg, bool isKill, int FrameIndex,

llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp

static void getLiveOutRegsAt(LivePhysRegs &Regs, const MachineInstr &MI) {
   auto E = ++MachineBasicBlock::const_iterator(MI.getIterator()).getReverse();
   for (auto I = B.rbegin(); I != E; ++I)
     Regs.stepBackward(*I);
 }
 
 void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
                                    MachineBasicBlock::iterator I,
                                    const DebugLoc &DL, MCRegister DestReg,
-                                   MCRegister SrcReg, bool KillSrc) const {
+                                   MCRegister SrcReg, bool KillSrc,
+                                   const LivePhysRegs &LiveRegs) const {
   const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
   unsigned KillFlag = getKillRegState(KillSrc);
 
   if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
     BuildMI(MBB, I, DL, get(Hexagon::A2_tfr), DestReg)
       .addReg(SrcReg, KillFlag);
     return;
   }

llvm/lib/Target/Lanai/LanaiInstrInfo.h

unsigned isLoadFromStackSlot(const MachineInstr &MI,
                                int &FrameIndex) const override;
 
   unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI,
                                      int &FrameIndex) const override;
 
   unsigned isStoreToStackSlot(const MachineInstr &MI,
                               int &FrameIndex) const override;
 
-  void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator Position,
-                   const DebugLoc &DL, MCRegister DestinationRegister,
-                   MCRegister SourceRegister, bool KillSource) const override;
+  void
+  copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator Position,
+              MCRegister SourceRegister, bool KillSource,
+              const LivePhysRegs &LiveRegs = LivePhysRegs()) const override;
 
   void
   storeRegToStackSlot(MachineBasicBlock &MBB,
                       MachineBasicBlock::iterator Position,
                       Register SourceRegister, bool IsKill, int FrameIndex,
                       const TargetRegisterClass *RegisterClass,
                       const TargetRegisterInfo *RegisterInfo) const override;
 

llvm/lib/Target/Lanai/LanaiInstrInfo.cpp

 LanaiInstrInfo::LanaiInstrInfo()
     : LanaiGenInstrInfo(Lanai::ADJCALLSTACKDOWN, Lanai::ADJCALLSTACKUP),
       RegisterInfo() {}
 
 void LanaiInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
                                  MachineBasicBlock::iterator Position,
                                  const DebugLoc &DL,
                                  MCRegister DestinationRegister,
-                                 MCRegister SourceRegister,
-                                 bool KillSource) const {
+                                 MCRegister SourceRegister, bool KillSource,
+                                 const LivePhysRegs &LiveRegs) const {
   if (!Lanai::GPRRegClass.contains(DestinationRegister, SourceRegister)) {
     llvm_unreachable("Impossible reg-to-reg copy");
   }
 
   BuildMI(MBB, Position, DL, get(Lanai::OR_I_LO), DestinationRegister)
       .addReg(SourceRegister, getKillRegState(KillSource))
       .addImm(0);
 }

llvm/lib/Target/M68k/M68kInstrInfo.h

public:
   unsigned removeBranch(MachineBasicBlock &MBB,
                         int *BytesRemoved = nullptr) const override;
 
   unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
                         MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
                         const DebugLoc &DL,
                         int *BytesAdded = nullptr) const override;
 
-  void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
-                   const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
-                   bool KillSrc) const override;
+  void
+  copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
+              bool KillSrc,
+              const LivePhysRegs &LiveRegs = LivePhysRegs()) const override;
 
   bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx,
                          unsigned &Size, unsigned &Offset,
                          const MachineFunction &MF) const override;
 
   void storeRegToStackSlot(MachineBasicBlock &MBB,
                            MachineBasicBlock::iterator MI, Register SrcReg,
                            bool IsKill, int FrameIndex,

llvm/lib/Target/M68k/M68kInstrInfo.cpp

for (const uint8_t Pat : EncEAk) {
     }
   }
   return true;
 }
 
 void M68kInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
                                 MachineBasicBlock::iterator MI,
                                 const DebugLoc &DL, MCRegister DstReg,
-                                MCRegister SrcReg, bool KillSrc) const {
+                                MCRegister SrcReg, bool KillSrc,
+                                const LivePhysRegs &LiveRegs) const {
   unsigned Opc = 0;
 
   // First deal with the normal symmetric copies.
   if (M68k::XR32RegClass.contains(DstReg, SrcReg))
     Opc = M68k::MOV32rr;
   else if (M68k::XR16RegClass.contains(DstReg, SrcReg))
     Opc = M68k::MOV16rr;
   else if (M68k::DR8RegClass.contains(DstReg, SrcReg))

llvm/lib/Target/MSP430/MSP430InstrInfo.h

public:
   explicit MSP430InstrInfo(MSP430Subtarget &STI);
 
   /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
   /// such, whenever a client has an instance of instruction info, it should
   /// always be able to get register info as well (through this method).
   ///
   const TargetRegisterInfo &getRegisterInfo() const { return RI; }
 
-  void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
-                   const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
-                   bool KillSrc) const override;
+  void
+  copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
+              bool KillSrc,
+              const LivePhysRegs &LiveRegs = LivePhysRegs()) const override;
 
   void storeRegToStackSlot(MachineBasicBlock &MBB,
                            MachineBasicBlock::iterator MI,
                            Register SrcReg, bool isKill,
                            int FrameIndex,
                            const TargetRegisterClass *RC,
                            const TargetRegisterInfo *TRI) const override;
   void loadRegFromStackSlot(MachineBasicBlock &MBB,

llvm/lib/Target/MSP430/MSP430InstrInfo.cpp

BuildMI(MBB, MI, DL, get(MSP430::MOV8rm))
       .addImm(0).addMemOperand(MMO);
   else
     llvm_unreachable("Cannot store this register to stack slot!");
 }
 
 void MSP430InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
                                   MachineBasicBlock::iterator I,
                                   const DebugLoc &DL, MCRegister DestReg,
-                                  MCRegister SrcReg, bool KillSrc) const {
+                                  MCRegister SrcReg, bool KillSrc,
+                                  const LivePhysRegs &LiveRegs) const {
   unsigned Opc;
   if (MSP430::GR16RegClass.contains(DestReg, SrcReg))
     Opc = MSP430::MOV16rr;
   else if (MSP430::GR8RegClass.contains(DestReg, SrcReg))
     Opc = MSP430::MOV8rr;
   else
     llvm_unreachable("Impossible reg-to-reg copy");
 

llvm/lib/Target/Mips/Mips16InstrInfo.h

public:
   /// isStoreToStackSlot - If the specified machine instruction is a direct
   /// store to a stack slot, return the virtual or physical register number of
   /// the source reg along with the FrameIndex of the loaded stack slot.  If
   /// not, return 0.  This predicate must return 0 if the instruction has
   /// any side effects other than storing to the stack slot.
   unsigned isStoreToStackSlot(const MachineInstr &MI,
                               int &FrameIndex) const override;
 
-  void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
-                   const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
-                   bool KillSrc) const override;
+  void
+  copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
+              bool KillSrc,
+              const LivePhysRegs &LiveRegs = LivePhysRegs()) const override;
 
   void storeRegToStack(MachineBasicBlock &MBB,
                        MachineBasicBlock::iterator MBBI,
                        Register SrcReg, bool isKill, int FrameIndex,
                        const TargetRegisterClass *RC,
                        const TargetRegisterInfo *TRI,
                        int64_t Offset) const override;
 

llvm/lib/Target/Mips/Mips16InstrInfo.cpp

 unsigned Mips16InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
                                              int &FrameIndex) const {
   return 0;
 }
 
 void Mips16InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
                                   MachineBasicBlock::iterator I,
                                   const DebugLoc &DL, MCRegister DestReg,
-                                  MCRegister SrcReg, bool KillSrc) const {
+                                  MCRegister SrcReg, bool KillSrc,
+                                  const LivePhysRegs &LiveRegs) const {
   unsigned Opc = 0;
 
   if (Mips::CPU16RegsRegClass.contains(DestReg) &&
       Mips::GPR32RegClass.contains(SrcReg))
     Opc = Mips::MoveR3216;
   else if (Mips::GPR32RegClass.contains(DestReg) &&
            Mips::CPU16RegsRegClass.contains(SrcReg))
     Opc = Mips::Move32R16;

llvm/lib/Target/Mips/MipsSEInstrInfo.h

public:
   /// isStoreToStackSlot - If the specified machine instruction is a direct
   /// store to a stack slot, return the virtual or physical register number of
   /// the source reg along with the FrameIndex of the loaded stack slot.  If
   /// not, return 0.  This predicate must return 0 if the instruction has
   /// any side effects other than storing to the stack slot.
   unsigned isStoreToStackSlot(const MachineInstr &MI,
                               int &FrameIndex) const override;
 
-  void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
-                   const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
-                   bool KillSrc) const override;
+  void
+  copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
+              bool KillSrc,
+              const LivePhysRegs &LiveRegs = LivePhysRegs()) const override;
 
   void storeRegToStack(MachineBasicBlock &MBB,
                        MachineBasicBlock::iterator MI,
                        Register SrcReg, bool isKill, int FrameIndex,
                        const TargetRegisterClass *RC,
                        const TargetRegisterInfo *TRI,
                        int64_t Offset) const override;
 

llvm/lib/Target/Mips/MipsSEInstrInfo.cpp

if ((Opc == Mips::SW)   || (Opc == Mips::SD)   ||
     }
   }
   return 0;
 }
 
 void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
                                   MachineBasicBlock::iterator I,
                                   const DebugLoc &DL, MCRegister DestReg,
-                                  MCRegister SrcReg, bool KillSrc) const {
+                                  MCRegister SrcReg, bool KillSrc,
+                                  const LivePhysRegs &LiveRegs) const {
   unsigned Opc = 0, ZeroReg = 0;
   bool isMicroMips = Subtarget.inMicroMipsMode();
 
   if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg.
     if (Mips::GPR32RegClass.contains(SrcReg)) {
       if (isMicroMips)
         Opc = Mips::MOVE16_MM;
       else

llvm/lib/Target/NVPTX/NVPTXInstrInfo.h

public:
    *                             unsigned SrcReg, bool isKill, int FrameIndex,
    *                              const TargetRegisterClass *RC) const;
    * virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
    *                               MachineBasicBlock::iterator MBBI,
    *                               unsigned DestReg, int FrameIndex,
    *                               const TargetRegisterClass *RC) const;
    */
 
-  void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
-                   const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
-                   bool KillSrc) const override;
+  void
+  copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
+              bool KillSrc,
+              const LivePhysRegs &LiveRegs = LivePhysRegs()) const override;
 
   // Branch analysis.
   bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
                      MachineBasicBlock *&FBB,
                      SmallVectorImpl<MachineOperand> &Cond,
                      bool AllowModify) const override;
   unsigned removeBranch(MachineBasicBlock &MBB,
                         int *BytesRemoved = nullptr) const override;

llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp

 // Pin the vtable to this file.
 void NVPTXInstrInfo::anchor() {}
 
 NVPTXInstrInfo::NVPTXInstrInfo() : NVPTXGenInstrInfo(), RegInfo() {}
 
 void NVPTXInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
                                  MachineBasicBlock::iterator I,
                                  const DebugLoc &DL, MCRegister DestReg,
-                                 MCRegister SrcReg, bool KillSrc) const {
+                                 MCRegister SrcReg, bool KillSrc,
+                                 const LivePhysRegs &LiveRegs) const {
   const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
   const TargetRegisterClass *DestRC = MRI.getRegClass(DestReg);
   const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
 
   if (RegInfo.getRegSizeInBits(*DestRC) != RegInfo.getRegSizeInBits(*SrcRC))
     report_fatal_error("Copy one register into another with a different width");
 
   unsigned Op;

llvm/lib/Target/PowerPC/PPCInstrInfo.h

public:
   bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond,
                        Register, Register, Register, int &, int &,
                        int &) const override;
   void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
                     const DebugLoc &DL, Register DstReg,
                     ArrayRef<MachineOperand> Cond, Register TrueReg,
                     Register FalseReg) const override;
 
-  void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
-                   const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
-                   bool KillSrc) const override;
+  void
+  copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
+              bool KillSrc,
+              const LivePhysRegs &LiveRegs = LivePhysRegs()) const override;
 
   void storeRegToStackSlot(MachineBasicBlock &MBB,
                            MachineBasicBlock::iterator MBBI,
                            Register SrcReg, bool isKill, int FrameIndex,
                            const TargetRegisterClass *RC,
                            const TargetRegisterInfo *TRI) const override;
 
   // Emits a register spill without updating the register class for vector

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

static unsigned getCRBitValue(unsigned CRBit) {
 
   assert(Ret != 4 && "Invalid CR bit register");
   return Ret;
 }
 
 void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
                                MachineBasicBlock::iterator I,
                                const DebugLoc &DL, MCRegister DestReg,
-                               MCRegister SrcReg, bool KillSrc) const {
+                               MCRegister SrcReg, bool KillSrc,
+                               const LivePhysRegs &LiveRegs) const {
   // We can end up with self copies and similar things as a result of VSX copy
   // legalization. Promote them here.
   const TargetRegisterInfo *TRI = &getRegisterInfo();
   if (PPC::F8RCRegClass.contains(DestReg) &&
       PPC::VSRCRegClass.contains(SrcReg)) {
     MCRegister SuperReg =
         TRI->getMatchingSuperReg(DestReg, PPC::sub_64, &PPC::VSRCRegClass);
 

llvm/lib/Target/RISCV/RISCVInstrInfo.h

public:
   MCInst getNop() const override;
   const MCInstrDesc &getBrCond(RISCVCC::CondCode CC) const;
 
   unsigned isLoadFromStackSlot(const MachineInstr &MI,
                                int &FrameIndex) const override;
   unsigned isStoreToStackSlot(const MachineInstr &MI,
                               int &FrameIndex) const override;
 
-  void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
-                   const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg,
-                   bool KillSrc) const override;
+  void
+  copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+              bool KillSrc,
+              const LivePhysRegs &LiveRegs = LivePhysRegs()) const override;
 
   void storeRegToStackSlot(MachineBasicBlock &MBB,
                            MachineBasicBlock::iterator MBBI, Register SrcReg,
                            bool IsKill, int FrameIndex,
                            const TargetRegisterClass *RC,
                            const TargetRegisterInfo *TRI) const override;
 
   void loadRegFromStackSlot(MachineBasicBlock &MBB,

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

static bool isConvertibleToVMV_V_V(const RISCVSubtarget &STI,
   }
 
   return false;
 }
 
 void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
                                  MachineBasicBlock::iterator MBBI,
                                  const DebugLoc &DL, MCRegister DstReg,
-                                 MCRegister SrcReg, bool KillSrc) const {
+                                 MCRegister SrcReg, bool KillSrc,
+                                 const LivePhysRegs &LiveRegs) const {
   if (RISCV::GPRRegClass.contains(DstReg, SrcReg)) {
     BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg)
         .addReg(SrcReg, getKillRegState(KillSrc))
         .addImm(0);
     return;
   }
 
   // FPR->FPR copies and VR->VR copies.

llvm/lib/Target/Sparc/SparcInstrInfo.h

public:
   unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
                         MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
                         const DebugLoc &DL,
                         int *BytesAdded = nullptr) const override;
 
   bool
   reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
 
-  void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
-                   const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
-                   bool KillSrc) const override;
+  void
+  copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
+              bool KillSrc,
+              const LivePhysRegs &LiveRegs = LivePhysRegs()) const override;
 
   void storeRegToStackSlot(MachineBasicBlock &MBB,
                            MachineBasicBlock::iterator MBBI,
                            Register SrcReg, bool isKill, int FrameIndex,
                            const TargetRegisterClass *RC,
                            const TargetRegisterInfo *TRI) const override;
 
   void loadRegFromStackSlot(MachineBasicBlock &MBB,

llvm/lib/Target/Sparc/SparcInstrInfo.cpp

bool SparcInstrInfo::reverseBranchCondition(
   SPCC::CondCodes CC = static_cast<SPCC::CondCodes>(Cond[0].getImm());
   Cond[0].setImm(GetOppositeBranchCondition(CC));
   return false;
 }
 
 void SparcInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
                                  MachineBasicBlock::iterator I,
                                  const DebugLoc &DL, MCRegister DestReg,
-                                 MCRegister SrcReg, bool KillSrc) const {
+                                 MCRegister SrcReg, bool KillSrc,
+                                 const LivePhysRegs &LiveRegs) const {
   unsigned numSubRegs = 0;
   unsigned movOpc     = 0;
   const unsigned *subRegIdx = nullptr;
   bool ExtraG0 = false;
 
   const unsigned DW_SubRegsIdx[]  = { SP::sub_even, SP::sub_odd };
   const unsigned DFP_FP_SubRegsIdx[]  = { SP::sub_even, SP::sub_odd };
   const unsigned QFP_DFP_SubRegsIdx[] = { SP::sub_even64, SP::sub_odd64 };

llvm/lib/Target/SystemZ/SystemZInstrInfo.h

bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
                            unsigned NumCyclesT, unsigned ExtraPredCyclesT,
                            MachineBasicBlock &FMBB,
                            unsigned NumCyclesF, unsigned ExtraPredCyclesF,
                            BranchProbability Probability) const override;
   bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
                             BranchProbability Probability) const override;
   bool PredicateInstruction(MachineInstr &MI,
                             ArrayRef<MachineOperand> Pred) const override;
-  void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
-                   const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
-                   bool KillSrc) const override;
+  void
+  copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+              bool KillSrc,
+              const LivePhysRegs &LiveRegs = LivePhysRegs()) const override;
   void storeRegToStackSlot(MachineBasicBlock &MBB,
                            MachineBasicBlock::iterator MBBI,
                            Register SrcReg, bool isKill, int FrameIndex,
                            const TargetRegisterClass *RC,
                            const TargetRegisterInfo *TRI) const override;
   void loadRegFromStackSlot(MachineBasicBlock &MBB,
                             MachineBasicBlock::iterator MBBI,
                             Register DestReg, int FrameIdx,

llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp

if (Opcode == SystemZ::CallBR) {
     return true;
   }
   return false;
 }
 
 void SystemZInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
                                    MachineBasicBlock::iterator MBBI,
                                    const DebugLoc &DL, MCRegister DestReg,
-                                   MCRegister SrcReg, bool KillSrc) const {
+                                   MCRegister SrcReg, bool KillSrc,
+                                   const LivePhysRegs &LiveRegs) const {
   // Split 128-bit GPR moves into two 64-bit moves. Add implicit uses of the
   // super register in case one of the subregs is undefined.
   // This handles ADDR128 too.
   if (SystemZ::GR128BitRegClass.contains(DestReg, SrcReg)) {
     copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_h64),
                 RI.getSubReg(SrcReg, SystemZ::subreg_h64), KillSrc);
     MachineInstrBuilder(*MBB.getParent(), std::prev(MBBI))
       .addReg(SrcReg, RegState::Implicit);

llvm/lib/Target/VE/VEInstrInfo.h

unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
                         MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
                         const DebugLoc &DL,
                         int *BytesAdded = nullptr) const override;
 
   bool
   reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
   /// } Branch Analysis & Modification
 
-  void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
-                   const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
-                   bool KillSrc) const override;
+  void
+  copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
+              bool KillSrc,
+              const LivePhysRegs &LiveRegs = LivePhysRegs()) const override;
 
   /// Stack Spill & Reload {
   unsigned isLoadFromStackSlot(const MachineInstr &MI,
                                int &FrameIndex) const override;
   unsigned isStoreToStackSlot(const MachineInstr &MI,
                               int &FrameIndex) const override;
   void storeRegToStackSlot(MachineBasicBlock &MBB,
                            MachineBasicBlock::iterator MBBI, Register SrcReg,

llvm/lib/Target/VE/VEInstrInfo.cpp

static void copyPhysSubRegs(MachineBasicBlock &MBB,
   MovMI->addRegisterDefined(DestReg, TRI);
   if (KillSrc)
     MovMI->addRegisterKilled(SrcReg, TRI, true);
 }
 
 void VEInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
                               MachineBasicBlock::iterator I, const DebugLoc &DL,
                               MCRegister DestReg, MCRegister SrcReg,
-                              bool KillSrc) const {
+                              bool KillSrc,
+                              const LivePhysRegs &LiveRegs) const {
 
   if (IsAliasOfSX(SrcReg) && IsAliasOfSX(DestReg)) {
     BuildMI(MBB, I, DL, get(VE::ORri), DestReg)
         .addReg(SrcReg, getKillRegState(KillSrc))
         .addImm(0);
   } else if (VE::V64RegClass.contains(DestReg, SrcReg)) {
     // Generate following instructions
     //   %sw16 = LEA32zii 256

llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.h

 public:
   explicit WebAssemblyInstrInfo(const WebAssemblySubtarget &STI);
 
   const WebAssemblyRegisterInfo &getRegisterInfo() const { return RI; }
 
   bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
                                          AAResults *AA) const override;
 
-  void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
-                   const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
-                   bool KillSrc) const override;
+  void
+  copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
+              bool KillSrc,
+              const LivePhysRegs &LiveRegs = LivePhysRegs()) const override;
   MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
                                        unsigned OpIdx1,
                                        unsigned OpIdx2) const override;
 
   bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
                      MachineBasicBlock *&FBB,
                      SmallVectorImpl<MachineOperand> &Cond,
                      bool AllowModify = false) const override;

llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp

bool WebAssemblyInstrInfo::isReallyTriviallyReMaterializable(
   default:
     return false;
   }
 }
 
 void WebAssemblyInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
                                        MachineBasicBlock::iterator I,
                                        const DebugLoc &DL, MCRegister DestReg,
-                                       MCRegister SrcReg, bool KillSrc) const {
+                                       MCRegister SrcReg, bool KillSrc,
+                                       const LivePhysRegs &LiveRegs) const {
   // This method is called by post-RA expansion, which expects only pregs to
   // exist. However we need to handle both here.
   auto &MRI = MBB.getParent()->getRegInfo();
   const TargetRegisterClass *RC =
       Register::isVirtualRegister(DestReg)
           ? MRI.getRegClass(DestReg)
           : MRI.getTargetRegisterInfo()->getMinimalPhysRegClass(DestReg);
 

llvm/lib/Target/X86/X86InstrInfo.h

unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
                         int *BytesAdded = nullptr) const override;
   bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond,
                        Register, Register, Register, int &, int &,
                        int &) const override;
   void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
                     const DebugLoc &DL, Register DstReg,
                     ArrayRef<MachineOperand> Cond, Register TrueReg,
                     Register FalseReg) const override;
-  void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
-                   const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
-                   bool KillSrc) const override;
+  void
+  copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
+              bool KillSrc,
+              const LivePhysRegs &LiveRegs = LivePhysRegs()) const override;
   void storeRegToStackSlot(MachineBasicBlock &MBB,
                            MachineBasicBlock::iterator MI, Register SrcReg,
                            bool isKill, int FrameIndex,
                            const TargetRegisterClass *RC,
                            const TargetRegisterInfo *TRI) const override;
 
   void loadRegFromStackSlot(MachineBasicBlock &MBB,
                             MachineBasicBlock::iterator MI, Register DestReg,

llvm/lib/Target/X86/X86InstrInfo.cpp

return HasAVX512 ? X86::VMOVDI2PDIZrr :
            HasAVX    ? X86::VMOVDI2PDIrr  :
                        X86::MOVDI2PDIrr;
   return 0;
 }
 
 void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
                                MachineBasicBlock::iterator MI,
                                const DebugLoc &DL, MCRegister DestReg,
-                               MCRegister SrcReg, bool KillSrc) const {
+                               MCRegister SrcReg, bool KillSrc,
+                               const LivePhysRegs &LiveRegs) const {
   // First deal with the normal symmetric copies.
   bool HasAVX = Subtarget.hasAVX();
   bool HasVLX = Subtarget.hasVLX();
   unsigned Opc = 0;
   if (X86::GR64RegClass.contains(DestReg, SrcReg))
     Opc = X86::MOV64rr;
   else if (X86::GR32RegClass.contains(DestReg, SrcReg))
     Opc = X86::MOV32rr;

llvm/lib/Target/XCore/XCoreInstrInfo.h

public:
   unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
                         MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
                         const DebugLoc &DL,
                         int *BytesAdded = nullptr) const override;
 
   unsigned removeBranch(MachineBasicBlock &MBB,
                         int *BytesRemoved = nullptr) const override;
 
-  void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
-                   const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
-                   bool KillSrc) const override;
+  void
+  copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
+              bool KillSrc,
+              const LivePhysRegs &LiveRegs = LivePhysRegs()) const override;
 
   void storeRegToStackSlot(MachineBasicBlock &MBB,
                            MachineBasicBlock::iterator MI,
                            Register SrcReg, bool isKill, int FrameIndex,
                            const TargetRegisterClass *RC,
                            const TargetRegisterInfo *TRI) const override;
 
   void loadRegFromStackSlot(MachineBasicBlock &MBB,

llvm/lib/Target/XCore/XCoreInstrInfo.cpp

XCoreInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved) const {
   // Remove the branch.
   I->eraseFromParent();
   return 2;
 }
 
 void XCoreInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
                                  MachineBasicBlock::iterator I,
                                  const DebugLoc &DL, MCRegister DestReg,
-                                 MCRegister SrcReg, bool KillSrc) const {
+                                 MCRegister SrcReg, bool KillSrc,
+                                 const LivePhysRegs &LiveRegs) const {
   bool GRDest = XCore::GRRegsRegClass.contains(DestReg);
   bool GRSrc  = XCore::GRRegsRegClass.contains(SrcReg);
 
   if (GRDest && GRSrc) {
     BuildMI(MBB, I, DL, get(XCore::ADD_2rus), DestReg)
       .addReg(SrcReg, getKillRegState(KillSrc))
       .addImm(0);
     return;