[RISCV][RFC] Add LLVM support for RISC-V overlay system

[edward-jones]

Summary

For a description of the riscv-overlay system proposal: https://github.com/riscv-software-src/riscv-overlay/

This is the LLVM component of a change to add support for a proposed 'overlay' system for RISC-V to LLVM.

This adds two new function attributes to LLVM, 'overlay-call' and "overlay-data". These functions are used to mark functions and data which must be accessed indirectly through the overlay engine.

For global data marked as 'overlay-data' this change causes a different relocation types to be used when accessing the data. Instead of calculating the address of the data, these relocations calculate the value of the 'token' representing the data in the overlay engine.

For functions marked as 'overlay-call' a similar change occur - a 'token' is used instead of the function address for any references to an 'overlay-call' function, however there is also some additional complexity when handling 'overlay-call':

• Both calls to an 'overlay-call' function *or* from an 'overlay-call' function must go indirectly through the overlay engine.

• Calls into the overlay engine use a different calling convention. The entry point to the engine is in x31, and the token value for the target is stored to x30.

An additional change made here is to reserve a number of registers for exclusive used by the overlay engine.

[craig.topper]

llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp

627

Period at the end of the comment.

633

Period at the end of the comment.

llvm/lib/LTO/LTO.cpp

1122–1124

First letter of variable names should be capitalized.

1125

Can this be

bool isOverlayCall = isa<Function>(GV) && cast<Function>(GV)->hasFnAttribute("overlay-call");

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

2239

These lines can be shortened slightly to

case RISCV::X1: return STI.hasFeature(RISCV::FeatureReserveX1);

2277

80 columns

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp

162

Is this outer if necessary? The inner if and the assert in the inner else should be enough to check the two opcodes.

172

This assert isn't really needed. The getExpr() call on the next line will assert.

174

This assert isn't really needed, the cast<MCSymbolRefExpr> on the next line will assert if it can't cast.

176

Capitalize isOVL

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

2896

else should be on the same line as the closing curly brace above

2901

Should this be HiFlags? Why wasn't this caught by the assert that both flags are non-zero in RISCVTargetLowering::getAddr

8372

Capitalize

8384

Move after close curly brace on previous line

8389

Same

8425

Does this condition fit on in 80 columns on one line? It looks like it should

8426

Looks like you could get have one getNode call after the ifs and make the ifs choose only the opcode?

[craig.topper]

Is there a RISCV document that can be linked in the description?

[jrtc27]

llvm/include/llvm/BinaryFormat/ELFRelocs/RISCV.def

61

Obviously can't be merged like this

llvm/include/llvm/MC/MCExpr.h

356–357

Why do you need both? Functions get PLTs, objects get data pointers, it should already be implied by the type.

If this is going to be a generic concept then this shouldn't be RISC-V specific.

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

1961

This needs to go through riscv-asm-manual/riscv-toolchain-conventions approval.

Also, when would you ever have this on? It seems like if you're writing assembly you're likely to want to use reserved registers? CodeGen certainly assumes it can, because it knows what they're for, so this would break, say, existing GCC or Clang output. And currently the notion of reserved registers is purely CodeGen and up, not at the MC layer.

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

168

This change doesn't cover any of your additions but does cover ones that are already there, so makes no sense

llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp

125

Even if overlays don't make much sense outside of 32-bit, it would be nicer if the scheme were in theory generalisable to 64-bit, like how R_RISCV_RELATIVE, for example, is for whatever your XLEN is.

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp

153

Does this need to be expanded so late? It's not like CALL where there's a single relocation for the entire sequence. Can it be expanded earlier like things like LLA?

172

Not helpful

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

2817–2825

This probably warrants just being a separate function

llvm/test/CodeGen/RISCV/ovlcall-fncall.ll

1 ↗

(On Diff #371109)

Tests need to match the style of existing ones. That includes update_llc_test_checks.py.

49 ↗

(On Diff #371109)

This smells a lot like you generated this from C with dodgy code (void foo() and void foo(void) are not the same in C).

124 ↗

(On Diff #371109)

optnone makes no sense for these kinds of tests.

Target features belong on the llc call, not per-function (this does matter for the output, as it governs what ends up in the ELF attributes).

llvm/test/MC/RISCV/ovlcall-pseudos.s

10 ↗

(On Diff #371109)

This seems redundant, ovlcall should imply overlay

17 ↗

(On Diff #371109)

All these implicit register uses really scare me. If you're writing assembly I feel you should just be writing the actual thing, to be honest. This is a lot of hidden magic, and it doesn't seem at all necessary, people are going to be mostly writing in C.

llvm/test/Transforms/Inline/RISCV/riscv-overlaycall.ll

19 ↗

(On Diff #371109)

Inline it

llvm/test/Transforms/Inline/RISCV/riscv-overlaycallee.ll

19 ↗

(On Diff #371109)

Inline it

[edward-jones]

Thanks for all of the prompt feedback, I'll incorporate the suggested changes and update the patch

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

1961

Yeah, there's approval needed for the ELF reloc numbers, and the assembler changes too. This patch will be linked from pull requests to those documentation repos.

Good question about warnreservedreg. The motivation here was to help with porting existing RISC-V code which might use registers reserved for the overlay engine, so this option could be selectively disabled if code was being written for the overlay engine itself.

llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp

125

Noted, this is definitely unnecessarily restrictive.

llvm/lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h

108

I realize these need comments about their usage too

llvm/test/MC/RISCV/ovlcall-pseudos.s

17 ↗

(On Diff #371109)

Yes, originally there was a motivation to make it simpler to write these calls, but in hindsight I don't think there's a good justification for using a pseudo instruction instead of just being explicit.

[edward-jones]

I've tried to take into account most of the suggested changes into this update:

• Tidied up with clang-format
• Merge 'overlaycall' and 'overlaydata' into a single attribute, just 'overlay'
• Remove the assembler pseudo instruction and expand the calls into the overlay engine earlier during call lowering. This meant that I could simplify quite a bit. It also means implicit register use/defs aren't hidden by a instruction
• Fix up the tests
• Renamed the relocations to be prefixed with RISCV_OVLTOK or RISCV_OVLPLT. I think these names are a bit more descriptive. A OVLTOK reloc encodes a 'token' which only makes sense to the overlay system, whereas a OVLPLT is an address of a thunk which is used to handle indirect functions
• Use %ovltok_hi/%ovltok_lo/%ovlplt_lo/%ovlplt_hi/@ovlplt/@ovltok as modifiers when writing assembly

I still need to rebase this, and there are some more tests which need to be written. This patch also depends on having a way to encode the reserved register attributes in the attributes in the ELF, but AFAIK there's no patch for that functionality yet.

[edward-jones]

Some of the previously changes made were undone in order to match the spec as-written (notably I undid the renaming of relocations).

This could do with another review now because I don't expect this patch will change too much now unless the spec also changes.

[jrtc27]

In D109371#3099949, @edward-jones wrote:

Some of the previously changes made were undone in order to match the spec as-written (notably I undid the renaming of relocations).

This could do with another review now because I don't expect this patch will change too much now unless the spec also changes.

Aside from the comment I just made about this attitude on the corresponding Clang patch, standard RISC-V relocations can only be specified by the psABI, so the names absolutely can still be changed if the spec authors propose bad names.

[edward-jones]

In D109371#3099989, @jrtc27 wrote:

In D109371#3099949, @edward-jones wrote:

Some of the previously changes made were undone in order to match the spec as-written (notably I undid the renaming of relocations).

This could do with another review now because I don't expect this patch will change too much now unless the spec also changes.

Aside from the comment I just made about this attitude on the corresponding Clang patch, standard RISC-V relocations can only be specified by the psABI, so the names absolutely can still be changed if the spec authors propose bad names.

Okay, I've opened an issue for renaming the relocation in the spec: https://github.com/riscv-software-src/riscv-overlay/issues/29

I'll try and drive the changes to the spec based on feedback first and only then request more feedback here.

llvm/include/llvm/BinaryFormat/ELFRelocs/RISCV.def

 ELF_RELOC(R_RISCV_RELAX,             51)
 ELF_RELOC(R_RISCV_SUB6,              52)
 ELF_RELOC(R_RISCV_SET6,              53)
 ELF_RELOC(R_RISCV_SET8,              54)
 ELF_RELOC(R_RISCV_SET16,             55)
 ELF_RELOC(R_RISCV_SET32,             56)
 ELF_RELOC(R_RISCV_32_PCREL,          57)
 ELF_RELOC(R_RISCV_IRELATIVE,         58)
+/* Overlay extension - awaiting real numbers as part of RISC-V psABI */
+ELF_RELOC(R_RISCV_OVLTOK_HI20,       220)
+ELF_RELOC(R_RISCV_OVLTOK_LO12_I,     221)
+ELF_RELOC(R_RISCV_OVLTOK32,          222)
+ELF_RELOC(R_RISCV_OVLPLT_HI20,       223)
+ELF_RELOC(R_RISCV_OVLPLT_LO12_I,     224)
+ELF_RELOC(R_RISCV_OVLPLT32,          225)

llvm/include/llvm/IR/Attributes.td

 def : CompatRule<"isEqual<SanitizeThreadAttr>">;
 def : CompatRule<"isEqual<SanitizeMemoryAttr>">;
 def : CompatRule<"isEqual<SanitizeHWAddressAttr>">;
 def : CompatRule<"isEqual<SanitizeMemTagAttr>">;
 def : CompatRule<"isEqual<SafeStackAttr>">;
 def : CompatRule<"isEqual<ShadowCallStackAttr>">;
 def : CompatRule<"isEqual<UseSampleProfileAttr>">;
 def : CompatRule<"isEqual<NoProfileAttr>">;
+def : CompatRule<"isOverlayInlineCompat">;
 
 class MergeRule<string F> {
   // The name of the function called to merge the attributes of the caller and
   // callee. The function's signature must match
   // "void(Function&, const Function &)", where the first parameter is the
   // reference to the caller and the second parameter is the reference to the
   // callee.
   string MergeFunc = F;

llvm/include/llvm/MC/MCExpr.h

enum VariantKind : uint16_t {
     VK_VE_GOTOFF_LO32, // symbol@gotoff_lo
     VK_VE_PLT_HI32,    // symbol@plt_hi
     VK_VE_PLT_LO32,    // symbol@plt_lo
     VK_VE_TLS_GD_HI32, // symbol@tls_gd_hi
     VK_VE_TLS_GD_LO32, // symbol@tls_gd_lo
     VK_VE_TPOFF_HI32,  // symbol@tpoff_hi
     VK_VE_TPOFF_LO32,  // symbol@tpoff_lo
 
+    VK_RISCV_OVL,    // symbol@ovl
+    VK_RISCV_OVLPLT, // symbol@ovlplt
+
     VK_TPREL,
     VK_DTPREL
   };
 
 private:
   /// The symbol being referenced.
   const MCSymbol *Symbol;
 

llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp

if (Kind.isMergeableCString()) {
     Name = SizeSpec + utostr(Alignment.value());
   } else if (Kind.isMergeableConst()) {
     Name = ".rodata.cst";
     Name += utostr(EntrySize);
   } else {
     Name = getSectionPrefixForGlobal(Kind);
   }
 
+  // For overlay functions or data, prefix the default section name with
+  // ".ovlinput"
+  // For overlay functions, replace the default section name with ".ovlinput"
+  if ((isa<Function>(GO) && cast<Function>(GO)->hasFnAttribute("overlay")) ||
+      (isa<GlobalVariable>(GO) &&
+       cast<GlobalVariable>(GO)->hasAttribute("overlay")))
+    Name = ".ovlinput";
+
   bool HasPrefix = false;
   if (const auto *F = dyn_cast<Function>(GO)) {
     if (Optional<StringRef> Prefix = F->getSectionPrefix()) {
       raw_svector_ostream(Name) << '.' << *Prefix;
       HasPrefix = true;
     }
   }
 
MCSection *TargetLoweringObjectFileELF::SelectSectionForGlobal(
   bool EmitUniqueSection = false;
   if (!(Flags & ELF::SHF_MERGE) && !Kind.isCommon()) {
     if (Kind.isText())
       EmitUniqueSection = TM.getFunctionSections();
     else
       EmitUniqueSection = TM.getDataSections();
   }
   EmitUniqueSection |= GO->hasComdat();
+
+  if (Kind.isText() && isa<Function>(GO) &&
+      cast<Function>(GO)->hasFnAttribute("overlay"))
+    EmitUniqueSection = true;
+  if (isa<GlobalVariable>(GO) &&
+      cast<GlobalVariable>(GO)->hasAttribute("overlay"))
+    EmitUniqueSection = true;
+
   return selectELFSectionForGlobal(getContext(), GO, Kind, getMangler(), TM,
                                    Used.count(GO), EmitUniqueSection, Flags,
                                    &NextUniqueID);
 }
 
 MCSection *TargetLoweringObjectFileELF::getUniqueSectionForFunction(
     const Function &F, const TargetMachine &TM) const {
   SectionKind Kind = SectionKind::getText();

llvm/lib/IR/Attributes.cpp

 /// is true.
 template<typename AttrClass>
 static void setOR(Function &Caller, const Function &Callee) {
   if (!AttrClass::isSet(Caller, AttrClass::getKind()) &&
       AttrClass::isSet(Callee, AttrClass::getKind()))
     AttrClass::set(Caller, AttrClass::getKind(), true);
 }
 
+/// Check whether it is safe to inline functions marked with the 'overlay'
+/// attribute.
+static bool isOverlayInlineCompat(const Function &Caller,
+                                  const Function &Callee) {
+  return !Caller.hasFnAttribute("overlay") && !Callee.hasFnAttribute("overlay");
+}
+
 /// If the inlined function had a higher stack protection level than the
 /// calling function, then bump up the caller's stack protection level.
 static void adjustCallerSSPLevel(Function &Caller, const Function &Callee) {
   // If upgrading the SSP attribute, clear out the old SSP Attributes first.
   // Having multiple SSP attributes doesn't actually hurt, but it adds useless
   // clutter to the IR.
   AttrBuilder OldSSPAttr;
   OldSSPAttr.addAttribute(Attribute::StackProtect)

llvm/lib/LTO/LTO.cpp

for (const auto &R : GlobalResolutions) {
       GlobalValue *GV =
           RegularLTO.CombinedModule->getNamedValue(R.second.IRName);
       // Ignore symbols defined in other partitions.
       // Also skip declarations, which are not allowed to have internal linkage.
       if (!GV || GV->hasLocalLinkage() || GV->isDeclaration())
         continue;
       GV->setUnnamedAddr(R.second.UnnamedAddr ? GlobalValue::UnnamedAddr::Global
                                               : GlobalValue::UnnamedAddr::None);
-      if (EnableLTOInternalization && R.second.Partition == 0)
+      bool IsOverlay =
+          isa<Function>(GV) && cast<Function>(GV)->hasFnAttribute("overlay");
+      if (EnableLTOInternalization && R.second.Partition == 0 && !IsOverlay)
         GV->setLinkage(GlobalValue::InternalLinkage);
     }
 
     RegularLTO.CombinedModule->addModuleFlag(Module::Error, "LTOPostLink", 1);
 
     if (Conf.PostInternalizeModuleHook &&
         !Conf.PostInternalizeModuleHook(0, *RegularLTO.CombinedModule))
       return Error::success();
   }

llvm/lib/MC/MCExpr.cpp

StringRef MCSymbolRefExpr::getVariantKindName(VariantKind Kind) {
   case VK_VE_GOTOFF_HI32: return "gotoff_hi";
   case VK_VE_GOTOFF_LO32: return "gotoff_lo";
   case VK_VE_PLT_HI32: return "plt_hi";
   case VK_VE_PLT_LO32: return "plt_lo";
   case VK_VE_TLS_GD_HI32: return "tls_gd_hi";
   case VK_VE_TLS_GD_LO32: return "tls_gd_lo";
   case VK_VE_TPOFF_HI32: return "tpoff_hi";
   case VK_VE_TPOFF_LO32: return "tpoff_lo";
+  case VK_RISCV_OVLPLT: return "ovlplt";
+  case VK_RISCV_OVL: return "ovl";
   }
   llvm_unreachable("Invalid variant kind");
 }
 
 MCSymbolRefExpr::VariantKind
 MCSymbolRefExpr::getVariantKindForName(StringRef Name) {
   return StringSwitch<VariantKind>(Name.lower())
     .Case("dtprel", VK_DTPREL)
return StringSwitch<VariantKind>(Name.lower())
     .Case("gotoff_hi", VK_VE_GOTOFF_HI32)
     .Case("gotoff_lo", VK_VE_GOTOFF_LO32)
     .Case("plt_hi", VK_VE_PLT_HI32)
     .Case("plt_lo", VK_VE_PLT_LO32)
     .Case("tls_gd_hi", VK_VE_TLS_GD_HI32)
     .Case("tls_gd_lo", VK_VE_TLS_GD_LO32)
     .Case("tpoff_hi", VK_VE_TPOFF_HI32)
     .Case("tpoff_lo", VK_VE_TPOFF_LO32)
+    .Case("ovlplt", VK_RISCV_OVLPLT)
+    .Case("ovl", VK_RISCV_OVL)
     .Default(VK_Invalid);
 }
 
 /* *** */
 
 void MCTargetExpr::anchor() {}
 
 /* *** */

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

 struct RISCVOperand;
 
 struct ParserOptionsSet {
   bool IsPicEnabled;
 };
 
 class RISCVAsmParser : public MCTargetAsmParser {
   SmallVector<FeatureBitset, 4> FeatureBitStack;
+  bool WarnOnReservedReg = true;
 
   SmallVector<ParserOptionsSet, 4> ParserOptionsStack;
   ParserOptionsSet ParserOptions;
 
   SMLoc getLoc() const { return getParser().getTok().getLoc(); }
   bool isRV64() const { return getSTI().hasFeature(RISCV::Feature64Bit); }
   bool isRV32E() const { return getSTI().hasFeature(RISCV::FeatureRV32E); }
 
bool isSImm12() const {
     bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
     if (!IsConstantImm)
       IsValid = RISCVAsmParser::classifySymbolRef(getImm(), VK);
     else
       IsValid = isInt<12>(Imm);
     return IsValid && ((IsConstantImm && VK == RISCVMCExpr::VK_RISCV_None) ||
                        VK == RISCVMCExpr::VK_RISCV_LO ||
                        VK == RISCVMCExpr::VK_RISCV_PCREL_LO ||
-                       VK == RISCVMCExpr::VK_RISCV_TPREL_LO);
+                       VK == RISCVMCExpr::VK_RISCV_TPREL_LO ||
+                       VK == RISCVMCExpr::VK_RISCV_OVLPLT_LO ||
+                       VK == RISCVMCExpr::VK_RISCV_OVLTOK_LO);
   }
 
   bool isSImm12Lsb0() const { return isBareSimmNLsb0<12>(); }
 
   bool isSImm13Lsb0() const { return isBareSimmNLsb0<13>(); }
 
   bool isSImm10Lsb0000NonZero() const {
     if (!isImm())
bool isUImm20LUI() const {
     int64_t Imm;
     bool IsValid;
     if (!isImm())
       return false;
     bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
     if (!IsConstantImm) {
       IsValid = RISCVAsmParser::classifySymbolRef(getImm(), VK);
       return IsValid && (VK == RISCVMCExpr::VK_RISCV_HI ||
-                         VK == RISCVMCExpr::VK_RISCV_TPREL_HI);
+                         VK == RISCVMCExpr::VK_RISCV_TPREL_HI ||
+                         VK == RISCVMCExpr::VK_RISCV_OVLPLT_HI ||
+                         VK == RISCVMCExpr::VK_RISCV_OVLTOK_HI);
     } else {
       return isUInt<20>(Imm) && (VK == RISCVMCExpr::VK_RISCV_None ||
                                  VK == RISCVMCExpr::VK_RISCV_HI ||
-                                 VK == RISCVMCExpr::VK_RISCV_TPREL_HI);
+                                 VK == RISCVMCExpr::VK_RISCV_TPREL_HI ||
+                                 VK == RISCVMCExpr::VK_RISCV_OVLPLT_HI ||
+                                 VK == RISCVMCExpr::VK_RISCV_OVLTOK_HI);
     }
   }
 
   bool isUImm20AUIPC() const {
     RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
     int64_t Imm;
     bool IsValid;
     if (!isImm())
if (Option == "norelax") {
     if (Parser.getTok().isNot(AsmToken::EndOfStatement))
       return Error(Parser.getTok().getLoc(),
                    "unexpected token, expected end of statement");
 
     clearFeatureBits(RISCV::FeatureRelax, "relax");
     return false;
   }
 
+  if (Option == "warnreservedreg") {
+    getTargetStreamer().emitDirectiveOptionWarnReservedReg();
+
+    Parser.Lex();
+    if (Parser.getTok().isNot(AsmToken::EndOfStatement))
+      return Error(Parser.getTok().getLoc(),
+                   "unexpected token, expected end of statement");
+
+    WarnOnReservedReg = true;
+    return false;
+  }
+
+  if (Option == "nowarnreservedreg") {
+    getTargetStreamer().emitDirectiveOptionNoWarnReservedReg();
+
+    Parser.Lex();
+    if (Parser.getTok().isNot(AsmToken::EndOfStatement))
+      return Error(Parser.getTok().getLoc(),
+                   "unexpected token, expected end of statement");
+
+    WarnOnReservedReg = false;
+    return false;
+  }
+
   // Unknown option.
   Warning(Parser.getTok().getLoc(),
-          "unknown option, expected 'push', 'pop', 'rvc', 'norvc', 'relax' or "
-          "'norelax'");
+          "unknown option, expected 'push', 'pop', 'rvc', 'norvc', 'relax', "
+          "'norelax', 'warnreservedreg' or 'nowarnreservedreg'");
   Parser.eatToEndOfStatement();
   return false;
 }
 
 /// parseDirectiveAttribute
 ///  ::= .attribute expression ',' ( expression | "string" )
 ///  ::= .attribute identifier ',' ( expression | "string" )
 bool RISCVAsmParser::parseDirectiveAttribute() {
if (Tag != RISCVAttrs::ARCH) {
 
       getTargetStreamer().emitTextAttribute(Tag, formalArchStr);
     }
   }
 
   return false;
 }
 
+// Since only a RISCVGenSubtargetInfo is available here, extract register
+// reservation directly from the STI bitfields.
+static bool isRegisterReserved(MCRegister Reg, const MCSubtargetInfo &STI) {
+  switch (Reg) {
+  default: return false;
+  case RISCV::X1: return STI.getFeatureBits()[RISCV::FeatureReserveX1];
+  case RISCV::X2: return STI.getFeatureBits()[RISCV::FeatureReserveX2];
+  case RISCV::X3: return STI.getFeatureBits()[RISCV::FeatureReserveX3];
+  case RISCV::X4: return STI.getFeatureBits()[RISCV::FeatureReserveX4];
+  case RISCV::X5: return STI.getFeatureBits()[RISCV::FeatureReserveX5];
+  case RISCV::X6: return STI.getFeatureBits()[RISCV::FeatureReserveX6];
+  case RISCV::X7: return STI.getFeatureBits()[RISCV::FeatureReserveX7];
+  case RISCV::X8: return STI.getFeatureBits()[RISCV::FeatureReserveX8];
+  case RISCV::X9: return STI.getFeatureBits()[RISCV::FeatureReserveX9];
+  case RISCV::X10: return STI.getFeatureBits()[RISCV::FeatureReserveX10];
+  case RISCV::X11: return STI.getFeatureBits()[RISCV::FeatureReserveX11];
+  case RISCV::X12: return STI.getFeatureBits()[RISCV::FeatureReserveX12];
+  case RISCV::X13: return STI.getFeatureBits()[RISCV::FeatureReserveX13];
+  case RISCV::X14: return STI.getFeatureBits()[RISCV::FeatureReserveX14];
+  case RISCV::X15: return STI.getFeatureBits()[RISCV::FeatureReserveX15];
+  case RISCV::X16: return STI.getFeatureBits()[RISCV::FeatureReserveX16];
+  case RISCV::X17: return STI.getFeatureBits()[RISCV::FeatureReserveX17];
+  case RISCV::X18: return STI.getFeatureBits()[RISCV::FeatureReserveX18];
+  case RISCV::X19: return STI.getFeatureBits()[RISCV::FeatureReserveX19];
+  case RISCV::X20: return STI.getFeatureBits()[RISCV::FeatureReserveX20];
+  case RISCV::X21: return STI.getFeatureBits()[RISCV::FeatureReserveX21];
+  case RISCV::X22: return STI.getFeatureBits()[RISCV::FeatureReserveX22];
+  case RISCV::X23: return STI.getFeatureBits()[RISCV::FeatureReserveX23];
+  case RISCV::X24: return STI.getFeatureBits()[RISCV::FeatureReserveX24];
+  case RISCV::X25: return STI.getFeatureBits()[RISCV::FeatureReserveX25];
+  case RISCV::X26: return STI.getFeatureBits()[RISCV::FeatureReserveX26];
+  case RISCV::X27: return STI.getFeatureBits()[RISCV::FeatureReserveX27];
+  case RISCV::X28: return STI.getFeatureBits()[RISCV::FeatureReserveX28];
+  case RISCV::X29: return STI.getFeatureBits()[RISCV::FeatureReserveX29];
+  case RISCV::X30: return STI.getFeatureBits()[RISCV::FeatureReserveX30];
+  case RISCV::X31: return STI.getFeatureBits()[RISCV::FeatureReserveX31];
+  }
+}
+
 void RISCVAsmParser::emitToStreamer(MCStreamer &S, const MCInst &Inst) {
+  // Provide a warning about defs of reserved registers.
+  auto &Desc = MII.get(Inst.getOpcode());
+  for (unsigned i = 0; i < Desc.getNumDefs(); i++) {
+    if (Inst.getOperand(i).isReg() &&
+        isRegisterReserved(Inst.getOperand(i).getReg(), getSTI()) &&
+        WarnOnReservedReg)
+      Warning(Inst.getLoc(), "Instruction modifies reserved register");
+  }
+
   MCInst CInst;
   bool Res = compressInst(CInst, Inst, getSTI(), S.getContext());
   if (Res)
     ++RISCVNumInstrsCompressed;
   S.emitInstruction((Res ? CInst : Inst), getSTI());
 }
 
 void RISCVAsmParser::emitLoadImm(MCRegister DestReg, int64_t Value,

llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp

const static MCFixupKindInfo Infos[] = {
       {"fixup_riscv_add_32", 0, 32, 0},
       {"fixup_riscv_sub_32", 0, 32, 0},
 
       {"fixup_riscv_add_64", 0, 64, 0},
       {"fixup_riscv_sub_64", 0, 64, 0},
 
       {"fixup_riscv_set_6b", 2, 6, 0},
       {"fixup_riscv_sub_6b", 2, 6, 0},
+
+      {"fixup_riscv_ovltok_hi20", 12, 20, 0},
+      {"fixup_riscv_ovltok_lo12_i", 20, 12, 0},
+      {"fixup_riscv_ovlplt_hi20", 12, 20, 0},
+      {"fixup_riscv_ovlplt_lo12_i", 20, 12, 0},
   };
   static_assert((array_lengthof(Infos)) == RISCV::NumTargetFixupKinds,
                 "Not all fixup kinds added to Infos array");
 
   // Fixup kinds from .reloc directive are like R_RISCV_NONE. They
   // do not require any extra processing.
   if (Kind >= FirstLiteralRelocationKind)
     return MCAsmBackend::getFixupKindInfo(FK_NONE);

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

enum {
   MO_PCREL_LO = 5,
   MO_PCREL_HI = 6,
   MO_GOT_HI = 7,
   MO_TPREL_LO = 8,
   MO_TPREL_HI = 9,
   MO_TPREL_ADD = 10,
   MO_TLS_GOT_HI = 11,
   MO_TLS_GD_HI = 12,
+  MO_OVLTOK_LO = 13,
+  MO_OVLTOK_HI = 14,
+  MO_OVLPLT_LO = 15,
+  MO_OVLPLT_HI = 16,
 
   // Used to differentiate between target-specific "direct" flags and "bitmask"
   // flags. A machine operand can only have one "direct" flag, but can have
   // multiple "bitmask" flags.
-  MO_DIRECT_FLAG_MASK = 15
+  MO_DIRECT_FLAG_MASK = 31
 };
 } // namespace RISCVII
 
 namespace RISCVOp {
 enum OperandType : unsigned {
   OPERAND_FIRST_RISCV_IMM = MCOI::OPERAND_FIRST_TARGET,
   OPERAND_UIMM4 = OPERAND_FIRST_RISCV_IMM,
   OPERAND_UIMM5,

llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp

case FK_Data_1:
     return ELF::R_RISCV_NONE;
   case FK_Data_2:
     Ctx.reportError(Fixup.getLoc(), "2-byte data relocations not supported");
     return ELF::R_RISCV_NONE;
   case FK_Data_4:
     if (Expr->getKind() == MCExpr::Target &&
         cast<RISCVMCExpr>(Expr)->getKind() == RISCVMCExpr::VK_RISCV_32_PCREL)
       return ELF::R_RISCV_32_PCREL;
+    if (Expr->getKind() == MCExpr::SymbolRef &&
+        cast<MCSymbolRefExpr>(Expr)->getKind() ==
+            MCSymbolRefExpr::VK_RISCV_OVLPLT)
+      return ELF::R_RISCV_OVLPLT32;
+    if (Expr->getKind() == MCExpr::SymbolRef &&
+        cast<MCSymbolRefExpr>(Expr)->getKind() ==
+            MCSymbolRefExpr::VK_RISCV_OVL)
+      return ELF::R_RISCV_OVLTOK32;
     return ELF::R_RISCV_32;
   case FK_Data_8:
     return ELF::R_RISCV_64;
   case RISCV::fixup_riscv_hi20:
     return ELF::R_RISCV_HI20;
   case RISCV::fixup_riscv_lo12_i:
     return ELF::R_RISCV_LO12_I;
   case RISCV::fixup_riscv_lo12_s:
unsigned RISCVELFObjectWriter::getRelocType(MCContext &Ctx,
   case RISCV::fixup_riscv_add_32:
     return ELF::R_RISCV_ADD32;
   case RISCV::fixup_riscv_sub_32:
     return ELF::R_RISCV_SUB32;
   case RISCV::fixup_riscv_add_64:
     return ELF::R_RISCV_ADD64;
   case RISCV::fixup_riscv_sub_64:
     return ELF::R_RISCV_SUB64;
+  case RISCV::fixup_riscv_ovltok_hi20:
+    return ELF::R_RISCV_OVLTOK_HI20;
+  case RISCV::fixup_riscv_ovltok_lo12_i:
+    return ELF::R_RISCV_OVLTOK_LO12_I;
+  case RISCV::fixup_riscv_ovlplt_hi20:
+    return ELF::R_RISCV_OVLPLT_HI20;
+  case RISCV::fixup_riscv_ovlplt_lo12_i:
+    return ELF::R_RISCV_OVLPLT_LO12_I;
   }
 }
 
 std::unique_ptr<MCObjectTargetWriter>
 llvm::createRISCVELFObjectWriter(uint8_t OSABI, bool Is64Bit) {
   return std::make_unique<RISCVELFObjectWriter>(OSABI, Is64Bit);
 }

llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h

public:
   void emitDirectiveOptionPush() override;
   void emitDirectiveOptionPop() override;
   void emitDirectiveOptionPIC() override;
   void emitDirectiveOptionNoPIC() override;
   void emitDirectiveOptionRVC() override;
   void emitDirectiveOptionNoRVC() override;
   void emitDirectiveOptionRelax() override;
   void emitDirectiveOptionNoRelax() override;
+  void emitDirectiveOptionWarnReservedReg() override;
+  void emitDirectiveOptionNoWarnReservedReg() override;
 };
 
 MCELFStreamer *createRISCVELFStreamer(MCContext &C,
                                       std::unique_ptr<MCAsmBackend> MAB,
                                       std::unique_ptr<MCObjectWriter> MOW,
                                       std::unique_ptr<MCCodeEmitter> MCE,
                                       bool RelaxAll);
 }
 #endif

llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp

 void RISCVTargetELFStreamer::emitDirectiveOptionPush() {}
 void RISCVTargetELFStreamer::emitDirectiveOptionPop() {}
 void RISCVTargetELFStreamer::emitDirectiveOptionPIC() {}
 void RISCVTargetELFStreamer::emitDirectiveOptionNoPIC() {}
 void RISCVTargetELFStreamer::emitDirectiveOptionRVC() {}
 void RISCVTargetELFStreamer::emitDirectiveOptionNoRVC() {}
 void RISCVTargetELFStreamer::emitDirectiveOptionRelax() {}
 void RISCVTargetELFStreamer::emitDirectiveOptionNoRelax() {}
+void RISCVTargetELFStreamer::emitDirectiveOptionWarnReservedReg() {}
+void RISCVTargetELFStreamer::emitDirectiveOptionNoWarnReservedReg() {}
 
 void RISCVTargetELFStreamer::emitAttribute(unsigned Attribute, unsigned Value) {
   setAttributeItem(Attribute, Value, /*OverwriteExisting=*/true);
 }
 
 void RISCVTargetELFStreamer::emitTextAttribute(unsigned Attribute,
                                                StringRef String) {
   setAttributeItem(Attribute, String, /*OverwriteExisting=*/true);

llvm/lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h

enum Fixups {
   fixup_riscv_sub_64,
   // 6-bit fixup corresponding to R_RISCV_SET6 for local label assignment in
   // DWARF CFA.
   fixup_riscv_set_6b,
   // 6-bit fixup corresponding to R_RISCV_SUB6 for local label assignment in
   // DWARF CFA.
   fixup_riscv_sub_6b,
 
+  // 20-bit fixup corresponding to %ovltok_hi(foo) for instructions like lui
+  fixup_riscv_ovltok_hi20,
+  // 12-bit fixup corresponding to %ovltok_lo(foo) for instructions like addi
+  fixup_riscv_ovltok_lo12_i,
+  // 20-bit fixup corresponding to %ovlplt_hi(foo) for instructions like lui
+  fixup_riscv_ovlplt_hi20,
+  // 12-bit fixup corresponding to %ovlplt_lo(foo) for instructions like addi
+  fixup_riscv_ovlplt_lo12_i,
+
   // Used as a sentinel, must be the last
   fixup_riscv_invalid,
   NumTargetFixupKinds = fixup_riscv_invalid - FirstTargetFixupKind
 };
 } // end namespace RISCV
 } // end namespace llvm
 
 #endif

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp

void RISCVMCCodeEmitter::expandFunctionCall(const MCInst &MI, raw_ostream &OS,
   else
     // Emit JALR Ra, Ra, 0
     TmpInst = MCInstBuilder(RISCV::JALR).addReg(Ra).addReg(Ra).addImm(0);
   Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
   support::endian::write(OS, Binary, support::little);
 }
 
 // Expand PseudoAddTPRel to a simple ADD with the correct relocation.
 void RISCVMCCodeEmitter::expandAddTPRel(const MCInst &MI, raw_ostream &OS,
                                         SmallVectorImpl<MCFixup> &Fixups,
                                         const MCSubtargetInfo &STI) const {
   MCOperand DestReg = MI.getOperand(0);
   MCOperand SrcReg = MI.getOperand(1);
   MCOperand TPReg = MI.getOperand(2);
   assert(TPReg.isReg() && TPReg.getReg() == RISCV::X4 &&
          "Expected thread pointer as second input to TP-relative add");
 
   MCOperand SrcSymbol = MI.getOperand(3);
   assert(SrcSymbol.isExpr() &&
          "Expected expression as third input to TP-relative add");
 
   const RISCVMCExpr *Expr = dyn_cast<RISCVMCExpr>(SrcSymbol.getExpr());
   assert(Expr && Expr->getKind() == RISCVMCExpr::VK_RISCV_TPREL_ADD &&
          "Expected tprel_add relocation on TP-relative symbol");
 
   // Emit the correct tprel_add relocation for the symbol.
   Fixups.push_back(MCFixup::create(
       0, Expr, MCFixupKind(RISCV::fixup_riscv_tprel_add), MI.getLoc()));
 
   // Emit fixup_riscv_relax for tprel_add where the relax feature is enabled.
   if (STI.getFeatureBits()[RISCV::FeatureRelax]) {
     const MCConstantExpr *Dummy = MCConstantExpr::create(0, Ctx);
     Fixups.push_back(MCFixup::create(
         0, Dummy, MCFixupKind(RISCV::fixup_riscv_relax), MI.getLoc()));
   }
 
   // Emit a normal ADD instruction with the given operands.
   MCInst TmpInst = MCInstBuilder(RISCV::ADD)
                        .addOperand(DestReg)
                        .addOperand(SrcReg)
if (Kind == MCExpr::Target) {
     case RISCVMCExpr::VK_RISCV_CALL:
       FixupKind = RISCV::fixup_riscv_call;
       RelaxCandidate = true;
       break;
     case RISCVMCExpr::VK_RISCV_CALL_PLT:
       FixupKind = RISCV::fixup_riscv_call_plt;
       RelaxCandidate = true;
       break;
+    case RISCVMCExpr::VK_RISCV_OVLTOK_LO:
+      FixupKind = RISCV::fixup_riscv_ovltok_lo12_i;
+      break;
+    case RISCVMCExpr::VK_RISCV_OVLTOK_HI:
+      FixupKind = RISCV::fixup_riscv_ovltok_hi20;
+      break;
+    case RISCVMCExpr::VK_RISCV_OVLPLT_LO:
+      FixupKind = RISCV::fixup_riscv_ovlplt_lo12_i;
+      break;
+    case RISCVMCExpr::VK_RISCV_OVLPLT_HI:
+      FixupKind = RISCV::fixup_riscv_ovlplt_hi20;
+      break;
     }
   } else if (Kind == MCExpr::SymbolRef &&
              cast<MCSymbolRefExpr>(Expr)->getKind() == MCSymbolRefExpr::VK_None) {
     if (Desc.getOpcode() == RISCV::JAL) {
       FixupKind = RISCV::fixup_riscv_jal;
     } else if (MIFrm == RISCVII::InstFormatB) {
       FixupKind = RISCV::fixup_riscv_branch;
     } else if (MIFrm == RISCVII::InstFormatCJ) {

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.h

enum VariantKind {
     VK_RISCV_GOT_HI,
     VK_RISCV_TPREL_LO,
     VK_RISCV_TPREL_HI,
     VK_RISCV_TPREL_ADD,
     VK_RISCV_TLS_GOT_HI,
     VK_RISCV_TLS_GD_HI,
     VK_RISCV_CALL,
     VK_RISCV_CALL_PLT,
+    VK_RISCV_OVLTOK_LO,
+    VK_RISCV_OVLTOK_HI,
+    VK_RISCV_OVLPLT_LO,
+    VK_RISCV_OVLPLT_HI,
     VK_RISCV_32_PCREL,
     VK_RISCV_Invalid // Must be the last item
   };
 
 private:
   const MCExpr *Expr;
   const VariantKind Kind;
 

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp

return StringSwitch<RISCVMCExpr::VariantKind>(name)
       .Case("pcrel_lo", VK_RISCV_PCREL_LO)
       .Case("pcrel_hi", VK_RISCV_PCREL_HI)
       .Case("got_pcrel_hi", VK_RISCV_GOT_HI)
       .Case("tprel_lo", VK_RISCV_TPREL_LO)
       .Case("tprel_hi", VK_RISCV_TPREL_HI)
       .Case("tprel_add", VK_RISCV_TPREL_ADD)
       .Case("tls_ie_pcrel_hi", VK_RISCV_TLS_GOT_HI)
       .Case("tls_gd_pcrel_hi", VK_RISCV_TLS_GD_HI)
+      .Case("ovltok_lo", VK_RISCV_OVLTOK_LO)
+      .Case("ovltok_hi", VK_RISCV_OVLTOK_HI)
+      .Case("ovlplt_lo", VK_RISCV_OVLPLT_LO)
+      .Case("ovlplt_hi", VK_RISCV_OVLPLT_HI)
       .Default(VK_RISCV_Invalid);
 }
 
 StringRef RISCVMCExpr::getVariantKindName(VariantKind Kind) {
   switch (Kind) {
   case VK_RISCV_Invalid:
   case VK_RISCV_None:
     llvm_unreachable("Invalid ELF symbol kind");
StringRef RISCVMCExpr::getVariantKindName(VariantKind Kind) {
   case VK_RISCV_TLS_GD_HI:
     return "tls_gd_pcrel_hi";
   case VK_RISCV_CALL:
     return "call";
   case VK_RISCV_CALL_PLT:
     return "call_plt";
   case VK_RISCV_32_PCREL:
     return "32_pcrel";
+  case VK_RISCV_OVLTOK_LO:
+    return "ovltok_lo";
+  case VK_RISCV_OVLTOK_HI:
+    return "ovltok_hi";
+  case VK_RISCV_OVLPLT_LO:
+    return "ovlplt_lo";
+  case VK_RISCV_OVLPLT_HI:
+    return "ovlplt_hi";
   }
   llvm_unreachable("Invalid ELF symbol kind");
 }
 
 static void fixELFSymbolsInTLSFixupsImpl(const MCExpr *Expr, MCAssembler &Asm) {
   switch (Expr->getKind()) {
   case MCExpr::Target:
     llvm_unreachable("Can't handle nested target expression");

llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h

public:
   virtual void emitDirectiveOptionPush();
   virtual void emitDirectiveOptionPop();
   virtual void emitDirectiveOptionPIC();
   virtual void emitDirectiveOptionNoPIC();
   virtual void emitDirectiveOptionRVC();
   virtual void emitDirectiveOptionNoRVC();
   virtual void emitDirectiveOptionRelax();
   virtual void emitDirectiveOptionNoRelax();
+  virtual void emitDirectiveOptionWarnReservedReg();
+  virtual void emitDirectiveOptionNoWarnReservedReg();
   virtual void emitAttribute(unsigned Attribute, unsigned Value);
   virtual void finishAttributeSection();
   virtual void emitTextAttribute(unsigned Attribute, StringRef String);
   virtual void emitIntTextAttribute(unsigned Attribute, unsigned IntValue,
                                     StringRef StringValue);
 
   void emitTargetAttributes(const MCSubtargetInfo &STI);
 };
public:
   void emitDirectiveOptionPush() override;
   void emitDirectiveOptionPop() override;
   void emitDirectiveOptionPIC() override;
   void emitDirectiveOptionNoPIC() override;
   void emitDirectiveOptionRVC() override;
   void emitDirectiveOptionNoRVC() override;
   void emitDirectiveOptionRelax() override;
   void emitDirectiveOptionNoRelax() override;
+  void emitDirectiveOptionWarnReservedReg() override;
+  void emitDirectiveOptionNoWarnReservedReg() override;
 };
 
 }
 #endif

llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp

 void RISCVTargetStreamer::emitDirectiveOptionNoRelax() {}
 void RISCVTargetStreamer::emitAttribute(unsigned Attribute, unsigned Value) {}
 void RISCVTargetStreamer::finishAttributeSection() {}
 void RISCVTargetStreamer::emitTextAttribute(unsigned Attribute,
                                             StringRef String) {}
 void RISCVTargetStreamer::emitIntTextAttribute(unsigned Attribute,
                                                unsigned IntValue,
                                                StringRef StringValue) {}
+void RISCVTargetStreamer::emitDirectiveOptionWarnReservedReg() {}
+void RISCVTargetStreamer::emitDirectiveOptionNoWarnReservedReg() {}
 
 void RISCVTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI) {
   if (STI.hasFeature(RISCV::FeatureRV32E))
     emitAttribute(RISCVAttrs::STACK_ALIGN, RISCVAttrs::ALIGN_4);
   else
     emitAttribute(RISCVAttrs::STACK_ALIGN, RISCVAttrs::ALIGN_16);
 
   std::string Arch = "rv32";
void RISCVTargetAsmStreamer::emitTextAttribute(unsigned Attribute,
   OS << "\t.attribute\t" << Attribute << ", \"" << String << "\"\n";
 }
 
 void RISCVTargetAsmStreamer::emitIntTextAttribute(unsigned Attribute,
                                                   unsigned IntValue,
                                                   StringRef StringValue) {}
 
 void RISCVTargetAsmStreamer::finishAttributeSection() {}
+
+void RISCVTargetAsmStreamer::emitDirectiveOptionWarnReservedReg() {
+  OS << "\t.option\twarnreservedreg\n";
+}
+
+void RISCVTargetAsmStreamer::emitDirectiveOptionNoWarnReservedReg() {
+  OS << "\t.option\tnowarnreservedreg\n";
+}

llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp

public:
   explicit RISCVAsmPrinter(TargetMachine &TM,
                            std::unique_ptr<MCStreamer> Streamer)
       : AsmPrinter(TM, std::move(Streamer)), STI(TM.getMCSubtargetInfo()) {}
 
   StringRef getPassName() const override { return "RISCV Assembly Printer"; }
 
   bool runOnMachineFunction(MachineFunction &MF) override;
 
+  const MCExpr *lowerConstant(const Constant *CV) override;
+  void SetupMachineFunction(MachineFunction &MF) override;
+
   void emitInstruction(const MachineInstr *MI) override;
 
   bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
                        const char *ExtraCode, raw_ostream &OS) override;
   bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
                              const char *ExtraCode, raw_ostream &OS) override;
 
   void EmitToStreamer(MCStreamer &S, const MCInst &Inst);

 }
 
 void RISCVAsmPrinter::emitAttributes() {
   RISCVTargetStreamer &RTS =
       static_cast<RISCVTargetStreamer &>(*OutStreamer->getTargetStreamer());
   RTS.emitTargetAttributes(*STI);
 }
 
+const MCExpr *RISCVAsmPrinter::lowerConstant(const Constant *CV) {
+  if (auto *Fn = dyn_cast<Function>(CV)) {
+    if (Fn->hasFnAttribute("overlay")) {
+      const MCSymbolRefExpr *Expr =
+          MCSymbolRefExpr::create(getSymbol(cast<GlobalValue>(CV)),
+                                  MCSymbolRefExpr::VK_RISCV_OVLPLT, OutContext);
+      return Expr;
+    }
+  }
+  if (auto *GV = dyn_cast<GlobalVariable>(CV)) {
+    if (GV->hasAttribute("overlay")) {
+      const MCSymbolRefExpr *Expr =
+          MCSymbolRefExpr::create(getSymbol(cast<GlobalValue>(CV)),
+                                  MCSymbolRefExpr::VK_RISCV_OVL, OutContext);
+      return Expr;
+    }
+  }
+  return AsmPrinter::lowerConstant(CV);
+}
+void RISCVAsmPrinter::SetupMachineFunction(MachineFunction &MF) {
+  // Set the current MCSubtargetInfo to a copy which has the correct
+  // feature bits for the current MachineFunction
+  MCSubtargetInfo &NewSTI =
+    OutStreamer->getContext().getSubtargetCopy(*TM.getMCSubtargetInfo());
+  NewSTI.setFeatureBits(MF.getSubtarget().getFeatureBits());
+  STI = &NewSTI;
+
+  return AsmPrinter::SetupMachineFunction(MF);
+}
+
 // Force static initialization.
 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVAsmPrinter() {
   RegisterAsmPrinter<RISCVAsmPrinter> X(getTheRISCV32Target());
   RegisterAsmPrinter<RISCVAsmPrinter> Y(getTheRISCV64Target());
 }

llvm/lib/Target/RISCV/RISCVISelLowering.h

 namespace RISCVISD {
 enum NodeType : unsigned {
   FIRST_NUMBER = ISD::BUILTIN_OP_END,
   RET_FLAG,
   URET_FLAG,
   SRET_FLAG,
   MRET_FLAG,
   CALL,
+  CALL_OVERLAY,
   /// Select with condition operator - This selects between a true value and
   /// a false value (ops #3 and #4) based on the boolean result of comparing
   /// the lhs and rhs (ops #0 and #1) of a conditional expression with the
   /// condition code in op #2, a XLenVT constant from the ISD::CondCode enum.
   /// The lhs and rhs are XLenVT integers. The true and false values can be
   /// integer or floating point.
   SELECT_CC,
   BR_CC,

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

 }
 
 template <class NodeTy>
 SDValue RISCVTargetLowering::getAddr(NodeTy *N, SelectionDAG &DAG,
                                      bool IsLocal) const {
   SDLoc DL(N);
   EVT Ty = getPointerTy(DAG.getDataLayout());
 
   if (isPositionIndependent()) {
     SDValue Addr = getTargetNode(N, DL, Ty, DAG, 0);
     if (IsLocal)
       // Use PC-relative addressing to access the symbol. This generates the
       // pattern (PseudoLLA sym), which expands to (addi (auipc %pcrel_hi(sym))
       // %pcrel_lo(auipc)).
       return SDValue(DAG.getMachineNode(RISCV::PseudoLLA, DL, Ty, Addr), 0);
 
     // Use PC-relative addressing to access the GOT for this symbol, then load
     // the address from the GOT. This generates the pattern (PseudoLA sym),
     // which expands to (ld (addi (auipc %got_pcrel_hi(sym)) %pcrel_lo(auipc))).
     return SDValue(DAG.getMachineNode(RISCV::PseudoLA, DL, Ty, Addr), 0);
   }
 
   switch (getTargetMachine().getCodeModel()) {
   default:
     report_fatal_error("Unsupported code model for lowering");
SDValue RISCVTargetLowering::lowerGlobalAddress(SDValue Op,
   SDLoc DL(Op);
   EVT Ty = Op.getValueType();
   GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op);
   int64_t Offset = N->getOffset();
   MVT XLenVT = Subtarget.getXLenVT();
 
   const GlobalValue *GV = N->getGlobal();
   bool IsLocal = getTargetMachine().shouldAssumeDSOLocal(*GV->getParent(), GV);
+
+  // Handle addresses of globals and functions which are in overlays.
+  auto *F = dyn_cast<Function>(GV);
+  auto *G = dyn_cast<GlobalVariable>(GV);
+  bool IsOverlayFn = F && F->hasFnAttribute("overlay");
+  bool IsOverlayData = G && G->hasAttribute("overlay");
+  if (IsOverlayFn || IsOverlayData) {
+    if (Offset != 0)
+      report_fatal_error("Arithmetic on overlay tokens is not supported");
+
+    SDValue AddrHi = getTargetNode(N, DL, Ty, DAG,
+                                   IsOverlayFn ? RISCVII::MO_OVLPLT_HI
+                                               : RISCVII::MO_OVLTOK_HI);
+    SDValue AddrLo = getTargetNode(N, DL, Ty, DAG,
+                                   IsOverlayFn ? RISCVII::MO_OVLPLT_LO
+                                               : RISCVII::MO_OVLTOK_LO);
+    SDValue LoadHi = SDValue(DAG.getMachineNode(RISCV::LUI, DL, Ty, AddrHi), 0);
+    return SDValue(DAG.getMachineNode(RISCV::ADDI, DL, Ty, LoadHi, AddrLo), 0);
+  }
+
   SDValue Addr = getAddr(N, DAG, IsLocal);
 
   // In order to maximise the opportunity for common subexpression elimination,
   // emit a separate ADD node for the global address offset instead of folding
   // it in the global address node. Later peephole optimisations may choose to
   // fold it back in when profitable.
   if (Offset != 0)
     return DAG.getNode(ISD::ADD, DL, Ty, Addr,
                        DAG.getConstant(Offset, DL, XLenVT));
   return Addr;
 }
 
 SDValue RISCVTargetLowering::lowerBlockAddress(SDValue Op,
                                                SelectionDAG &DAG) const {
   BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op);
 
   return getAddr(N, DAG);
 }
 
 SDValue RISCVTargetLowering::lowerConstantPool(SDValue Op,
                                                SelectionDAG &DAG) const {
   ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
 
   return getAddr(N, DAG);
 }
 
 SDValue RISCVTargetLowering::lowerJumpTable(SDValue Op,
                                             SelectionDAG &DAG) const {

 // benchmark. But theoretically, it may has benenfit for some cases.
 static bool CC_RISCV_FastCC(const DataLayout &DL, RISCVABI::ABI ABI,
                             unsigned ValNo, MVT ValVT, MVT LocVT,
                             CCValAssign::LocInfo LocInfo,
                             ISD::ArgFlagsTy ArgFlags, CCState &State,
                             bool IsFixed, bool IsRet, Type *OrigTy,
                             const RISCVTargetLowering &TLI,
                             Optional<unsigned> FirstMaskArgument) {
+  const auto &STI = TLI.getSubtarget();
 
   // X5 and X6 might be used for save-restore libcall.
   static const MCPhysReg GPRList[] = {
       RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14,
       RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X7,  RISCV::X28,
       RISCV::X29, RISCV::X30, RISCV::X31};
 
   if (LocVT == MVT::i32 || LocVT == MVT::i64) {
-    if (unsigned Reg = State.AllocateReg(GPRList)) {
+    ArrayRef<MCPhysReg> Regs = GPRList;
+    for (unsigned i = 0; i < Regs.size(); i++) {
+      // Skip registers that the user has reserved
+      if (STI.isRegisterReservedByUser(Regs[i]))
+        continue;
+
+      if (unsigned Reg = State.AllocateReg(Regs[i])) {
         State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
         return false;
       }
     }
+  }
 
   if (LocVT == MVT::f16) {
     static const MCPhysReg FPR16List[] = {
         RISCV::F10_H, RISCV::F11_H, RISCV::F12_H, RISCV::F13_H, RISCV::F14_H,
         RISCV::F15_H, RISCV::F16_H, RISCV::F17_H, RISCV::F0_H,  RISCV::F1_H,
         RISCV::F2_H,  RISCV::F3_H,  RISCV::F4_H,  RISCV::F5_H,  RISCV::F6_H,
         RISCV::F7_H,  RISCV::F28_H, RISCV::F29_H, RISCV::F30_H, RISCV::F31_H};
     if (unsigned Reg = State.AllocateReg(FPR16List)) {
bool RISCVTargetLowering::isEligibleForTailCallOptimization(
   // Exception-handling functions need a special set of instructions to
   // indicate a return to the hardware. Tail-calling another function would
   // probably break this.
   // TODO: The "interrupt" attribute isn't currently defined by RISC-V. This
   // should be expanded as new function attributes are introduced.
   if (Caller.hasFnAttribute("interrupt"))
     return false;
 
+  // Overlay function can never tailcall, nor can be tail called
+  if (Caller.hasFnAttribute("overlay"))
+    return false;
+  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
+    if (auto *CalleeF = dyn_cast<Function>(G->getGlobal()))
+      if (CalleeF->hasFnAttribute("overlay"))
+        return false;
+  }
+
   // Do not tail call opt if the stack is used to pass parameters.
   if (CCInfo.getNextStackOffset() != 0)
     return false;
 
   // Do not tail call opt if any parameters need to be passed indirectly.
   // Since long doubles (fp128) and i128 are larger than 2*XLEN, they are
   // passed indirectly. So the address of the value will be passed in a
   // register, or if not available, then the address is put on the stack. In
SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI,
   SDValue Glue;
 
   // Build a sequence of copy-to-reg nodes, chained and glued together.
   for (auto &Reg : RegsToPass) {
     Chain = DAG.getCopyToReg(Chain, DL, Reg.first, Reg.second, Glue);
     Glue = Chain.getValue(1);
   }
 
+  // If the caller is a globaladdress, and the caller or callee is marked
+  // 'overlay', then the target token must be placed in x30 and then a call
+  // must be made through the overlay system entry point preserved in x31.
+  bool IsOverlayCall = false;
+  if (auto *N = dyn_cast<GlobalAddressSDNode>(Callee)) {
+    IsOverlayCall = MF.getFunction().hasFnAttribute("overlay");
+    auto *F = dyn_cast<Function>(N->getGlobal());
+    if (F && F->hasFnAttribute("overlay")) {
+      EVT Ty = N->getValueType(0);
+      IsOverlayCall = true;
+      SDValue AddrHi = getTargetNode(N, DL, Ty, DAG, RISCVII::MO_OVLTOK_HI);
+      SDValue AddrLo = getTargetNode(N, DL, Ty, DAG, RISCVII::MO_OVLTOK_LO);
+      SDValue LoadHi =
+          SDValue(DAG.getMachineNode(RISCV::LUI, DL, Ty, AddrHi), 0);
+      Callee =
+          SDValue(DAG.getMachineNode(RISCV::ADDI, DL, Ty, LoadHi, AddrLo), 0);
+    }
+  }
+  if (IsOverlayCall) {
+    IsTailCall = false;
+    Chain = DAG.getCopyToReg(Chain, DL, RISCV::X30, Callee, Glue);
+    Glue = Chain.getValue(1);
+  }
+
   // Validate that none of the argument registers have been marked as
   // reserved, if so report an error. Do the same for the return address if this
   // is not a tailcall.
   validateCCReservedRegs(RegsToPass, MF);
   if (!IsTailCall &&
       MF.getSubtarget<RISCVSubtarget>().isRegisterReservedByUser(RISCV::X1))
     MF.getFunction().getContext().diagnose(DiagnosticInfoUnsupported{
         MF.getFunction(),
         "Return address register required, but has been reserved."});
 
+  // The first call operand is the chain
+  SmallVector<SDValue, 8> Ops;
+  Ops.push_back(Chain);
+
+  // For a non-overlay call
   // If the callee is a GlobalAddress/ExternalSymbol node, turn it into a
   // TargetGlobalAddress/TargetExternalSymbol node so that legalize won't
   // split it and then direct call can be matched by PseudoCALL.
+  if (!IsOverlayCall) {
     if (GlobalAddressSDNode *S = dyn_cast<GlobalAddressSDNode>(Callee)) {
       const GlobalValue *GV = S->getGlobal();
 
       unsigned OpFlags = RISCVII::MO_CALL;
       if (!getTargetMachine().shouldAssumeDSOLocal(*GV->getParent(), GV))
         OpFlags = RISCVII::MO_PLT;
 
       Callee = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, OpFlags);
     } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
       unsigned OpFlags = RISCVII::MO_CALL;
 
       if (!getTargetMachine().shouldAssumeDSOLocal(*MF.getFunction().getParent(),
                                                    nullptr))
         OpFlags = RISCVII::MO_PLT;
 
       Callee = DAG.getTargetExternalSymbol(S->getSymbol(), PtrVT, OpFlags);
     }
 
-  // The first call operand is the chain and the second is the target address.
-  SmallVector<SDValue, 8> Ops;
-  Ops.push_back(Chain);
+    // The second operand for a non-overlay call is the target address
     Ops.push_back(Callee);
+  }
 
   // Add argument registers to the end of the list so that they are
   // known live into the call.
   for (auto &Reg : RegsToPass)
     Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType()));
 
   if (!IsTailCall) {
     // Add a register mask operand representing the call-preserved registers.
SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI,
   // Emit the call.
   SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
 
   if (IsTailCall) {
     MF.getFrameInfo().setHasTailCall();
     return DAG.getNode(RISCVISD::TAIL, DL, NodeTys, Ops);
   }
 
+  if (!IsOverlayCall)
     Chain = DAG.getNode(RISCVISD::CALL, DL, NodeTys, Ops);
+  else
+    Chain = DAG.getNode(RISCVISD::CALL_OVERLAY, DL, NodeTys, Ops);
+
   DAG.addNoMergeSiteInfo(Chain.getNode(), CLI.NoMerge);
   Glue = Chain.getValue(1);
 
   // Mark the end of the call, which is glued to the call itself.
   Chain = DAG.getCALLSEQ_END(Chain,
                              DAG.getConstant(NumBytes, DL, PtrVT, true),
                              DAG.getConstant(0, DL, PtrVT, true),
                              Glue, DL);
   Glue = Chain.getValue(1);
 
#define NODE_NAME_CASE(NODE)                                                   \
   switch ((RISCVISD::NodeType)Opcode) {
   case RISCVISD::FIRST_NUMBER:
     break;
   NODE_NAME_CASE(RET_FLAG)
   NODE_NAME_CASE(URET_FLAG)
   NODE_NAME_CASE(SRET_FLAG)
   NODE_NAME_CASE(MRET_FLAG)
   NODE_NAME_CASE(CALL)
+  NODE_NAME_CASE(CALL_OVERLAY)
   NODE_NAME_CASE(SELECT_CC)
   NODE_NAME_CASE(BR_CC)
   NODE_NAME_CASE(BuildPairF64)
   NODE_NAME_CASE(SplitF64)
   NODE_NAME_CASE(TAIL)
   NODE_NAME_CASE(MULHSU)
   NODE_NAME_CASE(SLLW)
   NODE_NAME_CASE(SRAW)

llvm/lib/Target/RISCV/RISCVInstrInfo.td

 // Target-independent type requirements, but with target-specific formats.
 def SDT_CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>,
                                        SDTCisVT<1, i32>]>;
 def SDT_CallSeqEnd   : SDCallSeqEnd<[SDTCisVT<0, i32>,
                                      SDTCisVT<1, i32>]>;
 
 // Target-dependent type requirements.
 def SDT_RISCVCall     : SDTypeProfile<0, -1, [SDTCisVT<0, XLenVT>]>;
+def SDT_RISCVCallOverlay : SDTypeProfile<0, -1, []>;
 def SDT_RISCVSelectCC : SDTypeProfile<1, 5, [SDTCisSameAs<1, 2>,
                                              SDTCisVT<3, OtherVT>,
                                              SDTCisSameAs<0, 4>,
                                              SDTCisSameAs<4, 5>]>;
 def SDT_RISCVBrCC : SDTypeProfile<0, 4, [SDTCisSameAs<0, 1>,
                                          SDTCisVT<2, OtherVT>,
                                          SDTCisVT<3, OtherVT>]>;
 def SDT_RISCVReadCSR  : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisInt<1>]>;
def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_CallSeqStart,
                            [SDNPHasChain, SDNPOutGlue]>;
 def callseq_end   : SDNode<"ISD::CALLSEQ_END", SDT_CallSeqEnd,
                            [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
 
 // Target-dependent nodes.
 def riscv_call      : SDNode<"RISCVISD::CALL", SDT_RISCVCall,
                              [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
                               SDNPVariadic]>;
+def riscv_call_overlay : SDNode<"RISCVISD::CALL_OVERLAY", SDT_RISCVCallOverlay,
+                                [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
+                                 SDNPVariadic]>;
 def riscv_ret_flag  : SDNode<"RISCVISD::RET_FLAG", SDTNone,
                              [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
 def riscv_uret_flag : SDNode<"RISCVISD::URET_FLAG", SDTNone,
                              [SDNPHasChain, SDNPOptInGlue]>;
 def riscv_sret_flag : SDNode<"RISCVISD::SRET_FLAG", SDTNone,
                              [SDNPHasChain, SDNPOptInGlue]>;
 def riscv_mret_flag : SDNode<"RISCVISD::MRET_FLAG", SDTNone,
                              [SDNPHasChain, SDNPOptInGlue]>;

 def : Pat<(riscv_sret_flag), (SRET X0, X0)>;
 def : Pat<(riscv_mret_flag), (MRET X0, X0)>;
 
 let isCall = 1, Defs = [X1] in
 def PseudoCALLIndirect : Pseudo<(outs), (ins GPRJALR:$rs1),
                                 [(riscv_call GPRJALR:$rs1)]>,
                          PseudoInstExpansion<(JALR X1, GPR:$rs1, 0)>;
 
+let isCall = 1, Defs = [X1], Uses = [X30, X31] in
+def PseudoCallOverlay : Pseudo<(outs), (ins),
+                               [(riscv_call_overlay)]>,
+                        PseudoInstExpansion<(JALR X1, X31, 0)>;
+
 let isBarrier = 1, isReturn = 1, isTerminator = 1 in
 def PseudoRET : Pseudo<(outs), (ins), [(riscv_ret_flag)]>,
                 PseudoInstExpansion<(JALR X0, X1, 0)>;
 
 // PseudoTAIL is a pseudo instruction similar to PseudoCALL and will eventually
 // expand to auipc and jalr while encoding.
 // Define AsmString to print "tail" when compile with -S flag.
 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [X2],

llvm/lib/Target/RISCV/RISCVMCInstLower.cpp

case RISCVII::MO_TPREL_ADD:
     Kind = RISCVMCExpr::VK_RISCV_TPREL_ADD;
     break;
   case RISCVII::MO_TLS_GOT_HI:
     Kind = RISCVMCExpr::VK_RISCV_TLS_GOT_HI;
     break;
   case RISCVII::MO_TLS_GD_HI:
     Kind = RISCVMCExpr::VK_RISCV_TLS_GD_HI;
     break;
+  case RISCVII::MO_OVLTOK_LO:
+    Kind = RISCVMCExpr::VK_RISCV_OVLTOK_LO;
+    break;
+  case RISCVII::MO_OVLTOK_HI:
+    Kind = RISCVMCExpr::VK_RISCV_OVLTOK_HI;
+    break;
+  case RISCVII::MO_OVLPLT_LO:
+    Kind = RISCVMCExpr::VK_RISCV_OVLPLT_LO;
+    break;
+  case RISCVII::MO_OVLPLT_HI:
+    Kind = RISCVMCExpr::VK_RISCV_OVLPLT_HI;
+    break;
   }
 
   const MCExpr *ME =
       MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, Ctx);
 
   if (!MO.isJTI() && !MO.isMBB() && MO.getOffset())
     ME = MCBinaryExpr::createAdd(
         ME, MCConstantExpr::create(MO.getOffset(), Ctx), Ctx);

llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp

if (Call.isConvergent() && !CalleeF->isConvergent() &&
       return &Call;
     }
 
     // If the call and callee calling conventions don't match, and neither one
     // of the calling conventions is compatible with C calling convention
     // this call must be unreachable, as the call is undefined.
     if ((CalleeF->getCallingConv() != Call.getCallingConv() &&
          !(CalleeF->getCallingConv() == llvm::CallingConv::C &&
+           Call.getFunction()->hasFnAttribute("overlay")) &&
+         !(Call.getCallingConv() == llvm::CallingConv::C &&
+           CalleeF->hasFnAttribute("overlay")) &&
+         !(CalleeF->getCallingConv() == llvm::CallingConv::C &&
            TargetLibraryInfoImpl::isCallingConvCCompatible(&Call)) &&
          !(Call.getCallingConv() == llvm::CallingConv::C &&
            TargetLibraryInfoImpl::isCallingConvCCompatible(CalleeF))) &&
         // Only do this for calls to a function with a body.  A prototype may
         // not actually end up matching the implementation's calling conv for a
         // variety of reasons (e.g. it may be written in assembly).
         !CalleeF->isDeclaration()) {
       Instruction *OldCall = &Call;

llvm/test/CodeGen/RISCV/overlay-calls.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 \
+; RUN:   -mattr=+reserve-x28,+reserve-x29,+reserve-x30,+reserve-x31 \
+; RUN:   -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s
+
+; Test for overlay system function call instructions/relocations
+
+@global_fnptr_to_overlay = global void ()* @overlay_callee, align 4
+@global_fnptr_to_resident = global void ()* @resident_callee, align 4
+
+declare void @overlay_callee() #0
+declare void @resident_callee() #1
+
+declare void @llvm.memcpy.p0i8.p0i8.i32(i8* noalias nocapture writeonly, i8* noalias nocapture readonly, i32, i1 immarg) #2
+
+define void @overlay_caller1() #0 {
+; CHECK-LABEL: overlay_caller1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -16
+; CHECK-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; CHECK-NEXT:    lui a0, %ovltok_hi(overlay_callee)
+; CHECK-NEXT:    addi t5, a0, %ovltok_lo(overlay_callee)
+; CHECK-NEXT:    jalr t6
+; CHECK-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    ret
+  call void @overlay_callee()
+  ret void
+}
+
+define void @overlay_caller2() #0 {
+; CHECK-LABEL: overlay_caller2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -16
+; CHECK-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; CHECK-NEXT:    lui a0, %hi(resident_callee)
+; CHECK-NEXT:    addi t5, a0, %lo(resident_callee)
+; CHECK-NEXT:    jalr t6
+; CHECK-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    ret
+  call void @resident_callee()
+  ret void
+}
+
+define void ()* @overlay_caller3() #0 {
+; CHECK-LABEL: overlay_caller3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, %ovlplt_hi(overlay_callee)
+; CHECK-NEXT:    addi a0, a0, %ovlplt_lo(overlay_callee)
+; CHECK-NEXT:    ret
+  ret void ()* @overlay_callee
+}
+
+define void ()* @overlay_caller4() #0 {
+; CHECK-LABEL: overlay_caller4:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, %hi(resident_callee)
+; CHECK-NEXT:    addi a0, a0, %lo(resident_callee)
+; CHECK-NEXT:    ret
+  ret void ()* @resident_callee
+}
+
+define void @overlay_caller5() #0 {
+; CHECK-LABEL: overlay_caller5:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -16
+; CHECK-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; CHECK-NEXT:    lui a0, %hi(global_fnptr_to_overlay)
+; CHECK-NEXT:    lw a0, %lo(global_fnptr_to_overlay)(a0)
+; CHECK-NEXT:    jalr a0
+; CHECK-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    ret
+  %1 = load void ()*, void ()** @global_fnptr_to_overlay, align 4
+  call void %1()
+  ret void
+}
+
+define void @overlay_caller6() #0 {
+; CHECK-LABEL: overlay_caller6:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -16
+; CHECK-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; CHECK-NEXT:    lui a0, %hi(global_fnptr_to_resident)
+; CHECK-NEXT:    lw a0, %lo(global_fnptr_to_resident)(a0)
+; CHECK-NEXT:    jalr a0
+; CHECK-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    ret
+  %1 = load void ()*, void ()** @global_fnptr_to_resident, align 4
+  call void %1()
+  ret void
+}
+
+; Check that a call to an external function like memcpy works correctly
+define void @overlay_caller_memcpy(i8* %a, i8* %b, i32 %c) #0 {
+; CHECK-LABEL: overlay_caller_memcpy:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -16
+; CHECK-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; CHECK-NEXT:    call memcpy@plt
+; CHECK-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    ret
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8* %a, i8* %b, i32 %c, i1 false)
+  ret void
+}
+
+define void @resident_caller1() #1 {
+; CHECK-LABEL: resident_caller1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -16
+; CHECK-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; CHECK-NEXT:    lui a0, %ovltok_hi(overlay_callee)
+; CHECK-NEXT:    addi t5, a0, %ovltok_lo(overlay_callee)
+; CHECK-NEXT:    jalr t6
+; CHECK-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    ret
+  call void @overlay_callee()
+  ret void
+}
+
+define void @resident_caller2() #1 {
+; CHECK-LABEL: resident_caller2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -16
+; CHECK-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; CHECK-NEXT:    call resident_callee@plt
+; CHECK-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    ret
+  call void @resident_callee()
+  ret void
+}
+
+define void ()* @resident_caller3() #1 {
+; CHECK-LABEL: resident_caller3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, %ovlplt_hi(overlay_callee)
+; CHECK-NEXT:    addi a0, a0, %ovlplt_lo(overlay_callee)
+; CHECK-NEXT:    ret
+  ret void ()* @overlay_callee
+}
+
+define void ()* @resident_caller4() #1 {
+; CHECK-LABEL: resident_caller4:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, %hi(resident_callee)
+; CHECK-NEXT:    addi a0, a0, %lo(resident_callee)
+; CHECK-NEXT:    ret
+  ret void ()* @resident_callee
+}
+
+define void @resident_caller5() #1 {
+; CHECK-LABEL: resident_caller5:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -16
+; CHECK-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; CHECK-NEXT:    lui a0, %hi(global_fnptr_to_overlay)
+; CHECK-NEXT:    lw a0, %lo(global_fnptr_to_overlay)(a0)
+; CHECK-NEXT:    jalr a0
+; CHECK-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    ret
+  %1 = load void ()*, void ()** @global_fnptr_to_overlay, align 4
+  call void %1()
+  ret void
+}
+
+define void @resident_caller6() #1 {
+; CHECK-LABEL: resident_caller6:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -16
+; CHECK-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; CHECK-NEXT:    lui a0, %hi(global_fnptr_to_resident)
+; CHECK-NEXT:    lw a0, %lo(global_fnptr_to_resident)(a0)
+; CHECK-NEXT:    jalr a0
+; CHECK-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    ret
+  %1 = load void ()*, void ()** @global_fnptr_to_resident, align 4
+  call void %1()
+  ret void
+}
+
+define void @resident_caller_memcpy(i8* %a, i8* %b, i32 %c) #1 {
+; CHECK-LABEL: resident_caller_memcpy:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -16
+; CHECK-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; CHECK-NEXT:    call memcpy@plt
+; CHECK-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    ret
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8* %a, i8* %b, i32 %c, i1 false)
+  ret void
+}
+
+attributes #0 = { noinline nounwind "overlay" }
+attributes #1 = { noinline nounwind }
+attributes #2 = { argmemonly nounwind willreturn }

llvm/test/CodeGen/RISCV/overlay-sections.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 \
+; RUN:   -mattr=+reserve-x28,+reserve-x29,+reserve-x30,+reserve-x31 \
+; RUN:   -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s
+
+; Test that overlay functions are placed into a section with the correct
+; prefix
+
+define i32 @overlay_fn() "overlay" {
+; CHECK: .section  .ovlinput.overlay_fn
+; CHECK-LABEL: overlay_fn:
+  ret i32 0
+}
+
+define i32 @resident_fn() {
+; CHECK: .text
+; CHECK-LABEL: resident_fn:
+  ret i32 0
+}

llvm/test/MC/RISCV/option-invalid.s

 # RUN: not llvm-mc -triple riscv32 < %s 2>&1 \
 # RUN:   | FileCheck -check-prefixes=CHECK %s
 
 # CHECK: error: unexpected token, expected identifier
 .option
 
 # CHECK: error: unexpected token, expected identifier
 .option 123
 
 # CHECK: error: unexpected token, expected identifier
 .option "str"
 
 # CHECK: error: unexpected token, expected end of statement
 .option rvc foo
 
-# CHECK: warning: unknown option, expected 'push', 'pop', 'rvc', 'norvc', 'relax' or 'norelax'
+# CHECK: warning: unknown option, expected 'push', 'pop', 'rvc', 'norvc', 'relax', 'norelax', 'warnreservedreg' or 'nowarnreservedreg'
 .option bar
 
 # CHECK: error: .option pop with no .option push
 .option pop
 
 # CHECK: error: unexpected token, expected end of statement
 .option push 123
 
 # CHECK: error: unexpected token, expected end of statement
 .option pop 123

llvm/test/MC/RISCV/overlay.s

+# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
+# RUN:   | llvm-objdump -d - | FileCheck --check-prefix=INSTR %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
+# RUN:   | llvm-readobj -r - | FileCheck -check-prefix=RELOC %s
+# RUN: llvm-mc -triple riscv32 < %s -show-encoding \
+# RUN:   | FileCheck -check-prefix=FIXUP %s
+
+lui a4, %ovltok_hi(foo)
+# RELOC: R_RISCV_OVLTOK_HI20 foo 0x0
+# INSTR: lui a4, 0
+# FIXUP: fixup A - offset: 0, value: %ovltok_hi(foo), kind: fixup_riscv_ovltok_hi20
+
+addi a4, a5, %ovltok_lo(foo)
+# RELOC: R_RISCV_OVLTOK_LO12_I foo 0x0
+# INSTR: mv a4, a5
+# FIXUP: fixup A - offset: 0, value: %ovltok_lo(foo), kind: fixup_riscv_ovltok_lo12_i
+
+lui a4, %ovlplt_hi(foo)
+# RELOC: R_RISCV_OVLPLT_HI20 foo 0x0
+# INSTR: lui a4, 0
+# FIXUP: fixup A - offset: 0, value: %ovlplt_hi(foo), kind: fixup_riscv_ovlplt_hi20
+
+addi a4, a5, %ovlplt_lo(foo)
+# RELOC: R_RISCV_OVLPLT_LO12_I foo 0x0
+# INSTR: mv a4, a5
+# FIXUP: fixup A - offset: 0, value: %ovlplt_lo(foo), kind: fixup_riscv_ovlplt_lo12_i
+
+.word foo@ovl
+# RELOC: R_RISCV_OVLTOK32 foo 0x0
+
+.word foo@ovlplt
+# RELOC: R_RISCV_OVLPLT32 foo 0x0

llvm/test/Transforms/Inline/RISCV/lit.local.cfg

+if not 'RISCV' in config.root.targets:
+    config.unsupported = True

llvm/test/Transforms/Inline/RISCV/riscv-overlay-callee.ll

+; RUN: opt -inline -S %s | FileCheck %s
+; RUN: opt -passes='cgscc(inline)' -S %s | FileCheck %s
+
+define void @f() {
+; CHECK-LABEL: @f
+; CHECK: call
+entry:
+  tail call void @g()
+  unreachable
+}
+
+define void @g() "overlay" {
+; CHECK-LABEL: @g
+entry:
+  unreachable
+}

llvm/test/Transforms/Inline/RISCV/riscv-overlay-caller.ll

+; RUN: opt -inline -S %s | FileCheck %s
+; RUN: opt -passes='cgscc(inline)' -S %s | FileCheck %s
+
+define void @f() "overlay" {
+; CHECK-LABEL: @f
+; CHECK: call
+entry:
+  tail call void @g()
+  unreachable
+}
+
+define void @g() {
+; CHECK-LABEL: @g
+entry:
+  unreachable
+}