Add RISC-V sifive-s51 cpu

[apivovarov]

Summary

Add RISC-V sifive-s51 cpu.

sifive-51 spec: https://www.sifive.com/cores/s51
gcc: https://github.com/riscv/riscv-gcc/blob/c3911e6425f35e0722129cb30cc5ccaf3390cd75/gcc/config/riscv/riscv-cores.def#L42

[apivovarov]

fix typo in MCPU-ABI-SIFIVE-S51

[craig.topper]

Please upload patches with full context. Using -U999999 as documented here https://llvm.org/docs/Phabricator.html#requesting-a-review-via-the-web-interface

[apivovarov]

updated the patch

[apivovarov]

Add sifive-s51 to test target-invalid-cpu-note.c error messages match string

[apivovarov]

@evandro @kito-cheng @kito.cheng @khchen @MaskRay Could you review this patch? Thank you

[jrtc27]

In D108886#2977730, @apivovarov wrote:

@evandro @kito-cheng @kito.cheng @khchen @MaskRay Could you review this patch? Thank you

You don't need to tag people as well as adding them as reviewers, it's just annoying. Also, it's only been four days; the developer policy is that for non-urgent patches you shouldn't ping more than once a week.

[MaskRay]

Looks reasonable. You can add a bullet point to clang/docs/ReleaseNotes.rst

[apivovarov]

In D108886#2977733, @jrtc27 wrote:

You don't need to tag people as well as adding them as reviewers, it's just annoying. Also, it's only been four days; the developer policy is that for non-urgent patches you shouldn't ping more than once a week.

Jessica, Contributing to LLVM says - To make sure the right people see your patch, please select suitable reviewers and add them to your patch when requesting a review. Suitable reviewers are the code owner (see CODE_OWNERS.txt) and other people doing work in the area your patch touches.

The people I added as reviewers have contributed to RISC-V target code in the past.

[evandro]

LGTM

[jrtc27]

In D108886#2977873, @apivovarov wrote:

In D108886#2977733, @jrtc27 wrote:

You don't need to tag people as well as adding them as reviewers, it's just annoying. Also, it's only been four days; the developer policy is that for non-urgent patches you shouldn't ping more than once a week.

Jessica, Contributing to LLVM says - To make sure the right people see your patch, please select suitable reviewers and add them to your patch when requesting a review. Suitable reviewers are the code owner (see CODE_OWNERS.txt) and other people doing work in the area your patch touches.

The people I added as reviewers have contributed to RISC-V target code in the past.

Yeah, but that means adding them as reviewers, you don't also need to @ them in general.

[apivovarov]

Fangrui, I've added a note to Release Notes

[evandro]

I don't think that such a minor change makes sense to be added to the release notes.

[apivovarov]

Evandro, similar notes have been made in the past for Release Notes 12.x and 11.x for Arm and RISC-V processors:
https://github.com/llvm/llvm-project/blob/release/12.x/clang/docs/ReleaseNotes.rst#modified-compiler-flags
https://github.com/llvm/llvm-project/blob/release/11.x/clang/docs/ReleaseNotes.rst#modified-compiler-flags

[evandro]

In D108886#2978038, @apivovarov wrote:

Evandro, similar notes have been made in the past for Release Notes 12.x and 11.x for Arm and RISC-V processors:
https://github.com/llvm/llvm-project/blob/release/12.x/clang/docs/ReleaseNotes.rst#modified-compiler-flags
https://github.com/llvm/llvm-project/blob/release/11.x/clang/docs/ReleaseNotes.rst#modified-compiler-flags

Exactly, but they were not similar changes, but more significant ones, including the addition pipeline models. But I don't feel strongly about it.

[apivovarov]

Add Cortex-A78C Support for Clang and LLVM is similar to this patch. As we can see cortex-a78c support was included to the ReleaseNotes 12.x. From the other side adding sifive-e76 and sifive-u74 support has not been mentioned in the Release Notes for version 12.0

[evandro]

In D108886#2978169, @apivovarov wrote:

Add Cortex-A78C Support for Clang and LLVM is similar to this patch. As we can see cortex-a78c support was included to the ReleaseNotes 12.x. From the other side adding sifive-e76 and sifive-u74 support has not been mentioned in the Release Notes for version 12.0

Fair enough.

clang/docs/ReleaseNotes.rst

 Deprecated Compiler Flags
 -------------------------
 
 - ...
 
 Modified Compiler Flags
 -----------------------
 
-- ...
+- Support has been added for the following processors (``-mcpu`` identifiers in parentheses):
+
+  - RISC-V SiFive S51 (``sifive-s51``).
 
 Removed Compiler Flags
 -------------------------
 
 - ...
 
 New Pragmas in Clang
 --------------------

clang/test/Driver/riscv-cpus.c

 // MTUNE-ROCKET-64: "-tune-cpu" "rocket-rv64"
 
 // RUN: %clang -target riscv32 -### -c %s 2>&1 -mtune=sifive-7-series | FileCheck -check-prefix=MTUNE-SIFIVE7-SERIES-32 %s
 // MTUNE-SIFIVE7-SERIES-32: "-tune-cpu" "sifive-7-rv32"
 
 // RUN: %clang -target riscv64 -### -c %s 2>&1 -mtune=sifive-7-series | FileCheck -check-prefix=MTUNE-SIFIVE7-SERIES-64 %s
 // MTUNE-SIFIVE7-SERIES-64: "-tune-cpu" "sifive-7-rv64"
 
+// mcpu with mabi option
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-s51 -mabi=lp64 | FileCheck -check-prefix=MCPU-ABI-SIFIVE-S51 %s
+// MCPU-ABI-SIFIVE-S51: "-nostdsysteminc" "-target-cpu" "sifive-s51"
+// MCPU-ABI-SIFIVE-S51: "-target-feature" "+m" "-target-feature" "+a"
+// MCPU-ABI-SIFIVE-S51: "-target-feature" "+c" "-target-feature" "+64bit"
+// MCPU-ABI-SIFIVE-S51: "-target-abi" "lp64"
+
 // mcpu with default march
 // RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-u54 | FileCheck -check-prefix=MCPU-SIFIVE-U54 %s
 // MCPU-SIFIVE-U54: "-nostdsysteminc" "-target-cpu" "sifive-u54"
 // MCPU-SIFIVE-U54: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d"
 // MCPU-SIFIVE-U54: "-target-feature" "+c" "-target-feature" "+64bit"
 // MCPU-SIFIVE-U54: "-target-abi" "lp64d"
 
 // mcpu with mabi option

clang/test/Misc/target-invalid-cpu-note.c

 // AVR-SAME: attiny102, attiny104
 
 // RUN: not %clang_cc1 -triple riscv32 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV32
 // RISCV32: error: unknown target CPU 'not-a-cpu'
 // RISCV32: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-7-rv32, sifive-e31, sifive-e76
 
 // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV64
 // RISCV64: error: unknown target CPU 'not-a-cpu'
-// RISCV64: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-7-rv64, sifive-u54, sifive-u74
+// RISCV64: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-7-rv64, sifive-s51, sifive-u54, sifive-u74
 
 // RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
 // TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
 // TUNE-RISCV32: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-7-rv32, sifive-e31, sifive-e76, generic, rocket, sifive-7-series
 
 // RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
 // TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV64: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-7-rv64, sifive-u54, sifive-u74, generic, rocket, sifive-7-series
+// TUNE-RISCV64: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-7-rv64, sifive-s51, sifive-u54, sifive-u74, generic, rocket, sifive-7-series

llvm/include/llvm/Support/RISCVTargetParser.def

 PROC(INVALID, {"invalid"}, FK_INVALID, {""})
 PROC(GENERIC_RV32, {"generic-rv32"}, FK_NONE, {""})
 PROC(GENERIC_RV64, {"generic-rv64"}, FK_64BIT, {""})
 PROC(ROCKET_RV32, {"rocket-rv32"}, FK_NONE, {""})
 PROC(ROCKET_RV64, {"rocket-rv64"}, FK_64BIT, {""})
 PROC(SIFIVE_732, {"sifive-7-rv32"}, FK_NONE, {""})
 PROC(SIFIVE_764, {"sifive-7-rv64"}, FK_64BIT, {""})
 PROC(SIFIVE_E31, {"sifive-e31"}, FK_NONE, {"rv32imac"})
+PROC(SIFIVE_S51, {"sifive-s51"}, FK_64BIT, {"rv64imac"})
 PROC(SIFIVE_U54, {"sifive-u54"}, FK_64BIT, {"rv64gc"})
 PROC(SIFIVE_E76, {"sifive-e76"}, FK_NONE, {"rv32imafc"})
 PROC(SIFIVE_U74, {"sifive-u74"}, FK_64BIT, {"rv64gc"})
 
 #undef PROC

llvm/lib/Target/RISCV/RISCV.td

 
 def : ProcessorModel<"sifive-7-rv32", SiFive7Model, []>;
 def : ProcessorModel<"sifive-7-rv64", SiFive7Model, [Feature64Bit]>;
 
 def : ProcessorModel<"sifive-e31", RocketModel, [FeatureStdExtM,
                                                  FeatureStdExtA,
                                                  FeatureStdExtC]>;
 
+def : ProcessorModel<"sifive-s51", RocketModel, [Feature64Bit,
+                                                 FeatureStdExtM,
+                                                 FeatureStdExtA,
+                                                 FeatureStdExtC]>;
+
 def : ProcessorModel<"sifive-u54", RocketModel, [Feature64Bit,
                                                  FeatureStdExtM,
                                                  FeatureStdExtA,
                                                  FeatureStdExtF,
                                                  FeatureStdExtD,
                                                  FeatureStdExtC]>;
 
 def : ProcessorModel<"sifive-e76", SiFive7Model, [FeatureStdExtM,