Add RISC-V sifive-s51 cpu.
sifive-51 spec: https://www.sifive.com/cores/s51
gcc: https://github.com/riscv/riscv-gcc/blob/c3911e6425f35e0722129cb30cc5ccaf3390cd75/gcc/config/riscv/riscv-cores.def#L42
Differential D108886
Add RISC-V sifive-s51 cpu apivovarov on Aug 28 2021, 11:07 PM. Authored by
Details
Add RISC-V sifive-s51 cpu. sifive-51 spec: https://www.sifive.com/cores/s51
Diff Detail
Event TimelineComment Actions Please upload patches with full context. Using -U999999 as documented here https://llvm.org/docs/Phabricator.html#requesting-a-review-via-the-web-interface Comment Actions @evandro @kito-cheng @kito.cheng @khchen @MaskRay Could you review this patch? Thank you Comment Actions You don't need to tag people as well as adding them as reviewers, it's just annoying. Also, it's only been four days; the developer policy is that for non-urgent patches you shouldn't ping more than once a week. Comment Actions Jessica, Contributing to LLVM says - To make sure the right people see your patch, please select suitable reviewers and add them to your patch when requesting a review. Suitable reviewers are the code owner (see CODE_OWNERS.txt) and other people doing work in the area your patch touches. The people I added as reviewers have contributed to RISC-V target code in the past. Comment Actions Yeah, but that means adding them as reviewers, you don't also need to @ them in general. Comment Actions Evandro, similar notes have been made in the past for Release Notes 12.x and 11.x for Arm and RISC-V processors: Comment Actions Exactly, but they were not similar changes, but more significant ones, including the addition pipeline models. But I don't feel strongly about it. Comment Actions Add Cortex-A78C Support for Clang and LLVM is similar to this patch. As we can see cortex-a78c support was included to the ReleaseNotes 12.x. From the other side adding sifive-e76 and sifive-u74 support has not been mentioned in the Release Notes for version 12.0 |