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[Clang][RISCV] Implement getConstraintRegister for RISC-V
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Authored by luismarques on Aug 24 2021, 5:15 AM.

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Summary

The getConstraintRegister method is used by semantic checking of inline assembly statements in order to diagnose conflicts between clobber list and input/output lists. By overriding getConstraintRegister we get those diagnostics and we match RISC-V GCC's behavior. The implementation is trivial due to the lack of single-register RISC-V-specific constraints.

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Event Timeline

luismarques created this revision.Aug 24 2021, 5:15 AM
luismarques requested review of this revision.Aug 24 2021, 5:15 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 24 2021, 5:15 AM

Nit: remove nop.

luismarques added inline comments.Aug 24 2021, 5:25 AM
clang/test/Sema/inline-asm-validate-riscv.c
27–28

I don't really understand the point of erroring-out in these two cases where the register is an input and is also clobbered. In fact, I've run into a case where that would be useful and accurately reflected the situation. But GCC's documentation explicitly prohibits that. I'm not sure if there's a fundamental reason for that, or if it's just an implementation quirk.

asb accepted this revision.Aug 26 2021, 9:39 AM

Looks good to me - I'm surprised only Arm, AArch64, and X86 implement this!

This revision is now accepted and ready to land.Aug 26 2021, 9:39 AM