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Differential D108487

[RISCV] Enable CONCAT_VECTORS for fixed FP vectors.
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Authored by craig.topper on Aug 20 2021, 2:25 PM.

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Reviewers
frasercrmck
Commits
rG0560a4adb3ef: [RISCV] Enable CONCAT_VECTORS for fixed FP vectors.

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Event Timeline

craig.topper created this revision.Aug 20 2021, 2:25 PM
Herald added subscribers: vkmr, evandro, luismarques and 24 others. · View Herald TranscriptAug 20 2021, 2:25 PM
craig.topper requested review of this revision.Aug 20 2021, 2:25 PM
Herald added a project: Restricted Project. · View Herald TranscriptAug 20 2021, 2:25 PM
Herald added a subscriber: MaskRay. · View Herald Transcript
Harbormaster completed remote builds in B120627: Diff 367897.Aug 20 2021, 3:04 PM
frasercrmck accepted this revision.Aug 30 2021, 2:19 AM

Oh good catch, thanks!

This revision is now accepted and ready to land.Aug 30 2021, 2:19 AM
Closed by commit rG0560a4adb3ef: [RISCV] Enable CONCAT_VECTORS for fixed FP vectors. (authored by craig.topper). · Explain WhyAug 30 2021, 9:01 AM
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rG0560a4adb3ef: [RISCV] Enable CONCAT_VECTORS for fixed FP vectors..

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
1 line
test/
CodeGen/
RISCV/
rvv/
65 lines
86 lines

Diff 369461

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 785 Lines • ▼ Show 20 Lines if (Subtarget.useRVVForFixedLengthVectors()) {
setTruncStoreAction(VT, OtherVT, Expand); setTruncStoreAction(VT, OtherVT, Expand);
} }
// We use EXTRACT_SUBVECTOR as a "cast" from scalable to fixed. // We use EXTRACT_SUBVECTOR as a "cast" from scalable to fixed.
setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
setOperationAction(ISD::BUILD_VECTOR, VT, Custom); setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
setOperationAction(ISD::LOAD, VT, Custom); setOperationAction(ISD::LOAD, VT, Custom);
setOperationAction(ISD::STORE, VT, Custom); setOperationAction(ISD::STORE, VT, Custom);
setOperationAction(ISD::MLOAD, VT, Custom); setOperationAction(ISD::MLOAD, VT, Custom);
setOperationAction(ISD::MSTORE, VT, Custom); setOperationAction(ISD::MSTORE, VT, Custom);
▲ Show 20 Lines • Show All 8,421 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll

Show First 20 Lines • Show All 151 Lines • ▼ Show 20 Lines
; LMULMAX8-NEXT: vle32.v v26, (a0) ; LMULMAX8-NEXT: vle32.v v26, (a0)
; LMULMAX8-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; LMULMAX8-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; LMULMAX8-NEXT: vfncvt.f.f.w v25, v26 ; LMULMAX8-NEXT: vfncvt.f.f.w v25, v26
; LMULMAX8-NEXT: vse16.v v25, (a1) ; LMULMAX8-NEXT: vse16.v v25, (a1)
; LMULMAX8-NEXT: ret ; LMULMAX8-NEXT: ret
; ;
; LMULMAX1-LABEL: fpround_v8f32_v8f16: ; LMULMAX1-LABEL: fpround_v8f32_v8f16:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi sp, sp, -32
; LMULMAX1-NEXT: .cfi_def_cfa_offset 32
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-NEXT: addi a2, a0, 16 ; LMULMAX1-NEXT: vle32.v v25, (a0)
; LMULMAX1-NEXT: vle32.v v25, (a2) ; LMULMAX1-NEXT: addi a0, a0, 16
; LMULMAX1-NEXT: vle32.v v26, (a0) ; LMULMAX1-NEXT: vle32.v v26, (a0)
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.f.f.w v27, v25 ; LMULMAX1-NEXT: vfncvt.f.f.w v27, v25
; LMULMAX1-NEXT: addi a0, sp, 24
; LMULMAX1-NEXT: vse16.v v27, (a0)
; LMULMAX1-NEXT: vfncvt.f.f.w v25, v26
; LMULMAX1-NEXT: addi a0, sp, 16
; LMULMAX1-NEXT: vse16.v v25, (a0)
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX1-NEXT: addi a0, sp, 16 ; LMULMAX1-NEXT: vmv.v.i v25, 0
; LMULMAX1-NEXT: vle16.v v25, (a0) ; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v25, v27, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.f.f.w v27, v26
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v25, v27, 4
; LMULMAX1-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; LMULMAX1-NEXT: vse16.v v25, (a1) ; LMULMAX1-NEXT: vse16.v v25, (a1)
; LMULMAX1-NEXT: addi sp, sp, 32
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%a = load <8 x float>, <8 x float>* %x %a = load <8 x float>, <8 x float>* %x
%d = fptrunc <8 x float> %a to <8 x half> %d = fptrunc <8 x float> %a to <8 x half>
store <8 x half> %d, <8 x half>* %y store <8 x half> %d, <8 x half>* %y
ret void ret void
} }
define void @fpround_v8f64_v8f16(<8 x double>* %x, <8 x half>* %y) { define void @fpround_v8f64_v8f16(<8 x double>* %x, <8 x half>* %y) {
; LMULMAX8-LABEL: fpround_v8f64_v8f16: ; LMULMAX8-LABEL: fpround_v8f64_v8f16:
; LMULMAX8: # %bb.0: ; LMULMAX8: # %bb.0:
; LMULMAX8-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; LMULMAX8-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; LMULMAX8-NEXT: vle64.v v28, (a0) ; LMULMAX8-NEXT: vle64.v v28, (a0)
; LMULMAX8-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; LMULMAX8-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; LMULMAX8-NEXT: vfncvt.rod.f.f.w v26, v28 ; LMULMAX8-NEXT: vfncvt.rod.f.f.w v26, v28
; LMULMAX8-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; LMULMAX8-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; LMULMAX8-NEXT: vfncvt.f.f.w v25, v26 ; LMULMAX8-NEXT: vfncvt.f.f.w v25, v26
; LMULMAX8-NEXT: vse16.v v25, (a1) ; LMULMAX8-NEXT: vse16.v v25, (a1)
; LMULMAX8-NEXT: ret ; LMULMAX8-NEXT: ret
; ;
; LMULMAX1-LABEL: fpround_v8f64_v8f16: ; LMULMAX1-LABEL: fpround_v8f64_v8f16:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi sp, sp, -32 ; LMULMAX1-NEXT: addi a2, a0, 48
; LMULMAX1-NEXT: .cfi_def_cfa_offset 32
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; LMULMAX1-NEXT: vle64.v v25, (a0) ; LMULMAX1-NEXT: vle64.v v25, (a2)
; LMULMAX1-NEXT: addi a2, a0, 16 ; LMULMAX1-NEXT: addi a2, a0, 32
; LMULMAX1-NEXT: vle64.v v26, (a2) ; LMULMAX1-NEXT: vle64.v v26, (a2)
; LMULMAX1-NEXT: addi a2, a0, 48 ; LMULMAX1-NEXT: vle64.v v27, (a0)
; LMULMAX1-NEXT: vle64.v v27, (a2) ; LMULMAX1-NEXT: addi a0, a0, 16
; LMULMAX1-NEXT: addi a0, a0, 32
; LMULMAX1-NEXT: vle64.v v28, (a0) ; LMULMAX1-NEXT: vle64.v v28, (a0)
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.rod.f.f.w v29, v27 ; LMULMAX1-NEXT: vfncvt.rod.f.f.w v29, v27
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vfncvt.f.f.w v27, v29 ; LMULMAX1-NEXT: vfncvt.f.f.w v27, v29
; LMULMAX1-NEXT: addi a0, sp, 28 ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX1-NEXT: vse16.v v27, (a0) ; LMULMAX1-NEXT: vmv.v.i v29, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e16, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v29, v27, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.rod.f.f.w v27, v28 ; LMULMAX1-NEXT: vfncvt.rod.f.f.w v27, v28
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vfncvt.f.f.w v28, v27 ; LMULMAX1-NEXT: vfncvt.f.f.w v28, v27
; LMULMAX1-NEXT: addi a0, sp, 24 ; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, tu, mu
; LMULMAX1-NEXT: vse16.v v28, (a0) ; LMULMAX1-NEXT: vslideup.vi v29, v28, 2
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.rod.f.f.w v27, v26 ; LMULMAX1-NEXT: vfncvt.rod.f.f.w v27, v26
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vfncvt.f.f.w v26, v27 ; LMULMAX1-NEXT: vfncvt.f.f.w v26, v27
; LMULMAX1-NEXT: addi a0, sp, 20 ; LMULMAX1-NEXT: vsetivli zero, 6, e16, m1, tu, mu
; LMULMAX1-NEXT: vse16.v v26, (a0) ; LMULMAX1-NEXT: vslideup.vi v29, v26, 4
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.rod.f.f.w v26, v25 ; LMULMAX1-NEXT: vfncvt.rod.f.f.w v26, v25
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vfncvt.f.f.w v25, v26 ; LMULMAX1-NEXT: vfncvt.f.f.w v25, v26
; LMULMAX1-NEXT: addi a0, sp, 16 ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu
; LMULMAX1-NEXT: vse16.v v25, (a0) ; LMULMAX1-NEXT: vslideup.vi v29, v25, 6
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; LMULMAX1-NEXT: addi a0, sp, 16 ; LMULMAX1-NEXT: vse16.v v29, (a1)
; LMULMAX1-NEXT: vle16.v v25, (a0)
; LMULMAX1-NEXT: vse16.v v25, (a1)
; LMULMAX1-NEXT: addi sp, sp, 32
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%a = load <8 x double>, <8 x double>* %x %a = load <8 x double>, <8 x double>* %x
%d = fptrunc <8 x double> %a to <8 x half> %d = fptrunc <8 x double> %a to <8 x half>
store <8 x half> %d, <8 x half>* %y store <8 x half> %d, <8 x half>* %y
ret void ret void
} }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll

Show First 20 Lines • Show All 460 Lines • ▼ Show 20 Lines
; LMULMAX8-NEXT: vfncvt.f.x.w v26, v28 ; LMULMAX8-NEXT: vfncvt.f.x.w v26, v28
; LMULMAX8-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; LMULMAX8-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; LMULMAX8-NEXT: vfncvt.f.f.w v25, v26 ; LMULMAX8-NEXT: vfncvt.f.f.w v25, v26
; LMULMAX8-NEXT: vse16.v v25, (a1) ; LMULMAX8-NEXT: vse16.v v25, (a1)
; LMULMAX8-NEXT: ret ; LMULMAX8-NEXT: ret
; ;
; LMULMAX1-LABEL: si2fp_v8i64_v8f16: ; LMULMAX1-LABEL: si2fp_v8i64_v8f16:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi sp, sp, -32 ; LMULMAX1-NEXT: addi a2, a0, 48
; LMULMAX1-NEXT: .cfi_def_cfa_offset 32
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; LMULMAX1-NEXT: vle64.v v25, (a0) ; LMULMAX1-NEXT: vle64.v v25, (a2)
; LMULMAX1-NEXT: addi a2, a0, 16 ; LMULMAX1-NEXT: addi a2, a0, 32
; LMULMAX1-NEXT: vle64.v v26, (a2) ; LMULMAX1-NEXT: vle64.v v26, (a2)
; LMULMAX1-NEXT: addi a2, a0, 48 ; LMULMAX1-NEXT: vle64.v v27, (a0)
; LMULMAX1-NEXT: vle64.v v27, (a2) ; LMULMAX1-NEXT: addi a0, a0, 16
; LMULMAX1-NEXT: addi a0, a0, 32
; LMULMAX1-NEXT: vle64.v v28, (a0) ; LMULMAX1-NEXT: vle64.v v28, (a0)
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.f.x.w v29, v27 ; LMULMAX1-NEXT: vfncvt.f.x.w v29, v27
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vfncvt.f.f.w v27, v29 ; LMULMAX1-NEXT: vfncvt.f.f.w v27, v29
; LMULMAX1-NEXT: addi a0, sp, 28 ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX1-NEXT: vse16.v v27, (a0) ; LMULMAX1-NEXT: vmv.v.i v29, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e16, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v29, v27, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.f.x.w v27, v28 ; LMULMAX1-NEXT: vfncvt.f.x.w v27, v28
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vfncvt.f.f.w v28, v27 ; LMULMAX1-NEXT: vfncvt.f.f.w v28, v27
; LMULMAX1-NEXT: addi a0, sp, 24 ; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, tu, mu
; LMULMAX1-NEXT: vse16.v v28, (a0) ; LMULMAX1-NEXT: vslideup.vi v29, v28, 2
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.f.x.w v27, v26 ; LMULMAX1-NEXT: vfncvt.f.x.w v27, v26
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vfncvt.f.f.w v26, v27 ; LMULMAX1-NEXT: vfncvt.f.f.w v26, v27
; LMULMAX1-NEXT: addi a0, sp, 20 ; LMULMAX1-NEXT: vsetivli zero, 6, e16, m1, tu, mu
; LMULMAX1-NEXT: vse16.v v26, (a0) ; LMULMAX1-NEXT: vslideup.vi v29, v26, 4
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.f.x.w v26, v25 ; LMULMAX1-NEXT: vfncvt.f.x.w v26, v25
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vfncvt.f.f.w v25, v26 ; LMULMAX1-NEXT: vfncvt.f.f.w v25, v26
; LMULMAX1-NEXT: addi a0, sp, 16 ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu
; LMULMAX1-NEXT: vse16.v v25, (a0) ; LMULMAX1-NEXT: vslideup.vi v29, v25, 6
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; LMULMAX1-NEXT: addi a0, sp, 16 ; LMULMAX1-NEXT: vse16.v v29, (a1)
; LMULMAX1-NEXT: vle16.v v25, (a0)
; LMULMAX1-NEXT: vse16.v v25, (a1)
; LMULMAX1-NEXT: addi sp, sp, 32
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%a = load <8 x i64>, <8 x i64>* %x %a = load <8 x i64>, <8 x i64>* %x
%d = sitofp <8 x i64> %a to <8 x half> %d = sitofp <8 x i64> %a to <8 x half>
store <8 x half> %d, <8 x half>* %y store <8 x half> %d, <8 x half>* %y
ret void ret void
} }
define void @ui2fp_v8i64_v8f16(<8 x i64>* %x, <8 x half>* %y) { define void @ui2fp_v8i64_v8f16(<8 x i64>* %x, <8 x half>* %y) {
; LMULMAX8-LABEL: ui2fp_v8i64_v8f16: ; LMULMAX8-LABEL: ui2fp_v8i64_v8f16:
; LMULMAX8: # %bb.0: ; LMULMAX8: # %bb.0:
; LMULMAX8-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; LMULMAX8-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; LMULMAX8-NEXT: vle64.v v28, (a0) ; LMULMAX8-NEXT: vle64.v v28, (a0)
; LMULMAX8-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; LMULMAX8-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; LMULMAX8-NEXT: vfncvt.f.xu.w v26, v28 ; LMULMAX8-NEXT: vfncvt.f.xu.w v26, v28
; LMULMAX8-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; LMULMAX8-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; LMULMAX8-NEXT: vfncvt.f.f.w v25, v26 ; LMULMAX8-NEXT: vfncvt.f.f.w v25, v26
; LMULMAX8-NEXT: vse16.v v25, (a1) ; LMULMAX8-NEXT: vse16.v v25, (a1)
; LMULMAX8-NEXT: ret ; LMULMAX8-NEXT: ret
; ;
; LMULMAX1-LABEL: ui2fp_v8i64_v8f16: ; LMULMAX1-LABEL: ui2fp_v8i64_v8f16:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi sp, sp, -32 ; LMULMAX1-NEXT: addi a2, a0, 48
; LMULMAX1-NEXT: .cfi_def_cfa_offset 32
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; LMULMAX1-NEXT: vle64.v v25, (a0) ; LMULMAX1-NEXT: vle64.v v25, (a2)
; LMULMAX1-NEXT: addi a2, a0, 16 ; LMULMAX1-NEXT: addi a2, a0, 32
; LMULMAX1-NEXT: vle64.v v26, (a2) ; LMULMAX1-NEXT: vle64.v v26, (a2)
; LMULMAX1-NEXT: addi a2, a0, 48 ; LMULMAX1-NEXT: vle64.v v27, (a0)
; LMULMAX1-NEXT: vle64.v v27, (a2) ; LMULMAX1-NEXT: addi a0, a0, 16
; LMULMAX1-NEXT: addi a0, a0, 32
; LMULMAX1-NEXT: vle64.v v28, (a0) ; LMULMAX1-NEXT: vle64.v v28, (a0)
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.f.xu.w v29, v27 ; LMULMAX1-NEXT: vfncvt.f.xu.w v29, v27
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vfncvt.f.f.w v27, v29 ; LMULMAX1-NEXT: vfncvt.f.f.w v27, v29
; LMULMAX1-NEXT: addi a0, sp, 28 ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX1-NEXT: vse16.v v27, (a0) ; LMULMAX1-NEXT: vmv.v.i v29, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e16, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v29, v27, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.f.xu.w v27, v28 ; LMULMAX1-NEXT: vfncvt.f.xu.w v27, v28
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vfncvt.f.f.w v28, v27 ; LMULMAX1-NEXT: vfncvt.f.f.w v28, v27
; LMULMAX1-NEXT: addi a0, sp, 24 ; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, tu, mu
; LMULMAX1-NEXT: vse16.v v28, (a0) ; LMULMAX1-NEXT: vslideup.vi v29, v28, 2
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.f.xu.w v27, v26 ; LMULMAX1-NEXT: vfncvt.f.xu.w v27, v26
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vfncvt.f.f.w v26, v27 ; LMULMAX1-NEXT: vfncvt.f.f.w v26, v27
; LMULMAX1-NEXT: addi a0, sp, 20 ; LMULMAX1-NEXT: vsetivli zero, 6, e16, m1, tu, mu
; LMULMAX1-NEXT: vse16.v v26, (a0) ; LMULMAX1-NEXT: vslideup.vi v29, v26, 4
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.f.xu.w v26, v25 ; LMULMAX1-NEXT: vfncvt.f.xu.w v26, v25
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vfncvt.f.f.w v25, v26 ; LMULMAX1-NEXT: vfncvt.f.f.w v25, v26
; LMULMAX1-NEXT: addi a0, sp, 16 ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu
; LMULMAX1-NEXT: vse16.v v25, (a0) ; LMULMAX1-NEXT: vslideup.vi v29, v25, 6
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; LMULMAX1-NEXT: addi a0, sp, 16 ; LMULMAX1-NEXT: vse16.v v29, (a1)
; LMULMAX1-NEXT: vle16.v v25, (a0)
; LMULMAX1-NEXT: vse16.v v25, (a1)
; LMULMAX1-NEXT: addi sp, sp, 32
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%a = load <8 x i64>, <8 x i64>* %x %a = load <8 x i64>, <8 x i64>* %x
%d = uitofp <8 x i64> %a to <8 x half> %d = uitofp <8 x i64> %a to <8 x half>
store <8 x half> %d, <8 x half>* %y store <8 x half> %d, <8 x half>* %y
ret void ret void
} }
define <8 x half> @si2fp_v8i1_v8f16(<8 x i1> %x) { define <8 x half> @si2fp_v8i1_v8f16(<8 x i1> %x) {
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