[DAGCombiner] Teach combineShiftToMULH to handle constant and const splat vector.

[jacquesguan]

Summary

Fold (srl (mul (zext i32:$a to i64), i64:c), 32) -> (mulhu $a, $b) if c can truncate to i32 without loss.

[jacquesguan]

Update mulhu case for (mulhu x, (1 << c)) -> x >> (bitwidth - c).

[frasercrmck]

I'm adding some non-RVV reviewers in this field; that may help move this patch along.

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

8561

I think the way HasConstant is interacting with checks below this could do with explanation (in the code). It's not clear to me why and how it interacts with logic later in this function.

8609–8610

I might be narrowly-focussed here, but I'm not sure why we need a ternary here. Can't we capture RightOp.getOperand(0) in a variable and ensure it's correct in the the if (HasConstant) block? Would that simplify any of the other logic?

[RKSimon]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

8572

Why not reuse LeftConstant/RightConstant?

[craig.topper]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

8555

Do we need to worry about Constant LHS? Won't the mul be canonicalized and then the shift will be revisited?

8571

Isn't ActiveBits the wrong thing to check for SIGN_EXTEND?

llvm/test/CodeGen/RISCV/rvv/vmulh-sdnode-rv32.ll

69 ↗

(On Diff #367134)

Was this test case supposed to match to mulh?

[jacquesguan]

Refactor code and support negative signed constant.

[jacquesguan]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

8555

Fixed, thanks a lot.

8571

Done, add check for negative signed constant, and postive constant shares same logic as unsigned one.

8572

Done, thanks a lot.

llvm/test/CodeGen/RISCV/rvv/vmulh-sdnode-rv32.ll

69 ↗

(On Diff #367134)

Done, thanks a lot.

[jacquesguan]

Refactor code.

[jacquesguan]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

8609–8610

Done, thank you.

[RKSimon]

Can the tests be pre-commited to trunk so we can see the effect of the patch on codegen?

[craig.topper]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

8565

Fold this into the if on line 8530 to limit the scope of Constant

8570

Why can't we use getMinSignedBits() for signed and getActiveBits() for unsigned.

[jacquesguan]

Refactor code.

[jacquesguan]

In D108129#3025471, @RKSimon wrote:

Can the tests be pre-commited to trunk so we can see the effect of the patch on codegen?

Done, I pre-commited these tests in D110675.

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

8565

Done, thanks a lot.

8570

Done, thanks a lot.

[RKSimon]

What about rv64?

[craig.topper]

llvm/test/CodeGen/RISCV/rvv/vmulh-sdnode-rv32.ll

1 ↗

(On Diff #375523)

I have renamed this file to remove "-rv32" and added an rv64 command line. Do the same to the new file please.

[jacquesguan]

Rebase and add RV64 tests.

[jacquesguan]

llvm/test/CodeGen/RISCV/rvv/vmulh-sdnode-rv32.ll

1 ↗

(On Diff #375523)

Done, thanks a lot.

[jacquesguan]

Format code.

[craig.topper]

llvm/test/CodeGen/RISCV/rvv/vmulhu-sdnode.ll

3

One of these RUN lines should be -mtriple=riscv64

[craig.topper]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

8559

Can you re-write this to

if (!IsSignExt && !ZeroExt)

[jacquesguan]

Fix test.

[jacquesguan]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

8559

Done

llvm/test/CodeGen/RISCV/rvv/vmulhu-sdnode.ll

3

Done.

[frasercrmck]

LGTM but either you need to land D110675 and rebase, or add D110675 as a parent revision. That way it's easier to see how this patch improves things.

[RKSimon]

Please can you rebase on top of D110675 - the whole point of the precommit is to show the codegen diff

[jacquesguan]

Rebase main.

[jacquesguan]

In D108129#3099875, @frasercrmck wrote:

LGTM but either you need to land D110675 and rebase, or add D110675 as a parent revision. That way it's easier to see how this patch improves things.

Done.

[jacquesguan]

In D108129#3099928, @RKSimon wrote:

Please can you rebase on top of D110675 - the whole point of the precommit is to show the codegen diff

Done.

[RKSimon]

LGTM - cheers

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

static SDValue combineShiftToMULH(SDNode *N, SelectionDAG &DAG,
   // The operation feeding into the shift must be a multiply.
   SDValue ShiftOperand = N->getOperand(0);
   if (ShiftOperand.getOpcode() != ISD::MUL)
     return SDValue();
 
   // Both operands must be equivalent extend nodes.
   SDValue LeftOp = ShiftOperand.getOperand(0);
   SDValue RightOp = ShiftOperand.getOperand(1);
+
   bool IsSignExt = LeftOp.getOpcode() == ISD::SIGN_EXTEND;
   bool IsZeroExt = LeftOp.getOpcode() == ISD::ZERO_EXTEND;
 
-  if ((!(IsSignExt || IsZeroExt)) || LeftOp.getOpcode() != RightOp.getOpcode())
+  if (!IsSignExt && !IsZeroExt)
     return SDValue();
 
-  EVT WideVT = LeftOp.getValueType();
-  // Proceed with the transformation if the wide types match.
-  assert((WideVT == RightOp.getValueType()) &&
-         "Cannot have a multiply node with two different operand types.");
-
   EVT NarrowVT = LeftOp.getOperand(0).getValueType();
+  unsigned NarrowVTSize = NarrowVT.getScalarSizeInBits();
+
+  SDValue MulhRightOp;
+  if (ConstantSDNode *Constant = isConstOrConstSplat(RightOp)) {
+    unsigned ActiveBits = IsSignExt
+                              ? Constant->getAPIntValue().getMinSignedBits()
+                              : Constant->getAPIntValue().getActiveBits();
+    if (ActiveBits > NarrowVTSize)
+      return SDValue();
+    MulhRightOp = DAG.getConstant(
+        Constant->getAPIntValue().trunc(NarrowVT.getScalarSizeInBits()), DL,
+        NarrowVT);
+  } else {
+    if (LeftOp.getOpcode() != RightOp.getOpcode())
+      return SDValue();
     // Check that the two extend nodes are the same type.
     if (NarrowVT != RightOp.getOperand(0).getValueType())
       return SDValue();
+    MulhRightOp = RightOp.getOperand(0);
+  }
+
+  EVT WideVT = LeftOp.getValueType();
+  // Proceed with the transformation if the wide types match.
+  assert((WideVT == RightOp.getValueType()) &&
+         "Cannot have a multiply node with two different operand types.");
 
   // Proceed with the transformation if the wide type is twice as large
   // as the narrow type.
-  unsigned NarrowVTSize = NarrowVT.getScalarSizeInBits();
   if (WideVT.getScalarSizeInBits() != 2 * NarrowVTSize)
     return SDValue();
 
   // Check the shift amount with the narrow type size.
   // Proceed with the transformation if the shift amount is the width
   // of the narrow type.
   unsigned ShiftAmt = ShiftAmtSrc->getZExtValue();
   if (ShiftAmt != NarrowVTSize)
     return SDValue();
 
   // If the operation feeding into the MUL is a sign extend (sext),
   // we use mulhs. Othewise, zero extends (zext) use mulhu.
   unsigned MulhOpcode = IsSignExt ? ISD::MULHS : ISD::MULHU;
 
   // Combine to mulh if mulh is legal/custom for the narrow type on the target.
   if (!TLI.isOperationLegalOrCustom(MulhOpcode, NarrowVT))
     return SDValue();
 
-  SDValue Result = DAG.getNode(MulhOpcode, DL, NarrowVT, LeftOp.getOperand(0),
-                               RightOp.getOperand(0));
+  SDValue Result =
+      DAG.getNode(MulhOpcode, DL, NarrowVT, LeftOp.getOperand(0), MulhRightOp);
   return (N->getOpcode() == ISD::SRA ? DAG.getSExtOrTrunc(Result, DL, WideVT)
                                      : DAG.getZExtOrTrunc(Result, DL, WideVT));
 }
 
 SDValue DAGCombiner::visitSRA(SDNode *N) {
   SDValue N0 = N->getOperand(0);
   SDValue N1 = N->getOperand(1);
   if (SDValue V = DAG.simplifyShift(N0, N1))

llvm/test/CodeGen/RISCV/rvv/vmulh-sdnode.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
 
 ; Test that the prepareSREMEqFold optimization doesn't crash on scalable
 ; vector types.
 define <vscale x 4 x i1> @srem_eq_fold_nxv4i8(<vscale x 4 x i8> %va) {
 ; CHECK-LABEL: srem_eq_fold_nxv4i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 42
 ; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, mu
; CHECK-NEXT:    ret
   %head2 = insertelement <vscale x 1 x i64> undef, i64 32, i32 0
   %splat2 = shufflevector <vscale x 1 x i64> %head2, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
   %ve = lshr <vscale x 1 x i64> %vd, %splat2
   %vf = trunc <vscale x 1 x i64> %ve to <vscale x 1 x i32>
   ret <vscale x 1 x i32> %vf
 }
 
 define <vscale x 1 x i32> @vmulh_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
-; CHECK-LABEL: vmulh_vi_nxv1i32_0:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT:    vsext.vf2 v9, v8
-; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v8, v9, a0
-; CHECK-NEXT:    addi a0, zero, 32
-; CHECK-NEXT:    vsrl.vx v8, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
-; CHECK-NEXT:    vnsrl.wi v8, v8, 0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vmulh_vi_nxv1i32_0:
+; RV32:       # %bb.0:
+; RV32-NEXT:    addi a0, zero, -7
+; RV32-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
+; RV32-NEXT:    vmulh.vx v8, v8, a0
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vmulh_vi_nxv1i32_0:
+; RV64:       # %bb.0:
+; RV64-NEXT:    addi a0, zero, 1
+; RV64-NEXT:    slli a0, a0, 32
+; RV64-NEXT:    addi a0, a0, -7
+; RV64-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
+; RV64-NEXT:    vmulh.vx v8, v8, a0
+; RV64-NEXT:    ret
   %head1 = insertelement <vscale x 1 x i32> undef, i32 -7, i32 0
   %splat1 = shufflevector <vscale x 1 x i32> %head1, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
   %vb = sext <vscale x 1 x i32> %splat1 to <vscale x 1 x i64>
   %vc = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>
   %vd = mul <vscale x 1 x i64> %vb, %vc
   %head2 = insertelement <vscale x 1 x i64> undef, i64 32, i32 0
   %splat2 = shufflevector <vscale x 1 x i64> %head2, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
   %ve = lshr <vscale x 1 x i64> %vd, %splat2
   %vf = trunc <vscale x 1 x i64> %ve to <vscale x 1 x i32>
   ret <vscale x 1 x i32> %vf
 }
 
 define <vscale x 1 x i32> @vmulh_vi_nxv1i32_1(<vscale x 1 x i32> %va) {
 ; CHECK-LABEL: vmulh_vi_nxv1i32_1:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT:    vsext.vf2 v9, v8
-; CHECK-NEXT:    vsll.vi v8, v9, 4
-; CHECK-NEXT:    addi a0, zero, 32
-; CHECK-NEXT:    vsrl.vx v8, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
-; CHECK-NEXT:    vnsrl.wi v8, v8, 0
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
+; CHECK-NEXT:    vmulh.vx v8, v8, a0
 ; CHECK-NEXT:    ret
   %head1 = insertelement <vscale x 1 x i32> undef, i32 16, i32 0
   %splat1 = shufflevector <vscale x 1 x i32> %head1, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
   %vb = sext <vscale x 1 x i32> %splat1 to <vscale x 1 x i64>
   %vc = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>
   %vd = mul <vscale x 1 x i64> %vb, %vc
   %head2 = insertelement <vscale x 1 x i64> undef, i64 32, i32 0
   %splat2 = shufflevector <vscale x 1 x i64> %head2, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
; CHECK-NEXT:    ret
   %head2 = insertelement <vscale x 2 x i64> undef, i64 32, i32 0
   %splat2 = shufflevector <vscale x 2 x i64> %head2, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %ve = lshr <vscale x 2 x i64> %vd, %splat2
   %vf = trunc <vscale x 2 x i64> %ve to <vscale x 2 x i32>
   ret <vscale x 2 x i32> %vf
 }
 
 define <vscale x 2 x i32> @vmulh_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
-; CHECK-LABEL: vmulh_vi_nxv2i32_0:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
-; CHECK-NEXT:    vsext.vf2 v10, v8
-; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v8, v10, a0
-; CHECK-NEXT:    addi a0, zero, 32
-; CHECK-NEXT:    vsrl.vx v10, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
-; CHECK-NEXT:    vnsrl.wi v8, v10, 0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vmulh_vi_nxv2i32_0:
+; RV32:       # %bb.0:
+; RV32-NEXT:    addi a0, zero, -7
+; RV32-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
+; RV32-NEXT:    vmulh.vx v8, v8, a0
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vmulh_vi_nxv2i32_0:
+; RV64:       # %bb.0:
+; RV64-NEXT:    addi a0, zero, 1
+; RV64-NEXT:    slli a0, a0, 32
+; RV64-NEXT:    addi a0, a0, -7
+; RV64-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
+; RV64-NEXT:    vmulh.vx v8, v8, a0
+; RV64-NEXT:    ret
   %head1 = insertelement <vscale x 2 x i32> undef, i32 -7, i32 0
   %splat1 = shufflevector <vscale x 2 x i32> %head1, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
   %vb = sext <vscale x 2 x i32> %splat1 to <vscale x 2 x i64>
   %vc = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>
   %vd = mul <vscale x 2 x i64> %vb, %vc
   %head2 = insertelement <vscale x 2 x i64> undef, i64 32, i32 0
   %splat2 = shufflevector <vscale x 2 x i64> %head2, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %ve = lshr <vscale x 2 x i64> %vd, %splat2
   %vf = trunc <vscale x 2 x i64> %ve to <vscale x 2 x i32>
   ret <vscale x 2 x i32> %vf
 }
 
 define <vscale x 2 x i32> @vmulh_vi_nxv2i32_1(<vscale x 2 x i32> %va) {
 ; CHECK-LABEL: vmulh_vi_nxv2i32_1:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
-; CHECK-NEXT:    vsext.vf2 v10, v8
-; CHECK-NEXT:    vsll.vi v8, v10, 4
-; CHECK-NEXT:    addi a0, zero, 32
-; CHECK-NEXT:    vsrl.vx v10, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
-; CHECK-NEXT:    vnsrl.wi v8, v10, 0
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
+; CHECK-NEXT:    vmulh.vx v8, v8, a0
 ; CHECK-NEXT:    ret
   %head1 = insertelement <vscale x 2 x i32> undef, i32 16, i32 0
   %splat1 = shufflevector <vscale x 2 x i32> %head1, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
   %vb = sext <vscale x 2 x i32> %splat1 to <vscale x 2 x i64>
   %vc = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>
   %vd = mul <vscale x 2 x i64> %vb, %vc
   %head2 = insertelement <vscale x 2 x i64> undef, i64 32, i32 0
   %splat2 = shufflevector <vscale x 2 x i64> %head2, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
; CHECK-NEXT:    ret
   %head2 = insertelement <vscale x 4 x i64> undef, i64 32, i32 0
   %splat2 = shufflevector <vscale x 4 x i64> %head2, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
   %ve = lshr <vscale x 4 x i64> %vd, %splat2
   %vf = trunc <vscale x 4 x i64> %ve to <vscale x 4 x i32>
   ret <vscale x 4 x i32> %vf
 }
 
 define <vscale x 4 x i32> @vmulh_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
-; CHECK-LABEL: vmulh_vi_nxv4i32_0:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
-; CHECK-NEXT:    vsext.vf2 v12, v8
-; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v8, v12, a0
-; CHECK-NEXT:    addi a0, zero, 32
-; CHECK-NEXT:    vsrl.vx v12, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
-; CHECK-NEXT:    vnsrl.wi v8, v12, 0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vmulh_vi_nxv4i32_0:
+; RV32:       # %bb.0:
+; RV32-NEXT:    addi a0, zero, -7
+; RV32-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
+; RV32-NEXT:    vmulh.vx v8, v8, a0
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vmulh_vi_nxv4i32_0:
+; RV64:       # %bb.0:
+; RV64-NEXT:    addi a0, zero, 1
+; RV64-NEXT:    slli a0, a0, 32
+; RV64-NEXT:    addi a0, a0, -7
+; RV64-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
+; RV64-NEXT:    vmulh.vx v8, v8, a0
+; RV64-NEXT:    ret
   %head1 = insertelement <vscale x 4 x i32> undef, i32 -7, i32 0
   %splat1 = shufflevector <vscale x 4 x i32> %head1, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
   %vb = sext <vscale x 4 x i32> %splat1 to <vscale x 4 x i64>
   %vc = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>
   %vd = mul <vscale x 4 x i64> %vb, %vc
   %head2 = insertelement <vscale x 4 x i64> undef, i64 32, i32 0
   %splat2 = shufflevector <vscale x 4 x i64> %head2, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
   %ve = lshr <vscale x 4 x i64> %vd, %splat2
   %vf = trunc <vscale x 4 x i64> %ve to <vscale x 4 x i32>
   ret <vscale x 4 x i32> %vf
 }
 
 define <vscale x 4 x i32> @vmulh_vi_nxv4i32_1(<vscale x 4 x i32> %va) {
 ; CHECK-LABEL: vmulh_vi_nxv4i32_1:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
-; CHECK-NEXT:    vsext.vf2 v12, v8
-; CHECK-NEXT:    vsll.vi v8, v12, 4
-; CHECK-NEXT:    addi a0, zero, 32
-; CHECK-NEXT:    vsrl.vx v12, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
-; CHECK-NEXT:    vnsrl.wi v8, v12, 0
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
+; CHECK-NEXT:    vmulh.vx v8, v8, a0
 ; CHECK-NEXT:    ret
   %head1 = insertelement <vscale x 4 x i32> undef, i32 16, i32 0
   %splat1 = shufflevector <vscale x 4 x i32> %head1, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
   %vb = sext <vscale x 4 x i32> %splat1 to <vscale x 4 x i64>
   %vc = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>
   %vd = mul <vscale x 4 x i64> %vb, %vc
   %head2 = insertelement <vscale x 4 x i64> undef, i64 32, i32 0
   %splat2 = shufflevector <vscale x 4 x i64> %head2, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
; CHECK-NEXT:    ret
   %head2 = insertelement <vscale x 8 x i64> undef, i64 32, i32 0
   %splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
   %ve = lshr <vscale x 8 x i64> %vd, %splat2
   %vf = trunc <vscale x 8 x i64> %ve to <vscale x 8 x i32>
   ret <vscale x 8 x i32> %vf
 }
 
 define <vscale x 8 x i32> @vmulh_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
-; CHECK-LABEL: vmulh_vi_nxv8i32_0:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT:    vsext.vf2 v16, v8
-; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v8, v16, a0
-; CHECK-NEXT:    addi a0, zero, 32
-; CHECK-NEXT:    vsrl.vx v16, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
-; CHECK-NEXT:    vnsrl.wi v8, v16, 0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vmulh_vi_nxv8i32_0:
+; RV32:       # %bb.0:
+; RV32-NEXT:    addi a0, zero, -7
+; RV32-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; RV32-NEXT:    vmulh.vx v8, v8, a0
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vmulh_vi_nxv8i32_0:
+; RV64:       # %bb.0:
+; RV64-NEXT:    addi a0, zero, 1
+; RV64-NEXT:    slli a0, a0, 32
+; RV64-NEXT:    addi a0, a0, -7
+; RV64-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; RV64-NEXT:    vmulh.vx v8, v8, a0
+; RV64-NEXT:    ret
   %head1 = insertelement <vscale x 8 x i32> undef, i32 -7, i32 0
   %splat1 = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
   %vb = sext <vscale x 8 x i32> %splat1 to <vscale x 8 x i64>
   %vc = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
   %vd = mul <vscale x 8 x i64> %vb, %vc
   %head2 = insertelement <vscale x 8 x i64> undef, i64 32, i32 0
   %splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
   %ve = lshr <vscale x 8 x i64> %vd, %splat2
   %vf = trunc <vscale x 8 x i64> %ve to <vscale x 8 x i32>
   ret <vscale x 8 x i32> %vf
 }
 
 define <vscale x 8 x i32> @vmulh_vi_nxv8i32_1(<vscale x 8 x i32> %va) {
 ; CHECK-LABEL: vmulh_vi_nxv8i32_1:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT:    vsext.vf2 v16, v8
-; CHECK-NEXT:    vsll.vi v8, v16, 4
-; CHECK-NEXT:    addi a0, zero, 32
-; CHECK-NEXT:    vsrl.vx v16, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
-; CHECK-NEXT:    vnsrl.wi v8, v16, 0
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vmulh.vx v8, v8, a0
 ; CHECK-NEXT:    ret
   %head1 = insertelement <vscale x 8 x i32> undef, i32 16, i32 0
   %splat1 = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
   %vb = sext <vscale x 8 x i32> %splat1 to <vscale x 8 x i64>
   %vc = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
   %vd = mul <vscale x 8 x i64> %vb, %vc
   %head2 = insertelement <vscale x 8 x i64> undef, i64 32, i32 0
   %splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
   %ve = lshr <vscale x 8 x i64> %vd, %splat2
   %vf = trunc <vscale x 8 x i64> %ve to <vscale x 8 x i32>
   ret <vscale x 8 x i32> %vf
 }

llvm/test/CodeGen/RISCV/rvv/vmulhu-sdnode.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
 
 define <vscale x 1 x i32> @vmulhu_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
 ; CHECK-LABEL: vmulhu_vv_nxv1i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
 ; CHECK-NEXT:    vmulhu.vv v8, v9, v8
 ; CHECK-NEXT:    ret
   %vc = zext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
; CHECK-NEXT:    ret
   %ve = lshr <vscale x 1 x i64> %vd, %splat2
   %vf = trunc <vscale x 1 x i64> %ve to <vscale x 1 x i32>
   ret <vscale x 1 x i32> %vf
 }
 
 define <vscale x 1 x i32> @vmulhu_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
 ; RV32-LABEL: vmulhu_vi_nxv1i32_0:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw zero, 12(sp)
 ; RV32-NEXT:    addi a0, zero, -7
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v9, (a0), zero
-; RV32-NEXT:    vzext.vf2 v10, v8
-; RV32-NEXT:    vmul.vv v8, v10, v9
-; RV32-NEXT:    addi a0, zero, 32
-; RV32-NEXT:    vsrl.vx v8, v8, a0
-; RV32-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
-; RV32-NEXT:    vnsrl.wi v8, v8, 0
-; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
+; RV32-NEXT:    vmulhu.vx v8, v8, a0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vmulhu_vi_nxv1i32_0:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
-; RV64-NEXT:    vzext.vf2 v9, v8
 ; RV64-NEXT:    addi a0, zero, 1
 ; RV64-NEXT:    slli a0, a0, 32
 ; RV64-NEXT:    addi a0, a0, -7
-; RV64-NEXT:    vmul.vx v8, v9, a0
-; RV64-NEXT:    addi a0, zero, 32
-; RV64-NEXT:    vsrl.vx v8, v8, a0
-; RV64-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
-; RV64-NEXT:    vnsrl.wi v8, v8, 0
+; RV64-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
+; RV64-NEXT:    vmulhu.vx v8, v8, a0
 ; RV64-NEXT:    ret
   %head1 = insertelement <vscale x 1 x i32> undef, i32 -7, i32 0
   %splat1 = shufflevector <vscale x 1 x i32> %head1, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
   %vb = zext <vscale x 1 x i32> %splat1 to <vscale x 1 x i64>
   %vc = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>
   %vd = mul <vscale x 1 x i64> %vb, %vc
   %head2 = insertelement <vscale x 1 x i64> undef, i64 32, i32 0
   %splat2 = shufflevector <vscale x 1 x i64> %head2, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
   %ve = lshr <vscale x 1 x i64> %vd, %splat2
   %vf = trunc <vscale x 1 x i64> %ve to <vscale x 1 x i32>
   ret <vscale x 1 x i32> %vf
 }
 
 define <vscale x 1 x i32> @vmulhu_vi_nxv1i32_1(<vscale x 1 x i32> %va) {
-; CHECK-LABEL: vmulhu_vi_nxv1i32_1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT:    vzext.vf2 v9, v8
-; CHECK-NEXT:    vsll.vi v8, v9, 4
-; CHECK-NEXT:    addi a0, zero, 32
-; CHECK-NEXT:    vsrl.vx v8, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
-; CHECK-NEXT:    vnsrl.wi v8, v8, 0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vmulhu_vi_nxv1i32_1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
+; RV32-NEXT:    vsrl.vi v8, v8, 28
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vmulhu_vi_nxv1i32_1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    addi a0, zero, 16
+; RV64-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
+; RV64-NEXT:    vmulhu.vx v8, v8, a0
+; RV64-NEXT:    ret
   %head1 = insertelement <vscale x 1 x i32> undef, i32 16, i32 0
   %splat1 = shufflevector <vscale x 1 x i32> %head1, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
   %vb = zext <vscale x 1 x i32> %splat1 to <vscale x 1 x i64>
   %vc = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>
   %vd = mul <vscale x 1 x i64> %vb, %vc
   %head2 = insertelement <vscale x 1 x i64> undef, i64 32, i32 0
   %splat2 = shufflevector <vscale x 1 x i64> %head2, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
   %ve = lshr <vscale x 1 x i64> %vd, %splat2
; CHECK-NEXT:    ret
   %ve = lshr <vscale x 2 x i64> %vd, %splat2
   %vf = trunc <vscale x 2 x i64> %ve to <vscale x 2 x i32>
   ret <vscale x 2 x i32> %vf
 }
 
 define <vscale x 2 x i32> @vmulhu_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
 ; RV32-LABEL: vmulhu_vi_nxv2i32_0:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw zero, 12(sp)
 ; RV32-NEXT:    addi a0, zero, -7
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v10, (a0), zero
-; RV32-NEXT:    vzext.vf2 v12, v8
-; RV32-NEXT:    vmul.vv v8, v12, v10
-; RV32-NEXT:    addi a0, zero, 32
-; RV32-NEXT:    vsrl.vx v10, v8, a0
-; RV32-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
-; RV32-NEXT:    vnsrl.wi v8, v10, 0
-; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
+; RV32-NEXT:    vmulhu.vx v8, v8, a0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vmulhu_vi_nxv2i32_0:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
-; RV64-NEXT:    vzext.vf2 v10, v8
 ; RV64-NEXT:    addi a0, zero, 1
 ; RV64-NEXT:    slli a0, a0, 32
 ; RV64-NEXT:    addi a0, a0, -7
-; RV64-NEXT:    vmul.vx v8, v10, a0
-; RV64-NEXT:    addi a0, zero, 32
-; RV64-NEXT:    vsrl.vx v10, v8, a0
-; RV64-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
-; RV64-NEXT:    vnsrl.wi v8, v10, 0
+; RV64-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
+; RV64-NEXT:    vmulhu.vx v8, v8, a0
 ; RV64-NEXT:    ret
   %head1 = insertelement <vscale x 2 x i32> undef, i32 -7, i32 0
   %splat1 = shufflevector <vscale x 2 x i32> %head1, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
   %vb = zext <vscale x 2 x i32> %splat1 to <vscale x 2 x i64>
   %vc = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>
   %vd = mul <vscale x 2 x i64> %vb, %vc
   %head2 = insertelement <vscale x 2 x i64> undef, i64 32, i32 0
   %splat2 = shufflevector <vscale x 2 x i64> %head2, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %ve = lshr <vscale x 2 x i64> %vd, %splat2
   %vf = trunc <vscale x 2 x i64> %ve to <vscale x 2 x i32>
   ret <vscale x 2 x i32> %vf
 }
 
 define <vscale x 2 x i32> @vmulhu_vi_nxv2i32_1(<vscale x 2 x i32> %va) {
-; CHECK-LABEL: vmulhu_vi_nxv2i32_1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
-; CHECK-NEXT:    vzext.vf2 v10, v8
-; CHECK-NEXT:    vsll.vi v8, v10, 4
-; CHECK-NEXT:    addi a0, zero, 32
-; CHECK-NEXT:    vsrl.vx v10, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
-; CHECK-NEXT:    vnsrl.wi v8, v10, 0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vmulhu_vi_nxv2i32_1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
+; RV32-NEXT:    vsrl.vi v8, v8, 28
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vmulhu_vi_nxv2i32_1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    addi a0, zero, 16
+; RV64-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
+; RV64-NEXT:    vmulhu.vx v8, v8, a0
+; RV64-NEXT:    ret
   %head1 = insertelement <vscale x 2 x i32> undef, i32 16, i32 0
   %splat1 = shufflevector <vscale x 2 x i32> %head1, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
   %vb = zext <vscale x 2 x i32> %splat1 to <vscale x 2 x i64>
   %vc = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>
   %vd = mul <vscale x 2 x i64> %vb, %vc
   %head2 = insertelement <vscale x 2 x i64> undef, i64 32, i32 0
   %splat2 = shufflevector <vscale x 2 x i64> %head2, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %ve = lshr <vscale x 2 x i64> %vd, %splat2
; CHECK-NEXT:    ret
   %ve = lshr <vscale x 4 x i64> %vd, %splat2
   %vf = trunc <vscale x 4 x i64> %ve to <vscale x 4 x i32>
   ret <vscale x 4 x i32> %vf
 }
 
 define <vscale x 4 x i32> @vmulhu_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
 ; RV32-LABEL: vmulhu_vi_nxv4i32_0:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw zero, 12(sp)
 ; RV32-NEXT:    addi a0, zero, -7
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v12, (a0), zero
-; RV32-NEXT:    vzext.vf2 v16, v8
-; RV32-NEXT:    vmul.vv v8, v16, v12
-; RV32-NEXT:    addi a0, zero, 32
-; RV32-NEXT:    vsrl.vx v12, v8, a0
-; RV32-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
-; RV32-NEXT:    vnsrl.wi v8, v12, 0
-; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
+; RV32-NEXT:    vmulhu.vx v8, v8, a0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vmulhu_vi_nxv4i32_0:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
-; RV64-NEXT:    vzext.vf2 v12, v8
 ; RV64-NEXT:    addi a0, zero, 1
 ; RV64-NEXT:    slli a0, a0, 32
 ; RV64-NEXT:    addi a0, a0, -7
-; RV64-NEXT:    vmul.vx v8, v12, a0
-; RV64-NEXT:    addi a0, zero, 32
-; RV64-NEXT:    vsrl.vx v12, v8, a0
-; RV64-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
-; RV64-NEXT:    vnsrl.wi v8, v12, 0
+; RV64-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
+; RV64-NEXT:    vmulhu.vx v8, v8, a0
 ; RV64-NEXT:    ret
   %head1 = insertelement <vscale x 4 x i32> undef, i32 -7, i32 0
   %splat1 = shufflevector <vscale x 4 x i32> %head1, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
   %vb = zext <vscale x 4 x i32> %splat1 to <vscale x 4 x i64>
   %vc = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>
   %vd = mul <vscale x 4 x i64> %vb, %vc
   %head2 = insertelement <vscale x 4 x i64> undef, i64 32, i32 0
   %splat2 = shufflevector <vscale x 4 x i64> %head2, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
   %ve = lshr <vscale x 4 x i64> %vd, %splat2
   %vf = trunc <vscale x 4 x i64> %ve to <vscale x 4 x i32>
   ret <vscale x 4 x i32> %vf
 }
 
 define <vscale x 4 x i32> @vmulhu_vi_nxv4i32_1(<vscale x 4 x i32> %va) {
-; CHECK-LABEL: vmulhu_vi_nxv4i32_1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
-; CHECK-NEXT:    vzext.vf2 v12, v8
-; CHECK-NEXT:    vsll.vi v8, v12, 4
-; CHECK-NEXT:    addi a0, zero, 32
-; CHECK-NEXT:    vsrl.vx v12, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
-; CHECK-NEXT:    vnsrl.wi v8, v12, 0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vmulhu_vi_nxv4i32_1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
+; RV32-NEXT:    vsrl.vi v8, v8, 28
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vmulhu_vi_nxv4i32_1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    addi a0, zero, 16
+; RV64-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
+; RV64-NEXT:    vmulhu.vx v8, v8, a0
+; RV64-NEXT:    ret
   %head1 = insertelement <vscale x 4 x i32> undef, i32 16, i32 0
   %splat1 = shufflevector <vscale x 4 x i32> %head1, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
   %vb = zext <vscale x 4 x i32> %splat1 to <vscale x 4 x i64>
   %vc = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>
   %vd = mul <vscale x 4 x i64> %vb, %vc
   %head2 = insertelement <vscale x 4 x i64> undef, i64 32, i32 0
   %splat2 = shufflevector <vscale x 4 x i64> %head2, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
   %ve = lshr <vscale x 4 x i64> %vd, %splat2
; CHECK-NEXT:    ret
   %ve = lshr <vscale x 8 x i64> %vd, %splat2
   %vf = trunc <vscale x 8 x i64> %ve to <vscale x 8 x i32>
   ret <vscale x 8 x i32> %vf
 }
 
 define <vscale x 8 x i32> @vmulhu_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
 ; RV32-LABEL: vmulhu_vi_nxv8i32_0:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw zero, 12(sp)
 ; RV32-NEXT:    addi a0, zero, -7
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v16, (a0), zero
-; RV32-NEXT:    vzext.vf2 v24, v8
-; RV32-NEXT:    vmul.vv v8, v24, v16
-; RV32-NEXT:    addi a0, zero, 32
-; RV32-NEXT:    vsrl.vx v16, v8, a0
-; RV32-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
-; RV32-NEXT:    vnsrl.wi v8, v16, 0
-; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; RV32-NEXT:    vmulhu.vx v8, v8, a0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vmulhu_vi_nxv8i32_0:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
-; RV64-NEXT:    vzext.vf2 v16, v8
 ; RV64-NEXT:    addi a0, zero, 1
 ; RV64-NEXT:    slli a0, a0, 32
 ; RV64-NEXT:    addi a0, a0, -7
-; RV64-NEXT:    vmul.vx v8, v16, a0
-; RV64-NEXT:    addi a0, zero, 32
-; RV64-NEXT:    vsrl.vx v16, v8, a0
-; RV64-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
-; RV64-NEXT:    vnsrl.wi v8, v16, 0
+; RV64-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; RV64-NEXT:    vmulhu.vx v8, v8, a0
 ; RV64-NEXT:    ret
   %head1 = insertelement <vscale x 8 x i32> undef, i32 -7, i32 0
   %splat1 = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
   %vb = zext <vscale x 8 x i32> %splat1 to <vscale x 8 x i64>
   %vc = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
   %vd = mul <vscale x 8 x i64> %vb, %vc
   %head2 = insertelement <vscale x 8 x i64> undef, i64 32, i32 0
   %splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
   %ve = lshr <vscale x 8 x i64> %vd, %splat2
   %vf = trunc <vscale x 8 x i64> %ve to <vscale x 8 x i32>
   ret <vscale x 8 x i32> %vf
 }
 
 define <vscale x 8 x i32> @vmulhu_vi_nxv8i32_1(<vscale x 8 x i32> %va) {
-; CHECK-LABEL: vmulhu_vi_nxv8i32_1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT:    vzext.vf2 v16, v8
-; CHECK-NEXT:    vsll.vi v8, v16, 4
-; CHECK-NEXT:    addi a0, zero, 32
-; CHECK-NEXT:    vsrl.vx v16, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
-; CHECK-NEXT:    vnsrl.wi v8, v16, 0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vmulhu_vi_nxv8i32_1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; RV32-NEXT:    vsrl.vi v8, v8, 28
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vmulhu_vi_nxv8i32_1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    addi a0, zero, 16
+; RV64-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; RV64-NEXT:    vmulhu.vx v8, v8, a0
+; RV64-NEXT:    ret
   %head1 = insertelement <vscale x 8 x i32> undef, i32 16, i32 0
   %splat1 = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
   %vb = zext <vscale x 8 x i32> %splat1 to <vscale x 8 x i64>
   %vc = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
   %vd = mul <vscale x 8 x i64> %vb, %vc
   %head2 = insertelement <vscale x 8 x i64> undef, i64 32, i32 0
   %splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
   %ve = lshr <vscale x 8 x i64> %vd, %splat2
   %vf = trunc <vscale x 8 x i64> %ve to <vscale x 8 x i32>
   ret <vscale x 8 x i32> %vf
 }