[AArch64][SVE] Handle svbool_t VLST <-> VLAT/GNUT conversion

[junparser]

Summary

According to https://godbolt.org/z/q5rME1naY and acle, we found that
there are different SVE conversion behaviours between clang and gcc. It turns
out that llvm does not handle SVE predicates width properly.

This patch 1) checks SVE predicates width rightly with svbool_t type.

2. removes warning on svbool_t VLST <-> VLAT/GNUT conversion.
3. disables VLST <-> VLAT/GNUT conversion between SVE vectors and predicates

due to different width.

[junparser]

@efriedma with this patch, all of conversion between VLST and VLAT should have same vector size(getElementType() * getElementCount()). The regression in D105097 will be fixed by using bitcast + vector.insert/extract directly

[junparser]

In D106333#2889168, @junparser wrote:

@efriedma with this patch, all of conversion between VLST and VLAT should have same vector size(getElementType() * getElementCount()). The regression in D105097 will be fixed by using bitcast + vector.insert/extract directly

OK, actually this is wrong due to vscale representation in llvm ir. However, we can still use bitcast as long as we can handle <32*i1> <64*i1>... in backend? any suggestion about this? @efriedma

[paulwalker-arm]

In D106333#2889168, @junparser wrote:

@efriedma with this patch, all of conversion between VLST and VLAT should have same vector size(getElementType() * getElementCount()). The regression in D105097 will be fixed by using bitcast + vector.insert/extract directly

I hope I've not got the wrong end of the stick here but the above is our intention. As in, Arm is looking at replacing the "via memory predicate casting" with a method that uses vector_of_i8s vector insert/extract with the necessary bitcasting. Before doing this we just had to fix up a bunch of failing INSERT_SUBVECTOR cases when it comes to the illegal types this idiom introduces.

[junparser]

In D106333#2889859, @paulwalker-arm wrote:

In D106333#2889168, @junparser wrote:

@efriedma with this patch, all of conversion between VLST and VLAT should have same vector size(getElementType() * getElementCount()). The regression in D105097 will be fixed by using bitcast + vector.insert/extract directly

I hope I've not got the wrong end of the stick here but the above is our intention. As in, Arm is looking at replacing the "via memory predicate casting" with a method that uses vector_of_i8s vector insert/extract with the necessary bitcasting. Before doing this we just had to fix up a bunch of failing INSERT_SUBVECTOR cases when it comes to the illegal types this idiom introduces.

Good to know this.

[efriedma]

Can you add a helper somewhere for the BT->getKind() == BuiltinType::SveBool ? getLangOpts().ArmSveVectorBits / getCharWidth() : getLangOpts().ArmSveVectorBits) pattern?

[junparser]

Address comments.

[paulwalker-arm]

clang/lib/AST/ASTContext.cpp

8677

Out of interest is this indirection necessary? I mean we know sve predicates are exactly an eighth the size of sve vectors so why not just use 8?

[junparser]

clang/lib/AST/ASTContext.cpp

8677

Just want to keep same style since HandleArmSveVectorBitsTypeAttr use this. 8 is make sense to me.

[c-rhodes]

clang/lib/AST/ASTContext.cpp

8673

s/perdicate/predicate

clang/test/SemaCXX/aarch64-sve-lax-vector-conversions.cpp

13–15

unused?

17

also unused?

clang/test/SemaCXX/attr-arm-sve-vector-bits.cpp

32

s/perdicates/predicates

[junparser]

Address comments.

[efriedma]

LGTM

clang/lib/AST/ASTContext.cpp

if (First->getNumElements() == Second->getNumElements() &&
       First->getVectorKind() != VectorType::SveFixedLengthPredicateVector &&
       Second->getVectorKind() != VectorType::SveFixedLengthDataVector &&
       Second->getVectorKind() != VectorType::SveFixedLengthPredicateVector)
     return true;
 
   return false;
 }
 
 bool ASTContext::areCompatibleSveTypes(QualType FirstType,
                                        QualType SecondType) {
   assert(((FirstType->isSizelessBuiltinType() && SecondType->isVectorType()) ||
           (FirstType->isVectorType() && SecondType->isSizelessBuiltinType())) &&
          "Expected SVE builtin type and vector type!");
 
   auto IsValidCast = [this](QualType FirstType, QualType SecondType) {
     if (const auto *BT = FirstType->getAs<BuiltinType>()) {
       if (const auto *VT = SecondType->getAs<VectorType>()) {
         // Predicates have the same representation as uint8 so we also have to
         // check the kind to make these types incompatible.
         if (VT->getVectorKind() == VectorType::SveFixedLengthPredicateVector)
           return BT->getKind() == BuiltinType::SveBool;
         else if (VT->getVectorKind() == VectorType::SveFixedLengthDataVector)
           return VT->getElementType().getCanonicalType() ==
                  FirstType->getSveEltType(*this);
         else if (VT->getVectorKind() == VectorType::GenericVector)
-          return getTypeSize(SecondType) == getLangOpts().ArmSveVectorBits &&
+          return getTypeSize(SecondType) ==
+                     (BT->getKind() == BuiltinType::SveBool
+                          ? getLangOpts().ArmSveVectorBits / getCharWidth()
+                          : getLangOpts().ArmSveVectorBits) &&
                  hasSameType(VT->getElementType(),
                              getBuiltinVectorTypeInfo(BT).ElementType);
       }
     }
     return false;
   };
 
   return IsValidCast(FirstType, SecondType) ||
          IsValidCast(SecondType, FirstType);
 }
 
 bool ASTContext::areLaxCompatibleSveTypes(QualType FirstType,
                                           QualType SecondType) {
   assert(((FirstType->isSizelessBuiltinType() && SecondType->isVectorType()) ||
           (FirstType->isVectorType() && SecondType->isSizelessBuiltinType())) &&
          "Expected SVE builtin type and vector type!");
 
   auto IsLaxCompatible = [this](QualType FirstType, QualType SecondType) {
-    if (!FirstType->getAs<BuiltinType>())
+    const auto *BT = FirstType->getAs<BuiltinType>();
+    if (!BT)
       return false;
 
     const auto *VecTy = SecondType->getAs<VectorType>();
     if (VecTy &&
         (VecTy->getVectorKind() == VectorType::SveFixedLengthDataVector ||
          VecTy->getVectorKind() == VectorType::GenericVector)) {
       const LangOptions::LaxVectorConversionKind LVCKind =
           getLangOpts().getLaxVectorConversions();
 
+      // Can not convert between sve predicates and sve vectors because of
+      // different size.
+      if (BT->getKind() == BuiltinType::SveBool &&
+          VecTy->getVectorKind() == VectorType::SveFixedLengthDataVector)
+        return false;
+
       // If __ARM_FEATURE_SVE_BITS != N do not allow GNU vector lax conversion.
       // "Whenever __ARM_FEATURE_SVE_BITS==N, GNUT implicitly
       // converts to VLAT and VLAT implicitly converts to GNUT."
       // ACLE Spec Version 00bet6, 3.7.3.2. Behavior common to vectors and
       // predicates.
       if (VecTy->getVectorKind() == VectorType::GenericVector &&
-          getTypeSize(SecondType) != getLangOpts().ArmSveVectorBits)
+          getTypeSize(SecondType) !=
+              (BT->getKind() == BuiltinType::SveBool
+                   ? getLangOpts().ArmSveVectorBits / getCharWidth()
+                   : getLangOpts().ArmSveVectorBits))
         return false;
 
       // If -flax-vector-conversions=all is specified, the types are
       // certainly compatible.
       if (LVCKind == LangOptions::LaxVectorConversionKind::All)
         return true;
 
       // If -flax-vector-conversions=integer is specified, the types are

clang/lib/Sema/SemaChecking.cpp

static void CheckImplicitConversion(Sema &S, Expr *E, QualType T,
 
   // Strip vector types.
   if (const auto *SourceVT = dyn_cast<VectorType>(Source)) {
     if (Target->isVLSTBuiltinType()) {
       auto SourceVectorKind = SourceVT->getVectorKind();
       if (SourceVectorKind == VectorType::SveFixedLengthDataVector ||
           SourceVectorKind == VectorType::SveFixedLengthPredicateVector ||
           (SourceVectorKind == VectorType::GenericVector &&
-           S.Context.getTypeSize(Source) == S.getLangOpts().ArmSveVectorBits))
+           S.Context.getTypeSize(Source) ==
+               (Target->getAs<BuiltinType>()->getKind() == BuiltinType::SveBool
+                    ? S.getLangOpts().ArmSveVectorBits /
+                          S.Context.getCharWidth()
+                    : S.getLangOpts().ArmSveVectorBits)))
         return;
     }
 
     if (!isa<VectorType>(Target)) {
       if (S.SourceMgr.isInSystemMacro(CC))
         return;
       return DiagnoseImpCast(S, E, T, CC, diag::warn_impcast_vector_scalar);
     }

clang/test/CodeGen/attr-arm-sve-vector-bits-codegen.c

 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -msve-vector-bits=512 -fallow-half-arguments-and-returns -S -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s
 
 #include <arm_sve.h>
 
 #define N __ARM_FEATURE_SVE_BITS
 
 typedef svint32_t fixed_int32_t __attribute__((arm_sve_vector_bits(N)));
 typedef svbool_t fixed_bool_t __attribute__((arm_sve_vector_bits(N)));
+typedef uint8_t uint8_vec_t __attribute__((vector_size(N / 64)));
 
 fixed_bool_t global_pred;
 fixed_int32_t global_vec;
 
 // CHECK-LABEL: @foo(
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:    [[RETVAL:%.*]] = alloca <16 x i32>, align 16
 // CHECK-NEXT:    [[PRED_ADDR:%.*]] = alloca <vscale x 16 x i1>, align 2
fixed_bool_t address_of_array_idx() {
   return *parr;
 }
 
 // CHECK-LABEL: @test_cast(
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:    [[RETVAL:%.*]] = alloca <16 x i32>, align 16
 // CHECK-NEXT:    [[PRED_ADDR:%.*]] = alloca <vscale x 16 x i1>, align 2
 // CHECK-NEXT:    [[VEC_ADDR:%.*]] = alloca <vscale x 4 x i32>, align 16
-// CHECK-NEXT:    [[XX:%.*]] = alloca <16 x i32>, align 16
-// CHECK-NEXT:    [[YY:%.*]] = alloca <16 x i32>, align 16
+// CHECK-NEXT:    [[XX:%.*]] = alloca <8 x i8>, align 8
+// CHECK-NEXT:    [[YY:%.*]] = alloca <8 x i8>, align 8
 // CHECK-NEXT:    [[PG:%.*]] = alloca <vscale x 16 x i1>, align 2
 // CHECK-NEXT:    [[SAVED_VALUE:%.*]] = alloca <8 x i8>, align 8
-// CHECK-NEXT:    [[SAVED_VALUE1:%.*]] = alloca <16 x i32>, align 64
+// CHECK-NEXT:    [[SAVED_VALUE1:%.*]] = alloca <8 x i8>, align 8
 // CHECK-NEXT:    store <vscale x 16 x i1> [[PRED:%.*]], <vscale x 16 x i1>* [[PRED_ADDR]], align 2
 // CHECK-NEXT:    store <vscale x 4 x i32> [[VEC:%.*]], <vscale x 4 x i32>* [[VEC_ADDR]], align 16
-// CHECK-NEXT:    store <16 x i32> <i32 1, i32 2, i32 3, i32 4, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>, <16 x i32>* [[XX]], align 16
-// CHECK-NEXT:    store <16 x i32> <i32 2, i32 5, i32 4, i32 6, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>, <16 x i32>* [[YY]], align 16
+// CHECK-NEXT:    store <8 x i8> <i8 1, i8 2, i8 3, i8 4, i8 0, i8 0, i8 0, i8 0>, <8 x i8>* [[XX]], align 8
+// CHECK-NEXT:    store <8 x i8> <i8 2, i8 5, i8 4, i8 6, i8 0, i8 0, i8 0, i8 0>, <8 x i8>* [[YY]], align 8
 // CHECK-NEXT:    [[TMP0:%.*]] = load <vscale x 16 x i1>, <vscale x 16 x i1>* [[PRED_ADDR]], align 2
 // CHECK-NEXT:    [[TMP1:%.*]] = load <8 x i8>, <8 x i8>* @global_pred, align 2
 // CHECK-NEXT:    store <8 x i8> [[TMP1]], <8 x i8>* [[SAVED_VALUE]], align 8
 // CHECK-NEXT:    [[CASTFIXEDSVE:%.*]] = bitcast <8 x i8>* [[SAVED_VALUE]] to <vscale x 16 x i1>*
 // CHECK-NEXT:    [[TMP2:%.*]] = load <vscale x 16 x i1>, <vscale x 16 x i1>* [[CASTFIXEDSVE]], align 8
-// CHECK-NEXT:    [[TMP3:%.*]] = load <16 x i32>, <16 x i32>* [[XX]], align 16
-// CHECK-NEXT:    [[TMP4:%.*]] = load <16 x i32>, <16 x i32>* [[YY]], align 16
-// CHECK-NEXT:    [[ADD:%.*]] = add <16 x i32> [[TMP3]], [[TMP4]]
-// CHECK-NEXT:    store <16 x i32> [[ADD]], <16 x i32>* [[SAVED_VALUE1]], align 64
-// CHECK-NEXT:    [[CASTFIXEDSVE2:%.*]] = bitcast <16 x i32>* [[SAVED_VALUE1]] to <vscale x 16 x i1>*
-// CHECK-NEXT:    [[TMP5:%.*]] = load <vscale x 16 x i1>, <vscale x 16 x i1>* [[CASTFIXEDSVE2]], align 64
+// CHECK-NEXT:    [[TMP3:%.*]] = load <8 x i8>, <8 x i8>* [[XX]], align 8
+// CHECK-NEXT:    [[TMP4:%.*]] = load <8 x i8>, <8 x i8>* [[YY]], align 8
+// CHECK-NEXT:    [[ADD:%.*]] = add <8 x i8> [[TMP3]], [[TMP4]]
+// CHECK-NEXT:    store <8 x i8> [[ADD]], <8 x i8>* [[SAVED_VALUE1]], align 8
+// CHECK-NEXT:    [[CASTFIXEDSVE2:%.*]] = bitcast <8 x i8>* [[SAVED_VALUE1]] to <vscale x 16 x i1>*
+// CHECK-NEXT:    [[TMP5:%.*]] = load <vscale x 16 x i1>, <vscale x 16 x i1>* [[CASTFIXEDSVE2]], align 8
 // CHECK-NEXT:    [[TMP6:%.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.and.z.nxv16i1(<vscale x 16 x i1> [[TMP0]], <vscale x 16 x i1> [[TMP2]], <vscale x 16 x i1> [[TMP5]])
 // CHECK-NEXT:    store <vscale x 16 x i1> [[TMP6]], <vscale x 16 x i1>* [[PG]], align 2
 // CHECK-NEXT:    [[TMP7:%.*]] = load <vscale x 16 x i1>, <vscale x 16 x i1>* [[PG]], align 2
 // CHECK-NEXT:    [[TMP8:%.*]] = load <16 x i32>, <16 x i32>* @global_vec, align 16
 // CHECK-NEXT:    [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[TMP8]], i64 0)
 // CHECK-NEXT:    [[TMP9:%.*]] = load <vscale x 4 x i32>, <vscale x 4 x i32>* [[VEC_ADDR]], align 16
 // CHECK-NEXT:    [[TMP10:%.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[TMP7]])
 // CHECK-NEXT:    [[TMP11:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.add.nxv4i32(<vscale x 4 x i1> [[TMP10]], <vscale x 4 x i32> [[CASTSCALABLESVE]], <vscale x 4 x i32> [[TMP9]])
 // CHECK-NEXT:    [[CASTFIXEDSVE3:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[TMP11]], i64 0)
 // CHECK-NEXT:    store <16 x i32> [[CASTFIXEDSVE3]], <16 x i32>* [[RETVAL]], align 16
 // CHECK-NEXT:    [[TMP12:%.*]] = load <16 x i32>, <16 x i32>* [[RETVAL]], align 16
 // CHECK-NEXT:    [[CASTSCALABLESVE4:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[TMP12]], i64 0)
 // CHECK-NEXT:    ret <vscale x 4 x i32> [[CASTSCALABLESVE4]]
 //
 fixed_int32_t test_cast(svbool_t pred, svint32_t vec) {
-  fixed_int32_t xx = {1, 2, 3, 4};
-  fixed_int32_t yy = {2, 5, 4, 6};
+  uint8_vec_t xx = {1, 2, 3, 4};
+  uint8_vec_t yy = {2, 5, 4, 6};
   svbool_t pg = svand_z(pred, global_pred, xx + yy);
   return svadd_m(pg, global_vec, vec);
 }

clang/test/SemaCXX/aarch64-sve-explicit-casts-fixed-size.cpp

 
 #define N __ARM_FEATURE_SVE_BITS
 #define FIXED_ATTR __attribute__((arm_sve_vector_bits(N)))
 
 typedef svfloat32_t fixed_float32_t FIXED_ATTR;
 typedef svfloat64_t fixed_float64_t FIXED_ATTR;
 typedef svint32_t fixed_int32_t FIXED_ATTR;
 typedef svint64_t fixed_int64_t FIXED_ATTR;
+typedef svbool_t fixed_bool_t FIXED_ATTR;
 
 // SVE VLSTs can be cast to SVE VLATs, regardless of lane size.
 // NOTE: the list below is NOT exhaustive for all SVE types.
 
 #define CAST(from, to) \
     void from##_to_##to(from a, to b) { \
         b = (to) a; \
     }

 TESTCASE(fixed_int32_t, svfloat64_t)
 TESTCASE(fixed_int32_t, svint32_t)
 TESTCASE(fixed_int32_t, svint64_t)
 
 TESTCASE(fixed_int64_t, svfloat32_t)
 TESTCASE(fixed_int64_t, svfloat64_t)
 TESTCASE(fixed_int64_t, svint32_t)
 TESTCASE(fixed_int64_t, svint64_t)
+
+TESTCASE(fixed_bool_t, svbool_t)

clang/test/SemaCXX/aarch64-sve-lax-vector-conversions.cpp

 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=512 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify=lax-vector-none %s
 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=512 -flax-vector-conversions=integer -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify=lax-vector-integer %s
 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=512 -flax-vector-conversions=all -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify=lax-vector-all %s
 
-// lax-vector-all-no-diagnostics
-
 #include <arm_sve.h>
 
 #define N __ARM_FEATURE_SVE_BITS
 #define SVE_FIXED_ATTR __attribute__((arm_sve_vector_bits(N)))
 #define GNU_FIXED_ATTR __attribute__((vector_size(N / 8)))
+#define GNU_BOOL_FIXED_ATTR __attribute__((vector_size(N / 64)))
 
 typedef svfloat32_t sve_fixed_float32_t SVE_FIXED_ATTR;
 typedef svint32_t sve_fixed_int32_t SVE_FIXED_ATTR;
+typedef svbool_t sve_fixed_bool_t SVE_FIXED_ATTR;
 typedef float gnu_fixed_float32_t GNU_FIXED_ATTR;
 typedef int gnu_fixed_int32_t GNU_FIXED_ATTR;
+typedef int8_t gnu_fixed_bool_t GNU_BOOL_FIXED_ATTR;
 
 void sve_allowed_with_integer_lax_conversions() {
   sve_fixed_int32_t fi32;
   svint64_t si64;
+  svbool_t sb8;
 
   // The implicit cast here should fail if -flax-vector-conversions=none, but pass if
   // -flax-vector-conversions={integer,all}.
   fi32 = si64;
   // lax-vector-none-error@-1 {{assigning to 'sve_fixed_int32_t' (vector of 16 'int' values) from incompatible type}}
   si64 = fi32;
   // lax-vector-none-error@-1 {{assigning to 'svint64_t' (aka '__SVInt64_t') from incompatible type}}
+
+  fi32 = sb8;
+  // lax-vector-none-error@-1 {{assigning to 'sve_fixed_int32_t' (vector of 16 'int' values) from incompatible type}}
+  // lax-vector-integer-error@-2 {{assigning to 'sve_fixed_int32_t' (vector of 16 'int' values) from incompatible type}}
+  // lax-vector-all-error@-3 {{assigning to 'sve_fixed_int32_t' (vector of 16 'int' values) from incompatible type}}
+  sb8 = fi32;
+  // lax-vector-none-error@-1 {{assigning to 'svbool_t' (aka '__SVBool_t') from incompatible type}}
+  // lax-vector-integer-error@-2 {{assigning to 'svbool_t' (aka '__SVBool_t') from incompatible type}}
+  // lax-vector-all-error@-3 {{assigning to 'svbool_t' (aka '__SVBool_t') from incompatible type}}
 }
 
 void sve_allowed_with_all_lax_conversions() {
   sve_fixed_float32_t ff32;
   svfloat64_t sf64;
 
   // The implicit cast here should fail if -flax-vector-conversions={none,integer}, but pass if
   // -flax-vector-conversions=all.
   ff32 = sf64;
   // lax-vector-none-error@-1 {{assigning to 'sve_fixed_float32_t' (vector of 16 'float' values) from incompatible type}}
   // lax-vector-integer-error@-2 {{assigning to 'sve_fixed_float32_t' (vector of 16 'float' values) from incompatible type}}
   sf64 = ff32;
   // lax-vector-none-error@-1 {{assigning to 'svfloat64_t' (aka '__SVFloat64_t') from incompatible type}}
   // lax-vector-integer-error@-2 {{assigning to 'svfloat64_t' (aka '__SVFloat64_t') from incompatible type}}
 }
 
 void gnu_allowed_with_integer_lax_conversions() {
   gnu_fixed_int32_t fi32;
   svint64_t si64;
+  svbool_t sb8;
 
   // The implicit cast here should fail if -flax-vector-conversions=none, but pass if
   // -flax-vector-conversions={integer,all}.
   fi32 = si64;
   // lax-vector-none-error@-1 {{assigning to 'gnu_fixed_int32_t' (vector of 16 'int' values) from incompatible type}}
   si64 = fi32;
   // lax-vector-none-error@-1 {{assigning to 'svint64_t' (aka '__SVInt64_t') from incompatible type}}
+
+  fi32 = sb8;
+  // lax-vector-none-error@-1 {{assigning to 'gnu_fixed_int32_t' (vector of 16 'int' values) from incompatible type}}
+  // lax-vector-integer-error@-2 {{assigning to 'gnu_fixed_int32_t' (vector of 16 'int' values) from incompatible type}}
+  // lax-vector-all-error@-3 {{assigning to 'gnu_fixed_int32_t' (vector of 16 'int' values) from incompatible type}}
+  sb8 = fi32;
+  // lax-vector-none-error@-1 {{assigning to 'svbool_t' (aka '__SVBool_t') from incompatible type}}
+  // lax-vector-integer-error@-2 {{assigning to 'svbool_t' (aka '__SVBool_t') from incompatible type}}
+  // lax-vector-all-error@-3 {{assigning to 'svbool_t' (aka '__SVBool_t') from incompatible type}}
 }
 
 void gnu_allowed_with_all_lax_conversions() {
   gnu_fixed_float32_t ff32;
   svfloat64_t sf64;
 
   // The implicit cast here should fail if -flax-vector-conversions={none,integer}, but pass if
   // -flax-vector-conversions=all.
   ff32 = sf64;
   // lax-vector-none-error@-1 {{assigning to 'gnu_fixed_float32_t' (vector of 16 'float' values) from incompatible type}}
   // lax-vector-integer-error@-2 {{assigning to 'gnu_fixed_float32_t' (vector of 16 'float' values) from incompatible type}}
   sf64 = ff32;
   // lax-vector-none-error@-1 {{assigning to 'svfloat64_t' (aka '__SVFloat64_t') from incompatible type}}
   // lax-vector-integer-error@-2 {{assigning to 'svfloat64_t' (aka '__SVFloat64_t') from incompatible type}}
 }

clang/test/SemaCXX/attr-arm-sve-vector-bits.cpp

 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -ffreestanding -fsyntax-only -verify -std=c++11 -msve-vector-bits=512 -fallow-half-arguments-and-returns -Wconversion %s
 // expected-no-diagnostics
 
 #include <stdint.h>
 
 #define N __ARM_FEATURE_SVE_BITS
 
 typedef __SVInt8_t svint8_t;
 typedef svint8_t fixed_int8_t __attribute__((arm_sve_vector_bits(N)));
 typedef int8_t gnu_int8_t __attribute__((vector_size(N / 8)));
 
+typedef __SVBool_t svbool_t;
+typedef svbool_t fixed_bool_t __attribute__((arm_sve_vector_bits(N)));
+typedef int8_t gnu_bool_t __attribute__((vector_size(N / 64)));
+
 template<typename T> struct S { T var; };
 
 S<fixed_int8_t> s;
 
 // Test implicit casts between VLA and VLS vectors
 svint8_t to_svint8_t(fixed_int8_t x) { return x; }
 fixed_int8_t from_svint8_t(svint8_t x) { return x; }
 
 // Test implicit casts between GNU and VLA vectors
 svint8_t to_svint8_t__from_gnu_int8_t(gnu_int8_t x) { return x; }
 gnu_int8_t from_svint8_t__to_gnu_int8_t(svint8_t x) { return x; }
 
 // Test implicit casts between GNU and VLS vectors
 fixed_int8_t to_fixed_int8_t__from_gnu_int8_t(gnu_int8_t x) { return x; }
 gnu_int8_t from_fixed_int8_t__to_gnu_int8_t(fixed_int8_t x) { return x; }
+
+// Test implicit casts between VLA and VLS perdicates
+svbool_t to_svbool_t(fixed_bool_t x) { return x; }
+fixed_bool_t from_svbool_t(svbool_t x) { return x; }
+
+// Test implicit casts between GNU and VLA predicates
+svbool_t to_svbool_t__from_gnu_bool_t(gnu_bool_t x) { return x; }
+gnu_bool_t from_svbool_t__to_gnu_bool_t(svbool_t x) { return x; }