[RISCV] Update to vlm.v and vsm.v according to v1.0-rc1.

[HsiangKai]

Summary

vle1.v -> vlm.v
vse1.v -> vsm.v

[rogfer01]

I'm confused because the PDF at https://github.com/riscv/riscv-v-spec/releases/tag/v1.0-rc1 doesn't seem to describe vcpop.m.

I can see this has changed in the ToT https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#changes-from-v1-0-rc1

Perhaps this will be part of a future 1.0-rc2?

llvm/test/CodeGen/RISCV/rvv/vse1-rv64.ll

13

Is this expected?

[HsiangKai]

In D106044#2879361, @rogfer01 wrote:

I'm confused because the PDF at https://github.com/riscv/riscv-v-spec/releases/tag/v1.0-rc1 doesn't seem to describe vcpop.m.

I can see this has changed in the ToT https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#changes-from-v1-0-rc1

Perhaps this will be part of a future 1.0-rc2?

You are right. I will revert it. Thanks.

[HsiangKai]

• Remove vcpop.m.
• Correct test cases.

[craig.topper]

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vse.c

1182

Was the call supposed to be renamed or just the test name?

clang/test/CodeGen/RISCV/rvv-intrinsics/vle.c

1258

Did you mean to leave the old test name? I don't see the same in the vse.c file

[HsiangKai]

Update test cases.

[HsiangKai]

Ping.

[craig.topper]

LGTM

[frasercrmck]

LGTM in principle but aliases.s is apparently failing with something that looks relevant.

clang/include/clang/Basic/riscv_vector.td

let HasNoMaskedOverloaded = false,
     }],
     ManualCodegenMask= [{
       // Move mask to right before vl.
       std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
       IntrinsicTypes = {ResultType, Ops[3]->getType()};
       Ops[1] = Builder.CreateBitCast(Ops[1], ResultType->getPointerTo());
     }] in {
   class RVVVLEMaskBuiltin : RVVBuiltin<"m", "mPCUe", "c"> {
-    let Name = "vle1_v";
-    let IRName = "vle1";
+    let Name = NAME;
+    let IRName = "vlm";
     let HasMask = false;
   }
   multiclass RVVVLEBuiltin<list<string> types> {
     let Name = NAME # "_v",
         IRName = "vle",
         IRNameMask ="vle_mask" in {
       foreach type = types in {
         def : RVVBuiltin<"v", "vPCe", type>;
let HasMaskedOffOperand = false,
     }],
     ManualCodegenMask= [{
       // Builtin: (mask, ptr, value, vl). Intrinsic: (value, ptr, mask, vl)
       std::swap(Ops[0], Ops[2]);
       Ops[1] = Builder.CreateBitCast(Ops[1], Ops[0]->getType()->getPointerTo());
       IntrinsicTypes = {Ops[0]->getType(), Ops[3]->getType()};
     }] in {
   class RVVVSEMaskBuiltin : RVVBuiltin<"m", "0PUem", "c"> {
-    let Name = "vse1_v";
-    let IRName = "vse1";
+    let Name = NAME;
+    let IRName = "vsm";
     let HasMask = false;
   }
   multiclass RVVVSEBuiltin<list<string> types> {
     let Name = NAME # "_v",
         IRName = "vse",
         IRNameMask = "vse_mask" in {
       foreach type = types in {
         def : RVVBuiltin<"v", "0Pev", type>;

 #define vsetvlmax_e64m8() __builtin_rvv_vsetvlimax(3, 3)
 
 }] in
   def vsetvlimax : RVVBuiltin<"", "zKzKz", "i">;
 }
 
 // 7. Vector Loads and Stores
 // 7.4. Vector Unit-Stride Instructions
-def vle1: RVVVLEMaskBuiltin;
+def vle1_v: RVVVLEMaskBuiltin;
+def vlm_v: RVVVLEMaskBuiltin;
 defm vle8: RVVVLEBuiltin<["c"]>;
 defm vle16: RVVVLEBuiltin<["s"]>;
 defm vle32: RVVVLEBuiltin<["i","f"]>;
 defm vle64: RVVVLEBuiltin<["l","d"]>;
 
-def vse1 : RVVVSEMaskBuiltin;
+def vse1_v : RVVVSEMaskBuiltin;
+def vsm_v : RVVVSEMaskBuiltin;
 defm vse8 : RVVVSEBuiltin<["c"]>;
 defm vse16: RVVVSEBuiltin<["s"]>;
 defm vse32: RVVVSEBuiltin<["i","f"]>;
 defm vse64: RVVVSEBuiltin<["l","d"]>;
 
 // 7.5. Vector Strided Instructions
 defm vlse8: RVVVLSEBuiltin<["c"]>;
 defm vlse16: RVVVLSEBuiltin<["s"]>;

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vse.c

 // CHECK-RV64-NEXT:    call void @llvm.riscv.vse.mask.nxv8f64.i64(<vscale x 8 x double> [[VALUE:%.*]], <vscale x 8 x double>* [[TMP0]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    ret void
 //
 void test_vse64_v_f64m8_m(vbool8_t mask, double *base, vfloat64m8_t value, size_t vl) {
   return vse64(mask, base, value, vl);
 }
 
 //
-// CHECK-RV64-LABEL: @test_vse1_v_b1(
+// CHECK-RV64-LABEL: @test_vsm_v_b1(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i1>*
-// CHECK-RV64-NEXT:    call void @llvm.riscv.vse1.nxv64i1.i64(<vscale x 64 x i1> [[VALUE:%.*]], <vscale x 64 x i1>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    call void @llvm.riscv.vsm.nxv64i1.i64(<vscale x 64 x i1> [[VALUE:%.*]], <vscale x 64 x i1>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    ret void
 //
-void test_vse1_v_b1(uint8_t *base, vbool1_t value, size_t vl) {
+void test_vsm_v_b1(uint8_t *base, vbool1_t value, size_t vl) {
   return vse1(base, value, vl);
 }
 
 //
-// CHECK-RV64-LABEL: @test_vse1_v_b2(
+// CHECK-RV64-LABEL: @test_vsm_v_b2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i1>*
-// CHECK-RV64-NEXT:    call void @llvm.riscv.vse1.nxv32i1.i64(<vscale x 32 x i1> [[VALUE:%.*]], <vscale x 32 x i1>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    call void @llvm.riscv.vsm.nxv32i1.i64(<vscale x 32 x i1> [[VALUE:%.*]], <vscale x 32 x i1>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    ret void
 //
-void test_vse1_v_b2(uint8_t *base, vbool2_t value, size_t vl) {
+void test_vsm_v_b2(uint8_t *base, vbool2_t value, size_t vl) {
   return vse1(base, value, vl);
 }
 
 //
-// CHECK-RV64-LABEL: @test_vse1_v_b4(
+// CHECK-RV64-LABEL: @test_vsm_v_b4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i1>*
-// CHECK-RV64-NEXT:    call void @llvm.riscv.vse1.nxv16i1.i64(<vscale x 16 x i1> [[VALUE:%.*]], <vscale x 16 x i1>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    call void @llvm.riscv.vsm.nxv16i1.i64(<vscale x 16 x i1> [[VALUE:%.*]], <vscale x 16 x i1>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    ret void
 //
-void test_vse1_v_b4(uint8_t *base, vbool4_t value, size_t vl) {
+void test_vsm_v_b4(uint8_t *base, vbool4_t value, size_t vl) {
   return vse1(base, value, vl);
 }
 
 //
-// CHECK-RV64-LABEL: @test_vse1_v_b8(
+// CHECK-RV64-LABEL: @test_vsm_v_b8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i1>*
-// CHECK-RV64-NEXT:    call void @llvm.riscv.vse1.nxv8i1.i64(<vscale x 8 x i1> [[VALUE:%.*]], <vscale x 8 x i1>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    call void @llvm.riscv.vsm.nxv8i1.i64(<vscale x 8 x i1> [[VALUE:%.*]], <vscale x 8 x i1>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    ret void
 //
-void test_vse1_v_b8(uint8_t *base, vbool8_t value, size_t vl) {
+void test_vsm_v_b8(uint8_t *base, vbool8_t value, size_t vl) {
   return vse1(base, value, vl);
 }
 
 //
-// CHECK-RV64-LABEL: @test_vse1_v_b16(
+// CHECK-RV64-LABEL: @test_vsm_v_b16(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i1>*
-// CHECK-RV64-NEXT:    call void @llvm.riscv.vse1.nxv4i1.i64(<vscale x 4 x i1> [[VALUE:%.*]], <vscale x 4 x i1>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    call void @llvm.riscv.vsm.nxv4i1.i64(<vscale x 4 x i1> [[VALUE:%.*]], <vscale x 4 x i1>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    ret void
 //
-void test_vse1_v_b16(uint8_t *base, vbool16_t value, size_t vl) {
+void test_vsm_v_b16(uint8_t *base, vbool16_t value, size_t vl) {
   return vse1(base, value, vl);
 }
 
 //
-// CHECK-RV64-LABEL: @test_vse1_v_b32(
+// CHECK-RV64-LABEL: @test_vsm_v_b32(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i1>*
-// CHECK-RV64-NEXT:    call void @llvm.riscv.vse1.nxv2i1.i64(<vscale x 2 x i1> [[VALUE:%.*]], <vscale x 2 x i1>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    call void @llvm.riscv.vsm.nxv2i1.i64(<vscale x 2 x i1> [[VALUE:%.*]], <vscale x 2 x i1>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    ret void
 //
-void test_vse1_v_b32(uint8_t *base, vbool32_t value, size_t vl) {
+void test_vsm_v_b32(uint8_t *base, vbool32_t value, size_t vl) {
   return vse1(base, value, vl);
 }
 
 //
-// CHECK-RV64-LABEL: @test_vse1_v_b64(
+// CHECK-RV64-LABEL: @test_vsm_v_b64(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i1>*
-// CHECK-RV64-NEXT:    call void @llvm.riscv.vse1.nxv1i1.i64(<vscale x 1 x i1> [[VALUE:%.*]], <vscale x 1 x i1>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    call void @llvm.riscv.vsm.nxv1i1.i64(<vscale x 1 x i1> [[VALUE:%.*]], <vscale x 1 x i1>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    ret void
 //
-void test_vse1_v_b64(uint8_t *base, vbool64_t value, size_t vl) {
+void test_vsm_v_b64(uint8_t *base, vbool64_t value, size_t vl) {
   return vse1(base, value, vl);
 }

clang/test/CodeGen/RISCV/rvv-intrinsics/vle.c

 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 8 x double> @llvm.riscv.vle.mask.nxv8f64.i64(<vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x double>* [[TMP0]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    ret <vscale x 8 x double> [[TMP1]]
 //
 vfloat64m8_t test_vle64_v_f64m8_m(vbool8_t mask, vfloat64m8_t maskedoff, const double *base, size_t vl) {
   return vle64_v_f64m8_m(mask, maskedoff, base, vl);
 }
 
 //
-// CHECK-RV64-LABEL: @test_vle1_v_b1(
+// CHECK-RV64-LABEL: @test_vlm_v_b1(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i1>*
-// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vle1.nxv64i1.i64(<vscale x 64 x i1>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vlm.nxv64i1.i64(<vscale x 64 x i1>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    ret <vscale x 64 x i1> [[TMP1]]
 //
-vbool1_t test_vle1_v_b1(const uint8_t *base, size_t vl) {
-  return vle1_v_b1(base, vl);
+vbool1_t test_vlm_v_b1(const uint8_t *base, size_t vl) {
+  return vlm_v_b1(base, vl);
 }
 
 //
-// CHECK-RV64-LABEL: @test_vle1_v_b2(
+// CHECK-RV64-LABEL: @test_vlm_v_b2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i1>*
-// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vle1.nxv32i1.i64(<vscale x 32 x i1>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vlm.nxv32i1.i64(<vscale x 32 x i1>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    ret <vscale x 32 x i1> [[TMP1]]
 //
-vbool2_t test_vle1_v_b2(const uint8_t *base, size_t vl) {
-  return vle1_v_b2(base, vl);
+vbool2_t test_vlm_v_b2(const uint8_t *base, size_t vl) {
+  return vlm_v_b2(base, vl);
 }
 
 //
-// CHECK-RV64-LABEL: @test_vle1_v_b4(
+// CHECK-RV64-LABEL: @test_vlm_v_b4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i1>*
-// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vle1.nxv16i1.i64(<vscale x 16 x i1>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vlm.nxv16i1.i64(<vscale x 16 x i1>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i1> [[TMP1]]
 //
-vbool4_t test_vle1_v_b4(const uint8_t *base, size_t vl) {
-  return vle1_v_b4(base, vl);
+vbool4_t test_vlm_v_b4(const uint8_t *base, size_t vl) {
+  return vlm_v_b4(base, vl);
 }
 
 //
-// CHECK-RV64-LABEL: @test_vle1_v_b8(
+// CHECK-RV64-LABEL: @test_vlm_v_b8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i1>*
-// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vle1.nxv8i1.i64(<vscale x 8 x i1>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vlm.nxv8i1.i64(<vscale x 8 x i1>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP1]]
 //
-vbool8_t test_vle1_v_b8(const uint8_t *base, size_t vl) {
-  return vle1_v_b8(base, vl);
+vbool8_t test_vlm_v_b8(const uint8_t *base, size_t vl) {
+  return vlm_v_b8(base, vl);
 }
 
 //
-// CHECK-RV64-LABEL: @test_vle1_v_b16(
+// CHECK-RV64-LABEL: @test_vlm_v_b16(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i1>*
-// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vle1.nxv4i1.i64(<vscale x 4 x i1>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vlm.nxv4i1.i64(<vscale x 4 x i1>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP1]]
 //
-vbool16_t test_vle1_v_b16(const uint8_t *base, size_t vl) {
-  return vle1_v_b16(base, vl);
+vbool16_t test_vlm_v_b16(const uint8_t *base, size_t vl) {
+  return vlm_v_b16(base, vl);
 }
 
 //
-// CHECK-RV64-LABEL: @test_vle1_v_b32(
+// CHECK-RV64-LABEL: @test_vlm_v_b32(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i1>*
-// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vle1.nxv2i1.i64(<vscale x 2 x i1>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vlm.nxv2i1.i64(<vscale x 2 x i1>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP1]]
 //
-vbool32_t test_vle1_v_b32(const uint8_t *base, size_t vl) {
-  return vle1_v_b32(base, vl);
+vbool32_t test_vlm_v_b32(const uint8_t *base, size_t vl) {
+  return vlm_v_b32(base, vl);
+}
+
+//
+// CHECK-RV64-LABEL: @test_vlm_v_b64(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i1>*
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vlm.nxv1i1.i64(<vscale x 1 x i1>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP1]]
+//
+vbool64_t test_vlm_v_b64(const uint8_t *base, size_t vl) {
+  return vlm_v_b64(base, vl);
 }
 
 //
 // CHECK-RV64-LABEL: @test_vle1_v_b64(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i1>*
-// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vle1.nxv1i1.i64(<vscale x 1 x i1>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vlm.nxv1i1.i64(<vscale x 1 x i1>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP1]]
 //
 vbool64_t test_vle1_v_b64(const uint8_t *base, size_t vl) {
   return vle1_v_b64(base, vl);
 }

clang/test/CodeGen/RISCV/rvv-intrinsics/vse.c

 // CHECK-RV64-NEXT:    call void @llvm.riscv.vse.mask.nxv8f64.i64(<vscale x 8 x double> [[VALUE:%.*]], <vscale x 8 x double>* [[TMP0]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    ret void
 //
 void test_vse64_v_f64m8_m(vbool8_t mask, double *base, vfloat64m8_t value, size_t vl) {
   return vse64_v_f64m8_m(mask, base, value, vl);
 }
 
 //
-// CHECK-RV64-LABEL: @test_vse1_v_b1(
+// CHECK-RV64-LABEL: @test_vsm_v_b1(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i1>*
-// CHECK-RV64-NEXT:    call void @llvm.riscv.vse1.nxv64i1.i64(<vscale x 64 x i1> [[VALUE:%.*]], <vscale x 64 x i1>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    call void @llvm.riscv.vsm.nxv64i1.i64(<vscale x 64 x i1> [[VALUE:%.*]], <vscale x 64 x i1>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    ret void
 //
-void test_vse1_v_b1(uint8_t *base, vbool1_t value, size_t vl) {
-  return vse1_v_b1(base, value, vl);
+void test_vsm_v_b1(uint8_t *base, vbool1_t value, size_t vl) {
+  return vsm_v_b1(base, value, vl);
 }
 
 //
-// CHECK-RV64-LABEL: @test_vse1_v_b2(
+// CHECK-RV64-LABEL: @test_vsm_v_b2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i1>*
-// CHECK-RV64-NEXT:    call void @llvm.riscv.vse1.nxv32i1.i64(<vscale x 32 x i1> [[VALUE:%.*]], <vscale x 32 x i1>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    call void @llvm.riscv.vsm.nxv32i1.i64(<vscale x 32 x i1> [[VALUE:%.*]], <vscale x 32 x i1>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    ret void
 //
-void test_vse1_v_b2(uint8_t *base, vbool2_t value, size_t vl) {
-  return vse1_v_b2(base, value, vl);
+void test_vsm_v_b2(uint8_t *base, vbool2_t value, size_t vl) {
+  return vsm_v_b2(base, value, vl);
 }
 
 //
-// CHECK-RV64-LABEL: @test_vse1_v_b4(
+// CHECK-RV64-LABEL: @test_vsm_v_b4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i1>*
-// CHECK-RV64-NEXT:    call void @llvm.riscv.vse1.nxv16i1.i64(<vscale x 16 x i1> [[VALUE:%.*]], <vscale x 16 x i1>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    call void @llvm.riscv.vsm.nxv16i1.i64(<vscale x 16 x i1> [[VALUE:%.*]], <vscale x 16 x i1>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    ret void
 //
-void test_vse1_v_b4(uint8_t *base, vbool4_t value, size_t vl) {
-  return vse1_v_b4(base, value, vl);
+void test_vsm_v_b4(uint8_t *base, vbool4_t value, size_t vl) {
+  return vsm_v_b4(base, value, vl);
 }
 
 //
-// CHECK-RV64-LABEL: @test_vse1_v_b8(
+// CHECK-RV64-LABEL: @test_vsm_v_b8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i1>*
-// CHECK-RV64-NEXT:    call void @llvm.riscv.vse1.nxv8i1.i64(<vscale x 8 x i1> [[VALUE:%.*]], <vscale x 8 x i1>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    call void @llvm.riscv.vsm.nxv8i1.i64(<vscale x 8 x i1> [[VALUE:%.*]], <vscale x 8 x i1>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    ret void
 //
-void test_vse1_v_b8(uint8_t *base, vbool8_t value, size_t vl) {
-  return vse1_v_b8(base, value, vl);
+void test_vsm_v_b8(uint8_t *base, vbool8_t value, size_t vl) {
+  return vsm_v_b8(base, value, vl);
 }
 
 //
-// CHECK-RV64-LABEL: @test_vse1_v_b16(
+// CHECK-RV64-LABEL: @test_vsm_v_b16(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i1>*
-// CHECK-RV64-NEXT:    call void @llvm.riscv.vse1.nxv4i1.i64(<vscale x 4 x i1> [[VALUE:%.*]], <vscale x 4 x i1>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    call void @llvm.riscv.vsm.nxv4i1.i64(<vscale x 4 x i1> [[VALUE:%.*]], <vscale x 4 x i1>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    ret void
 //
-void test_vse1_v_b16(uint8_t *base, vbool16_t value, size_t vl) {
-  return vse1_v_b16(base, value, vl);
+void test_vsm_v_b16(uint8_t *base, vbool16_t value, size_t vl) {
+  return vsm_v_b16(base, value, vl);
 }
 
 //
-// CHECK-RV64-LABEL: @test_vse1_v_b32(
+// CHECK-RV64-LABEL: @test_vsm_v_b32(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i1>*
-// CHECK-RV64-NEXT:    call void @llvm.riscv.vse1.nxv2i1.i64(<vscale x 2 x i1> [[VALUE:%.*]], <vscale x 2 x i1>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    call void @llvm.riscv.vsm.nxv2i1.i64(<vscale x 2 x i1> [[VALUE:%.*]], <vscale x 2 x i1>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    ret void
 //
-void test_vse1_v_b32(uint8_t *base, vbool32_t value, size_t vl) {
-  return vse1_v_b32(base, value, vl);
+void test_vsm_v_b32(uint8_t *base, vbool32_t value, size_t vl) {
+  return vsm_v_b32(base, value, vl);
 }
 
 //
-// CHECK-RV64-LABEL: @test_vse1_v_b64(
+// CHECK-RV64-LABEL: @test_vsm_v_b64(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i1>*
-// CHECK-RV64-NEXT:    call void @llvm.riscv.vse1.nxv1i1.i64(<vscale x 1 x i1> [[VALUE:%.*]], <vscale x 1 x i1>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    call void @llvm.riscv.vsm.nxv1i1.i64(<vscale x 1 x i1> [[VALUE:%.*]], <vscale x 1 x i1>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    ret void
 //
-void test_vse1_v_b64(uint8_t *base, vbool64_t value, size_t vl) {
-  return vse1_v_b64(base, value, vl);
+void test_vsm_v_b64(uint8_t *base, vbool64_t value, size_t vl) {
+  return vsm_v_b64(base, value, vl);
 }

llvm/include/llvm/IR/IntrinsicsRISCV.td

let TargetPrefix = "riscv" in {
   defm vse : RISCVUSStore;
   defm vlse: RISCVSLoad;
   defm vsse: RISCVSStore;
   defm vluxei : RISCVILoad;
   defm vloxei : RISCVILoad;
   defm vsoxei : RISCVIStore;
   defm vsuxei : RISCVIStore;
 
-  def int_riscv_vle1 : RISCVUSLoad;
-  def int_riscv_vse1 : RISCVUSStore;
+  def int_riscv_vlm : RISCVUSLoad;
+  def int_riscv_vsm : RISCVUSStore;
 
   defm vamoswap : RISCVAMO;
   defm vamoadd : RISCVAMO;
   defm vamoxor : RISCVAMO;
   defm vamoand : RISCVAMO;
   defm vamoor : RISCVAMO;
   defm vamomin : RISCVAMO;
   defm vamomax : RISCVAMO;

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

case Intrinsic::riscv_vluxei_mask: {
           CurDAG->getMachineNode(P->Pseudo, DL, Node->getVTList(), Operands);
 
       if (auto *MemOp = dyn_cast<MemSDNode>(Node))
         CurDAG->setNodeMemRefs(Load, {MemOp->getMemOperand()});
 
       ReplaceNode(Node, Load);
       return;
     }
-    case Intrinsic::riscv_vle1:
+    case Intrinsic::riscv_vlm:
     case Intrinsic::riscv_vle:
     case Intrinsic::riscv_vle_mask:
     case Intrinsic::riscv_vlse:
     case Intrinsic::riscv_vlse_mask: {
       bool IsMasked = IntNo == Intrinsic::riscv_vle_mask ||
                       IntNo == Intrinsic::riscv_vlse_mask;
       bool IsStrided =
           IntNo == Intrinsic::riscv_vlse || IntNo == Intrinsic::riscv_vlse_mask;
case Intrinsic::riscv_vsuxei_mask: {
           CurDAG->getMachineNode(P->Pseudo, DL, Node->getVTList(), Operands);
 
       if (auto *MemOp = dyn_cast<MemSDNode>(Node))
         CurDAG->setNodeMemRefs(Store, {MemOp->getMemOperand()});
 
       ReplaceNode(Node, Store);
       return;
     }
-    case Intrinsic::riscv_vse1:
+    case Intrinsic::riscv_vsm:
     case Intrinsic::riscv_vse:
     case Intrinsic::riscv_vse_mask:
     case Intrinsic::riscv_vsse:
     case Intrinsic::riscv_vsse_mask: {
       bool IsMasked = IntNo == Intrinsic::riscv_vse_mask ||
                       IntNo == Intrinsic::riscv_vsse_mask;
       bool IsStrided =
           IntNo == Intrinsic::riscv_vsse || IntNo == Intrinsic::riscv_vsse_mask;

llvm/lib/Target/RISCV/RISCVInstrInfoV.td

 def VLE32_V : VUnitStrideLoad<LUMOPUnitStride, LSWidth32, "vle32.v">;
 def VLE64_V : VUnitStrideLoad<LUMOPUnitStride, LSWidth64, "vle64.v">;
 
 def VLE8FF_V : VUnitStrideLoad<LUMOPUnitStrideFF, LSWidth8, "vle8ff.v">;
 def VLE16FF_V : VUnitStrideLoad<LUMOPUnitStrideFF, LSWidth16, "vle16ff.v">;
 def VLE32FF_V : VUnitStrideLoad<LUMOPUnitStrideFF, LSWidth32, "vle32ff.v">;
 def VLE64FF_V : VUnitStrideLoad<LUMOPUnitStrideFF, LSWidth64, "vle64ff.v">;
 
-def VLE1_V : VUnitStrideLoadMask<"vle1.v">;
-def VSE1_V : VUnitStrideStoreMask<"vse1.v">;
+def VLM_V : VUnitStrideLoadMask<"vlm.v">;
+def VSM_V : VUnitStrideStoreMask<"vsm.v">;
+def : InstAlias<"vle1.v $vd, (${rs1})",
+                (VLM_V VR:$vd, GPR:$rs1), 0>;
+def : InstAlias<"vse1.v $vs3, (${rs1})",
+                (VSM_V VR:$vs3, GPR:$rs1), 0>;
 
 def VSE8_V : VUnitStrideStore<SUMOPUnitStride, LSWidth8, "vse8.v">;
 def VSE16_V : VUnitStrideStore<SUMOPUnitStride, LSWidth16, "vse16.v">;
 def VSE32_V : VUnitStrideStore<SUMOPUnitStride, LSWidth32, "vse32.v">;
 def VSE64_V : VUnitStrideStore<SUMOPUnitStride, LSWidth64, "vse64.v">;
 
 // Vector Strided Instructions
 def VLSE8_V : VStridedLoad<LSWidth8, "vlse8.v">;

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

 //===----------------------------------------------------------------------===//
 // 7.4 Vector Unit-Stride Instructions
 //===----------------------------------------------------------------------===//
 
 // Pseudos Unit-Stride Loads and Stores
 defm PseudoVL : VPseudoUSLoad</*isFF=*/false>;
 defm PseudoVS : VPseudoUSStore;
 
-defm PseudoVLE1 : VPseudoLoadMask;
-defm PseudoVSE1 : VPseudoStoreMask;
+defm PseudoVLM : VPseudoLoadMask;
+defm PseudoVSM : VPseudoStoreMask;
 
 //===----------------------------------------------------------------------===//
 // 7.5 Vector Strided Instructions
 //===----------------------------------------------------------------------===//
 
 // Vector Strided Loads and Stores
 defm PseudoVLS : VPseudoSLoad;
 defm PseudoVSS : VPseudoSStore;

llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

def : Pat<(type (load BaseAddr:$rs1)),
             (load_instr BaseAddr:$rs1)>;
   // Store
   def : Pat<(store type:$rs2, BaseAddr:$rs1),
             (store_instr reg_class:$rs2, BaseAddr:$rs1)>;
 }
 
 multiclass VPatUSLoadStoreMaskSDNode<MTypeInfo m>
 {
-  defvar load_instr = !cast<Instruction>("PseudoVLE1_V_"#m.BX);
-  defvar store_instr = !cast<Instruction>("PseudoVSE1_V_"#m.BX);
+  defvar load_instr = !cast<Instruction>("PseudoVLM_V_"#m.BX);
+  defvar store_instr = !cast<Instruction>("PseudoVSM_V_"#m.BX);
   // Load
   def : Pat<(m.Mask (load BaseAddr:$rs1)),
             (load_instr BaseAddr:$rs1, m.AVL, m.Log2SEW)>;
   // Store
   def : Pat<(store m.Mask:$rs2, BaseAddr:$rs1),
             (store_instr VR:$rs2, BaseAddr:$rs1, m.AVL, m.Log2SEW)>;
 }
 

llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

def : Pat<(vti.Vector (riscv_vle_vl BaseAddr:$rs1, VLOpFrag)),
             (load_instr BaseAddr:$rs1, GPR:$vl, vti.Log2SEW)>;
   // Store
   def : Pat<(riscv_vse_vl (vti.Vector vti.RegClass:$rs2), BaseAddr:$rs1,
                           VLOpFrag),
             (store_instr vti.RegClass:$rs2, BaseAddr:$rs1, GPR:$vl, vti.Log2SEW)>;
 }
 
 foreach mti = AllMasks in {
-  defvar load_instr = !cast<Instruction>("PseudoVLE1_V_"#mti.BX);
-  defvar store_instr = !cast<Instruction>("PseudoVSE1_V_"#mti.BX);
+  defvar load_instr = !cast<Instruction>("PseudoVLM_V_"#mti.BX);
+  defvar store_instr = !cast<Instruction>("PseudoVSM_V_"#mti.BX);
   def : Pat<(mti.Mask (riscv_vle_vl BaseAddr:$rs1, VLOpFrag)),
             (load_instr BaseAddr:$rs1, GPR:$vl, mti.Log2SEW)>;
   def : Pat<(riscv_vse_vl (mti.Mask VR:$rs2), BaseAddr:$rs1,
                           VLOpFrag),
             (store_instr VR:$rs2, BaseAddr:$rs1, GPR:$vl, mti.Log2SEW)>;
 }
 
 // 12.1. Vector Single-Width Integer Add and Subtract

llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll

; CHECK-NEXT:    ret
   %v = load <vscale x 16 x i64>, <vscale x 16 x i64>* %p
   ret <vscale x 16 x i64> %v
 }
 
 define fastcc <vscale x 8 x i1> @ret_mask_nxv8i1(<vscale x 8 x i1>* %p) {
 ; CHECK-LABEL: ret_mask_nxv8i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT:    vle1.v v0, (a0)
+; CHECK-NEXT:    vlm.v v0, (a0)
 ; CHECK-NEXT:    ret
   %v = load <vscale x 8 x i1>, <vscale x 8 x i1>* %p
   ret <vscale x 8 x i1> %v
 }
 
 define fastcc <vscale x 32 x i1> @ret_mask_nxv32i1(<vscale x 32 x i1>* %p) {
 ; CHECK-LABEL: ret_mask_nxv32i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e8, m4, ta, mu
-; CHECK-NEXT:    vle1.v v0, (a0)
+; CHECK-NEXT:    vlm.v v0, (a0)
 ; CHECK-NEXT:    ret
   %v = load <vscale x 32 x i1>, <vscale x 32 x i1>* %p
   ret <vscale x 32 x i1> %v
 }
 
 ; Return the vector via registers v8-v23
 define fastcc <vscale x 64 x i32> @ret_split_nxv64i32(<vscale x 64 x i32>* %x) {
 ; CHECK-LABEL: ret_split_nxv64i32:

llvm/test/CodeGen/RISCV/rvv/extload-truncstore.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -verify-machineinstrs < %s | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -verify-machineinstrs < %s | FileCheck %s
 
 define <vscale x 1 x i8> @sextload_nxv1i1_nxv1i8(<vscale x 1 x i1>* %x) {
 ; CHECK-LABEL: sextload_nxv1i1_nxv1i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, mu
-; CHECK-NEXT:    vle1.v v0, (a0)
+; CHECK-NEXT:    vlm.v v0, (a0)
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v8, v25, -1, v0
 ; CHECK-NEXT:    ret
   %y = load <vscale x 1 x i1>, <vscale x 1 x i1>* %x
   %z = sext <vscale x 1 x i1> %y to <vscale x 1 x i8>
   ret <vscale x 1 x i8> %z
 }
 

 }
 
 define void @truncstore_nxv1i8_nxv1i1(<vscale x 1 x i8> %x, <vscale x 1 x i1> *%z) {
 ; CHECK-LABEL: truncstore_nxv1i8_nxv1i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, mu
 ; CHECK-NEXT:    vand.vi v25, v8, 1
 ; CHECK-NEXT:    vmsne.vi v25, v25, 0
-; CHECK-NEXT:    vse1.v v25, (a0)
+; CHECK-NEXT:    vsm.v v25, (a0)
 ; CHECK-NEXT:    ret
   %y = trunc <vscale x 1 x i8> %x to <vscale x 1 x i1>
   store <vscale x 1 x i1> %y, <vscale x 1 x i1>* %z
   ret void
 }
 
 define void @truncstore_nxv1i16_nxv1i8(<vscale x 1 x i16> %x, <vscale x 1 x i8>* %z) {
 ; CHECK-LABEL: truncstore_nxv1i16_nxv1i8:

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll

; LMULMAX4-NEXT:    ret
   %v = load <16 x i64>, <16 x i64>* %p
   ret <16 x i64> %v
 }
 
 define fastcc <8 x i1> @ret_mask_v8i1(<8 x i1>* %p) {
 ; CHECK-LABEL: ret_mask_v8i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT:    vle1.v v0, (a0)
+; CHECK-NEXT:    vlm.v v0, (a0)
 ; CHECK-NEXT:    ret
   %v = load <8 x i1>, <8 x i1>* %p
   ret <8 x i1> %v
 }
 
 define fastcc <32 x i1> @ret_mask_v32i1(<32 x i1>* %p) {
 ; CHECK-LABEL: ret_mask_v32i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT:    vle1.v v0, (a0)
+; CHECK-NEXT:    vlm.v v0, (a0)
 ; CHECK-NEXT:    ret
   %v = load <32 x i1>, <32 x i1>* %p
   ret <32 x i1> %v
 }
 
 ; Return the vector via registers v8-v23
 define fastcc <64 x i32> @ret_split_v64i32(<64 x i32>* %x) {
 ; LMULMAX8-LABEL: ret_split_v64i32:

 ; mask argument %m2. %m1 is passed via v0.
 define fastcc <4 x i1> @vector_mask_arg_direct_stack(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6, i32 %7, i32 %8, i32 %9, i32 %10, i32 %11, i32 %12, i32 %13, <32 x i32> %x, <32 x i32> %y, <32 x i32> %z, <4 x i1> %m1, <4 x i1> %m2, i32 %last) {
 ; CHECK-LABEL: vector_mask_arg_direct_stack:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi sp, sp, -16
 ; CHECK-NEXT:    .cfi_def_cfa_offset 16
 ; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, mu
 ; CHECK-NEXT:    addi a0, sp, 152
-; CHECK-NEXT:    vle1.v v25, (a0)
+; CHECK-NEXT:    vlm.v v25, (a0)
 ; CHECK-NEXT:    vmxor.mm v0, v0, v25
 ; CHECK-NEXT:    addi sp, sp, 16
 ; CHECK-NEXT:    ret
   %r = xor <4 x i1> %m1, %m2
   ret <4 x i1> %r
 }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll

; LMULMAX1-NEXT:    ret
   %v = load <16 x i64>, <16 x i64>* %p
   ret <16 x i64> %v
 }
 
 define <8 x i1> @ret_mask_v8i1(<8 x i1>* %p) {
 ; CHECK-LABEL: ret_mask_v8i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT:    vle1.v v0, (a0)
+; CHECK-NEXT:    vlm.v v0, (a0)
 ; CHECK-NEXT:    ret
   %v = load <8 x i1>, <8 x i1>* %p
   ret <8 x i1> %v
 }
 
 define <32 x i1> @ret_mask_v32i1(<32 x i1>* %p) {
 ; LMULMAX8-LABEL: ret_mask_v32i1:
 ; LMULMAX8:       # %bb.0:
 ; LMULMAX8-NEXT:    addi a1, zero, 32
 ; LMULMAX8-NEXT:    vsetvli zero, a1, e8, m2, ta, mu
-; LMULMAX8-NEXT:    vle1.v v0, (a0)
+; LMULMAX8-NEXT:    vlm.v v0, (a0)
 ; LMULMAX8-NEXT:    ret
 ;
 ; LMULMAX4-LABEL: ret_mask_v32i1:
 ; LMULMAX4:       # %bb.0:
 ; LMULMAX4-NEXT:    addi a1, zero, 32
 ; LMULMAX4-NEXT:    vsetvli zero, a1, e8, m2, ta, mu
-; LMULMAX4-NEXT:    vle1.v v0, (a0)
+; LMULMAX4-NEXT:    vlm.v v0, (a0)
 ; LMULMAX4-NEXT:    ret
 ;
 ; LMULMAX2-LABEL: ret_mask_v32i1:
 ; LMULMAX2:       # %bb.0:
 ; LMULMAX2-NEXT:    addi a1, zero, 32
 ; LMULMAX2-NEXT:    vsetvli zero, a1, e8, m2, ta, mu
-; LMULMAX2-NEXT:    vle1.v v0, (a0)
+; LMULMAX2-NEXT:    vlm.v v0, (a0)
 ; LMULMAX2-NEXT:    ret
 ;
 ; LMULMAX1-LABEL: ret_mask_v32i1:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-NEXT:    vle1.v v0, (a0)
+; LMULMAX1-NEXT:    vlm.v v0, (a0)
 ; LMULMAX1-NEXT:    addi a0, a0, 2
-; LMULMAX1-NEXT:    vle1.v v8, (a0)
+; LMULMAX1-NEXT:    vlm.v v8, (a0)
 ; LMULMAX1-NEXT:    ret
   %v = load <32 x i1>, <32 x i1>* %p
   ret <32 x i1> %v
 }
 
 ; Return the vector via registers v8-v23
 define <64 x i32> @ret_split_v64i32(<64 x i32>* %x) {
 ; LMULMAX8-LABEL: ret_split_v64i32:

 ; stack.
 define <4 x i1> @vector_mask_arg_via_stack(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6, i32 %7, <32 x i32> %x, <32 x i32> %y, <32 x i32> %z, i32 %8, <4 x i1> %9, <4 x i1> %10) {
 ; CHECK-LABEL: vector_mask_arg_via_stack:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi sp, sp, -16
 ; CHECK-NEXT:    .cfi_def_cfa_offset 16
 ; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, mu
 ; CHECK-NEXT:    addi a0, sp, 152
-; CHECK-NEXT:    vle1.v v0, (a0)
+; CHECK-NEXT:    vlm.v v0, (a0)
 ; CHECK-NEXT:    addi sp, sp, 16
 ; CHECK-NEXT:    ret
   ret <4 x i1> %10
 }
 
 ; Calling the function above. Ensure we pass the mask arguments correctly. We
 ; legalize stores of small masks such that the value is at least byte-sized.
 define <4 x i1> @pass_vector_mask_arg_via_stack(<4 x i1> %v) {

 ; LMULMAX8-NEXT:    vsetivli zero, 4, e8, mf2, tu, mu
 ; LMULMAX8-NEXT:    vslideup.vi v26, v25, 0
 ; LMULMAX8-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; LMULMAX8-NEXT:    vmsne.vi v25, v26, 0
 ; LMULMAX8-NEXT:    addi a0, sp, 136
 ; LMULMAX8-NEXT:    addi a5, zero, 5
 ; LMULMAX8-NEXT:    addi a6, zero, 6
 ; LMULMAX8-NEXT:    addi a7, zero, 7
-; LMULMAX8-NEXT:    vse1.v v25, (a0)
+; LMULMAX8-NEXT:    vsm.v v25, (a0)
 ; LMULMAX8-NEXT:    mv a0, zero
 ; LMULMAX8-NEXT:    mv a1, zero
 ; LMULMAX8-NEXT:    mv a2, zero
 ; LMULMAX8-NEXT:    mv a3, zero
 ; LMULMAX8-NEXT:    mv a4, zero
 ; LMULMAX8-NEXT:    vmv8r.v v16, v8
 ; LMULMAX8-NEXT:    call vector_mask_arg_via_stack@plt
 ; LMULMAX8-NEXT:    ld ra, 152(sp) # 8-byte Folded Reload

 ; LMULMAX4-NEXT:    vsetivli zero, 4, e8, mf2, tu, mu
 ; LMULMAX4-NEXT:    vslideup.vi v26, v25, 0
 ; LMULMAX4-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; LMULMAX4-NEXT:    vmsne.vi v25, v26, 0
 ; LMULMAX4-NEXT:    addi a0, sp, 136
 ; LMULMAX4-NEXT:    addi a5, zero, 5
 ; LMULMAX4-NEXT:    addi a6, zero, 6
 ; LMULMAX4-NEXT:    addi a7, zero, 7
-; LMULMAX4-NEXT:    vse1.v v25, (a0)
+; LMULMAX4-NEXT:    vsm.v v25, (a0)
 ; LMULMAX4-NEXT:    mv a0, zero
 ; LMULMAX4-NEXT:    mv a1, zero
 ; LMULMAX4-NEXT:    mv a2, zero
 ; LMULMAX4-NEXT:    mv a3, zero
 ; LMULMAX4-NEXT:    mv a4, zero
 ; LMULMAX4-NEXT:    vmv4r.v v12, v8
 ; LMULMAX4-NEXT:    vmv4r.v v16, v8
 ; LMULMAX4-NEXT:    vmv4r.v v20, v8

 ; LMULMAX2-NEXT:    vsetivli zero, 4, e8, mf2, tu, mu
 ; LMULMAX2-NEXT:    vslideup.vi v26, v25, 0
 ; LMULMAX2-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; LMULMAX2-NEXT:    vmsne.vi v25, v26, 0
 ; LMULMAX2-NEXT:    addi a0, sp, 136
 ; LMULMAX2-NEXT:    addi a5, zero, 5
 ; LMULMAX2-NEXT:    addi a6, zero, 6
 ; LMULMAX2-NEXT:    addi a7, zero, 7
-; LMULMAX2-NEXT:    vse1.v v25, (a0)
+; LMULMAX2-NEXT:    vsm.v v25, (a0)
 ; LMULMAX2-NEXT:    mv a0, zero
 ; LMULMAX2-NEXT:    mv a1, zero
 ; LMULMAX2-NEXT:    mv a2, zero
 ; LMULMAX2-NEXT:    mv a3, zero
 ; LMULMAX2-NEXT:    mv a4, zero
 ; LMULMAX2-NEXT:    vmv2r.v v10, v8
 ; LMULMAX2-NEXT:    vmv2r.v v12, v8
 ; LMULMAX2-NEXT:    vmv2r.v v14, v8

 ; LMULMAX1-NEXT:    vsetivli zero, 4, e8, mf2, tu, mu
 ; LMULMAX1-NEXT:    vslideup.vi v26, v25, 0
 ; LMULMAX1-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; LMULMAX1-NEXT:    vmsne.vi v25, v26, 0
 ; LMULMAX1-NEXT:    addi a0, sp, 136
 ; LMULMAX1-NEXT:    addi a5, zero, 5
 ; LMULMAX1-NEXT:    addi a6, zero, 6
 ; LMULMAX1-NEXT:    addi a7, zero, 7
-; LMULMAX1-NEXT:    vse1.v v25, (a0)
+; LMULMAX1-NEXT:    vsm.v v25, (a0)
 ; LMULMAX1-NEXT:    mv a0, zero
 ; LMULMAX1-NEXT:    mv a1, zero
 ; LMULMAX1-NEXT:    mv a2, zero
 ; LMULMAX1-NEXT:    mv a3, zero
 ; LMULMAX1-NEXT:    mv a4, zero
 ; LMULMAX1-NEXT:    vmv1r.v v9, v8
 ; LMULMAX1-NEXT:    vmv1r.v v10, v8
 ; LMULMAX1-NEXT:    vmv1r.v v11, v8

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1
 ; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=4 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX4
 ; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1
 ; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=4 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX4
 
 define <2 x i16> @sextload_v2i1_v2i16(<2 x i1>* %x) {
 ; CHECK-LABEL: sextload_v2i1_v2i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT:    vle1.v v0, (a0)
+; CHECK-NEXT:    vlm.v v0, (a0)
 ; CHECK-NEXT:    vsetvli zero, zero, e16, mf4, ta, mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v8, v25, -1, v0
 ; CHECK-NEXT:    ret
   %y = load <2 x i1>, <2 x i1>* %x
   %z = sext <2 x i1> %y to <2 x i16>
   ret <2 x i16> %z
 }

 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli zero, 2, e8, mf2, tu, mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
-; CHECK-NEXT:    vse1.v v25, (a0)
+; CHECK-NEXT:    vsm.v v25, (a0)
 ; CHECK-NEXT:    ret
   %y = trunc <2 x i8> %x to <2 x i1>
   store <2 x i1> %y, <2 x i1>* %z
   ret void
 }
 
 define void @truncstore_v2i16_v2i8(<2 x i16> %x, <2 x i8>* %z) {
 ; CHECK-LABEL: truncstore_v2i16_v2i8:

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll

; LMULMAX1-NEXT:    ret
   ret void
 }
 
 define void @extract_v8i1_v64i1_0(<64 x i1>* %x, <8 x i1>* %y) {
 ; LMULMAX2-LABEL: extract_v8i1_v64i1_0:
 ; LMULMAX2:       # %bb.0:
 ; LMULMAX2-NEXT:    addi a2, zero, 32
 ; LMULMAX2-NEXT:    vsetvli zero, a2, e8, m2, ta, mu
-; LMULMAX2-NEXT:    vle1.v v25, (a0)
+; LMULMAX2-NEXT:    vlm.v v25, (a0)
 ; LMULMAX2-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX2-NEXT:    vse1.v v25, (a1)
+; LMULMAX2-NEXT:    vsm.v v25, (a1)
 ; LMULMAX2-NEXT:    ret
 ;
 ; LMULMAX1-LABEL: extract_v8i1_v64i1_0:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-NEXT:    vle1.v v25, (a0)
+; LMULMAX1-NEXT:    vlm.v v25, (a0)
 ; LMULMAX1-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX1-NEXT:    vse1.v v25, (a1)
+; LMULMAX1-NEXT:    vsm.v v25, (a1)
 ; LMULMAX1-NEXT:    ret
   %a = load <64 x i1>, <64 x i1>* %x
   %c = call <8 x i1> @llvm.experimental.vector.extract.v8i1.v64i1(<64 x i1> %a, i64 0)
   store <8 x i1> %c, <8 x i1>* %y
   ret void
 }
 
 define void @extract_v8i1_v64i1_8(<64 x i1>* %x, <8 x i1>* %y) {
 ; LMULMAX2-LABEL: extract_v8i1_v64i1_8:
 ; LMULMAX2:       # %bb.0:
 ; LMULMAX2-NEXT:    addi a2, zero, 32
 ; LMULMAX2-NEXT:    vsetvli zero, a2, e8, m2, ta, mu
-; LMULMAX2-NEXT:    vle1.v v25, (a0)
+; LMULMAX2-NEXT:    vlm.v v25, (a0)
 ; LMULMAX2-NEXT:    vsetivli zero, 1, e8, mf4, ta, mu
 ; LMULMAX2-NEXT:    vslidedown.vi v25, v25, 1
 ; LMULMAX2-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX2-NEXT:    vse1.v v25, (a1)
+; LMULMAX2-NEXT:    vsm.v v25, (a1)
 ; LMULMAX2-NEXT:    ret
 ;
 ; LMULMAX1-LABEL: extract_v8i1_v64i1_8:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-NEXT:    vle1.v v25, (a0)
+; LMULMAX1-NEXT:    vlm.v v25, (a0)
 ; LMULMAX1-NEXT:    vsetivli zero, 1, e8, mf8, ta, mu
 ; LMULMAX1-NEXT:    vslidedown.vi v25, v25, 1
 ; LMULMAX1-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX1-NEXT:    vse1.v v25, (a1)
+; LMULMAX1-NEXT:    vsm.v v25, (a1)
 ; LMULMAX1-NEXT:    ret
   %a = load <64 x i1>, <64 x i1>* %x
   %c = call <8 x i1> @llvm.experimental.vector.extract.v8i1.v64i1(<64 x i1> %a, i64 8)
   store <8 x i1> %c, <8 x i1>* %y
   ret void
 }
 
 define void @extract_v8i1_v64i1_48(<64 x i1>* %x, <8 x i1>* %y) {
 ; LMULMAX2-LABEL: extract_v8i1_v64i1_48:
 ; LMULMAX2:       # %bb.0:
 ; LMULMAX2-NEXT:    addi a0, a0, 4
 ; LMULMAX2-NEXT:    addi a2, zero, 32
 ; LMULMAX2-NEXT:    vsetvli zero, a2, e8, m2, ta, mu
-; LMULMAX2-NEXT:    vle1.v v25, (a0)
+; LMULMAX2-NEXT:    vlm.v v25, (a0)
 ; LMULMAX2-NEXT:    vsetivli zero, 1, e8, mf4, ta, mu
 ; LMULMAX2-NEXT:    vslidedown.vi v25, v25, 2
 ; LMULMAX2-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX2-NEXT:    vse1.v v25, (a1)
+; LMULMAX2-NEXT:    vsm.v v25, (a1)
 ; LMULMAX2-NEXT:    ret
 ;
 ; LMULMAX1-LABEL: extract_v8i1_v64i1_48:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    addi a0, a0, 6
 ; LMULMAX1-NEXT:    vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-NEXT:    vle1.v v25, (a0)
+; LMULMAX1-NEXT:    vlm.v v25, (a0)
 ; LMULMAX1-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX1-NEXT:    vse1.v v25, (a1)
+; LMULMAX1-NEXT:    vsm.v v25, (a1)
 ; LMULMAX1-NEXT:    ret
   %a = load <64 x i1>, <64 x i1>* %x
   %c = call <8 x i1> @llvm.experimental.vector.extract.v8i1.v64i1(<64 x i1> %a, i64 48)
   store <8 x i1> %c, <8 x i1>* %y
   ret void
 }
 
 define void @extract_v8i1_nxv2i1_0(<vscale x 2 x i1> %x, <8 x i1>* %y) {
 ; CHECK-LABEL: extract_v8i1_nxv2i1_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT:    vse1.v v0, (a0)
+; CHECK-NEXT:    vsm.v v0, (a0)
 ; CHECK-NEXT:    ret
   %c = call <8 x i1> @llvm.experimental.vector.extract.v8i1.nxv2i1(<vscale x 2 x i1> %x, i64 0)
   store <8 x i1> %c, <8 x i1>* %y
   ret void
 }
 
 define void @extract_v8i1_nxv64i1_0(<vscale x 64 x i1> %x, <8 x i1>* %y) {
 ; CHECK-LABEL: extract_v8i1_nxv64i1_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT:    vse1.v v0, (a0)
+; CHECK-NEXT:    vsm.v v0, (a0)
 ; CHECK-NEXT:    ret
   %c = call <8 x i1> @llvm.experimental.vector.extract.v8i1.nxv64i1(<vscale x 64 x i1> %x, i64 0)
   store <8 x i1> %c, <8 x i1>* %y
   ret void
 }
 
 define void @extract_v8i1_nxv64i1_8(<vscale x 64 x i1> %x, <8 x i1>* %y) {
 ; CHECK-LABEL: extract_v8i1_nxv64i1_8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, mu
 ; CHECK-NEXT:    vslidedown.vi v25, v0, 1
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT:    vse1.v v25, (a0)
+; CHECK-NEXT:    vsm.v v25, (a0)
 ; CHECK-NEXT:    ret
   %c = call <8 x i1> @llvm.experimental.vector.extract.v8i1.nxv64i1(<vscale x 64 x i1> %x, i64 8)
   store <8 x i1> %c, <8 x i1>* %y
   ret void
 }
 
 define void @extract_v8i1_nxv64i1_48(<vscale x 64 x i1> %x, <8 x i1>* %y) {
 ; CHECK-LABEL: extract_v8i1_nxv64i1_48:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, mu
 ; CHECK-NEXT:    vslidedown.vi v25, v0, 6
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT:    vse1.v v25, (a0)
+; CHECK-NEXT:    vsm.v v25, (a0)
 ; CHECK-NEXT:    ret
   %c = call <8 x i1> @llvm.experimental.vector.extract.v8i1.nxv64i1(<vscale x 64 x i1> %x, i64 48)
   store <8 x i1> %c, <8 x i1>* %y
   ret void
 }
 
 
 define void @extract_v2i1_v64i1_0(<64 x i1>* %x, <2 x i1>* %y) {
 ; LMULMAX2-LABEL: extract_v2i1_v64i1_0:
 ; LMULMAX2:       # %bb.0:
 ; LMULMAX2-NEXT:    addi a2, zero, 32
 ; LMULMAX2-NEXT:    vsetvli zero, a2, e8, m2, ta, mu
-; LMULMAX2-NEXT:    vle1.v v0, (a0)
+; LMULMAX2-NEXT:    vlm.v v0, (a0)
 ; LMULMAX2-NEXT:    vsetivli zero, 2, e8, mf8, ta, mu
 ; LMULMAX2-NEXT:    vmv.v.i v25, 0
 ; LMULMAX2-NEXT:    vmerge.vim v25, v25, 1, v0
 ; LMULMAX2-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; LMULMAX2-NEXT:    vmv.v.i v26, 0
 ; LMULMAX2-NEXT:    vsetivli zero, 2, e8, mf2, tu, mu
 ; LMULMAX2-NEXT:    vslideup.vi v26, v25, 0
 ; LMULMAX2-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; LMULMAX2-NEXT:    vmsne.vi v25, v26, 0
-; LMULMAX2-NEXT:    vse1.v v25, (a1)
+; LMULMAX2-NEXT:    vsm.v v25, (a1)
 ; LMULMAX2-NEXT:    ret
 ;
 ; LMULMAX1-LABEL: extract_v2i1_v64i1_0:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-NEXT:    vle1.v v0, (a0)
+; LMULMAX1-NEXT:    vlm.v v0, (a0)
 ; LMULMAX1-NEXT:    vsetivli zero, 2, e8, mf8, ta, mu
 ; LMULMAX1-NEXT:    vmv.v.i v25, 0
 ; LMULMAX1-NEXT:    vmerge.vim v25, v25, 1, v0
 ; LMULMAX1-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; LMULMAX1-NEXT:    vmv.v.i v26, 0
 ; LMULMAX1-NEXT:    vsetivli zero, 2, e8, mf2, tu, mu
 ; LMULMAX1-NEXT:    vslideup.vi v26, v25, 0
 ; LMULMAX1-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; LMULMAX1-NEXT:    vmsne.vi v25, v26, 0
-; LMULMAX1-NEXT:    vse1.v v25, (a1)
+; LMULMAX1-NEXT:    vsm.v v25, (a1)
 ; LMULMAX1-NEXT:    ret
   %a = load <64 x i1>, <64 x i1>* %x
   %c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.v64i1(<64 x i1> %a, i64 0)
   store <2 x i1> %c, <2 x i1>* %y
   ret void
 }
 
 define void @extract_v2i1_v64i1_2(<64 x i1>* %x, <2 x i1>* %y) {
 ; LMULMAX2-LABEL: extract_v2i1_v64i1_2:
 ; LMULMAX2:       # %bb.0:
 ; LMULMAX2-NEXT:    addi a2, zero, 32
 ; LMULMAX2-NEXT:    vsetvli zero, a2, e8, m2, ta, mu
-; LMULMAX2-NEXT:    vle1.v v0, (a0)
+; LMULMAX2-NEXT:    vlm.v v0, (a0)
 ; LMULMAX2-NEXT:    vmv.v.i v26, 0
 ; LMULMAX2-NEXT:    vmerge.vim v26, v26, 1, v0
 ; LMULMAX2-NEXT:    vsetivli zero, 2, e8, m2, ta, mu
 ; LMULMAX2-NEXT:    vslidedown.vi v26, v26, 2
 ; LMULMAX2-NEXT:    vsetivli zero, 2, e8, mf8, ta, mu
 ; LMULMAX2-NEXT:    vmsne.vi v0, v26, 0
 ; LMULMAX2-NEXT:    vmv.v.i v25, 0
 ; LMULMAX2-NEXT:    vmerge.vim v25, v25, 1, v0
 ; LMULMAX2-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; LMULMAX2-NEXT:    vmv.v.i v26, 0
 ; LMULMAX2-NEXT:    vsetivli zero, 2, e8, mf2, tu, mu
 ; LMULMAX2-NEXT:    vslideup.vi v26, v25, 0
 ; LMULMAX2-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; LMULMAX2-NEXT:    vmsne.vi v25, v26, 0
-; LMULMAX2-NEXT:    vse1.v v25, (a1)
+; LMULMAX2-NEXT:    vsm.v v25, (a1)
 ; LMULMAX2-NEXT:    ret
 ;
 ; LMULMAX1-LABEL: extract_v2i1_v64i1_2:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-NEXT:    vle1.v v0, (a0)
+; LMULMAX1-NEXT:    vlm.v v0, (a0)
 ; LMULMAX1-NEXT:    vmv.v.i v25, 0
 ; LMULMAX1-NEXT:    vmerge.vim v25, v25, 1, v0
 ; LMULMAX1-NEXT:    vsetivli zero, 2, e8, m1, ta, mu
 ; LMULMAX1-NEXT:    vslidedown.vi v25, v25, 2
 ; LMULMAX1-NEXT:    vsetivli zero, 2, e8, mf8, ta, mu
 ; LMULMAX1-NEXT:    vmsne.vi v0, v25, 0
 ; LMULMAX1-NEXT:    vmv.v.i v25, 0
 ; LMULMAX1-NEXT:    vmerge.vim v25, v25, 1, v0
 ; LMULMAX1-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; LMULMAX1-NEXT:    vmv.v.i v26, 0
 ; LMULMAX1-NEXT:    vsetivli zero, 2, e8, mf2, tu, mu
 ; LMULMAX1-NEXT:    vslideup.vi v26, v25, 0
 ; LMULMAX1-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; LMULMAX1-NEXT:    vmsne.vi v25, v26, 0
-; LMULMAX1-NEXT:    vse1.v v25, (a1)
+; LMULMAX1-NEXT:    vsm.v v25, (a1)
 ; LMULMAX1-NEXT:    ret
   %a = load <64 x i1>, <64 x i1>* %x
   %c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.v64i1(<64 x i1> %a, i64 2)
   store <2 x i1> %c, <2 x i1>* %y
   ret void
 }
 
 define void @extract_v2i1_v64i1_42(<64 x i1>* %x, <2 x i1>* %y) {
 ; LMULMAX2-LABEL: extract_v2i1_v64i1_42:
 ; LMULMAX2:       # %bb.0:
 ; LMULMAX2-NEXT:    addi a0, a0, 4
 ; LMULMAX2-NEXT:    addi a2, zero, 32
 ; LMULMAX2-NEXT:    vsetvli zero, a2, e8, m2, ta, mu
-; LMULMAX2-NEXT:    vle1.v v0, (a0)
+; LMULMAX2-NEXT:    vlm.v v0, (a0)
 ; LMULMAX2-NEXT:    vmv.v.i v26, 0
 ; LMULMAX2-NEXT:    vmerge.vim v26, v26, 1, v0
 ; LMULMAX2-NEXT:    vsetivli zero, 2, e8, m2, ta, mu
 ; LMULMAX2-NEXT:    vslidedown.vi v26, v26, 10
 ; LMULMAX2-NEXT:    vsetivli zero, 2, e8, mf8, ta, mu
 ; LMULMAX2-NEXT:    vmsne.vi v0, v26, 0
 ; LMULMAX2-NEXT:    vmv.v.i v25, 0
 ; LMULMAX2-NEXT:    vmerge.vim v25, v25, 1, v0
 ; LMULMAX2-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; LMULMAX2-NEXT:    vmv.v.i v26, 0
 ; LMULMAX2-NEXT:    vsetivli zero, 2, e8, mf2, tu, mu
 ; LMULMAX2-NEXT:    vslideup.vi v26, v25, 0
 ; LMULMAX2-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; LMULMAX2-NEXT:    vmsne.vi v25, v26, 0
-; LMULMAX2-NEXT:    vse1.v v25, (a1)
+; LMULMAX2-NEXT:    vsm.v v25, (a1)
 ; LMULMAX2-NEXT:    ret
 ;
 ; LMULMAX1-LABEL: extract_v2i1_v64i1_42:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    addi a0, a0, 4
 ; LMULMAX1-NEXT:    vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-NEXT:    vle1.v v0, (a0)
+; LMULMAX1-NEXT:    vlm.v v0, (a0)
 ; LMULMAX1-NEXT:    vmv.v.i v25, 0
 ; LMULMAX1-NEXT:    vmerge.vim v25, v25, 1, v0
 ; LMULMAX1-NEXT:    vsetivli zero, 2, e8, m1, ta, mu
 ; LMULMAX1-NEXT:    vslidedown.vi v25, v25, 10
 ; LMULMAX1-NEXT:    vsetivli zero, 2, e8, mf8, ta, mu
 ; LMULMAX1-NEXT:    vmsne.vi v0, v25, 0
 ; LMULMAX1-NEXT:    vmv.v.i v25, 0
 ; LMULMAX1-NEXT:    vmerge.vim v25, v25, 1, v0
 ; LMULMAX1-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; LMULMAX1-NEXT:    vmv.v.i v26, 0
 ; LMULMAX1-NEXT:    vsetivli zero, 2, e8, mf2, tu, mu
 ; LMULMAX1-NEXT:    vslideup.vi v26, v25, 0
 ; LMULMAX1-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; LMULMAX1-NEXT:    vmsne.vi v25, v26, 0
-; LMULMAX1-NEXT:    vse1.v v25, (a1)
+; LMULMAX1-NEXT:    vsm.v v25, (a1)
 ; LMULMAX1-NEXT:    ret
   %a = load <64 x i1>, <64 x i1>* %x
   %c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.v64i1(<64 x i1> %a, i64 42)
   store <2 x i1> %c, <2 x i1>* %y
   ret void
 }
 
 define void @extract_v2i1_nxv2i1_0(<vscale x 2 x i1> %x, <2 x i1>* %y) {
 ; CHECK-LABEL: extract_v2i1_nxv2i1_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli zero, 2, e8, mf2, tu, mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
-; CHECK-NEXT:    vse1.v v25, (a0)
+; CHECK-NEXT:    vsm.v v25, (a0)
 ; CHECK-NEXT:    ret
   %c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv2i1(<vscale x 2 x i1> %x, i64 0)
   store <2 x i1> %c, <2 x i1>* %y
   ret void
 }
 
 define void @extract_v2i1_nxv2i1_2(<vscale x 2 x i1> %x, <2 x i1>* %y) {
 ; CHECK-LABEL: extract_v2i1_nxv2i1_2:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
 ; CHECK-NEXT:    vsetivli zero, 2, e8, mf4, ta, mu
 ; CHECK-NEXT:    vslidedown.vi v25, v25, 2
 ; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, mu
 ; CHECK-NEXT:    vmsne.vi v0, v25, 0
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli zero, 2, e8, mf2, tu, mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
-; CHECK-NEXT:    vse1.v v25, (a0)
+; CHECK-NEXT:    vsm.v v25, (a0)
 ; CHECK-NEXT:    ret
   %c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv2i1(<vscale x 2 x i1> %x, i64 2)
   store <2 x i1> %c, <2 x i1>* %y
   ret void
 }
 
 define void @extract_v2i1_nxv64i1_0(<vscale x 64 x i1> %x, <2 x i1>* %y) {
 ; CHECK-LABEL: extract_v2i1_nxv64i1_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli zero, 2, e8, mf2, tu, mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
-; CHECK-NEXT:    vse1.v v25, (a0)
+; CHECK-NEXT:    vsm.v v25, (a0)
 ; CHECK-NEXT:    ret
   %c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv64i1(<vscale x 64 x i1> %x, i64 0)
   store <2 x i1> %c, <2 x i1>* %y
   ret void
 }
 
 define void @extract_v2i1_nxv64i1_2(<vscale x 64 x i1> %x, <2 x i1>* %y) {
 ; CHECK-LABEL: extract_v2i1_nxv64i1_2:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e8, m8, ta, mu
 ; CHECK-NEXT:    vmv.v.i v8, 0
 ; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
 ; CHECK-NEXT:    vsetivli zero, 2, e8, m8, ta, mu
 ; CHECK-NEXT:    vslidedown.vi v8, v8, 2
 ; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, mu
 ; CHECK-NEXT:    vmsne.vi v0, v8, 0
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli zero, 2, e8, mf2, tu, mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
-; CHECK-NEXT:    vse1.v v25, (a0)
+; CHECK-NEXT:    vsm.v v25, (a0)
 ; CHECK-NEXT:    ret
   %c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv64i1(<vscale x 64 x i1> %x, i64 2)
   store <2 x i1> %c, <2 x i1>* %y
   ret void
 }
 
 define void @extract_v2i1_nxv64i1_42(<vscale x 64 x i1> %x, <2 x i1>* %y) {
 ; CHECK-LABEL: extract_v2i1_nxv64i1_42:

 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli zero, 2, e8, mf2, tu, mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
-; CHECK-NEXT:    vse1.v v25, (a0)
+; CHECK-NEXT:    vsm.v v25, (a0)
 ; CHECK-NEXT:    ret
   %c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv64i1(<vscale x 64 x i1> %x, i64 42)
   store <2 x i1> %c, <2 x i1>* %y
   ret void
 }
 
 define void @extract_v2i1_nxv32i1_26(<vscale x 32 x i1> %x, <2 x i1>* %y) {
 ; CHECK-LABEL: extract_v2i1_nxv32i1_26:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e8, m4, ta, mu
 ; CHECK-NEXT:    vmv.v.i v28, 0
 ; CHECK-NEXT:    vmerge.vim v28, v28, 1, v0
 ; CHECK-NEXT:    vsetivli zero, 2, e8, m4, ta, mu
 ; CHECK-NEXT:    vslidedown.vi v28, v28, 26
 ; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, mu
 ; CHECK-NEXT:    vmsne.vi v0, v28, 0
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli zero, 2, e8, mf2, tu, mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
-; CHECK-NEXT:    vse1.v v25, (a0)
+; CHECK-NEXT:    vsm.v v25, (a0)
 ; CHECK-NEXT:    ret
   %c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv32i1(<vscale x 32 x i1> %x, i64 26)
   store <2 x i1> %c, <2 x i1>* %y
   ret void
 }
 
 define void @extract_v8i1_nxv32i1_16(<vscale x 32 x i1> %x, <8 x i1>* %y) {
 ; CHECK-LABEL: extract_v8i1_nxv32i1_16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 1, e8, mf2, ta, mu
 ; CHECK-NEXT:    vslidedown.vi v25, v0, 2
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT:    vse1.v v25, (a0)
+; CHECK-NEXT:    vsm.v v25, (a0)
 ; CHECK-NEXT:    ret
   %c = call <8 x i1> @llvm.experimental.vector.extract.v8i1.nxv32i1(<vscale x 32 x i1> %x, i64 16)
   store <8 x i1> %c, <8 x i1>* %y
   ret void
 }
 
 declare <2 x i1> @llvm.experimental.vector.extract.v2i1.v64i1(<64 x i1> %vec, i64 %idx)
 declare <8 x i1> @llvm.experimental.vector.extract.v8i1.v64i1(<64 x i1> %vec, i64 %idx)

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v,+experimental-zfh,+f,+d -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v,+experimental-zfh,+f,+d -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s
 
 define void @fcmp_oeq_vv_v8f16(<8 x half>* %x, <8 x half>* %y, <8 x i1>* %z) {
 ; CHECK-LABEL: fcmp_oeq_vv_v8f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vle16.v v26, (a1)
 ; CHECK-NEXT:    vmfeq.vv v25, v25, v26
-; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    vsm.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <8 x half>, <8 x half>* %x
   %b = load <8 x half>, <8 x half>* %y
   %c = fcmp oeq <8 x half> %a, %b
   store <8 x i1> %c, <8 x i1>* %z
   ret void
 }
 
 define void @fcmp_oeq_vv_v8f16_nonans(<8 x half>* %x, <8 x half>* %y, <8 x i1>* %z) {
 ; CHECK-LABEL: fcmp_oeq_vv_v8f16_nonans:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vle16.v v26, (a1)
 ; CHECK-NEXT:    vmfeq.vv v25, v25, v26
-; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    vsm.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <8 x half>, <8 x half>* %x
   %b = load <8 x half>, <8 x half>* %y
   %c = fcmp nnan oeq <8 x half> %a, %b
   store <8 x i1> %c, <8 x i1>* %z
   ret void
 }
 
 define void @fcmp_une_vv_v4f32(<4 x float>* %x, <4 x float>* %y, <4 x i1>* %z) {
 ; CHECK-LABEL: fcmp_une_vv_v4f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, mu
 ; CHECK-NEXT:    vle32.v v25, (a0)
 ; CHECK-NEXT:    vle32.v v26, (a1)
 ; CHECK-NEXT:    vmfne.vv v0, v25, v26
 ; CHECK-NEXT:    vsetvli zero, zero, e8, mf4, ta, mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli zero, 4, e8, mf2, tu, mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
-; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    vsm.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <4 x float>, <4 x float>* %x
   %b = load <4 x float>, <4 x float>* %y
   %c = fcmp une <4 x float> %a, %b
   store <4 x i1> %c, <4 x i1>* %z
   ret void
 }
 
 define void @fcmp_une_vv_v4f32_nonans(<4 x float>* %x, <4 x float>* %y, <4 x i1>* %z) {
 ; CHECK-LABEL: fcmp_une_vv_v4f32_nonans:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, mu
 ; CHECK-NEXT:    vle32.v v25, (a0)
 ; CHECK-NEXT:    vle32.v v26, (a1)
 ; CHECK-NEXT:    vmfne.vv v0, v25, v26
 ; CHECK-NEXT:    vsetvli zero, zero, e8, mf4, ta, mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli zero, 4, e8, mf2, tu, mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
-; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    vsm.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <4 x float>, <4 x float>* %x
   %b = load <4 x float>, <4 x float>* %y
   %c = fcmp nnan une <4 x float> %a, %b
   store <4 x i1> %c, <4 x i1>* %z
   ret void
 }
 
 define void @fcmp_ogt_vv_v2f64(<2 x double>* %x, <2 x double>* %y, <2 x i1>* %z) {
 ; CHECK-LABEL: fcmp_ogt_vv_v2f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, mu
 ; CHECK-NEXT:    vle64.v v25, (a0)
 ; CHECK-NEXT:    vle64.v v26, (a1)
 ; CHECK-NEXT:    vmflt.vv v0, v26, v25
 ; CHECK-NEXT:    vsetvli zero, zero, e8, mf8, ta, mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli zero, 2, e8, mf2, tu, mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
-; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    vsm.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <2 x double>, <2 x double>* %x
   %b = load <2 x double>, <2 x double>* %y
   %c = fcmp ogt <2 x double> %a, %b
   store <2 x i1> %c, <2 x i1>* %z
   ret void
 }
 
 define void @fcmp_ogt_vv_v2f64_nonans(<2 x double>* %x, <2 x double>* %y, <2 x i1>* %z) {
 ; CHECK-LABEL: fcmp_ogt_vv_v2f64_nonans:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, mu
 ; CHECK-NEXT:    vle64.v v25, (a0)
 ; CHECK-NEXT:    vle64.v v26, (a1)
 ; CHECK-NEXT:    vmflt.vv v0, v26, v25
 ; CHECK-NEXT:    vsetvli zero, zero, e8, mf8, ta, mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli zero, 2, e8, mf2, tu, mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
-; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    vsm.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <2 x double>, <2 x double>* %x
   %b = load <2 x double>, <2 x double>* %y
   %c = fcmp nnan ogt <2 x double> %a, %b
   store <2 x i1> %c, <2 x i1>* %z
   ret void
 }
 
 define void @fcmp_olt_vv_v16f16(<16 x half>* %x, <16 x half>* %y, <16 x i1>* %z) {
 ; CHECK-LABEL: fcmp_olt_vv_v16f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, mu
 ; CHECK-NEXT:    vle16.v v26, (a0)
 ; CHECK-NEXT:    vle16.v v28, (a1)
 ; CHECK-NEXT:    vmflt.vv v25, v26, v28
-; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    vsm.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <16 x half>, <16 x half>* %x
   %b = load <16 x half>, <16 x half>* %y
   %c = fcmp olt <16 x half> %a, %b
   store <16 x i1> %c, <16 x i1>* %z
   ret void
 }
 
 define void @fcmp_olt_vv_v16f16_nonans(<16 x half>* %x, <16 x half>* %y, <16 x i1>* %z) {
 ; CHECK-LABEL: fcmp_olt_vv_v16f16_nonans:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, mu
 ; CHECK-NEXT:    vle16.v v26, (a0)
 ; CHECK-NEXT:    vle16.v v28, (a1)
 ; CHECK-NEXT:    vmflt.vv v25, v26, v28
-; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    vsm.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <16 x half>, <16 x half>* %x
   %b = load <16 x half>, <16 x half>* %y
   %c = fcmp nnan olt <16 x half> %a, %b
   store <16 x i1> %c, <16 x i1>* %z
   ret void
 }
 
 define void @fcmp_oge_vv_v8f32(<8 x float>* %x, <8 x float>* %y, <8 x i1>* %z) {
 ; CHECK-LABEL: fcmp_oge_vv_v8f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, mu
 ; CHECK-NEXT:    vle32.v v26, (a0)
 ; CHECK-NEXT:    vle32.v v28, (a1)
 ; CHECK-NEXT:    vmfle.vv v25, v28, v26
-; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    vsm.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <8 x float>, <8 x float>* %x
   %b = load <8 x float>, <8 x float>* %y
   %c = fcmp oge <8 x float> %a, %b
   store <8 x i1> %c, <8 x i1>* %z
   ret void
 }
 
 define void @fcmp_oge_vv_v8f32_nonans(<8 x float>* %x, <8 x float>* %y, <8 x i1>* %z) {
 ; CHECK-LABEL: fcmp_oge_vv_v8f32_nonans:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, mu
 ; CHECK-NEXT:    vle32.v v26, (a0)
 ; CHECK-NEXT:    vle32.v v28, (a1)
 ; CHECK-NEXT:    vmfle.vv v25, v28, v26
-; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    vsm.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <8 x float>, <8 x float>* %x
   %b = load <8 x float>, <8 x float>* %y
   %c = fcmp nnan oge <8 x float> %a, %b
   store <8 x i1> %c, <8 x i1>* %z
   ret void
 }
 
 define void @fcmp_ole_vv_v4f64(<4 x double>* %x, <4 x double>* %y, <4 x i1>* %z) {
 ; CHECK-LABEL: fcmp_ole_vv_v4f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, mu
 ; CHECK-NEXT:    vle64.v v26, (a0)
 ; CHECK-NEXT:    vle64.v v28, (a1)
 ; CHECK-NEXT:    vmfle.vv v0, v26, v28
 ; CHECK-NEXT:    vsetvli zero, zero, e8, mf4, ta, mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli zero, 4, e8, mf2, tu, mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
-; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    vsm.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <4 x double>, <4 x double>* %x
   %b = load <4 x double>, <4 x double>* %y
   %c = fcmp ole <4 x double> %a, %b
   store <4 x i1> %c, <4 x i1>* %z
   ret void
 }
 
 define void @fcmp_ole_vv_v4f64_nonans(<4 x double>* %x, <4 x double>* %y, <4 x i1>* %z) {
 ; CHECK-LABEL: fcmp_ole_vv_v4f64_nonans:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, mu
 ; CHECK-NEXT:    vle64.v v26, (a0)
 ; CHECK-NEXT:    vle64.v v28, (a1)
 ; CHECK-NEXT:    vmfle.vv v0, v26, v28
 ; CHECK-NEXT:    vsetvli zero, zero, e8, mf4, ta, mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli zero, 4, e8, mf2, tu, mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
-; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    vsm.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <4 x double>, <4 x double>* %x
   %b = load <4 x double>, <4 x double>* %y
   %c = fcmp nnan ole <4 x double> %a, %b
   store <4 x i1> %c, <4 x i1>* %z
   ret void
 }
 
 define void @fcmp_ule_vv_v32f16(<32 x half>* %x, <32 x half>* %y, <32 x i1>* %z) {
 ; CHECK-LABEL: fcmp_ule_vv_v32f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a3, zero, 32
 ; CHECK-NEXT:    vsetvli zero, a3, e16, m4, ta, mu
 ; CHECK-NEXT:    vle16.v v28, (a0)
 ; CHECK-NEXT:    vle16.v v8, (a1)
 ; CHECK-NEXT:    vmflt.vv v25, v8, v28
 ; CHECK-NEXT:    vmnand.mm v25, v25, v25
-; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    vsm.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <32 x half>, <32 x half>* %x
   %b = load <32 x half>, <32 x half>* %y
   %c = fcmp ule <32 x half> %a, %b
   store <32 x i1> %c, <32 x i1>* %z
   ret void
 }
 
 define void @fcmp_ule_vv_v32f16_nonans(<32 x half>* %x, <32 x half>* %y, <32 x i1>* %z) {
 ; CHECK-LABEL: fcmp_ule_vv_v32f16_nonans:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a3, zero, 32
 ; CHECK-NEXT:    vsetvli zero, a3, e16, m4, ta, mu
 ; CHECK-NEXT:    vle16.v v28, (a0)
 ; CHECK-NEXT:    vle16.v v8, (a1)
 ; CHECK-NEXT:    vmfle.vv v25, v28, v8
-; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    vsm.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <32 x half>, <32 x half>* %x
   %b = load <32 x half>, <32 x half>* %y
   %c = fcmp nnan ule <32 x half> %a, %b
   store <32 x i1> %c, <32 x i1>* %z
   ret void
 }
 
 define void @fcmp_uge_vv_v16f32(<16 x float>* %x, <16 x float>* %y, <16 x i1>* %z) {
 ; CHECK-LABEL: fcmp_uge_vv_v16f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 16, e32, m4, ta, mu
 ; CHECK-NEXT:    vle32.v v28, (a0)
 ; CHECK-NEXT:    vle32.v v8, (a1)
 ; CHECK-NEXT:    vmflt.vv v25, v28, v8
 ; CHECK-NEXT:    vmnand.mm v25, v25, v25
-; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    vsm.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <16 x float>, <16 x float>* %x
   %b = load <16 x float>, <16 x float>* %y
   %c = fcmp uge <16 x float> %a, %b
   store <16 x i1> %c, <16 x i1>* %z
   ret void
 }
 
 define void @fcmp_uge_vv_v16f32_nonans(<16 x float>* %x, <16 x float>* %y, <16 x i1>* %z) {
 ; CHECK-LABEL: fcmp_uge_vv_v16f32_nonans:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 16, e32, m4, ta, mu
 ; CHECK-NEXT:    vle32.v v28, (a0)
 ; CHECK-NEXT:    vle32.v v8, (a1)
 ; CHECK-NEXT:    vmfle.vv v25, v8, v28
-; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    vsm.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <16 x float>, <16 x float>* %x
   %b = load <16 x float>, <16 x float>* %y
   %c = fcmp nnan uge <16 x float> %a, %b
   store <16 x i1> %c, <16 x i1>* %z
   ret void
 }
 
 define void @fcmp_ult_vv_v8f64(<8 x double>* %x, <8 x double>* %y, <8 x i1>* %z) {
 ; CHECK-LABEL: fcmp_ult_vv_v8f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e64, m4, ta, mu
 ; CHECK-NEXT:    vle64.v v28, (a0)
 ; CHECK-NEXT:    vle64.v v8, (a1)
 ; CHECK-NEXT:    vmfle.vv v25, v8, v28
 ; CHECK-NEXT:    vmnand.mm v25, v25, v25
-; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    vsm.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <8 x double>, <8 x double>* %x
   %b = load <8 x double>, <8 x double>* %y
   %c = fcmp ult <8 x double> %a, %b
   store <8 x i1> %c, <8 x i1>* %z
   ret void
 }
 
 define void @fcmp_ult_vv_v8f64_nonans(<8 x double>* %x, <8 x double>* %y, <8 x i1>* %z) {
 ; CHECK-LABEL: fcmp_ult_vv_v8f64_nonans:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e64, m4, ta, mu
 ; CHECK-NEXT:    vle64.v v28, (a0)
 ; CHECK-NEXT:    vle64.v v8, (a1)
 ; CHECK-NEXT:    vmflt.vv v25, v28, v8
-; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    vsm.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <8 x double>, <8 x double>* %x
   %b = load <8 x double>, <8 x double>* %y
   %c = fcmp nnan ult <8 x double> %a, %b
   store <8 x i1> %c, <8 x i1>* %z
   ret void
 }
 
 define void @fcmp_ugt_vv_v64f16(<64 x half>* %x, <64 x half>* %y, <64 x i1>* %z) {
 ; CHECK-LABEL: fcmp_ugt_vv_v64f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a3, zero, 64
 ; CHECK-NEXT:    vsetvli zero, a3, e16, m8, ta, mu
 ; CHECK-NEXT:    vle16.v v8, (a0)
 ; CHECK-NEXT:    vle16.v v16, (a1)
 ; CHECK-NEXT:    vmfle.vv v25, v8, v16
 ; CHECK-NEXT:    vmnand.mm v25, v25, v25
-; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    vsm.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <64 x half>, <64 x half>* %x
   %b = load <64 x half>, <64 x half>* %y
   %c = fcmp ugt <64 x half> %a, %b
   store <64 x i1> %c, <64 x i1>* %z
   ret void
 }
 
 define void @fcmp_ugt_vv_v64f16_nonans(<64 x half>* %x, <64 x half>* %y, <64 x i1>* %z) {
 ; CHECK-LABEL: fcmp_ugt_vv_v64f16_nonans:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a3, zero, 64
 ; CHECK-NEXT:    vsetvli zero, a3, e16, m8, ta, mu
 ; CHECK-NEXT:    vle16.v v8, (a0)
 ; CHECK-NEXT:    vle16.v v16, (a1)
 ; CHECK-NEXT:    vmflt.vv v25, v16, v8
-; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    vsm.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <64 x half>, <64 x half>* %x
   %b = load <64 x half>, <64 x half>* %y
   %c = fcmp nnan ugt <64 x half> %a, %b
   store <64 x i1> %c, <64 x i1>* %z
   ret void
 }
 
 define void @fcmp_ueq_vv_v32f32(<32 x float>* %x, <32 x float>* %y, <32 x i1>* %z) {
 ; CHECK-LABEL: fcmp_ueq_vv_v32f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a3, zero, 32
 ; CHECK-NEXT:    vsetvli zero, a3, e32, m8, ta, mu
 ; CHECK-NEXT:    vle32.v v8, (a0)
 ; CHECK-NEXT:    vle32.v v16, (a1)
 ; CHECK-NEXT:    vmflt.vv v25, v8, v16
 ; CHECK-NEXT:    vmflt.vv v26, v16, v8
 ; CHECK-NEXT:    vmnor.mm v25, v26, v25
-; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    vsm.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <32 x float>, <32 x float>* %x
   %b = load <32 x float>, <32 x float>* %y
   %c = fcmp ueq <32 x float> %a, %b
   store <32 x i1> %c, <32 x i1>* %z
   ret void
 }
 
 define void @fcmp_ueq_vv_v32f32_nonans(<32 x float>* %x, <32 x float>* %y, <32 x i1>* %z) {
 ; CHECK-LABEL: fcmp_ueq_vv_v32f32_nonans:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a3, zero, 32
 ; CHECK-NEXT:    vsetvli zero, a3, e32, m8, ta, mu
 ; CHECK-NEXT:    vle32.v v8, (a0)
 ; CHECK-NEXT:    vle32.v v16, (a1)
 ; CHECK-NEXT:    vmfeq.vv v25, v8, v16
-; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    vsm.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <32 x float>, <32 x float>* %x
   %b = load <32 x float>, <32 x float>* %y
   %c = fcmp nnan ueq <32 x float> %a, %b
   store <32 x i1> %c, <32 x i1>* %z
   ret void
 }
 
 define void @fcmp_one_vv_v8f64(<16 x double>* %x, <16 x double>* %y, <16 x i1>* %z) {
 ; CHECK-LABEL: fcmp_one_vv_v8f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; CHECK-NEXT:    vle64.v v8, (a0)
 ; CHECK-NEXT:    vle64.v v16, (a1)
 ; CHECK-NEXT:    vmflt.vv v25, v8, v16
 ; CHECK-NEXT:    vmflt.vv v26, v16, v8
 ; CHECK-NEXT:    vmor.mm v25, v26, v25
-; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    vsm.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <16 x double>, <16 x double>* %x
   %b = load <16 x double>, <16 x double>* %y
   %c = fcmp one <16 x double> %a, %b
   store <16 x i1> %c, <16 x i1>* %z
   ret void
 }
 
 define void @fcmp_one_vv_v8f64_nonans(<16 x double>* %x, <16 x double>* %y, <16 x i1>* %z) {
 ; CHECK-LABEL: fcmp_one_vv_v8f64_nonans:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; CHECK-NEXT:    vle64.v v8, (a0)
 ; CHECK-NEXT:    vle64.v v16, (a1)
 ; CHECK-NEXT:    vmfne.vv v25, v8, v16
-; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    vsm.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <16 x double>, <16 x double>* %x
   %b = load <16 x double>, <16 x double>* %y
   %c = fcmp nnan one <16 x double> %a, %b
   store <16 x i1> %c, <16 x i1>* %z
   ret void
 }
 

 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli zero, 4, e8, mf2, tu, mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
-; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    vsm.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <4 x half>, <4 x half>* %x
   %b = load <4 x half>, <4 x half>* %y
   %c = fcmp ord <4 x half> %a, %b
   store <4 x i1> %c, <4 x i1>* %z
   ret void
 }
 

 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli zero, 2, e8, mf2, tu, mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
-; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    vsm.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <2 x half>, <2 x half>* %x
   %b = load <2 x half>, <2 x half>* %y
   %c = fcmp uno <2 x half> %a, %b
   store <2 x i1> %c, <2 x i1>* %z
   ret void
 }
 
 define void @fcmp_oeq_vf_v8f16(<8 x half>* %x, half %y, <8 x i1>* %z) {
 ; CHECK-LABEL: fcmp_oeq_vf_v8f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vmfeq.vf v25, v25, fa0
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <8 x half>, <8 x half>* %x
   %b = insertelement <8 x half> undef, half %y, i32 0
   %c = shufflevector <8 x half> %b, <8 x half> undef, <8 x i32> zeroinitializer
   %d = fcmp oeq <8 x half> %a, %c
   store <8 x i1> %d, <8 x i1>* %z
   ret void
 }
 
 define void @fcmp_oeq_vf_v8f16_nonans(<8 x half>* %x, half %y, <8 x i1>* %z) {
 ; CHECK-LABEL: fcmp_oeq_vf_v8f16_nonans:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vmfeq.vf v25, v25, fa0
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <8 x half>, <8 x half>* %x
   %b = insertelement <8 x half> undef, half %y, i32 0
   %c = shufflevector <8 x half> %b, <8 x half> undef, <8 x i32> zeroinitializer
   %d = fcmp nnan oeq <8 x half> %a, %c
   store <8 x i1> %d, <8 x i1>* %z
   ret void
 }
 
 define void @fcmp_une_vf_v4f32(<4 x float>* %x, float %y, <4 x i1>* %z) {
 ; CHECK-LABEL: fcmp_une_vf_v4f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, mu
 ; CHECK-NEXT:    vle32.v v25, (a0)
 ; CHECK-NEXT:    vmfne.vf v0, v25, fa0
 ; CHECK-NEXT:    vsetvli zero, zero, e8, mf4, ta, mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli zero, 4, e8, mf2, tu, mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <4 x float>, <4 x float>* %x
   %b = insertelement <4 x float> undef, float %y, i32 0
   %c = shufflevector <4 x float> %b, <4 x float> undef, <4 x i32> zeroinitializer
   %d = fcmp une <4 x float> %a, %c
   store <4 x i1> %d, <4 x i1>* %z
   ret void
 }
 
 define void @fcmp_une_vf_v4f32_nonans(<4 x float>* %x, float %y, <4 x i1>* %z) {
 ; CHECK-LABEL: fcmp_une_vf_v4f32_nonans:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, mu
 ; CHECK-NEXT:    vle32.v v25, (a0)
 ; CHECK-NEXT:    vmfne.vf v0, v25, fa0
 ; CHECK-NEXT:    vsetvli zero, zero, e8, mf4, ta, mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli zero, 4, e8, mf2, tu, mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <4 x float>, <4 x float>* %x
   %b = insertelement <4 x float> undef, float %y, i32 0
   %c = shufflevector <4 x float> %b, <4 x float> undef, <4 x i32> zeroinitializer
   %d = fcmp nnan une <4 x float> %a, %c
   store <4 x i1> %d, <4 x i1>* %z
   ret void
 }
 
 define void @fcmp_ogt_vf_v2f64(<2 x double>* %x, double %y, <2 x i1>* %z) {
 ; CHECK-LABEL: fcmp_ogt_vf_v2f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, mu
 ; CHECK-NEXT:    vle64.v v25, (a0)
 ; CHECK-NEXT:    vmfgt.vf v0, v25, fa0
 ; CHECK-NEXT:    vsetvli zero, zero, e8, mf8, ta, mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli zero, 2, e8, mf2, tu, mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <2 x double>, <2 x double>* %x
   %b = insertelement <2 x double> undef, double %y, i32 0
   %c = shufflevector <2 x double> %b, <2 x double> undef, <2 x i32> zeroinitializer
   %d = fcmp ogt <2 x double> %a, %c
   store <2 x i1> %d, <2 x i1>* %z
   ret void
 }
 
 define void @fcmp_ogt_vf_v2f64_nonans(<2 x double>* %x, double %y, <2 x i1>* %z) {
 ; CHECK-LABEL: fcmp_ogt_vf_v2f64_nonans:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, mu
 ; CHECK-NEXT:    vle64.v v25, (a0)
 ; CHECK-NEXT:    vmfgt.vf v0, v25, fa0
 ; CHECK-NEXT:    vsetvli zero, zero, e8, mf8, ta, mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli zero, 2, e8, mf2, tu, mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <2 x double>, <2 x double>* %x
   %b = insertelement <2 x double> undef, double %y, i32 0
   %c = shufflevector <2 x double> %b, <2 x double> undef, <2 x i32> zeroinitializer
   %d = fcmp nnan ogt <2 x double> %a, %c
   store <2 x i1> %d, <2 x i1>* %z
   ret void
 }
 
 define void @fcmp_olt_vf_v16f16(<16 x half>* %x, half %y, <16 x i1>* %z) {
 ; CHECK-LABEL: fcmp_olt_vf_v16f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, mu
 ; CHECK-NEXT:    vle16.v v26, (a0)
 ; CHECK-NEXT:    vmflt.vf v25, v26, fa0
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <16 x half>, <16 x half>* %x
   %b = insertelement <16 x half> undef, half %y, i32 0
   %c = shufflevector <16 x half> %b, <16 x half> undef, <16 x i32> zeroinitializer
   %d = fcmp olt <16 x half> %a, %c
   store <16 x i1> %d, <16 x i1>* %z
   ret void
 }
 
 define void @fcmp_olt_vf_v16f16_nonans(<16 x half>* %x, half %y, <16 x i1>* %z) {
 ; CHECK-LABEL: fcmp_olt_vf_v16f16_nonans:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, mu
 ; CHECK-NEXT:    vle16.v v26, (a0)
 ; CHECK-NEXT:    vmflt.vf v25, v26, fa0
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <16 x half>, <16 x half>* %x
   %b = insertelement <16 x half> undef, half %y, i32 0
   %c = shufflevector <16 x half> %b, <16 x half> undef, <16 x i32> zeroinitializer
   %d = fcmp nnan olt <16 x half> %a, %c
   store <16 x i1> %d, <16 x i1>* %z
   ret void
 }
 
 define void @fcmp_oge_vf_v8f32(<8 x float>* %x, float %y, <8 x i1>* %z) {
 ; CHECK-LABEL: fcmp_oge_vf_v8f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, mu
 ; CHECK-NEXT:    vle32.v v26, (a0)
 ; CHECK-NEXT:    vmfge.vf v25, v26, fa0
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <8 x float>, <8 x float>* %x
   %b = insertelement <8 x float> undef, float %y, i32 0
   %c = shufflevector <8 x float> %b, <8 x float> undef, <8 x i32> zeroinitializer
   %d = fcmp oge <8 x float> %a, %c
   store <8 x i1> %d, <8 x i1>* %z
   ret void
 }
 
 define void @fcmp_oge_vf_v8f32_nonans(<8 x float>* %x, float %y, <8 x i1>* %z) {
 ; CHECK-LABEL: fcmp_oge_vf_v8f32_nonans:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, mu
 ; CHECK-NEXT:    vle32.v v26, (a0)
 ; CHECK-NEXT:    vmfge.vf v25, v26, fa0
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <8 x float>, <8 x float>* %x
   %b = insertelement <8 x float> undef, float %y, i32 0
   %c = shufflevector <8 x float> %b, <8 x float> undef, <8 x i32> zeroinitializer
   %d = fcmp nnan oge <8 x float> %a, %c
   store <8 x i1> %d, <8 x i1>* %z
   ret void
 }
 
 define void @fcmp_ole_vf_v4f64(<4 x double>* %x, double %y, <4 x i1>* %z) {
 ; CHECK-LABEL: fcmp_ole_vf_v4f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, mu
 ; CHECK-NEXT:    vle64.v v26, (a0)
 ; CHECK-NEXT:    vmfle.vf v0, v26, fa0
 ; CHECK-NEXT:    vsetvli zero, zero, e8, mf4, ta, mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli zero, 4, e8, mf2, tu, mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <4 x double>, <4 x double>* %x
   %b = insertelement <4 x double> undef, double %y, i32 0
   %c = shufflevector <4 x double> %b, <4 x double> undef, <4 x i32> zeroinitializer
   %d = fcmp ole <4 x double> %a, %c
   store <4 x i1> %d, <4 x i1>* %z
   ret void
 }
 
 define void @fcmp_ole_vf_v4f64_nonans(<4 x double>* %x, double %y, <4 x i1>* %z) {
 ; CHECK-LABEL: fcmp_ole_vf_v4f64_nonans:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, mu
 ; CHECK-NEXT:    vle64.v v26, (a0)
 ; CHECK-NEXT:    vmfle.vf v0, v26, fa0
 ; CHECK-NEXT:    vsetvli zero, zero, e8, mf4, ta, mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli zero, 4, e8, mf2, tu, mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <4 x double>, <4 x double>* %x
   %b = insertelement <4 x double> undef, double %y, i32 0
   %c = shufflevector <4 x double> %b, <4 x double> undef, <4 x i32> zeroinitializer
   %d = fcmp nnan ole <4 x double> %a, %c
   store <4 x i1> %d, <4 x i1>* %z
   ret void
 }
 
 define void @fcmp_ule_vf_v32f16(<32 x half>* %x, half %y, <32 x i1>* %z) {
 ; CHECK-LABEL: fcmp_ule_vf_v32f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a2, zero, 32
 ; CHECK-NEXT:    vsetvli zero, a2, e16, m4, ta, mu
 ; CHECK-NEXT:    vle16.v v28, (a0)
 ; CHECK-NEXT:    vmfgt.vf v25, v28, fa0
 ; CHECK-NEXT:    vmnand.mm v25, v25, v25
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <32 x half>, <32 x half>* %x
   %b = insertelement <32 x half> undef, half %y, i32 0
   %c = shufflevector <32 x half> %b, <32 x half> undef, <32 x i32> zeroinitializer
   %d = fcmp ule <32 x half> %a, %c
   store <32 x i1> %d, <32 x i1>* %z
   ret void
 }
 
 define void @fcmp_ule_vf_v32f16_nonans(<32 x half>* %x, half %y, <32 x i1>* %z) {
 ; CHECK-LABEL: fcmp_ule_vf_v32f16_nonans:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a2, zero, 32
 ; CHECK-NEXT:    vsetvli zero, a2, e16, m4, ta, mu
 ; CHECK-NEXT:    vle16.v v28, (a0)
 ; CHECK-NEXT:    vmfle.vf v25, v28, fa0
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <32 x half>, <32 x half>* %x
   %b = insertelement <32 x half> undef, half %y, i32 0
   %c = shufflevector <32 x half> %b, <32 x half> undef, <32 x i32> zeroinitializer
   %d = fcmp nnan ule <32 x half> %a, %c
   store <32 x i1> %d, <32 x i1>* %z
   ret void
 }
 
 define void @fcmp_uge_vf_v16f32(<16 x float>* %x, float %y, <16 x i1>* %z) {
 ; CHECK-LABEL: fcmp_uge_vf_v16f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 16, e32, m4, ta, mu
 ; CHECK-NEXT:    vle32.v v28, (a0)
 ; CHECK-NEXT:    vmflt.vf v25, v28, fa0
 ; CHECK-NEXT:    vmnand.mm v25, v25, v25
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <16 x float>, <16 x float>* %x
   %b = insertelement <16 x float> undef, float %y, i32 0
   %c = shufflevector <16 x float> %b, <16 x float> undef, <16 x i32> zeroinitializer
   %d = fcmp uge <16 x float> %a, %c
   store <16 x i1> %d, <16 x i1>* %z
   ret void
 }
 
 define void @fcmp_uge_vf_v16f32_nonans(<16 x float>* %x, float %y, <16 x i1>* %z) {
 ; CHECK-LABEL: fcmp_uge_vf_v16f32_nonans:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 16, e32, m4, ta, mu
 ; CHECK-NEXT:    vle32.v v28, (a0)
 ; CHECK-NEXT:    vmfge.vf v25, v28, fa0
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <16 x float>, <16 x float>* %x
   %b = insertelement <16 x float> undef, float %y, i32 0
   %c = shufflevector <16 x float> %b, <16 x float> undef, <16 x i32> zeroinitializer
   %d = fcmp nnan uge <16 x float> %a, %c
   store <16 x i1> %d, <16 x i1>* %z
   ret void
 }
 
 define void @fcmp_ult_vf_v8f64(<8 x double>* %x, double %y, <8 x i1>* %z) {
 ; CHECK-LABEL: fcmp_ult_vf_v8f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e64, m4, ta, mu
 ; CHECK-NEXT:    vle64.v v28, (a0)
 ; CHECK-NEXT:    vmfge.vf v25, v28, fa0
 ; CHECK-NEXT:    vmnand.mm v25, v25, v25
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <8 x double>, <8 x double>* %x
   %b = insertelement <8 x double> undef, double %y, i32 0
   %c = shufflevector <8 x double> %b, <8 x double> undef, <8 x i32> zeroinitializer
   %d = fcmp ult <8 x double> %a, %c
   store <8 x i1> %d, <8 x i1>* %z
   ret void
 }
 
 define void @fcmp_ult_vf_v8f64_nonans(<8 x double>* %x, double %y, <8 x i1>* %z) {
 ; CHECK-LABEL: fcmp_ult_vf_v8f64_nonans:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e64, m4, ta, mu
 ; CHECK-NEXT:    vle64.v v28, (a0)
 ; CHECK-NEXT:    vmflt.vf v25, v28, fa0
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <8 x double>, <8 x double>* %x
   %b = insertelement <8 x double> undef, double %y, i32 0
   %c = shufflevector <8 x double> %b, <8 x double> undef, <8 x i32> zeroinitializer
   %d = fcmp nnan ult <8 x double> %a, %c
   store <8 x i1> %d, <8 x i1>* %z
   ret void
 }
 
 define void @fcmp_ugt_vf_v64f16(<64 x half>* %x, half %y, <64 x i1>* %z) {
 ; CHECK-LABEL: fcmp_ugt_vf_v64f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a2, zero, 64
 ; CHECK-NEXT:    vsetvli zero, a2, e16, m8, ta, mu
 ; CHECK-NEXT:    vle16.v v8, (a0)
 ; CHECK-NEXT:    vmfle.vf v25, v8, fa0
 ; CHECK-NEXT:    vmnand.mm v25, v25, v25
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <64 x half>, <64 x half>* %x
   %b = insertelement <64 x half> undef, half %y, i32 0
   %c = shufflevector <64 x half> %b, <64 x half> undef, <64 x i32> zeroinitializer
   %d = fcmp ugt <64 x half> %a, %c
   store <64 x i1> %d, <64 x i1>* %z
   ret void
 }
 
 define void @fcmp_ugt_vf_v64f16_nonans(<64 x half>* %x, half %y, <64 x i1>* %z) {
 ; CHECK-LABEL: fcmp_ugt_vf_v64f16_nonans:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a2, zero, 64
 ; CHECK-NEXT:    vsetvli zero, a2, e16, m8, ta, mu
 ; CHECK-NEXT:    vle16.v v8, (a0)
 ; CHECK-NEXT:    vmfgt.vf v25, v8, fa0
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <64 x half>, <64 x half>* %x
   %b = insertelement <64 x half> undef, half %y, i32 0
   %c = shufflevector <64 x half> %b, <64 x half> undef, <64 x i32> zeroinitializer
   %d = fcmp nnan ugt <64 x half> %a, %c
   store <64 x i1> %d, <64 x i1>* %z
   ret void
 }
 
 define void @fcmp_ueq_vf_v32f32(<32 x float>* %x, float %y, <32 x i1>* %z) {
 ; CHECK-LABEL: fcmp_ueq_vf_v32f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a2, zero, 32
 ; CHECK-NEXT:    vsetvli zero, a2, e32, m8, ta, mu
 ; CHECK-NEXT:    vle32.v v8, (a0)
 ; CHECK-NEXT:    vmflt.vf v25, v8, fa0
 ; CHECK-NEXT:    vmfgt.vf v26, v8, fa0
 ; CHECK-NEXT:    vmnor.mm v25, v26, v25
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <32 x float>, <32 x float>* %x
   %b = insertelement <32 x float> undef, float %y, i32 0
   %c = shufflevector <32 x float> %b, <32 x float> undef, <32 x i32> zeroinitializer
   %d = fcmp ueq <32 x float> %a, %c
   store <32 x i1> %d, <32 x i1>* %z
   ret void
 }
 
 define void @fcmp_ueq_vf_v32f32_nonans(<32 x float>* %x, float %y, <32 x i1>* %z) {
 ; CHECK-LABEL: fcmp_ueq_vf_v32f32_nonans:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a2, zero, 32
 ; CHECK-NEXT:    vsetvli zero, a2, e32, m8, ta, mu
 ; CHECK-NEXT:    vle32.v v8, (a0)
 ; CHECK-NEXT:    vmfeq.vf v25, v8, fa0
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <32 x float>, <32 x float>* %x
   %b = insertelement <32 x float> undef, float %y, i32 0
   %c = shufflevector <32 x float> %b, <32 x float> undef, <32 x i32> zeroinitializer
   %d = fcmp nnan ueq <32 x float> %a, %c
   store <32 x i1> %d, <32 x i1>* %z
   ret void
 }
 
 define void @fcmp_one_vf_v8f64(<16 x double>* %x, double %y, <16 x i1>* %z) {
 ; CHECK-LABEL: fcmp_one_vf_v8f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; CHECK-NEXT:    vle64.v v8, (a0)
 ; CHECK-NEXT:    vmflt.vf v25, v8, fa0
 ; CHECK-NEXT:    vmfgt.vf v26, v8, fa0
 ; CHECK-NEXT:    vmor.mm v25, v26, v25
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <16 x double>, <16 x double>* %x
   %b = insertelement <16 x double> undef, double %y, i32 0
   %c = shufflevector <16 x double> %b, <16 x double> undef, <16 x i32> zeroinitializer
   %d = fcmp one <16 x double> %a, %c
   store <16 x i1> %d, <16 x i1>* %z
   ret void
 }
 
 define void @fcmp_one_vf_v8f64_nonans(<16 x double>* %x, double %y, <16 x i1>* %z) {
 ; CHECK-LABEL: fcmp_one_vf_v8f64_nonans:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; CHECK-NEXT:    vle64.v v8, (a0)
 ; CHECK-NEXT:    vmfne.vf v25, v8, fa0
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <16 x double>, <16 x double>* %x
   %b = insertelement <16 x double> undef, double %y, i32 0
   %c = shufflevector <16 x double> %b, <16 x double> undef, <16 x i32> zeroinitializer
   %d = fcmp nnan one <16 x double> %a, %c
   store <16 x i1> %d, <16 x i1>* %z
   ret void
 }

 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli zero, 4, e8, mf2, tu, mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <4 x half>, <4 x half>* %x
   %b = insertelement <4 x half> undef, half %y, i32 0
   %c = shufflevector <4 x half> %b, <4 x half> undef, <4 x i32> zeroinitializer
   %d = fcmp ord <4 x half> %a, %c
   store <4 x i1> %d, <4 x i1>* %z
   ret void
 }

 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli zero, 2, e8, mf2, tu, mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <2 x half>, <2 x half>* %x
   %b = insertelement <2 x half> undef, half %y, i32 0
   %c = shufflevector <2 x half> %b, <2 x half> undef, <2 x i32> zeroinitializer
   %d = fcmp uno <2 x half> %a, %c
   store <2 x i1> %d, <2 x i1>* %z
   ret void
 }
 
 define void @fcmp_oeq_fv_v8f16(<8 x half>* %x, half %y, <8 x i1>* %z) {
 ; CHECK-LABEL: fcmp_oeq_fv_v8f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vmfeq.vf v25, v25, fa0
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <8 x half>, <8 x half>* %x
   %b = insertelement <8 x half> undef, half %y, i32 0
   %c = shufflevector <8 x half> %b, <8 x half> undef, <8 x i32> zeroinitializer
   %d = fcmp oeq <8 x half> %c, %a
   store <8 x i1> %d, <8 x i1>* %z
   ret void
 }
 
 define void @fcmp_oeq_fv_v8f16_nonans(<8 x half>* %x, half %y, <8 x i1>* %z) {
 ; CHECK-LABEL: fcmp_oeq_fv_v8f16_nonans:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vmfeq.vf v25, v25, fa0
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <8 x half>, <8 x half>* %x
   %b = insertelement <8 x half> undef, half %y, i32 0
   %c = shufflevector <8 x half> %b, <8 x half> undef, <8 x i32> zeroinitializer
   %d = fcmp nnan oeq <8 x half> %c, %a
   store <8 x i1> %d, <8 x i1>* %z
   ret void
 }
 
 define void @fcmp_une_fv_v4f32(<4 x float>* %x, float %y, <4 x i1>* %z) {
 ; CHECK-LABEL: fcmp_une_fv_v4f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, mu
 ; CHECK-NEXT:    vle32.v v25, (a0)
 ; CHECK-NEXT:    vmfne.vf v0, v25, fa0
 ; CHECK-NEXT:    vsetvli zero, zero, e8, mf4, ta, mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli zero, 4, e8, mf2, tu, mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <4 x float>, <4 x float>* %x
   %b = insertelement <4 x float> undef, float %y, i32 0
   %c = shufflevector <4 x float> %b, <4 x float> undef, <4 x i32> zeroinitializer
   %d = fcmp une <4 x float> %c, %a
   store <4 x i1> %d, <4 x i1>* %z
   ret void
 }
 
 define void @fcmp_une_fv_v4f32_nonans(<4 x float>* %x, float %y, <4 x i1>* %z) {
 ; CHECK-LABEL: fcmp_une_fv_v4f32_nonans:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, mu
 ; CHECK-NEXT:    vle32.v v25, (a0)
 ; CHECK-NEXT:    vmfne.vf v0, v25, fa0
 ; CHECK-NEXT:    vsetvli zero, zero, e8, mf4, ta, mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli zero, 4, e8, mf2, tu, mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <4 x float>, <4 x float>* %x
   %b = insertelement <4 x float> undef, float %y, i32 0
   %c = shufflevector <4 x float> %b, <4 x float> undef, <4 x i32> zeroinitializer
   %d = fcmp nnan une <4 x float> %c, %a
   store <4 x i1> %d, <4 x i1>* %z
   ret void
 }
 
 define void @fcmp_ogt_fv_v2f64(<2 x double>* %x, double %y, <2 x i1>* %z) {
 ; CHECK-LABEL: fcmp_ogt_fv_v2f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, mu
 ; CHECK-NEXT:    vle64.v v25, (a0)
 ; CHECK-NEXT:    vmflt.vf v0, v25, fa0
 ; CHECK-NEXT:    vsetvli zero, zero, e8, mf8, ta, mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli zero, 2, e8, mf2, tu, mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <2 x double>, <2 x double>* %x
   %b = insertelement <2 x double> undef, double %y, i32 0
   %c = shufflevector <2 x double> %b, <2 x double> undef, <2 x i32> zeroinitializer
   %d = fcmp ogt <2 x double> %c, %a
   store <2 x i1> %d, <2 x i1>* %z
   ret void
 }
 
 define void @fcmp_ogt_fv_v2f64_nonans(<2 x double>* %x, double %y, <2 x i1>* %z) {
 ; CHECK-LABEL: fcmp_ogt_fv_v2f64_nonans:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, mu
 ; CHECK-NEXT:    vle64.v v25, (a0)
 ; CHECK-NEXT:    vmflt.vf v0, v25, fa0
 ; CHECK-NEXT:    vsetvli zero, zero, e8, mf8, ta, mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli zero, 2, e8, mf2, tu, mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <2 x double>, <2 x double>* %x
   %b = insertelement <2 x double> undef, double %y, i32 0
   %c = shufflevector <2 x double> %b, <2 x double> undef, <2 x i32> zeroinitializer
   %d = fcmp nnan ogt <2 x double> %c, %a
   store <2 x i1> %d, <2 x i1>* %z
   ret void
 }
 
 define void @fcmp_olt_fv_v16f16(<16 x half>* %x, half %y, <16 x i1>* %z) {
 ; CHECK-LABEL: fcmp_olt_fv_v16f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, mu
 ; CHECK-NEXT:    vle16.v v26, (a0)
 ; CHECK-NEXT:    vmfgt.vf v25, v26, fa0
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <16 x half>, <16 x half>* %x
   %b = insertelement <16 x half> undef, half %y, i32 0
   %c = shufflevector <16 x half> %b, <16 x half> undef, <16 x i32> zeroinitializer
   %d = fcmp olt <16 x half> %c, %a
   store <16 x i1> %d, <16 x i1>* %z
   ret void
 }
 
 define void @fcmp_olt_fv_v16f16_nonans(<16 x half>* %x, half %y, <16 x i1>* %z) {
 ; CHECK-LABEL: fcmp_olt_fv_v16f16_nonans:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, mu
 ; CHECK-NEXT:    vle16.v v26, (a0)
 ; CHECK-NEXT:    vmfgt.vf v25, v26, fa0
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <16 x half>, <16 x half>* %x
   %b = insertelement <16 x half> undef, half %y, i32 0
   %c = shufflevector <16 x half> %b, <16 x half> undef, <16 x i32> zeroinitializer
   %d = fcmp nnan olt <16 x half> %c, %a
   store <16 x i1> %d, <16 x i1>* %z
   ret void
 }
 
 define void @fcmp_oge_fv_v8f32(<8 x float>* %x, float %y, <8 x i1>* %z) {
 ; CHECK-LABEL: fcmp_oge_fv_v8f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, mu
 ; CHECK-NEXT:    vle32.v v26, (a0)
 ; CHECK-NEXT:    vmfle.vf v25, v26, fa0
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <8 x float>, <8 x float>* %x
   %b = insertelement <8 x float> undef, float %y, i32 0
   %c = shufflevector <8 x float> %b, <8 x float> undef, <8 x i32> zeroinitializer
   %d = fcmp oge <8 x float> %c, %a
   store <8 x i1> %d, <8 x i1>* %z
   ret void
 }
 
 define void @fcmp_oge_fv_v8f32_nonans(<8 x float>* %x, float %y, <8 x i1>* %z) {
 ; CHECK-LABEL: fcmp_oge_fv_v8f32_nonans:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, mu
 ; CHECK-NEXT:    vle32.v v26, (a0)
 ; CHECK-NEXT:    vmfle.vf v25, v26, fa0
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <8 x float>, <8 x float>* %x
   %b = insertelement <8 x float> undef, float %y, i32 0
   %c = shufflevector <8 x float> %b, <8 x float> undef, <8 x i32> zeroinitializer
   %d = fcmp nnan oge <8 x float> %c, %a
   store <8 x i1> %d, <8 x i1>* %z
   ret void
 }
 
 define void @fcmp_ole_fv_v4f64(<4 x double>* %x, double %y, <4 x i1>* %z) {
 ; CHECK-LABEL: fcmp_ole_fv_v4f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, mu
 ; CHECK-NEXT:    vle64.v v26, (a0)
 ; CHECK-NEXT:    vmfge.vf v0, v26, fa0
 ; CHECK-NEXT:    vsetvli zero, zero, e8, mf4, ta, mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli zero, 4, e8, mf2, tu, mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <4 x double>, <4 x double>* %x
   %b = insertelement <4 x double> undef, double %y, i32 0
   %c = shufflevector <4 x double> %b, <4 x double> undef, <4 x i32> zeroinitializer
   %d = fcmp ole <4 x double> %c, %a
   store <4 x i1> %d, <4 x i1>* %z
   ret void
 }
 
 define void @fcmp_ole_fv_v4f64_nonans(<4 x double>* %x, double %y, <4 x i1>* %z) {
 ; CHECK-LABEL: fcmp_ole_fv_v4f64_nonans:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, mu
 ; CHECK-NEXT:    vle64.v v26, (a0)
 ; CHECK-NEXT:    vmfge.vf v0, v26, fa0
 ; CHECK-NEXT:    vsetvli zero, zero, e8, mf4, ta, mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli zero, 4, e8, mf2, tu, mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <4 x double>, <4 x double>* %x
   %b = insertelement <4 x double> undef, double %y, i32 0
   %c = shufflevector <4 x double> %b, <4 x double> undef, <4 x i32> zeroinitializer
   %d = fcmp nnan ole <4 x double> %c, %a
   store <4 x i1> %d, <4 x i1>* %z
   ret void
 }
 
 define void @fcmp_ule_fv_v32f16(<32 x half>* %x, half %y, <32 x i1>* %z) {
 ; CHECK-LABEL: fcmp_ule_fv_v32f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a2, zero, 32
 ; CHECK-NEXT:    vsetvli zero, a2, e16, m4, ta, mu
 ; CHECK-NEXT:    vle16.v v28, (a0)
 ; CHECK-NEXT:    vmflt.vf v25, v28, fa0
 ; CHECK-NEXT:    vmnand.mm v25, v25, v25
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <32 x half>, <32 x half>* %x
   %b = insertelement <32 x half> undef, half %y, i32 0
   %c = shufflevector <32 x half> %b, <32 x half> undef, <32 x i32> zeroinitializer
   %d = fcmp ule <32 x half> %c, %a
   store <32 x i1> %d, <32 x i1>* %z
   ret void
 }
 
 define void @fcmp_ule_fv_v32f16_nonans(<32 x half>* %x, half %y, <32 x i1>* %z) {
 ; CHECK-LABEL: fcmp_ule_fv_v32f16_nonans:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a2, zero, 32
 ; CHECK-NEXT:    vsetvli zero, a2, e16, m4, ta, mu
 ; CHECK-NEXT:    vle16.v v28, (a0)
 ; CHECK-NEXT:    vmfge.vf v25, v28, fa0
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <32 x half>, <32 x half>* %x
   %b = insertelement <32 x half> undef, half %y, i32 0
   %c = shufflevector <32 x half> %b, <32 x half> undef, <32 x i32> zeroinitializer
   %d = fcmp nnan ule <32 x half> %c, %a
   store <32 x i1> %d, <32 x i1>* %z
   ret void
 }
 
 define void @fcmp_uge_fv_v16f32(<16 x float>* %x, float %y, <16 x i1>* %z) {
 ; CHECK-LABEL: fcmp_uge_fv_v16f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 16, e32, m4, ta, mu
 ; CHECK-NEXT:    vle32.v v28, (a0)
 ; CHECK-NEXT:    vmfgt.vf v25, v28, fa0
 ; CHECK-NEXT:    vmnand.mm v25, v25, v25
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <16 x float>, <16 x float>* %x
   %b = insertelement <16 x float> undef, float %y, i32 0
   %c = shufflevector <16 x float> %b, <16 x float> undef, <16 x i32> zeroinitializer
   %d = fcmp uge <16 x float> %c, %a
   store <16 x i1> %d, <16 x i1>* %z
   ret void
 }
 
 define void @fcmp_uge_fv_v16f32_nonans(<16 x float>* %x, float %y, <16 x i1>* %z) {
 ; CHECK-LABEL: fcmp_uge_fv_v16f32_nonans:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 16, e32, m4, ta, mu
 ; CHECK-NEXT:    vle32.v v28, (a0)
 ; CHECK-NEXT:    vmfle.vf v25, v28, fa0
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <16 x float>, <16 x float>* %x
   %b = insertelement <16 x float> undef, float %y, i32 0
   %c = shufflevector <16 x float> %b, <16 x float> undef, <16 x i32> zeroinitializer
   %d = fcmp nnan uge <16 x float> %c, %a
   store <16 x i1> %d, <16 x i1>* %z
   ret void
 }
 
 define void @fcmp_ult_fv_v8f64(<8 x double>* %x, double %y, <8 x i1>* %z) {
 ; CHECK-LABEL: fcmp_ult_fv_v8f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e64, m4, ta, mu
 ; CHECK-NEXT:    vle64.v v28, (a0)
 ; CHECK-NEXT:    vmfle.vf v25, v28, fa0
 ; CHECK-NEXT:    vmnand.mm v25, v25, v25
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <8 x double>, <8 x double>* %x
   %b = insertelement <8 x double> undef, double %y, i32 0
   %c = shufflevector <8 x double> %b, <8 x double> undef, <8 x i32> zeroinitializer
   %d = fcmp ult <8 x double> %c, %a
   store <8 x i1> %d, <8 x i1>* %z
   ret void
 }
 
 define void @fcmp_ult_fv_v8f64_nonans(<8 x double>* %x, double %y, <8 x i1>* %z) {
 ; CHECK-LABEL: fcmp_ult_fv_v8f64_nonans:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e64, m4, ta, mu
 ; CHECK-NEXT:    vle64.v v28, (a0)
 ; CHECK-NEXT:    vmfgt.vf v25, v28, fa0
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <8 x double>, <8 x double>* %x
   %b = insertelement <8 x double> undef, double %y, i32 0
   %c = shufflevector <8 x double> %b, <8 x double> undef, <8 x i32> zeroinitializer
   %d = fcmp nnan ult <8 x double> %c, %a
   store <8 x i1> %d, <8 x i1>* %z
   ret void
 }
 
 define void @fcmp_ugt_fv_v64f16(<64 x half>* %x, half %y, <64 x i1>* %z) {
 ; CHECK-LABEL: fcmp_ugt_fv_v64f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a2, zero, 64
 ; CHECK-NEXT:    vsetvli zero, a2, e16, m8, ta, mu
 ; CHECK-NEXT:    vle16.v v8, (a0)
 ; CHECK-NEXT:    vmfge.vf v25, v8, fa0
 ; CHECK-NEXT:    vmnand.mm v25, v25, v25
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <64 x half>, <64 x half>* %x
   %b = insertelement <64 x half> undef, half %y, i32 0
   %c = shufflevector <64 x half> %b, <64 x half> undef, <64 x i32> zeroinitializer
   %d = fcmp ugt <64 x half> %c, %a
   store <64 x i1> %d, <64 x i1>* %z
   ret void
 }
 
 define void @fcmp_ugt_fv_v64f16_nonans(<64 x half>* %x, half %y, <64 x i1>* %z) {
 ; CHECK-LABEL: fcmp_ugt_fv_v64f16_nonans:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a2, zero, 64
 ; CHECK-NEXT:    vsetvli zero, a2, e16, m8, ta, mu
 ; CHECK-NEXT:    vle16.v v8, (a0)
 ; CHECK-NEXT:    vmflt.vf v25, v8, fa0
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <64 x half>, <64 x half>* %x
   %b = insertelement <64 x half> undef, half %y, i32 0
   %c = shufflevector <64 x half> %b, <64 x half> undef, <64 x i32> zeroinitializer
   %d = fcmp nnan ugt <64 x half> %c, %a
   store <64 x i1> %d, <64 x i1>* %z
   ret void
 }
 
 define void @fcmp_ueq_fv_v32f32(<32 x float>* %x, float %y, <32 x i1>* %z) {
 ; CHECK-LABEL: fcmp_ueq_fv_v32f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a2, zero, 32
 ; CHECK-NEXT:    vsetvli zero, a2, e32, m8, ta, mu
 ; CHECK-NEXT:    vle32.v v8, (a0)
 ; CHECK-NEXT:    vmfgt.vf v25, v8, fa0
 ; CHECK-NEXT:    vmflt.vf v26, v8, fa0
 ; CHECK-NEXT:    vmnor.mm v25, v26, v25
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <32 x float>, <32 x float>* %x
   %b = insertelement <32 x float> undef, float %y, i32 0
   %c = shufflevector <32 x float> %b, <32 x float> undef, <32 x i32> zeroinitializer
   %d = fcmp ueq <32 x float> %c, %a
   store <32 x i1> %d, <32 x i1>* %z
   ret void
 }
 
 define void @fcmp_ueq_fv_v32f32_nonans(<32 x float>* %x, float %y, <32 x i1>* %z) {
 ; CHECK-LABEL: fcmp_ueq_fv_v32f32_nonans:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a2, zero, 32
 ; CHECK-NEXT:    vsetvli zero, a2, e32, m8, ta, mu
 ; CHECK-NEXT:    vle32.v v8, (a0)
 ; CHECK-NEXT:    vmfeq.vf v25, v8, fa0
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <32 x float>, <32 x float>* %x
   %b = insertelement <32 x float> undef, float %y, i32 0
   %c = shufflevector <32 x float> %b, <32 x float> undef, <32 x i32> zeroinitializer
   %d = fcmp nnan ueq <32 x float> %c, %a
   store <32 x i1> %d, <32 x i1>* %z
   ret void
 }
 
 define void @fcmp_one_fv_v8f64(<16 x double>* %x, double %y, <16 x i1>* %z) {
 ; CHECK-LABEL: fcmp_one_fv_v8f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; CHECK-NEXT:    vle64.v v8, (a0)
 ; CHECK-NEXT:    vmfgt.vf v25, v8, fa0
 ; CHECK-NEXT:    vmflt.vf v26, v8, fa0
 ; CHECK-NEXT:    vmor.mm v25, v26, v25
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <16 x double>, <16 x double>* %x
   %b = insertelement <16 x double> undef, double %y, i32 0
   %c = shufflevector <16 x double> %b, <16 x double> undef, <16 x i32> zeroinitializer
   %d = fcmp one <16 x double> %c, %a
   store <16 x i1> %d, <16 x i1>* %z
   ret void
 }
 
 define void @fcmp_one_fv_v8f64_nonans(<16 x double>* %x, double %y, <16 x i1>* %z) {
 ; CHECK-LABEL: fcmp_one_fv_v8f64_nonans:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; CHECK-NEXT:    vle64.v v8, (a0)
 ; CHECK-NEXT:    vmfne.vf v25, v8, fa0
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <16 x double>, <16 x double>* %x
   %b = insertelement <16 x double> undef, double %y, i32 0
   %c = shufflevector <16 x double> %b, <16 x double> undef, <16 x i32> zeroinitializer
   %d = fcmp nnan one <16 x double> %c, %a
   store <16 x i1> %d, <16 x i1>* %z
   ret void
 }

 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli zero, 4, e8, mf2, tu, mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <4 x half>, <4 x half>* %x
   %b = insertelement <4 x half> undef, half %y, i32 0
   %c = shufflevector <4 x half> %b, <4 x half> undef, <4 x i32> zeroinitializer
   %d = fcmp ord <4 x half> %c, %a
   store <4 x i1> %d, <4 x i1>* %z
   ret void
 }

 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli zero, 2, e8, mf2, tu, mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <2 x half>, <2 x half>* %x
   %b = insertelement <2 x half> undef, half %y, i32 0
   %c = shufflevector <2 x half> %b, <2 x half> undef, <2 x i32> zeroinitializer
   %d = fcmp uno <2 x half> %c, %a
   store <2 x i1> %d, <2 x i1>* %z
   ret void
 }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll

; CHECK-NEXT:    ret
   ret void
 }
 
 define void @insert_v32i1_v8i1_0(<32 x i1>* %vp, <8 x i1>* %svp) {
 ; LMULMAX2-LABEL: insert_v32i1_v8i1_0:
 ; LMULMAX2:       # %bb.0:
 ; LMULMAX2-NEXT:    addi a2, zero, 32
 ; LMULMAX2-NEXT:    vsetvli zero, a2, e8, m2, ta, mu
-; LMULMAX2-NEXT:    vle1.v v25, (a0)
+; LMULMAX2-NEXT:    vlm.v v25, (a0)
 ; LMULMAX2-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX2-NEXT:    vle1.v v26, (a1)
+; LMULMAX2-NEXT:    vlm.v v26, (a1)
 ; LMULMAX2-NEXT:    vsetivli zero, 1, e8, mf4, tu, mu
 ; LMULMAX2-NEXT:    vslideup.vi v25, v26, 0
 ; LMULMAX2-NEXT:    vsetvli zero, a2, e8, m2, ta, mu
-; LMULMAX2-NEXT:    vse1.v v25, (a0)
+; LMULMAX2-NEXT:    vsm.v v25, (a0)
 ; LMULMAX2-NEXT:    ret
 ;
 ; LMULMAX1-LABEL: insert_v32i1_v8i1_0:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-NEXT:    vle1.v v25, (a0)
+; LMULMAX1-NEXT:    vlm.v v25, (a0)
 ; LMULMAX1-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX1-NEXT:    vle1.v v26, (a1)
+; LMULMAX1-NEXT:    vlm.v v26, (a1)
 ; LMULMAX1-NEXT:    vsetivli zero, 1, e8, mf8, tu, mu
 ; LMULMAX1-NEXT:    vslideup.vi v25, v26, 0
 ; LMULMAX1-NEXT:    vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-NEXT:    vse1.v v25, (a0)
+; LMULMAX1-NEXT:    vsm.v v25, (a0)
 ; LMULMAX1-NEXT:    ret
   %v = load <32 x i1>, <32 x i1>* %vp
   %sv = load <8 x i1>, <8 x i1>* %svp
   %c = call <32 x i1> @llvm.experimental.vector.insert.v8i1.v32i1(<32 x i1> %v, <8 x i1> %sv, i64 0)
   store <32 x i1> %c, <32 x i1>* %vp
   ret void
 }
 
 define void @insert_v32i1_v8i1_16(<32 x i1>* %vp, <8 x i1>* %svp) {
 ; LMULMAX2-LABEL: insert_v32i1_v8i1_16:
 ; LMULMAX2:       # %bb.0:
 ; LMULMAX2-NEXT:    addi a2, zero, 32
 ; LMULMAX2-NEXT:    vsetvli zero, a2, e8, m2, ta, mu
-; LMULMAX2-NEXT:    vle1.v v25, (a0)
+; LMULMAX2-NEXT:    vlm.v v25, (a0)
 ; LMULMAX2-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX2-NEXT:    vle1.v v26, (a1)
+; LMULMAX2-NEXT:    vlm.v v26, (a1)
 ; LMULMAX2-NEXT:    vsetivli zero, 3, e8, mf4, tu, mu
 ; LMULMAX2-NEXT:    vslideup.vi v25, v26, 2
 ; LMULMAX2-NEXT:    vsetvli zero, a2, e8, m2, ta, mu
-; LMULMAX2-NEXT:    vse1.v v25, (a0)
+; LMULMAX2-NEXT:    vsm.v v25, (a0)
 ; LMULMAX2-NEXT:    ret
 ;
 ; LMULMAX1-LABEL: insert_v32i1_v8i1_16:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    addi a0, a0, 2
 ; LMULMAX1-NEXT:    vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-NEXT:    vle1.v v25, (a0)
+; LMULMAX1-NEXT:    vlm.v v25, (a0)
 ; LMULMAX1-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX1-NEXT:    vle1.v v26, (a1)
+; LMULMAX1-NEXT:    vlm.v v26, (a1)
 ; LMULMAX1-NEXT:    vsetivli zero, 1, e8, mf8, tu, mu
 ; LMULMAX1-NEXT:    vslideup.vi v25, v26, 0
 ; LMULMAX1-NEXT:    vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-NEXT:    vse1.v v25, (a0)
+; LMULMAX1-NEXT:    vsm.v v25, (a0)
 ; LMULMAX1-NEXT:    ret
   %v = load <32 x i1>, <32 x i1>* %vp
   %sv = load <8 x i1>, <8 x i1>* %svp
   %c = call <32 x i1> @llvm.experimental.vector.insert.v8i1.v32i1(<32 x i1> %v, <8 x i1> %sv, i64 16)
   store <32 x i1> %c, <32 x i1>* %vp
   ret void
 }
 
 define void @insert_v8i1_v4i1_0(<8 x i1>* %vp, <4 x i1>* %svp) {
 ; CHECK-LABEL: insert_v8i1_v4i1_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT:    vle1.v v0, (a0)
+; CHECK-NEXT:    vlm.v v0, (a0)
 ; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT:    vle1.v v27, (a1)
+; CHECK-NEXT:    vlm.v v27, (a1)
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
 ; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vmv1r.v v0, v27
 ; CHECK-NEXT:    vmerge.vim v26, v26, 1, v0
 ; CHECK-NEXT:    vsetivli zero, 4, e8, mf2, tu, mu
 ; CHECK-NEXT:    vslideup.vi v25, v26, 0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmsne.vi v25, v25, 0
-; CHECK-NEXT:    vse1.v v25, (a0)
+; CHECK-NEXT:    vsm.v v25, (a0)
 ; CHECK-NEXT:    ret
   %v = load <8 x i1>, <8 x i1>* %vp
   %sv = load <4 x i1>, <4 x i1>* %svp
   %c = call <8 x i1> @llvm.experimental.vector.insert.v4i1.v8i1(<8 x i1> %v, <4 x i1> %sv, i64 0)
   store <8 x i1> %c, <8 x i1>* %vp
   ret void
 }
 
 define void @insert_v8i1_v4i1_4(<8 x i1>* %vp, <4 x i1>* %svp) {
 ; CHECK-LABEL: insert_v8i1_v4i1_4:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT:    vle1.v v0, (a0)
+; CHECK-NEXT:    vlm.v v0, (a0)
 ; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT:    vle1.v v27, (a1)
+; CHECK-NEXT:    vlm.v v27, (a1)
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
 ; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vmv1r.v v0, v27
 ; CHECK-NEXT:    vmerge.vim v26, v26, 1, v0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, tu, mu
 ; CHECK-NEXT:    vslideup.vi v25, v26, 4
 ; CHECK-NEXT:    vsetvli zero, zero, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmsne.vi v25, v25, 0
-; CHECK-NEXT:    vse1.v v25, (a0)
+; CHECK-NEXT:    vsm.v v25, (a0)
 ; CHECK-NEXT:    ret
   %v = load <8 x i1>, <8 x i1>* %vp
   %sv = load <4 x i1>, <4 x i1>* %svp
   %c = call <8 x i1> @llvm.experimental.vector.insert.v4i1.v8i1(<8 x i1> %v, <4 x i1> %sv, i64 4)
   store <8 x i1> %c, <8 x i1>* %vp
   ret void
 }
 
; CHECK-NEXT:    ret
   %c = call <vscale x 2 x i16> @llvm.experimental.vector.insert.v2i16.nxv2i16(<vscale x 2 x i16> %v, <2 x i16> %sv, i64 4)
   ret <vscale x 2 x i16> %c
 }
 
 define <vscale x 2 x i1> @insert_nxv2i1_v4i1_0(<vscale x 2 x i1> %v, <4 x i1>* %svp) {
 ; CHECK-LABEL: insert_nxv2i1_v4i1_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT:    vle1.v v27, (a0)
+; CHECK-NEXT:    vlm.v v27, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
 ; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vmv1r.v v0, v27
 ; CHECK-NEXT:    vmerge.vim v26, v26, 1, v0
 ; CHECK-NEXT:    vsetvli zero, zero, e8, mf4, tu, mu
 ; CHECK-NEXT:    vslideup.vi v25, v26, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, mu
 ; CHECK-NEXT:    vmsne.vi v0, v25, 0
 ; CHECK-NEXT:    ret
   %sv = load <4 x i1>, <4 x i1>* %svp
   %c = call <vscale x 2 x i1> @llvm.experimental.vector.insert.v4i1.nxv2i1(<vscale x 2 x i1> %v, <4 x i1> %sv, i64 0)
   ret <vscale x 2 x i1> %c
 }
 
 define <vscale x 8 x i1> @insert_nxv8i1_v4i1_0(<vscale x 8 x i1> %v, <8 x i1>* %svp) {
 ; CHECK-LABEL: insert_nxv8i1_v4i1_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT:    vle1.v v25, (a0)
+; CHECK-NEXT:    vlm.v v25, (a0)
 ; CHECK-NEXT:    vsetivli zero, 1, e8, mf8, tu, mu
 ; CHECK-NEXT:    vslideup.vi v0, v25, 0
 ; CHECK-NEXT:    ret
   %sv = load <8 x i1>, <8 x i1>* %svp
   %c = call <vscale x 8 x i1> @llvm.experimental.vector.insert.v8i1.nxv8i1(<vscale x 8 x i1> %v, <8 x i1> %sv, i64 0)
   ret <vscale x 8 x i1> %c
 }
 
 define <vscale x 8 x i1> @insert_nxv8i1_v8i1_16(<vscale x 8 x i1> %v, <8 x i1>* %svp) {
 ; CHECK-LABEL: insert_nxv8i1_v8i1_16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT:    vle1.v v25, (a0)
+; CHECK-NEXT:    vlm.v v25, (a0)
 ; CHECK-NEXT:    vsetivli zero, 3, e8, mf8, tu, mu
 ; CHECK-NEXT:    vslideup.vi v0, v25, 2
 ; CHECK-NEXT:    ret
   %sv = load <8 x i1>, <8 x i1>* %svp
   %c = call <vscale x 8 x i1> @llvm.experimental.vector.insert.v8i1.nxv8i1(<vscale x 8 x i1> %v, <8 x i1> %sv, i64 16)
   ret <vscale x 8 x i1> %c
 }
 

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll

 define void @setgt_vv_v64i8(<64 x i8>* %x, <64 x i8>* %y, <64 x i1>* %z) {
 ; CHECK-LABEL: setgt_vv_v64i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a3, zero, 64
 ; CHECK-NEXT:    vsetvli zero, a3, e8, m4, ta, mu
 ; CHECK-NEXT:    vle8.v v28, (a0)
 ; CHECK-NEXT:    vle8.v v8, (a1)
 ; CHECK-NEXT:    vmslt.vv v25, v8, v28
-; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    vsm.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <64 x i8>, <64 x i8>* %x
   %b = load <64 x i8>, <64 x i8>* %y
   %c = icmp sgt <64 x i8> %a, %b
   store <64 x i1> %c, <64 x i1>* %z
   ret void
 }
 
 define void @setlt_vv_v128i8(<128 x i8>* %x, <128 x i8>* %y, <128 x i1>* %z) {
 ; CHECK-LABEL: setlt_vv_v128i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a3, zero, 128
 ; CHECK-NEXT:    vsetvli zero, a3, e8, m8, ta, mu
 ; CHECK-NEXT:    vle8.v v8, (a0)
 ; CHECK-NEXT:    vle8.v v16, (a1)
 ; CHECK-NEXT:    vmslt.vv v25, v8, v16
-; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    vsm.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <128 x i8>, <128 x i8>* %x
   %b = load <128 x i8>, <128 x i8>* %y
   %c = icmp slt <128 x i8> %a, %b
   store <128 x i1> %c, <128 x i1>* %z
   ret void
 }
 
 define void @setge_vv_v8i8(<8 x i8>* %x, <8 x i8>* %y, <8 x i1>* %z) {
 ; CHECK-LABEL: setge_vv_v8i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vle8.v v26, (a1)
 ; CHECK-NEXT:    vmsle.vv v25, v26, v25
-; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    vsm.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <8 x i8>, <8 x i8>* %x
   %b = load <8 x i8>, <8 x i8>* %y
   %c = icmp sge <8 x i8> %a, %b
   store <8 x i1> %c, <8 x i1>* %z
   ret void
 }
 
 define void @setle_vv_v16i8(<16 x i8>* %x, <16 x i8>* %y, <16 x i1>* %z) {
 ; CHECK-LABEL: setle_vv_v16i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vle8.v v26, (a1)
 ; CHECK-NEXT:    vmsle.vv v25, v25, v26
-; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    vsm.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <16 x i8>, <16 x i8>* %x
   %b = load <16 x i8>, <16 x i8>* %y
   %c = icmp sle <16 x i8> %a, %b
   store <16 x i1> %c, <16 x i1>* %z
   ret void
 }
 
 define void @setugt_vv_v32i8(<32 x i8>* %x, <32 x i8>* %y, <32 x i1>* %z) {
 ; CHECK-LABEL: setugt_vv_v32i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a3, zero, 32
 ; CHECK-NEXT:    vsetvli zero, a3, e8, m2, ta, mu
 ; CHECK-NEXT:    vle8.v v26, (a0)
 ; CHECK-NEXT:    vle8.v v28, (a1)
 ; CHECK-NEXT:    vmsltu.vv v25, v28, v26
-; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    vsm.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <32 x i8>, <32 x i8>* %x
   %b = load <32 x i8>, <32 x i8>* %y
   %c = icmp ugt <32 x i8> %a, %b
   store <32 x i1> %c, <32 x i1>* %z
   ret void
 }
 
 define void @setult_vv_v64i8(<64 x i8>* %x, <64 x i8>* %y, <64 x i1>* %z) {
 ; CHECK-LABEL: setult_vv_v64i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a3, zero, 64
 ; CHECK-NEXT:    vsetvli zero, a3, e8, m4, ta, mu
 ; CHECK-NEXT:    vle8.v v28, (a0)
 ; CHECK-NEXT:    vle8.v v8, (a1)
 ; CHECK-NEXT:    vmsltu.vv v25, v28, v8
-; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    vsm.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <64 x i8>, <64 x i8>* %x
   %b = load <64 x i8>, <64 x i8>* %y
   %c = icmp ult <64 x i8> %a, %b
   store <64 x i1> %c, <64 x i1>* %z
   ret void
 }
 
 define void @setuge_vv_v128i8(<128 x i8>* %x, <128 x i8>* %y, <128 x i1>* %z) {
 ; CHECK-LABEL: setuge_vv_v128i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a3, zero, 128
 ; CHECK-NEXT:    vsetvli zero, a3, e8, m8, ta, mu
 ; CHECK-NEXT:    vle8.v v8, (a0)
 ; CHECK-NEXT:    vle8.v v16, (a1)
 ; CHECK-NEXT:    vmsleu.vv v25, v16, v8
-; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    vsm.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <128 x i8>, <128 x i8>* %x
   %b = load <128 x i8>, <128 x i8>* %y
   %c = icmp uge <128 x i8> %a, %b
   store <128 x i1> %c, <128 x i1>* %z
   ret void
 }
 
 define void @setule_vv_v8i8(<8 x i8>* %x, <8 x i8>* %y, <8 x i1>* %z) {
 ; CHECK-LABEL: setule_vv_v8i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vle8.v v26, (a1)
 ; CHECK-NEXT:    vmsleu.vv v25, v25, v26
-; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    vsm.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <8 x i8>, <8 x i8>* %x
   %b = load <8 x i8>, <8 x i8>* %y
   %c = icmp ule <8 x i8> %a, %b
   store <8 x i1> %c, <8 x i1>* %z
   ret void
 }
 
 define void @seteq_vx_v16i8(<16 x i8>* %x, i8 %y, <16 x i1>* %z) {
 ; CHECK-LABEL: seteq_vx_v16i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vmseq.vx v25, v25, a1
-; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    vsm.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <16 x i8>, <16 x i8>* %x
   %b = insertelement <16 x i8> undef, i8 %y, i32 0
   %c = shufflevector <16 x i8> %b, <16 x i8> undef, <16 x i32> zeroinitializer
   %d = icmp eq <16 x i8> %a, %c
   store <16 x i1> %d, <16 x i1>* %z
   ret void
 }
 
 define void @setne_vx_v32i8(<32 x i8>* %x, i8 %y, <32 x i1>* %z) {
 ; CHECK-LABEL: setne_vx_v32i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a3, zero, 32
 ; CHECK-NEXT:    vsetvli zero, a3, e8, m2, ta, mu
 ; CHECK-NEXT:    vle8.v v26, (a0)
 ; CHECK-NEXT:    vmsne.vx v25, v26, a1
-; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    vsm.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <32 x i8>, <32 x i8>* %x
   %b = insertelement <32 x i8> undef, i8 %y, i32 0
   %c = shufflevector <32 x i8> %b, <32 x i8> undef, <32 x i32> zeroinitializer
   %d = icmp ne <32 x i8> %a, %c
   store <32 x i1> %d, <32 x i1>* %z
   ret void
 }
 
 define void @setgt_vx_v64i8(<64 x i8>* %x, i8 %y, <64 x i1>* %z) {
 ; CHECK-LABEL: setgt_vx_v64i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a3, zero, 64
 ; CHECK-NEXT:    vsetvli zero, a3, e8, m4, ta, mu
 ; CHECK-NEXT:    vle8.v v28, (a0)
 ; CHECK-NEXT:    vmsgt.vx v25, v28, a1
-; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    vsm.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <64 x i8>, <64 x i8>* %x
   %b = insertelement <64 x i8> undef, i8 %y, i32 0
   %c = shufflevector <64 x i8> %b, <64 x i8> undef, <64 x i32> zeroinitializer
   %d = icmp sgt <64 x i8> %a, %c
   store <64 x i1> %d, <64 x i1>* %z
   ret void
 }
 
 define void @setlt_vx_v128i8(<128 x i8>* %x, i8 %y, <128 x i1>* %z) {
 ; CHECK-LABEL: setlt_vx_v128i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a3, zero, 128
 ; CHECK-NEXT:    vsetvli zero, a3, e8, m8, ta, mu
 ; CHECK-NEXT:    vle8.v v8, (a0)
 ; CHECK-NEXT:    vmslt.vx v25, v8, a1
-; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    vsm.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <128 x i8>, <128 x i8>* %x
   %b = insertelement <128 x i8> undef, i8 %y, i32 0
   %c = shufflevector <128 x i8> %b, <128 x i8> undef, <128 x i32> zeroinitializer
   %d = icmp slt <128 x i8> %a, %c
   store <128 x i1> %d, <128 x i1>* %z
   ret void
 }
 
 define void @setge_vx_v8i8(<8 x i8>* %x, i8 %y, <8 x i1>* %z) {
 ; CHECK-LABEL: setge_vx_v8i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vmv.v.x v26, a1
 ; CHECK-NEXT:    vmsle.vv v25, v26, v25
-; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    vsm.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <8 x i8>, <8 x i8>* %x
   %b = insertelement <8 x i8> undef, i8 %y, i32 0
   %c = shufflevector <8 x i8> %b, <8 x i8> undef, <8 x i32> zeroinitializer
   %d = icmp sge <8 x i8> %a, %c
   store <8 x i1> %d, <8 x i1>* %z
   ret void
 }
 
 define void @setle_vx_v16i8(<16 x i8>* %x, i8 %y, <16 x i1>* %z) {
 ; CHECK-LABEL: setle_vx_v16i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vmsle.vx v25, v25, a1
-; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    vsm.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <16 x i8>, <16 x i8>* %x
   %b = insertelement <16 x i8> undef, i8 %y, i32 0
   %c = shufflevector <16 x i8> %b, <16 x i8> undef, <16 x i32> zeroinitializer
   %d = icmp sle <16 x i8> %a, %c
   store <16 x i1> %d, <16 x i1>* %z
   ret void
 }
 
 define void @setugt_vx_v32i8(<32 x i8>* %x, i8 %y, <32 x i1>* %z) {
 ; CHECK-LABEL: setugt_vx_v32i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a3, zero, 32
 ; CHECK-NEXT:    vsetvli zero, a3, e8, m2, ta, mu
 ; CHECK-NEXT:    vle8.v v26, (a0)
 ; CHECK-NEXT:    vmsgtu.vx v25, v26, a1
-; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    vsm.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <32 x i8>, <32 x i8>* %x
   %b = insertelement <32 x i8> undef, i8 %y, i32 0
   %c = shufflevector <32 x i8> %b, <32 x i8> undef, <32 x i32> zeroinitializer
   %d = icmp ugt <32 x i8> %a, %c
   store <32 x i1> %d, <32 x i1>* %z
   ret void
 }
 
 define void @setult_vx_v64i8(<64 x i8>* %x, i8 %y, <64 x i1>* %z) {
 ; CHECK-LABEL: setult_vx_v64i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a3, zero, 64
 ; CHECK-NEXT:    vsetvli zero, a3, e8, m4, ta, mu
 ; CHECK-NEXT:    vle8.v v28, (a0)
 ; CHECK-NEXT:    vmsltu.vx v25, v28, a1
-; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    vsm.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <64 x i8>, <64 x i8>* %x
   %b = insertelement <64 x i8> undef, i8 %y, i32 0
   %c = shufflevector <64 x i8> %b, <64 x i8> undef, <64 x i32> zeroinitializer
   %d = icmp ult <64 x i8> %a, %c
   store <64 x i1> %d, <64 x i1>* %z
   ret void
 }
 
 define void @setuge_vx_v128i8(<128 x i8>* %x, i8 %y, <128 x i1>* %z) {
 ; CHECK-LABEL: setuge_vx_v128i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a3, zero, 128
 ; CHECK-NEXT:    vsetvli zero, a3, e8, m8, ta, mu
 ; CHECK-NEXT:    vle8.v v8, (a0)
 ; CHECK-NEXT:    vmv.v.x v16, a1
 ; CHECK-NEXT:    vmsleu.vv v25, v16, v8
-; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    vsm.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <128 x i8>, <128 x i8>* %x
   %b = insertelement <128 x i8> undef, i8 %y, i32 0
   %c = shufflevector <128 x i8> %b, <128 x i8> undef, <128 x i32> zeroinitializer
   %d = icmp uge <128 x i8> %a, %c
   store <128 x i1> %d, <128 x i1>* %z
   ret void
 }
 
 define void @setule_vx_v8i8(<8 x i8>* %x, i8 %y, <8 x i1>* %z) {
 ; CHECK-LABEL: setule_vx_v8i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vmsleu.vx v25, v25, a1
-; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    vsm.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <8 x i8>, <8 x i8>* %x
   %b = insertelement <8 x i8> undef, i8 %y, i32 0
   %c = shufflevector <8 x i8> %b, <8 x i8> undef, <8 x i32> zeroinitializer
   %d = icmp ule <8 x i8> %a, %c
   store <8 x i1> %d, <8 x i1>* %z
   ret void
 }
 
 define void @seteq_xv_v16i8(<16 x i8>* %x, i8 %y, <16 x i1>* %z) {
 ; CHECK-LABEL: seteq_xv_v16i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vmseq.vx v25, v25, a1
-; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    vsm.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <16 x i8>, <16 x i8>* %x
   %b = insertelement <16 x i8> undef, i8 %y, i32 0
   %c = shufflevector <16 x i8> %b, <16 x i8> undef, <16 x i32> zeroinitializer
   %d = icmp eq <16 x i8> %c, %a
   store <16 x i1> %d, <16 x i1>* %z
   ret void
 }
 
 define void @setne_xv_v32i8(<32 x i8>* %x, i8 %y, <32 x i1>* %z) {
 ; CHECK-LABEL: setne_xv_v32i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a3, zero, 32
 ; CHECK-NEXT:    vsetvli zero, a3, e8, m2, ta, mu
 ; CHECK-NEXT:    vle8.v v26, (a0)
 ; CHECK-NEXT:    vmsne.vx v25, v26, a1
-; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    vsm.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <32 x i8>, <32 x i8>* %x
   %b = insertelement <32 x i8> undef, i8 %y, i32 0
   %c = shufflevector <32 x i8> %b, <32 x i8> undef, <32 x i32> zeroinitializer
   %d = icmp ne <32 x i8> %c, %a
   store <32 x i1> %d, <32 x i1>* %z
   ret void
 }
 
 define void @setgt_xv_v64i8(<64 x i8>* %x, i8 %y, <64 x i1>* %z) {
 ; CHECK-LABEL: setgt_xv_v64i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a3, zero, 64
 ; CHECK-NEXT:    vsetvli zero, a3, e8, m4, ta, mu
 ; CHECK-NEXT:    vle8.v v28, (a0)
 ; CHECK-NEXT:    vmslt.vx v25, v28, a1
-; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    vsm.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <64 x i8>, <64 x i8>* %x
   %b = insertelement <64 x i8> undef, i8 %y, i32 0
   %c = shufflevector <64 x i8> %b, <64 x i8> undef, <64 x i32> zeroinitializer
   %d = icmp sgt <64 x i8> %c, %a
   store <64 x i1> %d, <64 x i1>* %z
   ret void
 }
 
 define void @setlt_xv_v128i8(<128 x i8>* %x, i8 %y, <128 x i1>* %z) {
 ; CHECK-LABEL: setlt_xv_v128i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a3, zero, 128
 ; CHECK-NEXT:    vsetvli zero, a3, e8, m8, ta, mu
 ; CHECK-NEXT:    vle8.v v8, (a0)
 ; CHECK-NEXT:    vmsgt.vx v25, v8, a1
-; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    vsm.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <128 x i8>, <128 x i8>* %x
   %b = insertelement <128 x i8> undef, i8 %y, i32 0
   %c = shufflevector <128 x i8> %b, <128 x i8> undef, <128 x i32> zeroinitializer
   %d = icmp slt <128 x i8> %c, %a
   store <128 x i1> %d, <128 x i1>* %z
   ret void
 }
 
 define void @setge_xv_v8i8(<8 x i8>* %x, i8 %y, <8 x i1>* %z) {
 ; CHECK-LABEL: setge_xv_v8i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vmsle.vx v25, v25, a1
-; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    vsm.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <8 x i8>, <8 x i8>* %x
   %b = insertelement <8 x i8> undef, i8 %y, i32 0
   %c = shufflevector <8 x i8> %b, <8 x i8> undef, <8 x i32> zeroinitializer
   %d = icmp sge <8 x i8> %c, %a
   store <8 x i1> %d, <8 x i1>* %z
   ret void
 }
 
 define void @setle_xv_v16i8(<16 x i8>* %x, i8 %y, <16 x i1>* %z) {
 ; CHECK-LABEL: setle_xv_v16i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vmv.v.x v26, a1
 ; CHECK-NEXT:    vmsle.vv v25, v26, v25
-; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    vsm.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <16 x i8>, <16 x i8>* %x
   %b = insertelement <16 x i8> undef, i8 %y, i32 0
   %c = shufflevector <16 x i8> %b, <16 x i8> undef, <16 x i32> zeroinitializer
   %d = icmp sle <16 x i8> %c, %a
   store <16 x i1> %d, <16 x i1>* %z
   ret void
 }
 
 define void @setugt_xv_v32i8(<32 x i8>* %x, i8 %y, <32 x i1>* %z) {
 ; CHECK-LABEL: setugt_xv_v32i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a3, zero, 32
 ; CHECK-NEXT:    vsetvli zero, a3, e8, m2, ta, mu
 ; CHECK-NEXT:    vle8.v v26, (a0)
 ; CHECK-NEXT:    vmsltu.vx v25, v26, a1
-; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    vsm.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <32 x i8>, <32 x i8>* %x
   %b = insertelement <32 x i8> undef, i8 %y, i32 0
   %c = shufflevector <32 x i8> %b, <32 x i8> undef, <32 x i32> zeroinitializer
   %d = icmp ugt <32 x i8> %c, %a
   store <32 x i1> %d, <32 x i1>* %z
   ret void
 }
 
 define void @setult_xv_v64i8(<64 x i8>* %x, i8 %y, <64 x i1>* %z) {
 ; CHECK-LABEL: setult_xv_v64i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a3, zero, 64
 ; CHECK-NEXT:    vsetvli zero, a3, e8, m4, ta, mu
 ; CHECK-NEXT:    vle8.v v28, (a0)
 ; CHECK-NEXT:    vmsgtu.vx v25, v28, a1
-; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    vsm.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <64 x i8>, <64 x i8>* %x
   %b = insertelement <64 x i8> undef, i8 %y, i32 0
   %c = shufflevector <64 x i8> %b, <64 x i8> undef, <64 x i32> zeroinitializer
   %d = icmp ult <64 x i8> %c, %a
   store <64 x i1> %d, <64 x i1>* %z
   ret void
 }
 
 define void @setuge_xv_v128i8(<128 x i8>* %x, i8 %y, <128 x i1>* %z) {
 ; CHECK-LABEL: setuge_xv_v128i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a3, zero, 128
 ; CHECK-NEXT:    vsetvli zero, a3, e8, m8, ta, mu
 ; CHECK-NEXT:    vle8.v v8, (a0)
 ; CHECK-NEXT:    vmsleu.vx v25, v8, a1
-; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    vsm.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <128 x i8>, <128 x i8>* %x
   %b = insertelement <128 x i8> undef, i8 %y, i32 0
   %c = shufflevector <128 x i8> %b, <128 x i8> undef, <128 x i32> zeroinitializer
   %d = icmp uge <128 x i8> %c, %a
   store <128 x i1> %d, <128 x i1>* %z
   ret void
 }
 
 define void @setule_xv_v8i8(<8 x i8>* %x, i8 %y, <8 x i1>* %z) {
 ; CHECK-LABEL: setule_xv_v8i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vmv.v.x v26, a1
 ; CHECK-NEXT:    vmsleu.vv v25, v26, v25
-; CHECK-NEXT:    vse1.v v25, (a2)
+; CHECK-NEXT:    vsm.v v25, (a2)
 ; CHECK-NEXT:    ret
   %a = load <8 x i8>, <8 x i8>* %x
   %b = insertelement <8 x i8> undef, i8 %y, i32 0
   %c = shufflevector <8 x i8> %b, <8 x i8> undef, <8 x i32> zeroinitializer
   %d = icmp ule <8 x i8> %c, %a
   store <8 x i1> %d, <8 x i1>* %z
   ret void
 }
 
 define void @seteq_vi_v16i8(<16 x i8>* %x, <16 x i1>* %z) {
 ; CHECK-LABEL: seteq_vi_v16i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vmseq.vi v25, v25, 0
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <16 x i8>, <16 x i8>* %x
   %b = insertelement <16 x i8> undef, i8 0, i32 0
   %c = shufflevector <16 x i8> %b, <16 x i8> undef, <16 x i32> zeroinitializer
   %d = icmp eq <16 x i8> %a, %c
   store <16 x i1> %d, <16 x i1>* %z
   ret void
 }
 
 define void @setne_vi_v32i8(<32 x i8>* %x, <32 x i1>* %z) {
 ; CHECK-LABEL: setne_vi_v32i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a2, zero, 32
 ; CHECK-NEXT:    vsetvli zero, a2, e8, m2, ta, mu
 ; CHECK-NEXT:    vle8.v v26, (a0)
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <32 x i8>, <32 x i8>* %x
   %b = insertelement <32 x i8> undef, i8 0, i32 0
   %c = shufflevector <32 x i8> %b, <32 x i8> undef, <32 x i32> zeroinitializer
   %d = icmp ne <32 x i8> %a, %c
   store <32 x i1> %d, <32 x i1>* %z
   ret void
 }
 
 define void @setgt_vi_v64i8(<64 x i8>* %x, <64 x i1>* %z) {
 ; CHECK-LABEL: setgt_vi_v64i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a2, zero, 64
 ; CHECK-NEXT:    vsetvli zero, a2, e8, m4, ta, mu
 ; CHECK-NEXT:    vle8.v v28, (a0)
 ; CHECK-NEXT:    vmsgt.vx v25, v28, zero
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <64 x i8>, <64 x i8>* %x
   %b = insertelement <64 x i8> undef, i8 0, i32 0
   %c = shufflevector <64 x i8> %b, <64 x i8> undef, <64 x i32> zeroinitializer
   %d = icmp sgt <64 x i8> %a, %c
   store <64 x i1> %d, <64 x i1>* %z
   ret void
 }
 
 define void @setlt_vi_v128i8(<128 x i8>* %x, <128 x i1>* %z) {
 ; CHECK-LABEL: setlt_vi_v128i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a2, zero, 128
 ; CHECK-NEXT:    vsetvli zero, a2, e8, m8, ta, mu
 ; CHECK-NEXT:    vle8.v v8, (a0)
 ; CHECK-NEXT:    vmsle.vi v25, v8, -1
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <128 x i8>, <128 x i8>* %x
   %b = insertelement <128 x i8> undef, i8 0, i32 0
   %c = shufflevector <128 x i8> %b, <128 x i8> undef, <128 x i32> zeroinitializer
   %d = icmp slt <128 x i8> %a, %c
   store <128 x i1> %d, <128 x i1>* %z
   ret void
 }
 
 define void @setge_vi_v8i8(<8 x i8>* %x, <8 x i1>* %z) {
 ; CHECK-LABEL: setge_vi_v8i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vmsgt.vi v25, v25, -1
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <8 x i8>, <8 x i8>* %x
   %b = insertelement <8 x i8> undef, i8 0, i32 0
   %c = shufflevector <8 x i8> %b, <8 x i8> undef, <8 x i32> zeroinitializer
   %d = icmp sge <8 x i8> %a, %c
   store <8 x i1> %d, <8 x i1>* %z
   ret void
 }
 
 define void @setle_vi_v16i8(<16 x i8>* %x, <16 x i1>* %z) {
 ; CHECK-LABEL: setle_vi_v16i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vmsle.vi v25, v25, 0
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <16 x i8>, <16 x i8>* %x
   %b = insertelement <16 x i8> undef, i8 0, i32 0
   %c = shufflevector <16 x i8> %b, <16 x i8> undef, <16 x i32> zeroinitializer
   %d = icmp sle <16 x i8> %a, %c
   store <16 x i1> %d, <16 x i1>* %z
   ret void
 }
 
 define void @setugt_vi_v32i8(<32 x i8>* %x, <32 x i1>* %z) {
 ; CHECK-LABEL: setugt_vi_v32i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a2, zero, 32
 ; CHECK-NEXT:    vsetvli zero, a2, e8, m2, ta, mu
 ; CHECK-NEXT:    vle8.v v26, (a0)
 ; CHECK-NEXT:    addi a0, zero, 5
 ; CHECK-NEXT:    vmsgtu.vx v25, v26, a0
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <32 x i8>, <32 x i8>* %x
   %b = insertelement <32 x i8> undef, i8 5, i32 0
   %c = shufflevector <32 x i8> %b, <32 x i8> undef, <32 x i32> zeroinitializer
   %d = icmp ugt <32 x i8> %a, %c
   store <32 x i1> %d, <32 x i1>* %z
   ret void
 }
 
 define void @setult_vi_v64i8(<64 x i8>* %x, <64 x i1>* %z) {
 ; CHECK-LABEL: setult_vi_v64i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a2, zero, 64
 ; CHECK-NEXT:    vsetvli zero, a2, e8, m4, ta, mu
 ; CHECK-NEXT:    vle8.v v28, (a0)
 ; CHECK-NEXT:    vmsleu.vi v25, v28, 4
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <64 x i8>, <64 x i8>* %x
   %b = insertelement <64 x i8> undef, i8 5, i32 0
   %c = shufflevector <64 x i8> %b, <64 x i8> undef, <64 x i32> zeroinitializer
   %d = icmp ult <64 x i8> %a, %c
   store <64 x i1> %d, <64 x i1>* %z
   ret void
 }
 
 define void @setuge_vi_v128i8(<128 x i8>* %x, <128 x i1>* %z) {
 ; CHECK-LABEL: setuge_vi_v128i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a2, zero, 128
 ; CHECK-NEXT:    vsetvli zero, a2, e8, m8, ta, mu
 ; CHECK-NEXT:    vle8.v v8, (a0)
 ; CHECK-NEXT:    vmsgtu.vi v25, v8, 4
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <128 x i8>, <128 x i8>* %x
   %b = insertelement <128 x i8> undef, i8 5, i32 0
   %c = shufflevector <128 x i8> %b, <128 x i8> undef, <128 x i32> zeroinitializer
   %d = icmp uge <128 x i8> %a, %c
   store <128 x i1> %d, <128 x i1>* %z
   ret void
 }
 
 define void @setule_vi_v8i8(<8 x i8>* %x, <8 x i1>* %z) {
 ; CHECK-LABEL: setule_vi_v8i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vmsleu.vi v25, v25, 5
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <8 x i8>, <8 x i8>* %x
   %b = insertelement <8 x i8> undef, i8 5, i32 0
   %c = shufflevector <8 x i8> %b, <8 x i8> undef, <8 x i32> zeroinitializer
   %d = icmp ule <8 x i8> %a, %c
   store <8 x i1> %d, <8 x i1>* %z
   ret void
 }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll

 ; RV64-LMULMAX2-NEXT:    ret
 ;
 ; RV32-LMULMAX4-LABEL: buildvec_mask_optsize_v128i1:
 ; RV32-LMULMAX4:       # %bb.0:
 ; RV32-LMULMAX4-NEXT:    lui a0, %hi(.LCPI21_0)
 ; RV32-LMULMAX4-NEXT:    addi a0, a0, %lo(.LCPI21_0)
 ; RV32-LMULMAX4-NEXT:    addi a1, zero, 64
 ; RV32-LMULMAX4-NEXT:    vsetvli zero, a1, e8, m4, ta, mu
-; RV32-LMULMAX4-NEXT:    vle1.v v0, (a0)
+; RV32-LMULMAX4-NEXT:    vlm.v v0, (a0)
 ; RV32-LMULMAX4-NEXT:    lui a0, %hi(.LCPI21_1)
 ; RV32-LMULMAX4-NEXT:    addi a0, a0, %lo(.LCPI21_1)
-; RV32-LMULMAX4-NEXT:    vle1.v v8, (a0)
+; RV32-LMULMAX4-NEXT:    vlm.v v8, (a0)
 ; RV32-LMULMAX4-NEXT:    ret
 ;
 ; RV64-LMULMAX4-LABEL: buildvec_mask_optsize_v128i1:
 ; RV64-LMULMAX4:       # %bb.0:
 ; RV64-LMULMAX4-NEXT:    lui a0, 841543
 ; RV64-LMULMAX4-NEXT:    addiw a0, a0, 511
 ; RV64-LMULMAX4-NEXT:    slli a0, a0, 14
 ; RV64-LMULMAX4-NEXT:    addi a0, a0, 859

 ; RV64-LMULMAX4-NEXT:    ret
 ;
 ; RV32-LMULMAX8-LABEL: buildvec_mask_optsize_v128i1:
 ; RV32-LMULMAX8:       # %bb.0:
 ; RV32-LMULMAX8-NEXT:    lui a0, %hi(.LCPI21_0)
 ; RV32-LMULMAX8-NEXT:    addi a0, a0, %lo(.LCPI21_0)
 ; RV32-LMULMAX8-NEXT:    addi a1, zero, 128
 ; RV32-LMULMAX8-NEXT:    vsetvli zero, a1, e8, m8, ta, mu
-; RV32-LMULMAX8-NEXT:    vle1.v v0, (a0)
+; RV32-LMULMAX8-NEXT:    vlm.v v0, (a0)
 ; RV32-LMULMAX8-NEXT:    ret
 ;
 ; RV64-LMULMAX8-LABEL: buildvec_mask_optsize_v128i1:
 ; RV64-LMULMAX8:       # %bb.0:
 ; RV64-LMULMAX8-NEXT:    lui a0, %hi(.LCPI21_0)
 ; RV64-LMULMAX8-NEXT:    addi a0, a0, %lo(.LCPI21_0)
 ; RV64-LMULMAX8-NEXT:    addi a1, zero, 128
 ; RV64-LMULMAX8-NEXT:    vsetvli zero, a1, e8, m8, ta, mu
-; RV64-LMULMAX8-NEXT:    vle1.v v0, (a0)
+; RV64-LMULMAX8-NEXT:    vlm.v v0, (a0)
 ; RV64-LMULMAX8-NEXT:    ret
   ret <128 x i1> <i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 0, i1 1, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 1, i1 1, i1 1>
 }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-load-store.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1-RV32
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1-RV64
 
 define void @load_store_v1i1(<1 x i1>* %x, <1 x i1>* %y) {
 ; CHECK-LABEL: load_store_v1i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 1, e8, mf8, ta, mu
-; CHECK-NEXT:    vle1.v v0, (a0)
+; CHECK-NEXT:    vlm.v v0, (a0)
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli zero, 1, e8, mf2, tu, mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <1 x i1>, <1 x i1>* %x
   store <1 x i1> %a, <1 x i1>* %y
   ret void
 }
 
 define void @load_store_v2i1(<2 x i1>* %x, <2 x i1>* %y) {
 ; CHECK-LABEL: load_store_v2i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT:    vle1.v v0, (a0)
+; CHECK-NEXT:    vlm.v v0, (a0)
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli zero, 2, e8, mf2, tu, mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <2 x i1>, <2 x i1>* %x
   store <2 x i1> %a, <2 x i1>* %y
   ret void
 }
 
 define void @load_store_v4i1(<4 x i1>* %x, <4 x i1>* %y) {
 ; CHECK-LABEL: load_store_v4i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT:    vle1.v v0, (a0)
+; CHECK-NEXT:    vlm.v v0, (a0)
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli zero, 4, e8, mf2, tu, mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <4 x i1>, <4 x i1>* %x
   store <4 x i1> %a, <4 x i1>* %y
   ret void
 }
 
 define void @load_store_v8i1(<8 x i1>* %x, <8 x i1>* %y) {
 ; CHECK-LABEL: load_store_v8i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT:    vle1.v v25, (a0)
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vlm.v v25, (a0)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <8 x i1>, <8 x i1>* %x
   store <8 x i1> %a, <8 x i1>* %y
   ret void
 }
 
 define void @load_store_v16i1(<16 x i1>* %x, <16 x i1>* %y) {
 ; CHECK-LABEL: load_store_v16i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT:    vle1.v v25, (a0)
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vlm.v v25, (a0)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <16 x i1>, <16 x i1>* %x
   store <16 x i1> %a, <16 x i1>* %y
   ret void
 }
 
 define void @load_store_v32i1(<32 x i1>* %x, <32 x i1>* %y) {
 ; LMULMAX2-LABEL: load_store_v32i1:
 ; LMULMAX2:       # %bb.0:
 ; LMULMAX2-NEXT:    addi a2, zero, 32
 ; LMULMAX2-NEXT:    vsetvli zero, a2, e8, m2, ta, mu
-; LMULMAX2-NEXT:    vle1.v v25, (a0)
-; LMULMAX2-NEXT:    vse1.v v25, (a1)
+; LMULMAX2-NEXT:    vlm.v v25, (a0)
+; LMULMAX2-NEXT:    vsm.v v25, (a1)
 ; LMULMAX2-NEXT:    ret
 ;
 ; LMULMAX1-RV32-LABEL: load_store_v32i1:
 ; LMULMAX1-RV32:       # %bb.0:
 ; LMULMAX1-RV32-NEXT:    lw a0, 0(a0)
 ; LMULMAX1-RV32-NEXT:    sw a0, 0(a1)
 ; LMULMAX1-RV32-NEXT:    ret
 ;

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-logic.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s
 
 define void @and_v8i1(<8 x i1>* %x, <8 x i1>* %y) {
 ; CHECK-LABEL: and_v8i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT:    vle1.v v25, (a0)
-; CHECK-NEXT:    vle1.v v26, (a1)
+; CHECK-NEXT:    vlm.v v25, (a0)
+; CHECK-NEXT:    vlm.v v26, (a1)
 ; CHECK-NEXT:    vmand.mm v25, v25, v26
-; CHECK-NEXT:    vse1.v v25, (a0)
+; CHECK-NEXT:    vsm.v v25, (a0)
 ; CHECK-NEXT:    ret
   %a = load <8 x i1>, <8 x i1>* %x
   %b = load <8 x i1>, <8 x i1>* %y
   %c = and <8 x i1> %a, %b
   store <8 x i1> %c, <8 x i1>* %x
   ret void
 }
 
 define void @or_v16i1(<16 x i1>* %x, <16 x i1>* %y) {
 ; CHECK-LABEL: or_v16i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT:    vle1.v v25, (a0)
-; CHECK-NEXT:    vle1.v v26, (a1)
+; CHECK-NEXT:    vlm.v v25, (a0)
+; CHECK-NEXT:    vlm.v v26, (a1)
 ; CHECK-NEXT:    vmor.mm v25, v25, v26
-; CHECK-NEXT:    vse1.v v25, (a0)
+; CHECK-NEXT:    vsm.v v25, (a0)
 ; CHECK-NEXT:    ret
   %a = load <16 x i1>, <16 x i1>* %x
   %b = load <16 x i1>, <16 x i1>* %y
   %c = or <16 x i1> %a, %b
   store <16 x i1> %c, <16 x i1>* %x
   ret void
 }
 
 define void @xor_v32i1(<32 x i1>* %x, <32 x i1>* %y) {
 ; CHECK-LABEL: xor_v32i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a2, zero, 32
 ; CHECK-NEXT:    vsetvli zero, a2, e8, m2, ta, mu
-; CHECK-NEXT:    vle1.v v25, (a0)
-; CHECK-NEXT:    vle1.v v26, (a1)
+; CHECK-NEXT:    vlm.v v25, (a0)
+; CHECK-NEXT:    vlm.v v26, (a1)
 ; CHECK-NEXT:    vmxor.mm v25, v25, v26
-; CHECK-NEXT:    vse1.v v25, (a0)
+; CHECK-NEXT:    vsm.v v25, (a0)
 ; CHECK-NEXT:    ret
   %a = load <32 x i1>, <32 x i1>* %x
   %b = load <32 x i1>, <32 x i1>* %y
   %c = xor <32 x i1> %a, %b
   store <32 x i1> %c, <32 x i1>* %x
   ret void
 }
 
 define void @not_v64i1(<64 x i1>* %x, <64 x i1>* %y) {
 ; CHECK-LABEL: not_v64i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 64
 ; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT:    vle1.v v25, (a0)
+; CHECK-NEXT:    vlm.v v25, (a0)
 ; CHECK-NEXT:    vmnand.mm v25, v25, v25
-; CHECK-NEXT:    vse1.v v25, (a0)
+; CHECK-NEXT:    vsm.v v25, (a0)
 ; CHECK-NEXT:    ret
   %a = load <64 x i1>, <64 x i1>* %x
   %b = load <64 x i1>, <64 x i1>* %y
   %c = xor <64 x i1> %a, <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>
   store <64 x i1> %c, <64 x i1>* %x
   ret void
 }
 
 define void @andnot_v8i1(<8 x i1>* %x, <8 x i1>* %y) {
 ; CHECK-LABEL: andnot_v8i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT:    vle1.v v25, (a0)
-; CHECK-NEXT:    vle1.v v26, (a1)
+; CHECK-NEXT:    vlm.v v25, (a0)
+; CHECK-NEXT:    vlm.v v26, (a1)
 ; CHECK-NEXT:    vmandnot.mm v25, v26, v25
-; CHECK-NEXT:    vse1.v v25, (a0)
+; CHECK-NEXT:    vsm.v v25, (a0)
 ; CHECK-NEXT:    ret
   %a = load <8 x i1>, <8 x i1>* %x
   %b = load <8 x i1>, <8 x i1>* %y
   %c = xor <8 x i1> %a, <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>
   %d = and <8 x i1> %b, %c
   store <8 x i1> %d, <8 x i1>* %x
   ret void
 }
 
 define void @ornot_v16i1(<16 x i1>* %x, <16 x i1>* %y) {
 ; CHECK-LABEL: ornot_v16i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT:    vle1.v v25, (a0)
-; CHECK-NEXT:    vle1.v v26, (a1)
+; CHECK-NEXT:    vlm.v v25, (a0)
+; CHECK-NEXT:    vlm.v v26, (a1)
 ; CHECK-NEXT:    vmornot.mm v25, v26, v25
-; CHECK-NEXT:    vse1.v v25, (a0)
+; CHECK-NEXT:    vsm.v v25, (a0)
 ; CHECK-NEXT:    ret
   %a = load <16 x i1>, <16 x i1>* %x
   %b = load <16 x i1>, <16 x i1>* %y
   %c = xor <16 x i1> %a, <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>
   %d = or <16 x i1> %b, %c
   store <16 x i1> %d, <16 x i1>* %x
   ret void
 }
 
 define void @xornot_v32i1(<32 x i1>* %x, <32 x i1>* %y) {
 ; CHECK-LABEL: xornot_v32i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a2, zero, 32
 ; CHECK-NEXT:    vsetvli zero, a2, e8, m2, ta, mu
-; CHECK-NEXT:    vle1.v v25, (a0)
-; CHECK-NEXT:    vle1.v v26, (a1)
+; CHECK-NEXT:    vlm.v v25, (a0)
+; CHECK-NEXT:    vlm.v v26, (a1)
 ; CHECK-NEXT:    vmxnor.mm v25, v25, v26
-; CHECK-NEXT:    vse1.v v25, (a0)
+; CHECK-NEXT:    vsm.v v25, (a0)
 ; CHECK-NEXT:    ret
   %a = load <32 x i1>, <32 x i1>* %x
   %b = load <32 x i1>, <32 x i1>* %y
   %c = xor <32 x i1> %a, <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>
   %d = xor <32 x i1> %b, %c
   store <32 x i1> %d, <32 x i1>* %x
   ret void
 }
 
 define void @nand_v8i1(<8 x i1>* %x, <8 x i1>* %y) {
 ; CHECK-LABEL: nand_v8i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT:    vle1.v v25, (a0)
-; CHECK-NEXT:    vle1.v v26, (a1)
+; CHECK-NEXT:    vlm.v v25, (a0)
+; CHECK-NEXT:    vlm.v v26, (a1)
 ; CHECK-NEXT:    vmnand.mm v25, v25, v26
-; CHECK-NEXT:    vse1.v v25, (a0)
+; CHECK-NEXT:    vsm.v v25, (a0)
 ; CHECK-NEXT:    ret
   %a = load <8 x i1>, <8 x i1>* %x
   %b = load <8 x i1>, <8 x i1>* %y
   %c = and <8 x i1> %a, %b
   %d = xor <8 x i1> %c, <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>
   store <8 x i1> %d, <8 x i1>* %x
   ret void
 }
 
 define void @nor_v16i1(<16 x i1>* %x, <16 x i1>* %y) {
 ; CHECK-LABEL: nor_v16i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT:    vle1.v v25, (a0)
-; CHECK-NEXT:    vle1.v v26, (a1)
+; CHECK-NEXT:    vlm.v v25, (a0)
+; CHECK-NEXT:    vlm.v v26, (a1)
 ; CHECK-NEXT:    vmnor.mm v25, v25, v26
-; CHECK-NEXT:    vse1.v v25, (a0)
+; CHECK-NEXT:    vsm.v v25, (a0)
 ; CHECK-NEXT:    ret
   %a = load <16 x i1>, <16 x i1>* %x
   %b = load <16 x i1>, <16 x i1>* %y
   %c = or <16 x i1> %a, %b
   %d = xor <16 x i1> %c, <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>
   store <16 x i1> %d, <16 x i1>* %x
   ret void
 }
 
 define void @xnor_v32i1(<32 x i1>* %x, <32 x i1>* %y) {
 ; CHECK-LABEL: xnor_v32i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a2, zero, 32
 ; CHECK-NEXT:    vsetvli zero, a2, e8, m2, ta, mu
-; CHECK-NEXT:    vle1.v v25, (a0)
-; CHECK-NEXT:    vle1.v v26, (a1)
+; CHECK-NEXT:    vlm.v v25, (a0)
+; CHECK-NEXT:    vlm.v v26, (a1)
 ; CHECK-NEXT:    vmxnor.mm v25, v25, v26
-; CHECK-NEXT:    vse1.v v25, (a0)
+; CHECK-NEXT:    vsm.v v25, (a0)
 ; CHECK-NEXT:    ret
   %a = load <32 x i1>, <32 x i1>* %x
   %b = load <32 x i1>, <32 x i1>* %y
   %c = xor <32 x i1> %a, %b
   %d = xor <32 x i1> %c, <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>
   store <32 x i1> %d, <32 x i1>* %x
   ret void
 }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll

 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli zero, 1, e8, mf2, tu, mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
-; CHECK-NEXT:    vse1.v v25, (a0)
+; CHECK-NEXT:    vsm.v v25, (a0)
 ; CHECK-NEXT:    ret
   store <1 x i1> <i1 1>, <1 x i1>* %x
   ret void
 }
 
 define void @splat_zeros_v2i1(<2 x i1>* %x) {
 ; CHECK-LABEL: splat_zeros_v2i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, mu
 ; CHECK-NEXT:    vmclr.m v0
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli zero, 2, e8, mf2, tu, mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
-; CHECK-NEXT:    vse1.v v25, (a0)
+; CHECK-NEXT:    vsm.v v25, (a0)
 ; CHECK-NEXT:    ret
   store <2 x i1> zeroinitializer, <2 x i1>* %x
   ret void
 }
 
 define void @splat_v1i1(<1 x i1>* %x, i1 %y) {
 ; CHECK-LABEL: splat_v1i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    andi a1, a1, 1
 ; CHECK-NEXT:    vsetivli zero, 1, e8, mf8, ta, mu
 ; CHECK-NEXT:    vmv.v.x v25, a1
 ; CHECK-NEXT:    vmsne.vi v0, v25, 0
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli zero, 1, e8, mf2, tu, mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
-; CHECK-NEXT:    vse1.v v25, (a0)
+; CHECK-NEXT:    vsm.v v25, (a0)
 ; CHECK-NEXT:    ret
   %a = insertelement <1 x i1> undef, i1 %y, i32 0
   %b = shufflevector <1 x i1> %a, <1 x i1> undef, <1 x i32> zeroinitializer
   store <1 x i1> %b, <1 x i1>* %x
   ret void
 }
 
 define void @splat_v1i1_icmp(<1 x i1>* %x, i32 signext %y, i32 signext %z) {
 ; CHECK-LABEL: splat_v1i1_icmp:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xor a1, a1, a2
 ; CHECK-NEXT:    seqz a1, a1
 ; CHECK-NEXT:    vsetivli zero, 1, e8, mf8, ta, mu
 ; CHECK-NEXT:    vmv.v.x v25, a1
 ; CHECK-NEXT:    vmsne.vi v0, v25, 0
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli zero, 1, e8, mf2, tu, mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
-; CHECK-NEXT:    vse1.v v25, (a0)
+; CHECK-NEXT:    vsm.v v25, (a0)
 ; CHECK-NEXT:    ret
   %c = icmp eq i32 %y, %z
   %a = insertelement <1 x i1> undef, i1 %c, i32 0
   %b = shufflevector <1 x i1> %a, <1 x i1> undef, <1 x i32> zeroinitializer
   store <1 x i1> %b, <1 x i1>* %x
   ret void
 }
 
 define void @splat_ones_v4i1(<4 x i1>* %x) {
 ; CHECK-LABEL: splat_ones_v4i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, mu
 ; CHECK-NEXT:    vmset.m v0
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli zero, 4, e8, mf2, tu, mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
-; CHECK-NEXT:    vse1.v v25, (a0)
+; CHECK-NEXT:    vsm.v v25, (a0)
 ; CHECK-NEXT:    ret
   store <4 x i1> <i1 1, i1 1, i1 1, i1 1>, <4 x i1>* %x
   ret void
 }
 
 define void @splat_v4i1(<4 x i1>* %x, i1 %y) {
 ; CHECK-LABEL: splat_v4i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    andi a1, a1, 1
 ; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, mu
 ; CHECK-NEXT:    vmv.v.x v25, a1
 ; CHECK-NEXT:    vmsne.vi v0, v25, 0
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli zero, 4, e8, mf2, tu, mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
-; CHECK-NEXT:    vse1.v v25, (a0)
+; CHECK-NEXT:    vsm.v v25, (a0)
 ; CHECK-NEXT:    ret
   %a = insertelement <4 x i1> undef, i1 %y, i32 0
   %b = shufflevector <4 x i1> %a, <4 x i1> undef, <4 x i32> zeroinitializer
   store <4 x i1> %b, <4 x i1>* %x
   ret void
 }
 
 define void @splat_zeros_v8i1(<8 x i1>* %x) {
 ; CHECK-LABEL: splat_zeros_v8i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmclr.m v25
-; CHECK-NEXT:    vse1.v v25, (a0)
+; CHECK-NEXT:    vsm.v v25, (a0)
 ; CHECK-NEXT:    ret
   store <8 x i1> zeroinitializer, <8 x i1>* %x
   ret void
 }
 
 define void @splat_v8i1(<8 x i1>* %x, i1 %y) {
 ; CHECK-LABEL: splat_v8i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    andi a1, a1, 1
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmv.v.x v25, a1
 ; CHECK-NEXT:    vmsne.vi v25, v25, 0
-; CHECK-NEXT:    vse1.v v25, (a0)
+; CHECK-NEXT:    vsm.v v25, (a0)
 ; CHECK-NEXT:    ret
   %a = insertelement <8 x i1> undef, i1 %y, i32 0
   %b = shufflevector <8 x i1> %a, <8 x i1> undef, <8 x i32> zeroinitializer
   store <8 x i1> %b, <8 x i1>* %x
   ret void
 }
 
 define void @splat_ones_v16i1(<16 x i1>* %x) {
 ; CHECK-LABEL: splat_ones_v16i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, mu
 ; CHECK-NEXT:    vmset.m v25
-; CHECK-NEXT:    vse1.v v25, (a0)
+; CHECK-NEXT:    vsm.v v25, (a0)
 ; CHECK-NEXT:    ret
   store <16 x i1> <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>, <16 x i1>* %x
   ret void
 }
 
 define void @splat_v16i1(<16 x i1>* %x, i1 %y) {
 ; CHECK-LABEL: splat_v16i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    andi a1, a1, 1
 ; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, mu
 ; CHECK-NEXT:    vmv.v.x v25, a1
 ; CHECK-NEXT:    vmsne.vi v25, v25, 0
-; CHECK-NEXT:    vse1.v v25, (a0)
+; CHECK-NEXT:    vsm.v v25, (a0)
 ; CHECK-NEXT:    ret
   %a = insertelement <16 x i1> undef, i1 %y, i32 0
   %b = shufflevector <16 x i1> %a, <16 x i1> undef, <16 x i32> zeroinitializer
   store <16 x i1> %b, <16 x i1>* %x
   ret void
 }
 
 define void @splat_zeros_v32i1(<32 x i1>* %x) {
 ; LMULMAX2-LABEL: splat_zeros_v32i1:
 ; LMULMAX2:       # %bb.0:
 ; LMULMAX2-NEXT:    addi a1, zero, 32
 ; LMULMAX2-NEXT:    vsetvli zero, a1, e8, m2, ta, mu
 ; LMULMAX2-NEXT:    vmclr.m v25
-; LMULMAX2-NEXT:    vse1.v v25, (a0)
+; LMULMAX2-NEXT:    vsm.v v25, (a0)
 ; LMULMAX2-NEXT:    ret
 ;
 ; LMULMAX1-RV32-LABEL: splat_zeros_v32i1:
 ; LMULMAX1-RV32:       # %bb.0:
 ; LMULMAX1-RV32-NEXT:    vsetivli zero, 16, e8, m1, ta, mu
 ; LMULMAX1-RV32-NEXT:    vmclr.m v25
-; LMULMAX1-RV32-NEXT:    vse1.v v25, (a0)
+; LMULMAX1-RV32-NEXT:    vsm.v v25, (a0)
 ; LMULMAX1-RV32-NEXT:    addi a0, a0, 2
-; LMULMAX1-RV32-NEXT:    vse1.v v25, (a0)
+; LMULMAX1-RV32-NEXT:    vsm.v v25, (a0)
 ; LMULMAX1-RV32-NEXT:    ret
 ;
 ; LMULMAX1-RV64-LABEL: splat_zeros_v32i1:
 ; LMULMAX1-RV64:       # %bb.0:
 ; LMULMAX1-RV64-NEXT:    vsetivli zero, 16, e8, m1, ta, mu
 ; LMULMAX1-RV64-NEXT:    vmclr.m v25
-; LMULMAX1-RV64-NEXT:    vse1.v v25, (a0)
+; LMULMAX1-RV64-NEXT:    vsm.v v25, (a0)
 ; LMULMAX1-RV64-NEXT:    addi a0, a0, 2
-; LMULMAX1-RV64-NEXT:    vse1.v v25, (a0)
+; LMULMAX1-RV64-NEXT:    vsm.v v25, (a0)
 ; LMULMAX1-RV64-NEXT:    ret
   store <32 x i1> zeroinitializer, <32 x i1>* %x
   ret void
 }
 
 define void @splat_v32i1(<32 x i1>* %x, i1 %y) {
 ; LMULMAX2-LABEL: splat_v32i1:
 ; LMULMAX2:       # %bb.0:
 ; LMULMAX2-NEXT:    andi a1, a1, 1
 ; LMULMAX2-NEXT:    addi a2, zero, 32
 ; LMULMAX2-NEXT:    vsetvli zero, a2, e8, m2, ta, mu
 ; LMULMAX2-NEXT:    vmv.v.x v26, a1
 ; LMULMAX2-NEXT:    vmsne.vi v25, v26, 0
-; LMULMAX2-NEXT:    vse1.v v25, (a0)
+; LMULMAX2-NEXT:    vsm.v v25, (a0)
 ; LMULMAX2-NEXT:    ret
 ;
 ; LMULMAX1-RV32-LABEL: splat_v32i1:
 ; LMULMAX1-RV32:       # %bb.0:
 ; LMULMAX1-RV32-NEXT:    andi a1, a1, 1
 ; LMULMAX1-RV32-NEXT:    vsetivli zero, 16, e8, m1, ta, mu
 ; LMULMAX1-RV32-NEXT:    vmv.v.x v25, a1
 ; LMULMAX1-RV32-NEXT:    vmsne.vi v25, v25, 0
 ; LMULMAX1-RV32-NEXT:    addi a1, a0, 2
-; LMULMAX1-RV32-NEXT:    vse1.v v25, (a1)
-; LMULMAX1-RV32-NEXT:    vse1.v v25, (a0)
+; LMULMAX1-RV32-NEXT:    vsm.v v25, (a1)
+; LMULMAX1-RV32-NEXT:    vsm.v v25, (a0)
 ; LMULMAX1-RV32-NEXT:    ret
 ;
 ; LMULMAX1-RV64-LABEL: splat_v32i1:
 ; LMULMAX1-RV64:       # %bb.0:
 ; LMULMAX1-RV64-NEXT:    andi a1, a1, 1
 ; LMULMAX1-RV64-NEXT:    vsetivli zero, 16, e8, m1, ta, mu
 ; LMULMAX1-RV64-NEXT:    vmv.v.x v25, a1
 ; LMULMAX1-RV64-NEXT:    vmsne.vi v25, v25, 0
 ; LMULMAX1-RV64-NEXT:    addi a1, a0, 2
-; LMULMAX1-RV64-NEXT:    vse1.v v25, (a1)
-; LMULMAX1-RV64-NEXT:    vse1.v v25, (a0)
+; LMULMAX1-RV64-NEXT:    vsm.v v25, (a1)
+; LMULMAX1-RV64-NEXT:    vsm.v v25, (a0)
 ; LMULMAX1-RV64-NEXT:    ret
   %a = insertelement <32 x i1> undef, i1 %y, i32 0
   %b = shufflevector <32 x i1> %a, <32 x i1> undef, <32 x i32> zeroinitializer
   store <32 x i1> %b, <32 x i1>* %x
   ret void
 }
 
 define void @splat_ones_v64i1(<64 x i1>* %x) {
 ; LMULMAX2-LABEL: splat_ones_v64i1:
 ; LMULMAX2:       # %bb.0:
 ; LMULMAX2-NEXT:    addi a1, a0, 4
 ; LMULMAX2-NEXT:    addi a2, zero, 32
 ; LMULMAX2-NEXT:    vsetvli zero, a2, e8, m2, ta, mu
 ; LMULMAX2-NEXT:    vmset.m v25
-; LMULMAX2-NEXT:    vse1.v v25, (a1)
-; LMULMAX2-NEXT:    vse1.v v25, (a0)
+; LMULMAX2-NEXT:    vsm.v v25, (a1)
+; LMULMAX2-NEXT:    vsm.v v25, (a0)
 ; LMULMAX2-NEXT:    ret
 ;
 ; LMULMAX1-RV32-LABEL: splat_ones_v64i1:
 ; LMULMAX1-RV32:       # %bb.0:
 ; LMULMAX1-RV32-NEXT:    vsetivli zero, 16, e8, m1, ta, mu
 ; LMULMAX1-RV32-NEXT:    vmset.m v25
-; LMULMAX1-RV32-NEXT:    vse1.v v25, (a0)
+; LMULMAX1-RV32-NEXT:    vsm.v v25, (a0)
 ; LMULMAX1-RV32-NEXT:    addi a1, a0, 6
-; LMULMAX1-RV32-NEXT:    vse1.v v25, (a1)
+; LMULMAX1-RV32-NEXT:    vsm.v v25, (a1)
 ; LMULMAX1-RV32-NEXT:    addi a1, a0, 4
-; LMULMAX1-RV32-NEXT:    vse1.v v25, (a1)
+; LMULMAX1-RV32-NEXT:    vsm.v v25, (a1)
 ; LMULMAX1-RV32-NEXT:    addi a0, a0, 2
-; LMULMAX1-RV32-NEXT:    vse1.v v25, (a0)
+; LMULMAX1-RV32-NEXT:    vsm.v v25, (a0)
 ; LMULMAX1-RV32-NEXT:    ret
 ;
 ; LMULMAX1-RV64-LABEL: splat_ones_v64i1:
 ; LMULMAX1-RV64:       # %bb.0:
 ; LMULMAX1-RV64-NEXT:    vsetivli zero, 16, e8, m1, ta, mu
 ; LMULMAX1-RV64-NEXT:    vmset.m v25
-; LMULMAX1-RV64-NEXT:    vse1.v v25, (a0)
+; LMULMAX1-RV64-NEXT:    vsm.v v25, (a0)
 ; LMULMAX1-RV64-NEXT:    addi a1, a0, 6
-; LMULMAX1-RV64-NEXT:    vse1.v v25, (a1)
+; LMULMAX1-RV64-NEXT:    vsm.v v25, (a1)
 ; LMULMAX1-RV64-NEXT:    addi a1, a0, 4
-; LMULMAX1-RV64-NEXT:    vse1.v v25, (a1)
+; LMULMAX1-RV64-NEXT:    vsm.v v25, (a1)
 ; LMULMAX1-RV64-NEXT:    addi a0, a0, 2
-; LMULMAX1-RV64-NEXT:    vse1.v v25, (a0)
+; LMULMAX1-RV64-NEXT:    vsm.v v25, (a0)
 ; LMULMAX1-RV64-NEXT:    ret
   store <64 x i1> <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>, <64 x i1>* %x
   ret void
 }
 
 define void @splat_v64i1(<64 x i1>* %x, i1 %y) {
 ; LMULMAX2-LABEL: splat_v64i1:
 ; LMULMAX2:       # %bb.0:
 ; LMULMAX2-NEXT:    andi a1, a1, 1
 ; LMULMAX2-NEXT:    addi a2, zero, 32
 ; LMULMAX2-NEXT:    vsetvli zero, a2, e8, m2, ta, mu
 ; LMULMAX2-NEXT:    vmv.v.x v26, a1
 ; LMULMAX2-NEXT:    vmsne.vi v25, v26, 0
 ; LMULMAX2-NEXT:    addi a1, a0, 4
-; LMULMAX2-NEXT:    vse1.v v25, (a1)
-; LMULMAX2-NEXT:    vse1.v v25, (a0)
+; LMULMAX2-NEXT:    vsm.v v25, (a1)
+; LMULMAX2-NEXT:    vsm.v v25, (a0)
 ; LMULMAX2-NEXT:    ret
 ;
 ; LMULMAX1-RV32-LABEL: splat_v64i1:
 ; LMULMAX1-RV32:       # %bb.0:
 ; LMULMAX1-RV32-NEXT:    andi a1, a1, 1
 ; LMULMAX1-RV32-NEXT:    vsetivli zero, 16, e8, m1, ta, mu
 ; LMULMAX1-RV32-NEXT:    vmv.v.x v25, a1
 ; LMULMAX1-RV32-NEXT:    vmsne.vi v25, v25, 0
 ; LMULMAX1-RV32-NEXT:    addi a1, a0, 6
-; LMULMAX1-RV32-NEXT:    vse1.v v25, (a1)
+; LMULMAX1-RV32-NEXT:    vsm.v v25, (a1)
 ; LMULMAX1-RV32-NEXT:    addi a1, a0, 4
-; LMULMAX1-RV32-NEXT:    vse1.v v25, (a1)
+; LMULMAX1-RV32-NEXT:    vsm.v v25, (a1)
 ; LMULMAX1-RV32-NEXT:    addi a1, a0, 2
-; LMULMAX1-RV32-NEXT:    vse1.v v25, (a1)
-; LMULMAX1-RV32-NEXT:    vse1.v v25, (a0)
+; LMULMAX1-RV32-NEXT:    vsm.v v25, (a1)
+; LMULMAX1-RV32-NEXT:    vsm.v v25, (a0)
 ; LMULMAX1-RV32-NEXT:    ret
 ;
 ; LMULMAX1-RV64-LABEL: splat_v64i1:
 ; LMULMAX1-RV64:       # %bb.0:
 ; LMULMAX1-RV64-NEXT:    andi a1, a1, 1
 ; LMULMAX1-RV64-NEXT:    vsetivli zero, 16, e8, m1, ta, mu
 ; LMULMAX1-RV64-NEXT:    vmv.v.x v25, a1
 ; LMULMAX1-RV64-NEXT:    vmsne.vi v25, v25, 0
 ; LMULMAX1-RV64-NEXT:    addi a1, a0, 6
-; LMULMAX1-RV64-NEXT:    vse1.v v25, (a1)
+; LMULMAX1-RV64-NEXT:    vsm.v v25, (a1)
 ; LMULMAX1-RV64-NEXT:    addi a1, a0, 4
-; LMULMAX1-RV64-NEXT:    vse1.v v25, (a1)
+; LMULMAX1-RV64-NEXT:    vsm.v v25, (a1)
 ; LMULMAX1-RV64-NEXT:    addi a1, a0, 2
-; LMULMAX1-RV64-NEXT:    vse1.v v25, (a1)
-; LMULMAX1-RV64-NEXT:    vse1.v v25, (a0)
+; LMULMAX1-RV64-NEXT:    vsm.v v25, (a1)
+; LMULMAX1-RV64-NEXT:    vsm.v v25, (a0)
 ; LMULMAX1-RV64-NEXT:    ret
   %a = insertelement <64 x i1> undef, i1 %y, i32 0
   %b = shufflevector <64 x i1> %a, <64 x i1> undef, <64 x i32> zeroinitializer
   store <64 x i1> %b, <64 x i1>* %x
   ret void
 }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll

 ; RV32-NEXT:    vmerge.vim v25, v25, 1, v0
 ; RV32-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; RV32-NEXT:    vmv.v.i v26, 0
 ; RV32-NEXT:    vsetivli zero, 2, e8, mf2, tu, mu
 ; RV32-NEXT:    vslideup.vi v26, v25, 0
 ; RV32-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; RV32-NEXT:    vmsne.vi v25, v26, 0
 ; RV32-NEXT:    addi a0, sp, 14
-; RV32-NEXT:    vse1.v v25, (a0)
+; RV32-NEXT:    vsm.v v25, (a0)
 ; RV32-NEXT:    lbu a0, 14(sp)
 ; RV32-NEXT:    andi a1, a0, 1
 ; RV32-NEXT:    beqz a1, .LBB4_2
 ; RV32-NEXT:  # %bb.1: # %cond.load
 ; RV32-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
 ; RV32-NEXT:    vmv.x.s a1, v8
 ; RV32-NEXT:    lb a2, 1(a1)
 ; RV32-NEXT:    lbu a1, 0(a1)

 ; RV64-NEXT:    vmerge.vim v25, v25, 1, v0
 ; RV64-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; RV64-NEXT:    vmv.v.i v26, 0
 ; RV64-NEXT:    vsetivli zero, 2, e8, mf2, tu, mu
 ; RV64-NEXT:    vslideup.vi v26, v25, 0
 ; RV64-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; RV64-NEXT:    vmsne.vi v25, v26, 0
 ; RV64-NEXT:    addi a0, sp, 14
-; RV64-NEXT:    vse1.v v25, (a0)
+; RV64-NEXT:    vsm.v v25, (a0)
 ; RV64-NEXT:    lbu a0, 14(sp)
 ; RV64-NEXT:    andi a1, a0, 1
 ; RV64-NEXT:    beqz a1, .LBB4_2
 ; RV64-NEXT:  # %bb.1: # %cond.load
 ; RV64-NEXT:    vsetvli zero, zero, e64, m1, ta, mu
 ; RV64-NEXT:    vmv.x.s a1, v8
 ; RV64-NEXT:    lb a2, 1(a1)
 ; RV64-NEXT:    lbu a1, 0(a1)

 ; RV32-NEXT:    vmerge.vim v25, v25, 1, v0
 ; RV32-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; RV32-NEXT:    vmv.v.i v26, 0
 ; RV32-NEXT:    vsetivli zero, 2, e8, mf2, tu, mu
 ; RV32-NEXT:    vslideup.vi v26, v25, 0
 ; RV32-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; RV32-NEXT:    vmsne.vi v25, v26, 0
 ; RV32-NEXT:    addi a0, sp, 14
-; RV32-NEXT:    vse1.v v25, (a0)
+; RV32-NEXT:    vsm.v v25, (a0)
 ; RV32-NEXT:    lbu a0, 14(sp)
 ; RV32-NEXT:    andi a1, a0, 1
 ; RV32-NEXT:    vsetivli zero, 2, e32, m1, ta, mu
 ; RV32-NEXT:    vmv.v.i v25, 0
 ; RV32-NEXT:    beqz a1, .LBB5_2
 ; RV32-NEXT:  # %bb.1: # %cond.load
 ; RV32-NEXT:    vmv.x.s a1, v8
 ; RV32-NEXT:    lw a2, 4(a1)

 ; RV64-NEXT:    vmerge.vim v25, v25, 1, v0
 ; RV64-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; RV64-NEXT:    vmv.v.i v26, 0
 ; RV64-NEXT:    vsetivli zero, 2, e8, mf2, tu, mu
 ; RV64-NEXT:    vslideup.vi v26, v25, 0
 ; RV64-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; RV64-NEXT:    vmsne.vi v25, v26, 0
 ; RV64-NEXT:    addi a0, sp, 14
-; RV64-NEXT:    vse1.v v25, (a0)
+; RV64-NEXT:    vsm.v v25, (a0)
 ; RV64-NEXT:    lbu a0, 14(sp)
 ; RV64-NEXT:    andi a1, a0, 1
 ; RV64-NEXT:    beqz a1, .LBB5_2
 ; RV64-NEXT:  # %bb.1: # %cond.load
 ; RV64-NEXT:    vsetvli zero, zero, e64, m1, ta, mu
 ; RV64-NEXT:    vmv.x.s a1, v8
 ; RV64-NEXT:    lwu a2, 4(a1)
 ; RV64-NEXT:    lwu a1, 0(a1)

 ; RV32-NEXT:    vmerge.vim v25, v25, 1, v0
 ; RV32-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; RV32-NEXT:    vmv.v.i v26, 0
 ; RV32-NEXT:    vsetivli zero, 4, e8, mf2, tu, mu
 ; RV32-NEXT:    vslideup.vi v26, v25, 0
 ; RV32-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; RV32-NEXT:    vmsne.vi v25, v26, 0
 ; RV32-NEXT:    addi a0, sp, 12
-; RV32-NEXT:    vse1.v v25, (a0)
+; RV32-NEXT:    vsm.v v25, (a0)
 ; RV32-NEXT:    lbu a0, 12(sp)
 ; RV32-NEXT:    andi a1, a0, 1
 ; RV32-NEXT:    bnez a1, .LBB6_5
 ; RV32-NEXT:  # %bb.1: # %else
 ; RV32-NEXT:    andi a1, a0, 2
 ; RV32-NEXT:    bnez a1, .LBB6_6
 ; RV32-NEXT:  .LBB6_2: # %else2
 ; RV32-NEXT:    andi a1, a0, 4

 ; RV64-NEXT:    vmerge.vim v25, v25, 1, v0
 ; RV64-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; RV64-NEXT:    vmv.v.i v26, 0
 ; RV64-NEXT:    vsetivli zero, 4, e8, mf2, tu, mu
 ; RV64-NEXT:    vslideup.vi v26, v25, 0
 ; RV64-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; RV64-NEXT:    vmsne.vi v25, v26, 0
 ; RV64-NEXT:    addi a0, sp, 12
-; RV64-NEXT:    vse1.v v25, (a0)
+; RV64-NEXT:    vsm.v v25, (a0)
 ; RV64-NEXT:    lbu a0, 12(sp)
 ; RV64-NEXT:    andi a1, a0, 1
 ; RV64-NEXT:    bnez a1, .LBB6_5
 ; RV64-NEXT:  # %bb.1: # %else
 ; RV64-NEXT:    andi a1, a0, 2
 ; RV64-NEXT:    bnez a1, .LBB6_6
 ; RV64-NEXT:  .LBB6_2: # %else2
 ; RV64-NEXT:    andi a1, a0, 4

 ; RV32-NEXT:    vmerge.vim v25, v25, 1, v0
 ; RV32-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; RV32-NEXT:    vmv.v.i v26, 0
 ; RV32-NEXT:    vsetivli zero, 2, e8, mf2, tu, mu
 ; RV32-NEXT:    vslideup.vi v26, v25, 0
 ; RV32-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; RV32-NEXT:    vmsne.vi v25, v26, 0
 ; RV32-NEXT:    addi a0, sp, 14
-; RV32-NEXT:    vse1.v v25, (a0)
+; RV32-NEXT:    vsm.v v25, (a0)
 ; RV32-NEXT:    lbu a0, 14(sp)
 ; RV32-NEXT:    andi a1, a0, 1
 ; RV32-NEXT:    bnez a1, .LBB7_3
 ; RV32-NEXT:  # %bb.1: # %else
 ; RV32-NEXT:    andi a0, a0, 2
 ; RV32-NEXT:    bnez a0, .LBB7_4
 ; RV32-NEXT:  .LBB7_2: # %else2
 ; RV32-NEXT:    addi sp, sp, 16

 ; RV64-NEXT:    vmerge.vim v25, v25, 1, v0
 ; RV64-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; RV64-NEXT:    vmv.v.i v26, 0
 ; RV64-NEXT:    vsetivli zero, 2, e8, mf2, tu, mu
 ; RV64-NEXT:    vslideup.vi v26, v25, 0
 ; RV64-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; RV64-NEXT:    vmsne.vi v25, v26, 0
 ; RV64-NEXT:    addi a0, sp, 14
-; RV64-NEXT:    vse1.v v25, (a0)
+; RV64-NEXT:    vsm.v v25, (a0)
 ; RV64-NEXT:    lbu a0, 14(sp)
 ; RV64-NEXT:    andi a1, a0, 1
 ; RV64-NEXT:    bnez a1, .LBB7_3
 ; RV64-NEXT:  # %bb.1: # %else
 ; RV64-NEXT:    andi a0, a0, 2
 ; RV64-NEXT:    bnez a0, .LBB7_4
 ; RV64-NEXT:  .LBB7_2: # %else2
 ; RV64-NEXT:    addi sp, sp, 16

 ; RV32-NEXT:    vmerge.vim v25, v25, 1, v0
 ; RV32-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; RV32-NEXT:    vmv.v.i v26, 0
 ; RV32-NEXT:    vsetivli zero, 2, e8, mf2, tu, mu
 ; RV32-NEXT:    vslideup.vi v26, v25, 0
 ; RV32-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; RV32-NEXT:    vmsne.vi v25, v26, 0
 ; RV32-NEXT:    addi a2, sp, 14
-; RV32-NEXT:    vse1.v v25, (a2)
+; RV32-NEXT:    vsm.v v25, (a2)
 ; RV32-NEXT:    lbu a2, 14(sp)
 ; RV32-NEXT:    andi a3, a2, 1
 ; RV32-NEXT:    beqz a3, .LBB8_2
 ; RV32-NEXT:  # %bb.1: # %cond.load
 ; RV32-NEXT:    lbu a6, 1(a0)
 ; RV32-NEXT:    lbu a7, 0(a0)
 ; RV32-NEXT:    lbu a5, 3(a0)
 ; RV32-NEXT:    lbu a3, 2(a0)

 ; RV64-NEXT:    vmerge.vim v25, v25, 1, v0
 ; RV64-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; RV64-NEXT:    vmv.v.i v26, 0
 ; RV64-NEXT:    vsetivli zero, 2, e8, mf2, tu, mu
 ; RV64-NEXT:    vslideup.vi v26, v25, 0
 ; RV64-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; RV64-NEXT:    vmsne.vi v25, v26, 0
 ; RV64-NEXT:    addi a2, sp, 14
-; RV64-NEXT:    vse1.v v25, (a2)
+; RV64-NEXT:    vsm.v v25, (a2)
 ; RV64-NEXT:    lbu a2, 14(sp)
 ; RV64-NEXT:    andi a3, a2, 1
 ; RV64-NEXT:    beqz a3, .LBB8_2
 ; RV64-NEXT:  # %bb.1: # %cond.load
 ; RV64-NEXT:    lbu a6, 1(a0)
 ; RV64-NEXT:    lbu a7, 0(a0)
 ; RV64-NEXT:    lb a5, 3(a0)
 ; RV64-NEXT:    lbu a3, 2(a0)

 ; RV32-NEXT:    vmerge.vim v25, v25, 1, v0
 ; RV32-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; RV32-NEXT:    vmv.v.i v26, 0
 ; RV32-NEXT:    vsetivli zero, 2, e8, mf2, tu, mu
 ; RV32-NEXT:    vslideup.vi v26, v25, 0
 ; RV32-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; RV32-NEXT:    vmsne.vi v25, v26, 0
 ; RV32-NEXT:    addi a1, sp, 14
-; RV32-NEXT:    vse1.v v25, (a1)
+; RV32-NEXT:    vsm.v v25, (a1)
 ; RV32-NEXT:    lbu a1, 14(sp)
 ; RV32-NEXT:    andi a2, a1, 1
 ; RV32-NEXT:    bnez a2, .LBB9_3
 ; RV32-NEXT:  # %bb.1: # %else
 ; RV32-NEXT:    andi a1, a1, 2
 ; RV32-NEXT:    bnez a1, .LBB9_4
 ; RV32-NEXT:  .LBB9_2: # %else2
 ; RV32-NEXT:    addi sp, sp, 16

 ; RV64-NEXT:    vmerge.vim v25, v25, 1, v0
 ; RV64-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; RV64-NEXT:    vmv.v.i v26, 0
 ; RV64-NEXT:    vsetivli zero, 2, e8, mf2, tu, mu
 ; RV64-NEXT:    vslideup.vi v26, v25, 0
 ; RV64-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; RV64-NEXT:    vmsne.vi v25, v26, 0
 ; RV64-NEXT:    addi a1, sp, 14
-; RV64-NEXT:    vse1.v v25, (a1)
+; RV64-NEXT:    vsm.v v25, (a1)
 ; RV64-NEXT:    lbu a1, 14(sp)
 ; RV64-NEXT:    andi a2, a1, 1
 ; RV64-NEXT:    bnez a2, .LBB9_3
 ; RV64-NEXT:  # %bb.1: # %else
 ; RV64-NEXT:    andi a1, a1, 2
 ; RV64-NEXT:    bnez a1, .LBB9_4
 ; RV64-NEXT:  .LBB9_2: # %else2
 ; RV64-NEXT:    addi sp, sp, 16

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v,+experimental-zfh,+f,+d -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v,+experimental-zfh,+f,+d -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s
 
 define void @vselect_vv_v8i32(<8 x i32>* %a, <8 x i32>* %b, <8 x i1>* %cc, <8 x i32>* %z) {
 ; CHECK-LABEL: vselect_vv_v8i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, mu
 ; CHECK-NEXT:    vle32.v v26, (a0)
 ; CHECK-NEXT:    vle32.v v28, (a1)
-; CHECK-NEXT:    vle1.v v0, (a2)
+; CHECK-NEXT:    vlm.v v0, (a2)
 ; CHECK-NEXT:    vmerge.vvm v26, v28, v26, v0
 ; CHECK-NEXT:    vse32.v v26, (a3)
 ; CHECK-NEXT:    ret
   %va = load <8 x i32>, <8 x i32>* %a
   %vb = load <8 x i32>, <8 x i32>* %b
   %vcc = load <8 x i1>, <8 x i1>* %cc
   %vsel = select <8 x i1> %vcc, <8 x i32> %va, <8 x i32> %vb
   store <8 x i32> %vsel, <8 x i32>* %z
   ret void
 }
 
 define void @vselect_vx_v8i32(i32 %a, <8 x i32>* %b, <8 x i1>* %cc, <8 x i32>* %z) {
 ; CHECK-LABEL: vselect_vx_v8i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, mu
 ; CHECK-NEXT:    vle32.v v26, (a1)
-; CHECK-NEXT:    vle1.v v0, (a2)
+; CHECK-NEXT:    vlm.v v0, (a2)
 ; CHECK-NEXT:    vmerge.vxm v26, v26, a0, v0
 ; CHECK-NEXT:    vse32.v v26, (a3)
 ; CHECK-NEXT:    ret
   %vb = load <8 x i32>, <8 x i32>* %b
   %ahead = insertelement <8 x i32> undef, i32 %a, i32 0
   %va = shufflevector <8 x i32> %ahead, <8 x i32> undef, <8 x i32> zeroinitializer
   %vcc = load <8 x i1>, <8 x i1>* %cc
   %vsel = select <8 x i1> %vcc, <8 x i32> %va, <8 x i32> %vb
   store <8 x i32> %vsel, <8 x i32>* %z
   ret void
 }
 
 define void @vselect_vi_v8i32(<8 x i32>* %b, <8 x i1>* %cc, <8 x i32>* %z) {
 ; CHECK-LABEL: vselect_vi_v8i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, mu
 ; CHECK-NEXT:    vle32.v v26, (a0)
-; CHECK-NEXT:    vle1.v v0, (a1)
+; CHECK-NEXT:    vlm.v v0, (a1)
 ; CHECK-NEXT:    vmerge.vim v26, v26, -1, v0
 ; CHECK-NEXT:    vse32.v v26, (a2)
 ; CHECK-NEXT:    ret
   %vb = load <8 x i32>, <8 x i32>* %b
   %a = insertelement <8 x i32> undef, i32 -1, i32 0
   %va = shufflevector <8 x i32> %a, <8 x i32> undef, <8 x i32> zeroinitializer
   %vcc = load <8 x i1>, <8 x i1>* %cc
   %vsel = select <8 x i1> %vcc, <8 x i32> %va, <8 x i32> %vb
   store <8 x i32> %vsel, <8 x i32>* %z
   ret void
 }
 
 define void @vselect_vv_v8f32(<8 x float>* %a, <8 x float>* %b, <8 x i1>* %cc, <8 x float>* %z) {
 ; CHECK-LABEL: vselect_vv_v8f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, mu
 ; CHECK-NEXT:    vle32.v v26, (a0)
 ; CHECK-NEXT:    vle32.v v28, (a1)
-; CHECK-NEXT:    vle1.v v0, (a2)
+; CHECK-NEXT:    vlm.v v0, (a2)
 ; CHECK-NEXT:    vmerge.vvm v26, v28, v26, v0
 ; CHECK-NEXT:    vse32.v v26, (a3)
 ; CHECK-NEXT:    ret
   %va = load <8 x float>, <8 x float>* %a
   %vb = load <8 x float>, <8 x float>* %b
   %vcc = load <8 x i1>, <8 x i1>* %cc
   %vsel = select <8 x i1> %vcc, <8 x float> %va, <8 x float> %vb
   store <8 x float> %vsel, <8 x float>* %z
   ret void
 }
 
 define void @vselect_vx_v8f32(float %a, <8 x float>* %b, <8 x i1>* %cc, <8 x float>* %z) {
 ; CHECK-LABEL: vselect_vx_v8f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, mu
 ; CHECK-NEXT:    vle32.v v26, (a0)
-; CHECK-NEXT:    vle1.v v0, (a1)
+; CHECK-NEXT:    vlm.v v0, (a1)
 ; CHECK-NEXT:    vfmerge.vfm v26, v26, fa0, v0
 ; CHECK-NEXT:    vse32.v v26, (a2)
 ; CHECK-NEXT:    ret
   %vb = load <8 x float>, <8 x float>* %b
   %ahead = insertelement <8 x float> undef, float %a, i32 0
   %va = shufflevector <8 x float> %ahead, <8 x float> undef, <8 x i32> zeroinitializer
   %vcc = load <8 x i1>, <8 x i1>* %cc
   %vsel = select <8 x i1> %vcc, <8 x float> %va, <8 x float> %vb
   store <8 x float> %vsel, <8 x float>* %z
   ret void
 }
 
 define void @vselect_vfpzero_v8f32(<8 x float>* %b, <8 x i1>* %cc, <8 x float>* %z) {
 ; CHECK-LABEL: vselect_vfpzero_v8f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, mu
 ; CHECK-NEXT:    vle32.v v26, (a0)
-; CHECK-NEXT:    vle1.v v0, (a1)
+; CHECK-NEXT:    vlm.v v0, (a1)
 ; CHECK-NEXT:    vmerge.vim v26, v26, 0, v0
 ; CHECK-NEXT:    vse32.v v26, (a2)
 ; CHECK-NEXT:    ret
   %vb = load <8 x float>, <8 x float>* %b
   %a = insertelement <8 x float> undef, float 0.0, i32 0
   %va = shufflevector <8 x float> %a, <8 x float> undef, <8 x i32> zeroinitializer
   %vcc = load <8 x i1>, <8 x i1>* %cc
   %vsel = select <8 x i1> %vcc, <8 x float> %va, <8 x float> %vb
   store <8 x float> %vsel, <8 x float>* %z
   ret void
 }
 
 define void @vselect_vv_v16i16(<16 x i16>* %a, <16 x i16>* %b, <16 x i1>* %cc, <16 x i16>* %z) {
 ; CHECK-LABEL: vselect_vv_v16i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, mu
 ; CHECK-NEXT:    vle16.v v26, (a0)
 ; CHECK-NEXT:    vle16.v v28, (a1)
-; CHECK-NEXT:    vle1.v v0, (a2)
+; CHECK-NEXT:    vlm.v v0, (a2)
 ; CHECK-NEXT:    vmerge.vvm v26, v28, v26, v0
 ; CHECK-NEXT:    vse16.v v26, (a3)
 ; CHECK-NEXT:    ret
   %va = load <16 x i16>, <16 x i16>* %a
   %vb = load <16 x i16>, <16 x i16>* %b
   %vcc = load <16 x i1>, <16 x i1>* %cc
   %vsel = select <16 x i1> %vcc, <16 x i16> %va, <16 x i16> %vb
   store <16 x i16> %vsel, <16 x i16>* %z
   ret void
 }
 
 define void @vselect_vx_v16i16(i16 signext %a, <16 x i16>* %b, <16 x i1>* %cc, <16 x i16>* %z) {
 ; CHECK-LABEL: vselect_vx_v16i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, mu
 ; CHECK-NEXT:    vle16.v v26, (a1)
-; CHECK-NEXT:    vle1.v v0, (a2)
+; CHECK-NEXT:    vlm.v v0, (a2)
 ; CHECK-NEXT:    vmerge.vxm v26, v26, a0, v0
 ; CHECK-NEXT:    vse16.v v26, (a3)
 ; CHECK-NEXT:    ret
   %vb = load <16 x i16>, <16 x i16>* %b
   %ahead = insertelement <16 x i16> undef, i16 %a, i32 0
   %va = shufflevector <16 x i16> %ahead, <16 x i16> undef, <16 x i32> zeroinitializer
   %vcc = load <16 x i1>, <16 x i1>* %cc
   %vsel = select <16 x i1> %vcc, <16 x i16> %va, <16 x i16> %vb
   store <16 x i16> %vsel, <16 x i16>* %z
   ret void
 }
 
 define void @vselect_vi_v16i16(<16 x i16>* %b, <16 x i1>* %cc, <16 x i16>* %z) {
 ; CHECK-LABEL: vselect_vi_v16i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, mu
 ; CHECK-NEXT:    vle16.v v26, (a0)
-; CHECK-NEXT:    vle1.v v0, (a1)
+; CHECK-NEXT:    vlm.v v0, (a1)
 ; CHECK-NEXT:    vmerge.vim v26, v26, 4, v0
 ; CHECK-NEXT:    vse16.v v26, (a2)
 ; CHECK-NEXT:    ret
   %vb = load <16 x i16>, <16 x i16>* %b
   %a = insertelement <16 x i16> undef, i16 4, i32 0
   %va = shufflevector <16 x i16> %a, <16 x i16> undef, <16 x i32> zeroinitializer
   %vcc = load <16 x i1>, <16 x i1>* %cc
   %vsel = select <16 x i1> %vcc, <16 x i16> %va, <16 x i16> %vb
   store <16 x i16> %vsel, <16 x i16>* %z
   ret void
 }
 
 define void @vselect_vv_v32f16(<32 x half>* %a, <32 x half>* %b, <32 x i1>* %cc, <32 x half>* %z) {
 ; CHECK-LABEL: vselect_vv_v32f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a4, zero, 32
 ; CHECK-NEXT:    vsetvli zero, a4, e16, m4, ta, mu
 ; CHECK-NEXT:    vle16.v v28, (a0)
 ; CHECK-NEXT:    vle16.v v8, (a1)
-; CHECK-NEXT:    vle1.v v0, (a2)
+; CHECK-NEXT:    vlm.v v0, (a2)
 ; CHECK-NEXT:    vmerge.vvm v28, v8, v28, v0
 ; CHECK-NEXT:    vse16.v v28, (a3)
 ; CHECK-NEXT:    ret
   %va = load <32 x half>, <32 x half>* %a
   %vb = load <32 x half>, <32 x half>* %b
   %vcc = load <32 x i1>, <32 x i1>* %cc
   %vsel = select <32 x i1> %vcc, <32 x half> %va, <32 x half> %vb
   store <32 x half> %vsel, <32 x half>* %z
   ret void
 }
 
 define void @vselect_vx_v32f16(half %a, <32 x half>* %b, <32 x i1>* %cc, <32 x half>* %z) {
 ; CHECK-LABEL: vselect_vx_v32f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a3, zero, 32
 ; CHECK-NEXT:    vsetvli zero, a3, e16, m4, ta, mu
 ; CHECK-NEXT:    vle16.v v28, (a0)
-; CHECK-NEXT:    vle1.v v0, (a1)
+; CHECK-NEXT:    vlm.v v0, (a1)
 ; CHECK-NEXT:    vfmerge.vfm v28, v28, fa0, v0
 ; CHECK-NEXT:    vse16.v v28, (a2)
 ; CHECK-NEXT:    ret
   %vb = load <32 x half>, <32 x half>* %b
   %ahead = insertelement <32 x half> undef, half %a, i32 0
   %va = shufflevector <32 x half> %ahead, <32 x half> undef, <32 x i32> zeroinitializer
   %vcc = load <32 x i1>, <32 x i1>* %cc
   %vsel = select <32 x i1> %vcc, <32 x half> %va, <32 x half> %vb
   store <32 x half> %vsel, <32 x half>* %z
   ret void
 }
 
 define void @vselect_vfpzero_v32f16(<32 x half>* %b, <32 x i1>* %cc, <32 x half>* %z) {
 ; CHECK-LABEL: vselect_vfpzero_v32f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a3, zero, 32
 ; CHECK-NEXT:    vsetvli zero, a3, e16, m4, ta, mu
 ; CHECK-NEXT:    vle16.v v28, (a0)
-; CHECK-NEXT:    vle1.v v0, (a1)
+; CHECK-NEXT:    vlm.v v0, (a1)
 ; CHECK-NEXT:    vmerge.vim v28, v28, 0, v0
 ; CHECK-NEXT:    vse16.v v28, (a2)
 ; CHECK-NEXT:    ret
   %vb = load <32 x half>, <32 x half>* %b
   %a = insertelement <32 x half> undef, half 0.0, i32 0
   %va = shufflevector <32 x half> %a, <32 x half> undef, <32 x i32> zeroinitializer
   %vcc = load <32 x i1>, <32 x i1>* %cc
   %vsel = select <32 x i1> %vcc, <32 x half> %va, <32 x half> %vb

llvm/test/CodeGen/RISCV/rvv/load-mask.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple riscv32 -mattr=+experimental-v %s -o - \
 ; RUN:     -verify-machineinstrs | FileCheck %s
 ; RUN: llc -mtriple riscv64 -mattr=+experimental-v %s -o - \
 ; RUN:     -verify-machineinstrs | FileCheck %s
 
 define void @test_load_mask_64(<vscale x 64 x i1>* %pa, <vscale x 64 x i1>* %pb) {
 ; CHECK-LABEL: test_load_mask_64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a2, zero, e8, m8, ta, mu
-; CHECK-NEXT:    vle1.v v25, (a0)
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vlm.v v25, (a0)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <vscale x 64 x i1>, <vscale x 64 x i1>* %pa
   store <vscale x 64 x i1> %a, <vscale x 64 x i1>* %pb
   ret void
 }
 
 define void @test_load_mask_32(<vscale x 32 x i1>* %pa, <vscale x 32 x i1>* %pb) {
 ; CHECK-LABEL: test_load_mask_32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a2, zero, e8, m4, ta, mu
-; CHECK-NEXT:    vle1.v v25, (a0)
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vlm.v v25, (a0)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <vscale x 32 x i1>, <vscale x 32 x i1>* %pa
   store <vscale x 32 x i1> %a, <vscale x 32 x i1>* %pb
   ret void
 }
 
 define void @test_load_mask_16(<vscale x 16 x i1>* %pa, <vscale x 16 x i1>* %pb) {
 ; CHECK-LABEL: test_load_mask_16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a2, zero, e8, m2, ta, mu
-; CHECK-NEXT:    vle1.v v25, (a0)
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vlm.v v25, (a0)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <vscale x 16 x i1>, <vscale x 16 x i1>* %pa
   store <vscale x 16 x i1> %a, <vscale x 16 x i1>* %pb
   ret void
 }
 
 define void @test_load_mask_8(<vscale x 8 x i1>* %pa, <vscale x 8 x i1>* %pb) {
 ; CHECK-LABEL: test_load_mask_8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a2, zero, e8, m1, ta, mu
-; CHECK-NEXT:    vle1.v v25, (a0)
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vlm.v v25, (a0)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <vscale x 8 x i1>, <vscale x 8 x i1>* %pa
   store <vscale x 8 x i1> %a, <vscale x 8 x i1>* %pb
   ret void
 }
 
 define void @test_load_mask_4(<vscale x 4 x i1>* %pa, <vscale x 4 x i1>* %pb) {
 ; CHECK-LABEL: test_load_mask_4:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a2, zero, e8, mf2, ta, mu
-; CHECK-NEXT:    vle1.v v25, (a0)
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vlm.v v25, (a0)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <vscale x 4 x i1>, <vscale x 4 x i1>* %pa
   store <vscale x 4 x i1> %a, <vscale x 4 x i1>* %pb
   ret void
 }
 
 define void @test_load_mask_2(<vscale x 2 x i1>* %pa, <vscale x 2 x i1>* %pb) {
 ; CHECK-LABEL: test_load_mask_2:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a2, zero, e8, mf4, ta, mu
-; CHECK-NEXT:    vle1.v v25, (a0)
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vlm.v v25, (a0)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <vscale x 2 x i1>, <vscale x 2 x i1>* %pa
   store <vscale x 2 x i1> %a, <vscale x 2 x i1>* %pb
   ret void
 }
 
 define void @test_load_mask_1(<vscale x 1 x i1>* %pa, <vscale x 1 x i1>* %pb) {
 ; CHECK-LABEL: test_load_mask_1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a2, zero, e8, mf8, ta, mu
-; CHECK-NEXT:    vle1.v v25, (a0)
-; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    vlm.v v25, (a0)
+; CHECK-NEXT:    vsm.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <vscale x 1 x i1>, <vscale x 1 x i1>* %pa
   store <vscale x 1 x i1> %a, <vscale x 1 x i1>* %pb
   ret void
 }

llvm/test/CodeGen/RISCV/rvv/unaligned-loads-stores.ll

; CHECK-NEXT:    ret
   ret <vscale x 2 x i64> %v
 }
 
 ; Masks should always be aligned
 define <vscale x 1 x i1> @unaligned_load_nxv1i1_a1(<vscale x 1 x i1>* %ptr) {
 ; CHECK-LABEL: unaligned_load_nxv1i1_a1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, mu
-; CHECK-NEXT:    vle1.v v0, (a0)
+; CHECK-NEXT:    vlm.v v0, (a0)
 ; CHECK-NEXT:    ret
   %v = load <vscale x 1 x i1>, <vscale x 1 x i1>* %ptr, align 1
   ret <vscale x 1 x i1> %v
 }
 
 define <vscale x 4 x float> @unaligned_load_nxv4f32_a1(<vscale x 4 x float>* %ptr) {
 ; CHECK-LABEL: unaligned_load_nxv4f32_a1:
 ; CHECK:       # %bb.0:

llvm/test/CodeGen/RISCV/rvv/vle1-rv32.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \
 ; RUN:   < %s | FileCheck %s
 
-declare <vscale x 1 x i1> @llvm.riscv.vle1.nxv1i1(<vscale x 1 x i1>*, i32);
+declare <vscale x 1 x i1> @llvm.riscv.vlm.nxv1i1(<vscale x 1 x i1>*, i32);
 
-define <vscale x 1 x i1> @intrinsic_vle1_v_nxv1i1(<vscale x 1 x i1>* %0, i32 %1) nounwind {
-; CHECK-LABEL: intrinsic_vle1_v_nxv1i1:
+define <vscale x 1 x i1> @intrinsic_vlm_v_nxv1i1(<vscale x 1 x i1>* %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_vlm_v_nxv1i1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT:    vle1.v v0, (a0)
+; CHECK-NEXT:    vlm.v v0, (a0)
 ; CHECK-NEXT:    ret
 entry:
-  %a = call <vscale x 1 x i1> @llvm.riscv.vle1.nxv1i1(<vscale x 1 x i1>* %0, i32 %1)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vlm.nxv1i1(<vscale x 1 x i1>* %0, i32 %1)
   ret <vscale x 1 x i1> %a
 }
 
-declare <vscale x 2 x i1> @llvm.riscv.vle1.nxv2i1(<vscale x 2 x i1>*, i32);
+declare <vscale x 2 x i1> @llvm.riscv.vlm.nxv2i1(<vscale x 2 x i1>*, i32);
 
-define <vscale x 2 x i1> @intrinsic_vle1_v_nxv2i1(<vscale x 2 x i1>* %0, i32 %1) nounwind {
-; CHECK-LABEL: intrinsic_vle1_v_nxv2i1:
+define <vscale x 2 x i1> @intrinsic_vlm_v_nxv2i1(<vscale x 2 x i1>* %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_vlm_v_nxv2i1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT:    vle1.v v0, (a0)
+; CHECK-NEXT:    vlm.v v0, (a0)
 ; CHECK-NEXT:    ret
 entry:
-  %a = call <vscale x 2 x i1> @llvm.riscv.vle1.nxv2i1(<vscale x 2 x i1>* %0, i32 %1)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vlm.nxv2i1(<vscale x 2 x i1>* %0, i32 %1)
   ret <vscale x 2 x i1> %a
 }
 
-declare <vscale x 4 x i1> @llvm.riscv.vle1.nxv4i1(<vscale x 4 x i1>*, i32);
+declare <vscale x 4 x i1> @llvm.riscv.vlm.nxv4i1(<vscale x 4 x i1>*, i32);
 
-define <vscale x 4 x i1> @intrinsic_vle1_v_nxv4i1(<vscale x 4 x i1>* %0, i32 %1) nounwind {
-; CHECK-LABEL: intrinsic_vle1_v_nxv4i1:
+define <vscale x 4 x i1> @intrinsic_vlm_v_nxv4i1(<vscale x 4 x i1>* %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_vlm_v_nxv4i1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT:    vle1.v v0, (a0)
+; CHECK-NEXT:    vlm.v v0, (a0)
 ; CHECK-NEXT:    ret
 entry:
-  %a = call <vscale x 4 x i1> @llvm.riscv.vle1.nxv4i1(<vscale x 4 x i1>* %0, i32 %1)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vlm.nxv4i1(<vscale x 4 x i1>* %0, i32 %1)
   ret <vscale x 4 x i1> %a
 }
 
-declare <vscale x 8 x i1> @llvm.riscv.vle1.nxv8i1(<vscale x 8 x i1>*, i32);
+declare <vscale x 8 x i1> @llvm.riscv.vlm.nxv8i1(<vscale x 8 x i1>*, i32);
 
-define <vscale x 8 x i1> @intrinsic_vle1_v_nxv8i1(<vscale x 8 x i1>* %0, i32 %1) nounwind {
-; CHECK-LABEL: intrinsic_vle1_v_nxv8i1:
+define <vscale x 8 x i1> @intrinsic_vlm_v_nxv8i1(<vscale x 8 x i1>* %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_vlm_v_nxv8i1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT:    vle1.v v0, (a0)
+; CHECK-NEXT:    vlm.v v0, (a0)
 ; CHECK-NEXT:    ret
 entry:
-  %a = call <vscale x 8 x i1> @llvm.riscv.vle1.nxv8i1(<vscale x 8 x i1>* %0, i32 %1)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vlm.nxv8i1(<vscale x 8 x i1>* %0, i32 %1)
   ret <vscale x 8 x i1> %a
 }
 
-declare <vscale x 16 x i1> @llvm.riscv.vle1.nxv16i1(<vscale x 16 x i1>*, i32);
+declare <vscale x 16 x i1> @llvm.riscv.vlm.nxv16i1(<vscale x 16 x i1>*, i32);
 
-define <vscale x 16 x i1> @intrinsic_vle1_v_nxv16i1(<vscale x 16 x i1>* %0, i32 %1) nounwind {
-; CHECK-LABEL: intrinsic_vle1_v_nxv16i1:
+define <vscale x 16 x i1> @intrinsic_vlm_v_nxv16i1(<vscale x 16 x i1>* %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_vlm_v_nxv16i1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT:    vle1.v v0, (a0)
+; CHECK-NEXT:    vlm.v v0, (a0)
 ; CHECK-NEXT:    ret
 entry:
-  %a = call <vscale x 16 x i1> @llvm.riscv.vle1.nxv16i1(<vscale x 16 x i1>* %0, i32 %1)
+  %a = call <vscale x 16 x i1> @llvm.riscv.vlm.nxv16i1(<vscale x 16 x i1>* %0, i32 %1)
   ret <vscale x 16 x i1> %a
 }
 
-declare <vscale x 32 x i1> @llvm.riscv.vle1.nxv32i1(<vscale x 32 x i1>*, i32);
+declare <vscale x 32 x i1> @llvm.riscv.vlm.nxv32i1(<vscale x 32 x i1>*, i32);
 
-define <vscale x 32 x i1> @intrinsic_vle1_v_nxv32i1(<vscale x 32 x i1>* %0, i32 %1) nounwind {
-; CHECK-LABEL: intrinsic_vle1_v_nxv32i1:
+define <vscale x 32 x i1> @intrinsic_vlm_v_nxv32i1(<vscale x 32 x i1>* %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_vlm_v_nxv32i1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT:    vle1.v v0, (a0)
+; CHECK-NEXT:    vlm.v v0, (a0)
 ; CHECK-NEXT:    ret
 entry:
-  %a = call <vscale x 32 x i1> @llvm.riscv.vle1.nxv32i1(<vscale x 32 x i1>* %0, i32 %1)
+  %a = call <vscale x 32 x i1> @llvm.riscv.vlm.nxv32i1(<vscale x 32 x i1>* %0, i32 %1)
   ret <vscale x 32 x i1> %a
 }
 
-declare <vscale x 64 x i1> @llvm.riscv.vle1.nxv64i1(<vscale x 64 x i1>*, i32);
+declare <vscale x 64 x i1> @llvm.riscv.vlm.nxv64i1(<vscale x 64 x i1>*, i32);
 
-define <vscale x 64 x i1> @intrinsic_vle1_v_nxv64i1(<vscale x 64 x i1>* %0, i32 %1) nounwind {
-; CHECK-LABEL: intrinsic_vle1_v_nxv64i1:
+define <vscale x 64 x i1> @intrinsic_vlm_v_nxv64i1(<vscale x 64 x i1>* %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_vlm_v_nxv64i1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, mu
-; CHECK-NEXT:    vle1.v v0, (a0)
+; CHECK-NEXT:    vlm.v v0, (a0)
 ; CHECK-NEXT:    ret
 entry:
-  %a = call <vscale x 64 x i1> @llvm.riscv.vle1.nxv64i1(<vscale x 64 x i1>* %0, i32 %1)
+  %a = call <vscale x 64 x i1> @llvm.riscv.vlm.nxv64i1(<vscale x 64 x i1>* %0, i32 %1)
   ret <vscale x 64 x i1> %a
 }

llvm/test/CodeGen/RISCV/rvv/vle1-rv64.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \
 ; RUN:   < %s | FileCheck %s
 
-declare <vscale x 1 x i1> @llvm.riscv.vle1.nxv1i1(<vscale x 1 x i1>*, i64);
+declare <vscale x 1 x i1> @llvm.riscv.vlm.nxv1i1(<vscale x 1 x i1>*, i64);
 
-define <vscale x 1 x i1> @intrinsic_vle1_v_nxv1i1(<vscale x 1 x i1>* %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vle1_v_nxv1i1:
+define <vscale x 1 x i1> @intrinsic_vlm_v_nxv1i1(<vscale x 1 x i1>* %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vlm_v_nxv1i1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT:    vle1.v v0, (a0)
+; CHECK-NEXT:    vlm.v v0, (a0)
 ; CHECK-NEXT:    ret
 entry:
-  %a = call <vscale x 1 x i1> @llvm.riscv.vle1.nxv1i1(<vscale x 1 x i1>* %0, i64 %1)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vlm.nxv1i1(<vscale x 1 x i1>* %0, i64 %1)
   ret <vscale x 1 x i1> %a
 }
 
-declare <vscale x 2 x i1> @llvm.riscv.vle1.nxv2i1(<vscale x 2 x i1>*, i64);
+declare <vscale x 2 x i1> @llvm.riscv.vlm.nxv2i1(<vscale x 2 x i1>*, i64);
 
-define <vscale x 2 x i1> @intrinsic_vle1_v_nxv2i1(<vscale x 2 x i1>* %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vle1_v_nxv2i1:
+define <vscale x 2 x i1> @intrinsic_vlm_v_nxv2i1(<vscale x 2 x i1>* %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vlm_v_nxv2i1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT:    vle1.v v0, (a0)
+; CHECK-NEXT:    vlm.v v0, (a0)
 ; CHECK-NEXT:    ret
 entry:
-  %a = call <vscale x 2 x i1> @llvm.riscv.vle1.nxv2i1(<vscale x 2 x i1>* %0, i64 %1)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vlm.nxv2i1(<vscale x 2 x i1>* %0, i64 %1)
   ret <vscale x 2 x i1> %a
 }
 
-declare <vscale x 4 x i1> @llvm.riscv.vle1.nxv4i1(<vscale x 4 x i1>*, i64);
+declare <vscale x 4 x i1> @llvm.riscv.vlm.nxv4i1(<vscale x 4 x i1>*, i64);
 
-define <vscale x 4 x i1> @intrinsic_vle1_v_nxv4i1(<vscale x 4 x i1>* %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vle1_v_nxv4i1:
+define <vscale x 4 x i1> @intrinsic_vlm_v_nxv4i1(<vscale x 4 x i1>* %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vlm_v_nxv4i1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT:    vle1.v v0, (a0)
+; CHECK-NEXT:    vlm.v v0, (a0)
 ; CHECK-NEXT:    ret
 entry:
-  %a = call <vscale x 4 x i1> @llvm.riscv.vle1.nxv4i1(<vscale x 4 x i1>* %0, i64 %1)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vlm.nxv4i1(<vscale x 4 x i1>* %0, i64 %1)
   ret <vscale x 4 x i1> %a
 }
 
-declare <vscale x 8 x i1> @llvm.riscv.vle1.nxv8i1(<vscale x 8 x i1>*, i64);
+declare <vscale x 8 x i1> @llvm.riscv.vlm.nxv8i1(<vscale x 8 x i1>*, i64);
 
-define <vscale x 8 x i1> @intrinsic_vle1_v_nxv8i1(<vscale x 8 x i1>* %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vle1_v_nxv8i1:
+define <vscale x 8 x i1> @intrinsic_vlm_v_nxv8i1(<vscale x 8 x i1>* %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vlm_v_nxv8i1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT:    vle1.v v0, (a0)
+; CHECK-NEXT:    vlm.v v0, (a0)
 ; CHECK-NEXT:    ret
 entry:
-  %a = call <vscale x 8 x i1> @llvm.riscv.vle1.nxv8i1(<vscale x 8 x i1>* %0, i64 %1)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vlm.nxv8i1(<vscale x 8 x i1>* %0, i64 %1)
   ret <vscale x 8 x i1> %a
 }
 
-declare <vscale x 16 x i1> @llvm.riscv.vle1.nxv16i1(<vscale x 16 x i1>*, i64);
+declare <vscale x 16 x i1> @llvm.riscv.vlm.nxv16i1(<vscale x 16 x i1>*, i64);
 
-define <vscale x 16 x i1> @intrinsic_vle1_v_nxv16i1(<vscale x 16 x i1>* %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vle1_v_nxv16i1:
+define <vscale x 16 x i1> @intrinsic_vlm_v_nxv16i1(<vscale x 16 x i1>* %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vlm_v_nxv16i1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT:    vle1.v v0, (a0)
+; CHECK-NEXT:    vlm.v v0, (a0)
 ; CHECK-NEXT:    ret
 entry:
-  %a = call <vscale x 16 x i1> @llvm.riscv.vle1.nxv16i1(<vscale x 16 x i1>* %0, i64 %1)
+  %a = call <vscale x 16 x i1> @llvm.riscv.vlm.nxv16i1(<vscale x 16 x i1>* %0, i64 %1)
   ret <vscale x 16 x i1> %a
 }
 
-declare <vscale x 32 x i1> @llvm.riscv.vle1.nxv32i1(<vscale x 32 x i1>*, i64);
+declare <vscale x 32 x i1> @llvm.riscv.vlm.nxv32i1(<vscale x 32 x i1>*, i64);
 
-define <vscale x 32 x i1> @intrinsic_vle1_v_nxv32i1(<vscale x 32 x i1>* %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vle1_v_nxv32i1:
+define <vscale x 32 x i1> @intrinsic_vlm_v_nxv32i1(<vscale x 32 x i1>* %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vlm_v_nxv32i1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT:    vle1.v v0, (a0)
+; CHECK-NEXT:    vlm.v v0, (a0)
 ; CHECK-NEXT:    ret
 entry:
-  %a = call <vscale x 32 x i1> @llvm.riscv.vle1.nxv32i1(<vscale x 32 x i1>* %0, i64 %1)
+  %a = call <vscale x 32 x i1> @llvm.riscv.vlm.nxv32i1(<vscale x 32 x i1>* %0, i64 %1)
   ret <vscale x 32 x i1> %a
 }
 
-declare <vscale x 64 x i1> @llvm.riscv.vle1.nxv64i1(<vscale x 64 x i1>*, i64);
+declare <vscale x 64 x i1> @llvm.riscv.vlm.nxv64i1(<vscale x 64 x i1>*, i64);
 
-define <vscale x 64 x i1> @intrinsic_vle1_v_nxv64i1(<vscale x 64 x i1>* %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vle1_v_nxv64i1:
+define <vscale x 64 x i1> @intrinsic_vlm_v_nxv64i1(<vscale x 64 x i1>* %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vlm_v_nxv64i1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, mu
-; CHECK-NEXT:    vle1.v v0, (a0)
+; CHECK-NEXT:    vlm.v v0, (a0)
 ; CHECK-NEXT:    ret
 entry:
-  %a = call <vscale x 64 x i1> @llvm.riscv.vle1.nxv64i1(<vscale x 64 x i1>* %0, i64 %1)
+  %a = call <vscale x 64 x i1> @llvm.riscv.vlm.nxv64i1(<vscale x 64 x i1>* %0, i64 %1)
   ret <vscale x 64 x i1> %a
 }

llvm/test/CodeGen/RISCV/rvv/vse1-rv32.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \
 ; RUN:   < %s | FileCheck %s
 
-declare void @llvm.riscv.vse1.nxv1i1(<vscale x 1 x i1>, <vscale x 1 x i1>*, i32);
+declare void @llvm.riscv.vsm.nxv1i1(<vscale x 1 x i1>, <vscale x 1 x i1>*, i32);
 
-define void @intrinsic_vse1_v_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1>* %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vse1_v_nxv1i1:
+define void @intrinsic_vsm_v_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1>* %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vsm_v_nxv1i1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT:    vse1.v v0, (a0)
+; CHECK-NEXT:    vsm.v v0, (a0)
 ; CHECK-NEXT:    ret
 entry:
-  call void @llvm.riscv.vse1.nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1>* %1, i32 %2)
+  call void @llvm.riscv.vsm.nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1>* %1, i32 %2)
   ret void
 }
 
-declare void @llvm.riscv.vse1.nxv2i1(<vscale x 2 x i1>, <vscale x 2 x i1>*, i32);
+declare void @llvm.riscv.vsm.nxv2i1(<vscale x 2 x i1>, <vscale x 2 x i1>*, i32);
 
-define void @intrinsic_vse1_v_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1>* %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vse1_v_nxv2i1:
+define void @intrinsic_vsm_v_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1>* %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vsm_v_nxv2i1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT:    vse1.v v0, (a0)
+; CHECK-NEXT:    vsm.v v0, (a0)
 ; CHECK-NEXT:    ret
 entry:
-  call void @llvm.riscv.vse1.nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1>* %1, i32 %2)
+  call void @llvm.riscv.vsm.nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1>* %1, i32 %2)
   ret void
 }
 
-declare void @llvm.riscv.vse1.nxv4i1(<vscale x 4 x i1>, <vscale x 4 x i1>*, i32);
+declare void @llvm.riscv.vsm.nxv4i1(<vscale x 4 x i1>, <vscale x 4 x i1>*, i32);
 
-define void @intrinsic_vse1_v_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1>* %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vse1_v_nxv4i1:
+define void @intrinsic_vsm_v_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1>* %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vsm_v_nxv4i1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT:    vse1.v v0, (a0)
+; CHECK-NEXT:    vsm.v v0, (a0)
 ; CHECK-NEXT:    ret
 entry:
-  call void @llvm.riscv.vse1.nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1>* %1, i32 %2)
+  call void @llvm.riscv.vsm.nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1>* %1, i32 %2)
   ret void
 }
 
-declare void @llvm.riscv.vse1.nxv8i1(<vscale x 8 x i1>, <vscale x 8 x i1>*, i32);
+declare void @llvm.riscv.vsm.nxv8i1(<vscale x 8 x i1>, <vscale x 8 x i1>*, i32);
 
-define void @intrinsic_vse1_v_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1>* %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vse1_v_nxv8i1:
+define void @intrinsic_vsm_v_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1>* %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vsm_v_nxv8i1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT:    vse1.v v0, (a0)
+; CHECK-NEXT:    vsm.v v0, (a0)
 ; CHECK-NEXT:    ret
 entry:
-  call void @llvm.riscv.vse1.nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1>* %1, i32 %2)
+  call void @llvm.riscv.vsm.nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1>* %1, i32 %2)
   ret void
 }
 
-declare void @llvm.riscv.vse1.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>*, i32);
+declare void @llvm.riscv.vsm.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>*, i32);
 
-define void @intrinsic_vse1_v_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1>* %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vse1_v_nxv16i1:
+define void @intrinsic_vsm_v_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1>* %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vsm_v_nxv16i1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT:    vse1.v v0, (a0)
+; CHECK-NEXT:    vsm.v v0, (a0)
 ; CHECK-NEXT:    ret
 entry:
-  call void @llvm.riscv.vse1.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1>* %1, i32 %2)
+  call void @llvm.riscv.vsm.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1>* %1, i32 %2)
   ret void
 }
 
-declare void @llvm.riscv.vse1.nxv32i1(<vscale x 32 x i1>, <vscale x 32 x i1>*, i32);
+declare void @llvm.riscv.vsm.nxv32i1(<vscale x 32 x i1>, <vscale x 32 x i1>*, i32);
 
-define void @intrinsic_vse1_v_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1>* %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vse1_v_nxv32i1:
+define void @intrinsic_vsm_v_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1>* %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vsm_v_nxv32i1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT:    vse1.v v0, (a0)
+; CHECK-NEXT:    vsm.v v0, (a0)
 ; CHECK-NEXT:    ret
 entry:
-  call void @llvm.riscv.vse1.nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1>* %1, i32 %2)
+  call void @llvm.riscv.vsm.nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1>* %1, i32 %2)
   ret void
 }
 
-declare void @llvm.riscv.vse1.nxv64i1(<vscale x 64 x i1>, <vscale x 64 x i1>*, i32);
+declare void @llvm.riscv.vsm.nxv64i1(<vscale x 64 x i1>, <vscale x 64 x i1>*, i32);
 
-define void @intrinsic_vse1_v_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1>* %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vse1_v_nxv64i1:
+define void @intrinsic_vsm_v_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1>* %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vsm_v_nxv64i1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, mu
-; CHECK-NEXT:    vse1.v v0, (a0)
+; CHECK-NEXT:    vsm.v v0, (a0)
 ; CHECK-NEXT:    ret
 entry:
-  call void @llvm.riscv.vse1.nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1>* %1, i32 %2)
+  call void @llvm.riscv.vsm.nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1>* %1, i32 %2)
   ret void
 }
 
 declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i16(
   <vscale x 1 x i16>,
   <vscale x 1 x i16>,
   i32);
 
 ; Make sure we can use the vsetvli from the producing instruction.
 define void @test_vsetvli_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1>* %2, i32 %3) nounwind {
 ; CHECK-LABEL: test_vsetvli_i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, mu
 ; CHECK-NEXT:    vmseq.vv v25, v8, v9
-; CHECK-NEXT:    vse1.v v25, (a0)
+; CHECK-NEXT:    vsm.v v25, (a0)
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i16(
     <vscale x 1 x i16> %0,
     <vscale x 1 x i16> %1,
     i32 %3)
-  call void @llvm.riscv.vse1.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1>* %2, i32 %3)
+  call void @llvm.riscv.vsm.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1>* %2, i32 %3)
   ret void
 }
 
 declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i32(
   <vscale x 1 x i32>,
   <vscale x 1 x i32>,
   i32);
 
 define void @test_vsetvli_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1>* %2, i32 %3) nounwind {
 ; CHECK-LABEL: test_vsetvli_i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, mu
 ; CHECK-NEXT:    vmseq.vv v25, v8, v9
-; CHECK-NEXT:    vse1.v v25, (a0)
+; CHECK-NEXT:    vsm.v v25, (a0)
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i32(
     <vscale x 1 x i32> %0,
     <vscale x 1 x i32> %1,
     i32 %3)
-  call void @llvm.riscv.vse1.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1>* %2, i32 %3)
+  call void @llvm.riscv.vsm.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1>* %2, i32 %3)
   ret void
 }

llvm/test/CodeGen/RISCV/rvv/vse1-rv64.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \
 ; RUN:   < %s | FileCheck %s
 
-declare void @llvm.riscv.vse1.nxv1i1(<vscale x 1 x i1>, <vscale x 1 x i1>*, i64);
+declare void @llvm.riscv.vsm.nxv1i1(<vscale x 1 x i1>, <vscale x 1 x i1>*, i64);
 
-define void @intrinsic_vse1_v_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1>* %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vse1_v_nxv1i1:
+define void @intrinsic_vsm_v_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1>* %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vsm_v_nxv1i1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT:    vse1.v v0, (a0)
+; CHECK-NEXT:    vsm.v v0, (a0)
 ; CHECK-NEXT:    ret
 entry:
-  call void @llvm.riscv.vse1.nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1>* %1, i64 %2)
+  call void @llvm.riscv.vsm.nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1>* %1, i64 %2)
   ret void
 }
 
-declare void @llvm.riscv.vse1.nxv2i1(<vscale x 2 x i1>, <vscale x 2 x i1>*, i64);
+declare void @llvm.riscv.vsm.nxv2i1(<vscale x 2 x i1>, <vscale x 2 x i1>*, i64);
 
-define void @intrinsic_vse1_v_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1>* %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vse1_v_nxv2i1:
+define void @intrinsic_vsm_v_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1>* %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vsm_v_nxv2i1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT:    vse1.v v0, (a0)
+; CHECK-NEXT:    vsm.v v0, (a0)
 ; CHECK-NEXT:    ret
 entry:
-  call void @llvm.riscv.vse1.nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1>* %1, i64 %2)
+  call void @llvm.riscv.vsm.nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1>* %1, i64 %2)
   ret void
 }
 
-declare void @llvm.riscv.vse1.nxv4i1(<vscale x 4 x i1>, <vscale x 4 x i1>*, i64);
+declare void @llvm.riscv.vsm.nxv4i1(<vscale x 4 x i1>, <vscale x 4 x i1>*, i64);
 
-define void @intrinsic_vse1_v_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1>* %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vse1_v_nxv4i1:
+define void @intrinsic_vsm_v_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1>* %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vsm_v_nxv4i1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT:    vse1.v v0, (a0)
+; CHECK-NEXT:    vsm.v v0, (a0)
 ; CHECK-NEXT:    ret
 entry:
-  call void @llvm.riscv.vse1.nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1>* %1, i64 %2)
+  call void @llvm.riscv.vsm.nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1>* %1, i64 %2)
   ret void
 }
 
-declare void @llvm.riscv.vse1.nxv8i1(<vscale x 8 x i1>, <vscale x 8 x i1>*, i64);
+declare void @llvm.riscv.vsm.nxv8i1(<vscale x 8 x i1>, <vscale x 8 x i1>*, i64);
 
-define void @intrinsic_vse1_v_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1>* %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vse1_v_nxv8i1:
+define void @intrinsic_vsm_v_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1>* %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vsm_v_nxv8i1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT:    vse1.v v0, (a0)
+; CHECK-NEXT:    vsm.v v0, (a0)
 ; CHECK-NEXT:    ret
 entry:
-  call void @llvm.riscv.vse1.nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1>* %1, i64 %2)
+  call void @llvm.riscv.vsm.nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1>* %1, i64 %2)
   ret void
 }
 
-declare void @llvm.riscv.vse1.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>*, i64);
+declare void @llvm.riscv.vsm.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>*, i64);
 
-define void @intrinsic_vse1_v_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1>* %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vse1_v_nxv16i1:
+define void @intrinsic_vsm_v_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1>* %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vsm_v_nxv16i1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT:    vse1.v v0, (a0)
+; CHECK-NEXT:    vsm.v v0, (a0)
 ; CHECK-NEXT:    ret
 entry:
-  call void @llvm.riscv.vse1.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1>* %1, i64 %2)
+  call void @llvm.riscv.vsm.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1>* %1, i64 %2)
   ret void
 }
 
-declare void @llvm.riscv.vse1.nxv32i1(<vscale x 32 x i1>, <vscale x 32 x i1>*, i64);
+declare void @llvm.riscv.vsm.nxv32i1(<vscale x 32 x i1>, <vscale x 32 x i1>*, i64);
 
-define void @intrinsic_vse1_v_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1>* %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vse1_v_nxv32i1:
+define void @intrinsic_vsm_v_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1>* %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vsm_v_nxv32i1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT:    vse1.v v0, (a0)
+; CHECK-NEXT:    vsm.v v0, (a0)
 ; CHECK-NEXT:    ret
 entry:
-  call void @llvm.riscv.vse1.nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1>* %1, i64 %2)
+  call void @llvm.riscv.vsm.nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1>* %1, i64 %2)
   ret void
 }
 
-declare void @llvm.riscv.vse1.nxv64i1(<vscale x 64 x i1>, <vscale x 64 x i1>*, i64);
+declare void @llvm.riscv.vsm.nxv64i1(<vscale x 64 x i1>, <vscale x 64 x i1>*, i64);
 
-define void @intrinsic_vse1_v_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1>* %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vse1_v_nxv64i1:
+define void @intrinsic_vsm_v_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1>* %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vsm_v_nxv64i1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, mu
-; CHECK-NEXT:    vse1.v v0, (a0)
+; CHECK-NEXT:    vsm.v v0, (a0)
 ; CHECK-NEXT:    ret
 entry:
-  call void @llvm.riscv.vse1.nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1>* %1, i64 %2)
+  call void @llvm.riscv.vsm.nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1>* %1, i64 %2)
   ret void
 }
 
 declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i16(
   <vscale x 1 x i16>,
   <vscale x 1 x i16>,
   i64);
 
 ; Make sure we can use the vsetvli from the producing instruction.
 define void @test_vsetvli_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1>* %2, i64 %3) nounwind {
 ; CHECK-LABEL: test_vsetvli_i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, mu
 ; CHECK-NEXT:    vmseq.vv v25, v8, v9
-; CHECK-NEXT:    vse1.v v25, (a0)
+; CHECK-NEXT:    vsm.v v25, (a0)
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i16(
     <vscale x 1 x i16> %0,
     <vscale x 1 x i16> %1,
     i64 %3)
-  call void @llvm.riscv.vse1.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1>* %2, i64 %3)
+  call void @llvm.riscv.vsm.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1>* %2, i64 %3)
   ret void
 }
 
 declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i32(
   <vscale x 1 x i32>,
   <vscale x 1 x i32>,
   i64);
 
 define void @test_vsetvli_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1>* %2, i64 %3) nounwind {
 ; CHECK-LABEL: test_vsetvli_i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, mu
 ; CHECK-NEXT:    vmseq.vv v25, v8, v9
-; CHECK-NEXT:    vse1.v v25, (a0)
+; CHECK-NEXT:    vsm.v v25, (a0)
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i32(
     <vscale x 1 x i32> %0,
     <vscale x 1 x i32> %1,
     i64 %3)
-  call void @llvm.riscv.vse1.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1>* %2, i64 %3)
+  call void @llvm.riscv.vsm.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1>* %2, i64 %3)
   ret void
 }

llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv32.ll

; CHECK-NEXT:    ret
   %sel = select <vscale x 16 x i1> %cond, <vscale x 16 x double> %vb, <vscale x 16 x double> zeroinitializer
   ret <vscale x 16 x double> %sel
 }
 
 define void @vselect_legalize_regression(<vscale x 16 x double> %a, <vscale x 16 x i1> %ma, <vscale x 16 x i1> %mb, <vscale x 16 x double>* %out) {
 ; CHECK-LABEL: vselect_legalize_regression:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a2, zero, e8, m2, ta, mu
-; CHECK-NEXT:    vle1.v v25, (a0)
+; CHECK-NEXT:    vlm.v v25, (a0)
 ; CHECK-NEXT:    vmand.mm v25, v0, v25
 ; CHECK-NEXT:    csrr a0, vlenb
 ; CHECK-NEXT:    srli a0, a0, 3
 ; CHECK-NEXT:    vsetvli a2, zero, e8, mf4, ta, mu
 ; CHECK-NEXT:    vslidedown.vx v0, v25, a0
 ; CHECK-NEXT:    vmv1r.v v2, v25
 ; CHECK-NEXT:    vsetvli a2, zero, e64, m8, ta, mu
 ; CHECK-NEXT:    vmv.v.i v24, 0

llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv64.ll

; CHECK-NEXT:    ret
   %sel = select <vscale x 16 x i1> %cond, <vscale x 16 x double> %vb, <vscale x 16 x double> zeroinitializer
   ret <vscale x 16 x double> %sel
 }
 
 define void @vselect_legalize_regression(<vscale x 16 x double> %a, <vscale x 16 x i1> %ma, <vscale x 16 x i1> %mb, <vscale x 16 x double>* %out) {
 ; CHECK-LABEL: vselect_legalize_regression:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a2, zero, e8, m2, ta, mu
-; CHECK-NEXT:    vle1.v v25, (a0)
+; CHECK-NEXT:    vlm.v v25, (a0)
 ; CHECK-NEXT:    vmand.mm v25, v0, v25
 ; CHECK-NEXT:    csrr a0, vlenb
 ; CHECK-NEXT:    srli a0, a0, 3
 ; CHECK-NEXT:    vsetvli a2, zero, e8, mf4, ta, mu
 ; CHECK-NEXT:    vslidedown.vx v0, v25, a0
 ; CHECK-NEXT:    vmv1r.v v2, v25
 ; CHECK-NEXT:    vsetvli a2, zero, e64, m8, ta, mu
 ; CHECK-NEXT:    vmv.v.i v24, 0

llvm/test/MC/RISCV/rvv/aliases.s

 # NO-ALIAS: vnsrl.wx        v2, v1, zero, v0.t # encoding: [0x57,0x41,0x10,0xb0]
 vncvt.x.x.w v2, v1, v0.t 
 # ALIAS:    vfneg.v         v2, v1, v0.t     # encoding: [0x57,0x91,0x10,0x24]
 # NO-ALIAS: vfsgnjn.vv      v2, v1, v1, v0.t # encoding: [0x57,0x91,0x10,0x24]
 vfneg.v v2, v1, v0.t 
 # ALIAS:    vfabs.v         v2, v1, v0.t     # encoding: [0x57,0x91,0x10,0x28]
 # NO-ALIAS: vfsgnjx.vv      v2, v1, v1, v0.t # encoding: [0x57,0x91,0x10,0x28]
 vfabs.v v2, v1, v0.t
+# ALIAS:    vle1.v          v8, (a0)         # encoding: [0x07,0x04,0xb5,0x02]
+# NO-ALIAS: vlm.v           v8, (a0)         # encoding: [0x07,0x04,0xb5,0x02]
+vle1.v v8, (a0)
+# ALIAS:    vse1.v          v8, (a0)         # encoding: [0x27,0x04,0xb5,0x02]
+# NO-ALIAS: vsm.v           v8, (a0)         # encoding: [0x27,0x04,0xb5,0x02]
+vse1.v v8, (a0)

llvm/test/MC/RISCV/rvv/load.s

 # RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
 # RUN:   --riscv-no-aliases | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 # RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
 # RUN:   | FileCheck %s --check-prefix=CHECK-ERROR
 # RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
 # RUN:   | llvm-objdump -d --mattr=+experimental-v -M no-aliases - \
 # RUN:   | FileCheck %s --check-prefix=CHECK-INST
 # RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
 # RUN:   | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
-vle1.v v0, (a0)
-# CHECK-INST: vle1.v v0, (a0)
+vlm.v v0, (a0)
+# CHECK-INST: vlm.v v0, (a0)
 # CHECK-ENCODING: [0x07,0x00,0xb5,0x02]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 07 00 b5 02 <unknown>
 
-vle1.v v8, (a0)
-# CHECK-INST: vle1.v v8, (a0)
+vlm.v v8, (a0)
+# CHECK-INST: vlm.v v8, (a0)
 # CHECK-ENCODING: [0x07,0x04,0xb5,0x02]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 07 04 b5 02 <unknown>
 
 vle8.v v8, (a0), v0.t
 # CHECK-INST: vle8.v v8, (a0), v0.t
 # CHECK-ENCODING: [0x07,0x04,0x05,0x00]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)

llvm/test/MC/RISCV/rvv/store.s

 # RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
 # RUN:   --riscv-no-aliases | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 # RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
 # RUN:   | FileCheck %s --check-prefix=CHECK-ERROR
 # RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
 # RUN:   | llvm-objdump -d --mattr=+experimental-v -M no-aliases - \
 # RUN:   | FileCheck %s --check-prefix=CHECK-INST
 # RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
 # RUN:   | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
-vse1.v v24, (a0)
-# CHECK-INST: vse1.v v24, (a0)
+vsm.v v24, (a0)
+# CHECK-INST: vsm.v v24, (a0)
 # CHECK-ENCODING: [0x27,0x0c,0xb5,0x02]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 0c b5 02 <unknown>
 
 vse8.v v24, (a0), v0.t
 # CHECK-INST: vse8.v v24, (a0), v0.t
 # CHECK-ENCODING: [0x27,0x0c,0x05,0x00]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)