[PowerPC] Fix popcntb XL Compat Builtin for 32bit

[quinnp]

Summary

This patch implements the __popcntb XL compatibility builtin for 32bit in the frontend and backend. This patch also updates tests for __popcntb and other XL Compat sync related builtins.

[amyk]

llvm/lib/Target/PowerPC/PPCInstr64Bit.td

912–915

Can we add a comment on why this is needed?

llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-32.ll

2

You can use update_llc_test_checks.py to update these.
Also nit, but might be nice to add -ppc-asm-full-reg-names.

[NeHuang]

clang/test/CodeGen/builtins-ppc-xlcompat-sync.c

241

From the document, __icbt only valid when -qarch is set to target pwr8 or higher processors. It looks like target cpu sema checking and error case are missing. If you are working on another patch to fix it, please put fixme comments for the __icbt implementation and test case in this patch.

469

same as above.

llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-64.ll

84

same here, pwr8 (or later processors) only

[quinnp]

Addressing review comments.

[nemanjai]

LGTM.

[amyk]

Minor indentation comments but LGTM.

clang/test/CodeGen/builtins-ppc-xlcompat-sync.c

3

llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-msync.ll

3

Minor indentation nit.

llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-32.ll

4

Minor indentation nit.

llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-64.ll

4

Minor indentation nit.

[efriedma]

llvm/lib/Target/PowerPC/PPCInstr64Bit.td

913

I'm sort of confused by the instruction variations here... let me see if I'm understanding correctly:

1. popcntb always produces a 64-bit result.
2. The 32-bit variation of the intrinsic just throws away the high bits.
3. We can't use the 64-bit instruction in "32-bit" mode because we marked the register class illegal in isel, and Feature64BitRegs has been marked "beta" for the last 15 years.
4. Therefore, there are two versions of the instruction: the real instruction that produces a 64-bit result, and a fake version of the instruction we can use in 32-bit mode.

[quinnp]

Addressing review comment about indentation.

[quinnp]

Removing a misleading comment.

[quinnp]

Removing another comment.

[nemanjai]

llvm/lib/Target/PowerPC/PPCInstr64Bit.td

913

This is correct. We have two GPR register classes that model the same register file. The gprc registers pretend the high bits don't exist. The two versions of the instructions that have GPR operands are quite common in PPC.

There have historically been some operating systems on which context switches spill the full width GPRs even in 32-bit mode. Others spill only the low 32 bits of the GPRs. The addition of two different register classes and Feature64BitRegs likely had to do with that.

[efriedma]

llvm/lib/Target/PowerPC/PPCInstr64Bit.td

913

There have historically been some operating systems on which context switches

Oh, that makes sense. You can't really use the high bits of a 64-bit register if they can get randomly zeroed out from under you.

Are any commonly used operating systems today in the "spill only the low 32 bits" category?

[nemanjai]

llvm/lib/Target/PowerPC/PPCInstr64Bit.td

913

Unfortunately, 32-bit AIX is in this category. We are hoping to be able to change that so that once we no longer support the old versions, we have more freedom with code generation.

clang/lib/CodeGen/CGBuiltin.cpp

#include "clang/Basic/BuiltinsPPC.def"
   case PPC::BI__builtin_ppc_fetch_and_swap:
   case PPC::BI__builtin_ppc_fetch_and_swaplp: {
     return MakeBinaryAtomicValue(*this, AtomicRMWInst::Xchg, E,
                                  llvm::AtomicOrdering::Monotonic);
   }
   case PPC::BI__builtin_ppc_ldarx:
   case PPC::BI__builtin_ppc_lwarx:
     return emitPPCLoadReserveIntrinsic(*this, BuiltinID, E);
+  case PPC::BI__builtin_ppc_popcntb: {
+    Value *ArgValue = EmitScalarExpr(E->getArg(0));
+    llvm::Type *ArgType = ArgValue->getType();
+    Function *F = CGM.getIntrinsic(Intrinsic::ppc_popcntb, {ArgType, ArgType});
+    return Builder.CreateCall(F, Ops, "popcntb");
+  }
   }
 }
 
 namespace {
 // If \p E is not null pointer, insert address space cast to match return
 // type of \p E if necessary.
 Value *EmitAMDGPUDispatchPtr(CodeGenFunction &CGF,
                              const CallExpr *E = nullptr) {

clang/test/CodeGen/builtins-ppc-xlcompat-sync.c

+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
-// RUN:    -emit-llvm %s -o -  -target-cpu pwr8 | FileCheck %s
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
 // RUN: %clang_cc1 -triple powerpc64le-unknown-unknown \
-// RUN:   -emit-llvm %s -o -  -target-cpu pwr8 | FileCheck %s
+// RUN:   -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s --check-prefix=CHECK-32
+
+extern unsigned long a;
+extern const void *b;
+extern void *c;
 
-void test_popcntb() {
 // CHECK-LABEL: @test_popcntb(
 // CHECK-NEXT:  entry:
- 
-  unsigned long a;
-  unsigned long b = __popcntb(a);
-// CHECK: %1 = call i64 @llvm.ppc.popcntb(i64 %0)
+// CHECK-NEXT:    [[TMP0:%.*]] = load i64, i64* @a, align 8
+// CHECK-NEXT:    [[TMP1:%.*]] = load i64, i64* @a, align 8
+// CHECK-NEXT:    [[POPCNTB:%.*]] = call i64 @llvm.ppc.popcntb.i64.i64(i64 [[TMP0]])
+// CHECK-NEXT:    ret i64 [[POPCNTB]]
+//
+// CHECK-32-LABEL: @test_popcntb(
+// CHECK-32-NEXT:  entry:
+// CHECK-32-NEXT:    [[TMP0:%.*]] = load i32, i32* @a, align 4
+// CHECK-32-NEXT:    [[TMP1:%.*]] = load i32, i32* @a, align 4
+// CHECK-32-NEXT:    [[POPCNTB:%.*]] = call i32 @llvm.ppc.popcntb.i32.i32(i32 [[TMP0]])
+// CHECK-32-NEXT:    ret i32 [[POPCNTB]]
+//
+unsigned long test_popcntb() {
+  return __popcntb(a);
 }
 
-void test_eieio() {
 // CHECK-LABEL: @test_eieio(
-// CHECK-NEXT: entry:
-
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    call void @llvm.ppc.eieio()
+// CHECK-NEXT:    ret void
+//
+// CHECK-32-LABEL: @test_eieio(
+// CHECK-32-NEXT:  entry:
+// CHECK-32-NEXT:    call void @llvm.ppc.eieio()
+// CHECK-32-NEXT:    ret void
+//
+void test_eieio() {
   __eieio();
-// CHECK: call void @llvm.ppc.eieio()
 }
 
-void test_iospace_eieio() {
 // CHECK-LABEL: @test_iospace_eieio(
-// CHECK-NEXT: entry:
-
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    call void @llvm.ppc.iospace.eieio()
+// CHECK-NEXT:    ret void
+//
+// CHECK-32-LABEL: @test_iospace_eieio(
+// CHECK-32-NEXT:  entry:
+// CHECK-32-NEXT:    call void @llvm.ppc.iospace.eieio()
+// CHECK-32-NEXT:    ret void
+//
+void test_iospace_eieio() {
   __iospace_eieio();
-// CHECK: call void @llvm.ppc.iospace.eieio()
 }
 
-void test_isync() {
 // CHECK-LABEL: @test_isync(
-// CHECK-NEXT: entry:
-
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    call void @llvm.ppc.isync()
+// CHECK-NEXT:    ret void
+//
+// CHECK-32-LABEL: @test_isync(
+// CHECK-32-NEXT:  entry:
+// CHECK-32-NEXT:    call void @llvm.ppc.isync()
+// CHECK-32-NEXT:    ret void
+//
+void test_isync() {
   __isync();
-// CHECK: call void @llvm.ppc.isync()
 }
 
-void test_lwsync() {
 // CHECK-LABEL: @test_lwsync(
-// CHECK-NEXT: entry:
-
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    call void @llvm.ppc.lwsync()
+// CHECK-NEXT:    ret void
+//
+// CHECK-32-LABEL: @test_lwsync(
+// CHECK-32-NEXT:  entry:
+// CHECK-32-NEXT:    call void @llvm.ppc.lwsync()
+// CHECK-32-NEXT:    ret void
+//
+void test_lwsync() {
   __lwsync();
-// CHECK: call void @llvm.ppc.lwsync()
 }
 
-void test_iospace_lwsync() {
 // CHECK-LABEL: @test_iospace_lwsync(
-// CHECK-NEXT: entry:
-
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    call void @llvm.ppc.iospace.lwsync()
+// CHECK-NEXT:    ret void
+//
+// CHECK-32-LABEL: @test_iospace_lwsync(
+// CHECK-32-NEXT:  entry:
+// CHECK-32-NEXT:    call void @llvm.ppc.iospace.lwsync()
+// CHECK-32-NEXT:    ret void
+//
+void test_iospace_lwsync() {
   __iospace_lwsync();
-// CHECK: call void @llvm.ppc.iospace.lwsync()
 }
 
-void test_sync() {
 // CHECK-LABEL: @test_sync(
-// CHECK-NEXT: entry:
-
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    call void @llvm.ppc.sync()
+// CHECK-NEXT:    ret void
+//
+// CHECK-32-LABEL: @test_sync(
+// CHECK-32-NEXT:  entry:
+// CHECK-32-NEXT:    call void @llvm.ppc.sync()
+// CHECK-32-NEXT:    ret void
+//
+void test_sync() {
   __sync();
-// CHECK: call void @llvm.ppc.sync()
 }
 
-void test_iospace_sync() {
 // CHECK-LABEL: @test_iospace_sync(
-// CHECK-NEXT: entry:
-
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    call void @llvm.ppc.iospace.sync()
+// CHECK-NEXT:    ret void
+//
+// CHECK-32-LABEL: @test_iospace_sync(
+// CHECK-32-NEXT:  entry:
+// CHECK-32-NEXT:    call void @llvm.ppc.iospace.sync()
+// CHECK-32-NEXT:    ret void
+//
+void test_iospace_sync() {
   __iospace_sync();
-// CHECK: call void @llvm.ppc.iospace.sync()  
 }
 
-void test_dcbfl() {
 // CHECK-LABEL: @test_dcbfl(
-// CHECK-NEXT: entry:
-
-  const void* a;
-  __dcbfl(a);
-// CHECK: call void @llvm.ppc.dcbfl(i8* %0)
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = load i8*, i8** @b, align 8
+// CHECK-NEXT:    call void @llvm.ppc.dcbfl(i8* [[TMP0]])
+// CHECK-NEXT:    ret void
+//
+// CHECK-32-LABEL: @test_dcbfl(
+// CHECK-32-NEXT:  entry:
+// CHECK-32-NEXT:    [[TMP0:%.*]] = load i8*, i8** @b, align 4
+// CHECK-32-NEXT:    call void @llvm.ppc.dcbfl(i8* [[TMP0]])
+// CHECK-32-NEXT:    ret void
+//
+void test_dcbfl() {
+  __dcbfl(b);
 }
 
-void test_dcbflp() {
 // CHECK-LABEL: @test_dcbflp(
-// CHECK-NEXT: entry:
-
-  const void* a;
-  __dcbflp(a);
-// CHECK: call void @llvm.ppc.dcbflp(i8* %0)
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = load i8*, i8** @b, align 8
+// CHECK-NEXT:    call void @llvm.ppc.dcbflp(i8* [[TMP0]])
+// CHECK-NEXT:    ret void
+//
+// CHECK-32-LABEL: @test_dcbflp(
+// CHECK-32-NEXT:  entry:
+// CHECK-32-NEXT:    [[TMP0:%.*]] = load i8*, i8** @b, align 4
+// CHECK-32-NEXT:    call void @llvm.ppc.dcbflp(i8* [[TMP0]])
+// CHECK-32-NEXT:    ret void
+//
+void test_dcbflp() {
+  __dcbflp(b);
 }
 
-void test_dcbst() {
 // CHECK-LABEL: @test_dcbst(
-// CHECK-NEXT: entry:
-
-  const void* a;
-  __dcbst(a);
-// CHECK: call void @llvm.ppc.dcbst(i8* %0)
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = load i8*, i8** @b, align 8
+// CHECK-NEXT:    call void @llvm.ppc.dcbst(i8* [[TMP0]])
+// CHECK-NEXT:    ret void
+//
+// CHECK-32-LABEL: @test_dcbst(
+// CHECK-32-NEXT:  entry:
+// CHECK-32-NEXT:    [[TMP0:%.*]] = load i8*, i8** @b, align 4
+// CHECK-32-NEXT:    call void @llvm.ppc.dcbst(i8* [[TMP0]])
+// CHECK-32-NEXT:    ret void
+//
+void test_dcbst() {
+  __dcbst(b);
 }
 
-void test_dcbt() {
 // CHECK-LABEL: @test_dcbt(
-// CHECK-NEXT: entry:
-
-  void* a;
-  __dcbt(a);
-// CHECK: call void @llvm.ppc.dcbt(i8* %0)
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = load i8*, i8** @c, align 8
+// CHECK-NEXT:    call void @llvm.ppc.dcbt(i8* [[TMP0]])
+// CHECK-NEXT:    ret void
+//
+// CHECK-32-LABEL: @test_dcbt(
+// CHECK-32-NEXT:  entry:
+// CHECK-32-NEXT:    [[TMP0:%.*]] = load i8*, i8** @c, align 4
+// CHECK-32-NEXT:    call void @llvm.ppc.dcbt(i8* [[TMP0]])
+// CHECK-32-NEXT:    ret void
+//
+void test_dcbt() {
+  __dcbt(c);
 }
 
-void test_dcbtst() {
 // CHECK-LABEL: @test_dcbtst(
-// CHECK-NEXT: entry:
-
-  void* a;
-  __dcbtst(a);
-// CHECK: call void @llvm.ppc.dcbtst(i8* %0)
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = load i8*, i8** @c, align 8
+// CHECK-NEXT:    call void @llvm.ppc.dcbtst(i8* [[TMP0]])
+// CHECK-NEXT:    ret void
+//
+// CHECK-32-LABEL: @test_dcbtst(
+// CHECK-32-NEXT:  entry:
+// CHECK-32-NEXT:    [[TMP0:%.*]] = load i8*, i8** @c, align 4
+// CHECK-32-NEXT:    call void @llvm.ppc.dcbtst(i8* [[TMP0]])
+// CHECK-32-NEXT:    ret void
+//
+void test_dcbtst() {
+  __dcbtst(c);
 }
 
-void test_dcbz() {
 // CHECK-LABEL: @test_dcbz(
-// CHECK-NEXT: entry:
-
-  void* a;
-  __dcbz(a);
-// CHECK: call void @llvm.ppc.dcbz(i8* %0)
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = load i8*, i8** @c, align 8
+// CHECK-NEXT:    call void @llvm.ppc.dcbz(i8* [[TMP0]])
+// CHECK-NEXT:    ret void
+//
+// CHECK-32-LABEL: @test_dcbz(
+// CHECK-32-NEXT:  entry:
+// CHECK-32-NEXT:    [[TMP0:%.*]] = load i8*, i8** @c, align 4
+// CHECK-32-NEXT:    call void @llvm.ppc.dcbz(i8* [[TMP0]])
+// CHECK-32-NEXT:    ret void
+//
+void test_dcbz() {
+  __dcbz(c);
 }
 
-void test_icbt() {
+// FIXME: __icbt is only valid for pwr8 and up.
 // CHECK-LABEL: @test_icbt(
-// CHECK-NEXT: entry:
-
-  void* a;
-  __icbt(a);
-// CHECK: call void @llvm.ppc.icbt(i8* %0)
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = load i8*, i8** @c, align 8
+// CHECK-NEXT:    call void @llvm.ppc.icbt(i8* [[TMP0]])
+// CHECK-NEXT:    ret void
+//
+// CHECK-32-LABEL: @test_icbt(
+// CHECK-32-NEXT:  entry:
+// CHECK-32-NEXT:    [[TMP0:%.*]] = load i8*, i8** @c, align 4
+// CHECK-32-NEXT:    call void @llvm.ppc.icbt(i8* [[TMP0]])
+// CHECK-32-NEXT:    ret void
+//
+void test_icbt() {
+  __icbt(c);
 }
 
-void test_builtin_ppc_popcntb() {
 // CHECK-LABEL: @test_builtin_ppc_popcntb(
 // CHECK-NEXT:  entry:
- 
-  unsigned long a;
-  unsigned long b = __builtin_ppc_popcntb(a);
-// CHECK: %1 = call i64 @llvm.ppc.popcntb(i64 %0)
+// CHECK-NEXT:    [[TMP0:%.*]] = load i64, i64* @a, align 8
+// CHECK-NEXT:    [[TMP1:%.*]] = load i64, i64* @a, align 8
+// CHECK-NEXT:    [[POPCNTB:%.*]] = call i64 @llvm.ppc.popcntb.i64.i64(i64 [[TMP0]])
+// CHECK-NEXT:    ret i64 [[POPCNTB]]
+//
+// CHECK-32-LABEL: @test_builtin_ppc_popcntb(
+// CHECK-32-NEXT:  entry:
+// CHECK-32-NEXT:    [[TMP0:%.*]] = load i32, i32* @a, align 4
+// CHECK-32-NEXT:    [[TMP1:%.*]] = load i32, i32* @a, align 4
+// CHECK-32-NEXT:    [[POPCNTB:%.*]] = call i32 @llvm.ppc.popcntb.i32.i32(i32 [[TMP0]])
+// CHECK-32-NEXT:    ret i32 [[POPCNTB]]
+//
+unsigned long test_builtin_ppc_popcntb() {
+  return __builtin_ppc_popcntb(a);
 }
 
-void test_builtin_ppc_eieio() {
 // CHECK-LABEL: @test_builtin_ppc_eieio(
-// CHECK-NEXT: entry:
-
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    call void @llvm.ppc.eieio()
+// CHECK-NEXT:    ret void
+//
+// CHECK-32-LABEL: @test_builtin_ppc_eieio(
+// CHECK-32-NEXT:  entry:
+// CHECK-32-NEXT:    call void @llvm.ppc.eieio()
+// CHECK-32-NEXT:    ret void
+//
+void test_builtin_ppc_eieio() {
   __builtin_ppc_eieio();
-// CHECK: call void @llvm.ppc.eieio()
 }
 
-void test_builtin_ppc_iospace_eieio() {
 // CHECK-LABEL: @test_builtin_ppc_iospace_eieio(
-// CHECK-NEXT: entry:
-
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    call void @llvm.ppc.iospace.eieio()
+// CHECK-NEXT:    ret void
+//
+// CHECK-32-LABEL: @test_builtin_ppc_iospace_eieio(
+// CHECK-32-NEXT:  entry:
+// CHECK-32-NEXT:    call void @llvm.ppc.iospace.eieio()
+// CHECK-32-NEXT:    ret void
+//
+void test_builtin_ppc_iospace_eieio() {
   __builtin_ppc_iospace_eieio();
-// CHECK: call void @llvm.ppc.iospace.eieio()
 }
 
-void test_builtin_ppc_isync() {
 // CHECK-LABEL: @test_builtin_ppc_isync(
-// CHECK-NEXT: entry:
-
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    call void @llvm.ppc.isync()
+// CHECK-NEXT:    ret void
+//
+// CHECK-32-LABEL: @test_builtin_ppc_isync(
+// CHECK-32-NEXT:  entry:
+// CHECK-32-NEXT:    call void @llvm.ppc.isync()
+// CHECK-32-NEXT:    ret void
+//
+void test_builtin_ppc_isync() {
   __builtin_ppc_isync();
-// CHECK: call void @llvm.ppc.isync()
 }
 
-void test_builtin_ppc_lwsync() {
 // CHECK-LABEL: @test_builtin_ppc_lwsync(
-// CHECK-NEXT: entry:
-
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    call void @llvm.ppc.lwsync()
+// CHECK-NEXT:    ret void
+//
+// CHECK-32-LABEL: @test_builtin_ppc_lwsync(
+// CHECK-32-NEXT:  entry:
+// CHECK-32-NEXT:    call void @llvm.ppc.lwsync()
+// CHECK-32-NEXT:    ret void
+//
+void test_builtin_ppc_lwsync() {
   __builtin_ppc_lwsync();
-// CHECK: call void @llvm.ppc.lwsync()
 }
 
-void test_builtin_ppc_iospace_lwsync() {
 // CHECK-LABEL: @test_builtin_ppc_iospace_lwsync(
-// CHECK-NEXT: entry:
-
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    call void @llvm.ppc.iospace.lwsync()
+// CHECK-NEXT:    ret void
+//
+// CHECK-32-LABEL: @test_builtin_ppc_iospace_lwsync(
+// CHECK-32-NEXT:  entry:
+// CHECK-32-NEXT:    call void @llvm.ppc.iospace.lwsync()
+// CHECK-32-NEXT:    ret void
+//
+void test_builtin_ppc_iospace_lwsync() {
   __builtin_ppc_iospace_lwsync();
-// CHECK: call void @llvm.ppc.iospace.lwsync()
 }
 
-void test_builtin_ppc_sync() {
 // CHECK-LABEL: @test_builtin_ppc_sync(
-// CHECK-NEXT: entry:
-
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    call void @llvm.ppc.sync()
+// CHECK-NEXT:    ret void
+//
+// CHECK-32-LABEL: @test_builtin_ppc_sync(
+// CHECK-32-NEXT:  entry:
+// CHECK-32-NEXT:    call void @llvm.ppc.sync()
+// CHECK-32-NEXT:    ret void
+//
+void test_builtin_ppc_sync() {
   __builtin_ppc_sync();
-// CHECK: call void @llvm.ppc.sync()
 }
 
-void test_builtin_ppc_iospace_sync() {
 // CHECK-LABEL: @test_builtin_ppc_iospace_sync(
-// CHECK-NEXT: entry:
-
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    call void @llvm.ppc.iospace.sync()
+// CHECK-NEXT:    ret void
+//
+// CHECK-32-LABEL: @test_builtin_ppc_iospace_sync(
+// CHECK-32-NEXT:  entry:
+// CHECK-32-NEXT:    call void @llvm.ppc.iospace.sync()
+// CHECK-32-NEXT:    ret void
+//
+void test_builtin_ppc_iospace_sync() {
   __builtin_ppc_iospace_sync();
-// CHECK: call void @llvm.ppc.iospace.sync()  
 }
 
-void test_builtin_ppc_dcbfl() {
 // CHECK-LABEL: @test_builtin_ppc_dcbfl(
-// CHECK-NEXT: entry:
-
-  const void* a;
-  __builtin_ppc_dcbfl(a);
-// CHECK: call void @llvm.ppc.dcbfl(i8* %0)
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = load i8*, i8** @b, align 8
+// CHECK-NEXT:    call void @llvm.ppc.dcbfl(i8* [[TMP0]])
+// CHECK-NEXT:    ret void
+//
+// CHECK-32-LABEL: @test_builtin_ppc_dcbfl(
+// CHECK-32-NEXT:  entry:
+// CHECK-32-NEXT:    [[TMP0:%.*]] = load i8*, i8** @b, align 4
+// CHECK-32-NEXT:    call void @llvm.ppc.dcbfl(i8* [[TMP0]])
+// CHECK-32-NEXT:    ret void
+//
+void test_builtin_ppc_dcbfl() {
+  __builtin_ppc_dcbfl(b);
 }
 
-void test_builtin_ppc_dcbflp() {
 // CHECK-LABEL: @test_builtin_ppc_dcbflp(
-// CHECK-NEXT: entry:
-
-  const void* a;
-  __builtin_ppc_dcbflp(a);
-// CHECK: call void @llvm.ppc.dcbflp(i8* %0)
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = load i8*, i8** @b, align 8
+// CHECK-NEXT:    call void @llvm.ppc.dcbflp(i8* [[TMP0]])
+// CHECK-NEXT:    ret void
+//
+// CHECK-32-LABEL: @test_builtin_ppc_dcbflp(
+// CHECK-32-NEXT:  entry:
+// CHECK-32-NEXT:    [[TMP0:%.*]] = load i8*, i8** @b, align 4
+// CHECK-32-NEXT:    call void @llvm.ppc.dcbflp(i8* [[TMP0]])
+// CHECK-32-NEXT:    ret void
+//
+void test_builtin_ppc_dcbflp() {
+  __builtin_ppc_dcbflp(b);
 }
 
-void test_builtin_ppc_dcbst() {
 // CHECK-LABEL: @test_builtin_ppc_dcbst(
-// CHECK-NEXT: entry:
-
-  const void* a;
-  __builtin_ppc_dcbst(a);
-// CHECK: call void @llvm.ppc.dcbst(i8* %0)
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = load i8*, i8** @b, align 8
+// CHECK-NEXT:    call void @llvm.ppc.dcbst(i8* [[TMP0]])
+// CHECK-NEXT:    ret void
+//
+// CHECK-32-LABEL: @test_builtin_ppc_dcbst(
+// CHECK-32-NEXT:  entry:
+// CHECK-32-NEXT:    [[TMP0:%.*]] = load i8*, i8** @b, align 4
+// CHECK-32-NEXT:    call void @llvm.ppc.dcbst(i8* [[TMP0]])
+// CHECK-32-NEXT:    ret void
+//
+void test_builtin_ppc_dcbst() {
+  __builtin_ppc_dcbst(b);
 }
 
-void test_builtin_ppc_dcbt() {
 // CHECK-LABEL: @test_builtin_ppc_dcbt(
-// CHECK-NEXT: entry:
-
-  void* a;
-  __builtin_ppc_dcbt(a);
-// CHECK: call void @llvm.ppc.dcbt(i8* %0)
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = load i8*, i8** @c, align 8
+// CHECK-NEXT:    call void @llvm.ppc.dcbt(i8* [[TMP0]])
+// CHECK-NEXT:    ret void
+//
+// CHECK-32-LABEL: @test_builtin_ppc_dcbt(
+// CHECK-32-NEXT:  entry:
+// CHECK-32-NEXT:    [[TMP0:%.*]] = load i8*, i8** @c, align 4
+// CHECK-32-NEXT:    call void @llvm.ppc.dcbt(i8* [[TMP0]])
+// CHECK-32-NEXT:    ret void
+//
+void test_builtin_ppc_dcbt() {
+  __builtin_ppc_dcbt(c);
 }
 
-void test_builtin_ppc_dcbtst() {
 // CHECK-LABEL: @test_builtin_ppc_dcbtst(
-// CHECK-NEXT: entry:
-
-  void* a;
-  __builtin_ppc_dcbtst(a);
-// CHECK: call void @llvm.ppc.dcbtst(i8* %0)
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = load i8*, i8** @c, align 8
+// CHECK-NEXT:    call void @llvm.ppc.dcbtst(i8* [[TMP0]])
+// CHECK-NEXT:    ret void
+//
+// CHECK-32-LABEL: @test_builtin_ppc_dcbtst(
+// CHECK-32-NEXT:  entry:
+// CHECK-32-NEXT:    [[TMP0:%.*]] = load i8*, i8** @c, align 4
+// CHECK-32-NEXT:    call void @llvm.ppc.dcbtst(i8* [[TMP0]])
+// CHECK-32-NEXT:    ret void
+//
+void test_builtin_ppc_dcbtst() {
+  __builtin_ppc_dcbtst(c);
 }
 
-void test_builtin_ppc_dcbz() {
 // CHECK-LABEL: @test_builtin_ppc_dcbz(
-// CHECK-NEXT: entry:
-
-  void* a;
-  __builtin_ppc_dcbz(a);
-// CHECK: call void @llvm.ppc.dcbz(i8* %0)
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = load i8*, i8** @c, align 8
+// CHECK-NEXT:    call void @llvm.ppc.dcbz(i8* [[TMP0]])
+// CHECK-NEXT:    ret void
+//
+// CHECK-32-LABEL: @test_builtin_ppc_dcbz(
+// CHECK-32-NEXT:  entry:
+// CHECK-32-NEXT:    [[TMP0:%.*]] = load i8*, i8** @c, align 4
+// CHECK-32-NEXT:    call void @llvm.ppc.dcbz(i8* [[TMP0]])
+// CHECK-32-NEXT:    ret void
+//
+void test_builtin_ppc_dcbz() {
+  __builtin_ppc_dcbz(c);
 }
 
-void test_builtin_ppc_icbt() {
+// FIXME: __icbt is only valid for pwr8 and up.
 // CHECK-LABEL: @test_builtin_ppc_icbt(
-// CHECK-NEXT: entry:
-
-  void* a;
-  __builtin_ppc_icbt(a);
-// CHECK: call void @llvm.ppc.icbt(i8* %0)
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = load i8*, i8** @c, align 8
+// CHECK-NEXT:    call void @llvm.ppc.icbt(i8* [[TMP0]])
+// CHECK-NEXT:    ret void
+//
+// CHECK-32-LABEL: @test_builtin_ppc_icbt(
+// CHECK-32-NEXT:  entry:
+// CHECK-32-NEXT:    [[TMP0:%.*]] = load i8*, i8** @c, align 4
+// CHECK-32-NEXT:    call void @llvm.ppc.icbt(i8* [[TMP0]])
+// CHECK-32-NEXT:    ret void
+//
+void test_builtin_ppc_icbt() {
+  __builtin_ppc_icbt(c);
 }

llvm/include/llvm/IR/IntrinsicsPowerPC.td

let TargetPrefix = "ppc" in {
   def int_ppc_dcbt  : GCCBuiltin<"__builtin_ppc_dcbt">,
                       Intrinsic<[], [llvm_ptr_ty],
     [IntrArgMemOnly, NoCapture<ArgIndex<0>>]>;
   def int_ppc_dcbtst : GCCBuiltin<"__builtin_ppc_dcbtst">,
                        Intrinsic<[], [llvm_ptr_ty],
     [IntrArgMemOnly, NoCapture<ArgIndex<0>>]>;
   def int_ppc_dcbz  : GCCBuiltin<"__builtin_ppc_dcbz">,
                       Intrinsic<[], [llvm_ptr_ty], []>;
+// FIXME: __icbt is only valid for pwr8 and up.
   def int_ppc_icbt : GCCBuiltin<"__builtin_ppc_icbt">,
                      Intrinsic<[], [llvm_ptr_ty], []>;
   
   // Population Count in each Byte.
-  def int_ppc_popcntb : GCCBuiltin<"__builtin_ppc_popcntb">,
-                        Intrinsic<[llvm_i64_ty], [llvm_i64_ty], [IntrNoMem]>;
+  def int_ppc_popcntb : Intrinsic<[llvm_anyint_ty], [llvm_anyint_ty], [IntrNoMem]>;
   
   // sync instruction (i.e. sync 0, a.k.a hwsync)
   def int_ppc_sync : GCCBuiltin<"__builtin_ppc_sync">,
                      Intrinsic<[], [], []>;
   def int_ppc_iospace_sync : GCCBuiltin<"__builtin_ppc_iospace_sync">,
                              Intrinsic<[], [], []>;
   // isync instruction
   def int_ppc_isync : GCCBuiltin<"__builtin_ppc_isync">,

llvm/lib/Target/PowerPC/P9InstrResources.td

def : InstRW<[P9_ALU_2C, IP_EXEC_1C, DISP_1C],
     (instregex "ANDI(S)?(8)?(_rec)?$"),
     (instregex "ADDC(8)?(O)?$"),
     (instregex "ADDIC(8)?(_rec)?$"),
     (instregex "ADD(8|4)(O)?(_rec)?$"),
     (instregex "ADD(E|ME|ZE)(8)?(O)?(_rec)?$"),
     (instregex "SUBF(E|ME|ZE)?(8)?(O)?(_rec)?$"),
     (instregex "NEG(8)?(O)?(_rec)?$"),
     (instregex "POPCNTB$"),
+    (instregex "POPCNTB8$"),
     (instregex "ADD(I|IS)?(8)?$"),
     (instregex "LI(S)?(8)?$"),
     (instregex "(X)?OR(I|IS)?(8)?(_rec)?$"),
     (instregex "NAND(8)?(_rec)?$"),
     (instregex "AND(C)?(8)?(_rec)?$"),
     (instregex "NOR(8)?(_rec)?$"),
     (instregex "OR(C)?(8)?(_rec)?$"),
     (instregex "EQV(8)?(_rec)?$"),

llvm/lib/Target/PowerPC/PPCInstr64Bit.td

 
 // popcntw also does a population count on the high 32 bits (storing the
 // results in the high 32-bits of the output). We'll ignore that here (which is
 // safe because we never separately use the high part of the 64-bit registers).
 def POPCNTW : XForm_11<31, 378, (outs gprc:$rA), (ins gprc:$rS),
                        "popcntw $rA, $rS", IIC_IntGeneral,
                        [(set i32:$rA, (ctpop i32:$rS))]>;
 
-def POPCNTB : XForm_11<31, 122, (outs g8rc:$rA), (ins g8rc:$rS),
+let isCodeGenOnly = 1 in
+def POPCNTB8 : XForm_11<31, 122, (outs g8rc:$rA), (ins g8rc:$rS),
                         "popcntb $rA, $rS", IIC_IntGeneral,
                         [(set i64:$rA, (int_ppc_popcntb i64:$rS))]>;
 
 defm DIVD  : XOForm_1rcr<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
                           "divd", "$rT, $rA, $rB", IIC_IntDivD,
                           [(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64;
 defm DIVDU : XOForm_1rcr<31, 457, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
                           "divdu", "$rT, $rA, $rB", IIC_IntDivD,
                           [(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64;
 defm DIVDE : XOForm_1rcr<31, 425, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),

llvm/lib/Target/PowerPC/PPCInstrInfo.td

def TWI : DForm_base<3, (outs), (ins u5imm:$to, gprc:$rA, s16imm:$imm),
                      "twi $to, $rA, $imm", IIC_IntTrapW, []>;
 def TW : XForm_1<31, 4, (outs), (ins u5imm:$to, gprc:$rA, gprc:$rB),
                  "tw $to, $rA, $rB", IIC_IntTrapW, []>;
 def TDI : DForm_base<2, (outs), (ins u5imm:$to, g8rc:$rA, s16imm:$imm),
                      "tdi $to, $rA, $imm", IIC_IntTrapD, []>;
 def TD : XForm_1<31, 68, (outs), (ins u5imm:$to, g8rc:$rA, g8rc:$rB),
                  "td $to, $rA, $rB", IIC_IntTrapD, []>;
 
+def POPCNTB : XForm_11<31, 122, (outs gprc:$rA), (ins gprc:$rS),
+                       "popcntb $rA, $rS", IIC_IntGeneral,
+                       [(set i32:$rA, (int_ppc_popcntb i32:$rS))]>;
+
 //===----------------------------------------------------------------------===//
 // PPC32 Load Instructions.
 //
 
 // Unindexed (r+i) Loads.
 let PPC970_Unit = 2 in {
 def LBZ : DForm_1<34, (outs gprc:$rD), (ins memri:$src),
                   "lbz $rD, $src", IIC_LdStLoad,

llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-msync.ll

-; RUN: llc -verify-machineinstrs -mtriple=powerpcle-unknown-linux-gnu \
-; RUN:    -mattr=+msync -mcpu=pwr8 < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu \
-; RUN:    -mattr=+msync -mcpu=pwr8 < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
-; RUN:    -mattr=+msync -mcpu=pwr8 < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
-; RUN:    -mattr=+msync -mcpu=pwr8 < %s | FileCheck %s
-
-define dso_local void @test_builtin_ppc_iospace_lwsync() #0 {
-; CHECK-LABEL: test_builtin_ppc_iospace_lwsync
-
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
+; RUN:   --ppc-asm-full-reg-names -mattr=+msync -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN:   --ppc-asm-full-reg-names -mattr=+msync -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   --ppc-asm-full-reg-names -mattr=+msync -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   --ppc-asm-full-reg-names -mattr=+msync -mcpu=pwr7 < %s | FileCheck %s
+
+define dso_local void @test_builtin_ppc_iospace_lwsync() {
+; CHECK-LABEL: test_builtin_ppc_iospace_lwsync:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    msync
+; CHECK-NEXT:    blr
 entry:
   call void @llvm.ppc.iospace.lwsync()
-; CHECK: msync
-
   ret void
 }
+declare void @llvm.ppc.iospace.lwsync()
 
-declare void @llvm.ppc.iospace.lwsync() #2
-
-define dso_local void @test_builtin_ppc_iospace_sync() #0 {
-; CHECK-LABEL: test_builtin_ppc_iospace_sync
-
+define dso_local void @test_builtin_ppc_iospace_sync() {
+; CHECK-LABEL: test_builtin_ppc_iospace_sync:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    msync
+; CHECK-NEXT:    blr
 entry:
   call void @llvm.ppc.iospace.sync()
-; CHECK: msync
-
   ret void
 }
-
-declare void @llvm.ppc.iospace.sync() #2
-
+declare void @llvm.ppc.iospace.sync()

llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-32.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   --ppc-asm-full-reg-names -mcpu=pwr7 < %s | FileCheck %s
+
+define dso_local i32 @test_builtin_ppc_popcntb_i32(i32 %a) local_unnamed_addr {
+; CHECK-LABEL: test_builtin_ppc_popcntb_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    popcntb 3, 3
+; CHECK-NEXT:    blr
+entry:
+  %popcntb = tail call i32 @llvm.ppc.popcntb.i32.i32(i32 %a)
+  ret i32 %popcntb
+}
+declare i32 @llvm.ppc.popcntb.i32.i32(i32)
+
+define dso_local void @test_builtin_ppc_eieio() {
+; CHECK-LABEL: test_builtin_ppc_eieio:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    ori 2, 2, 0
+; CHECK-NEXT:    ori 2, 2, 0
+; CHECK-NEXT:    eieio
+; CHECK-NEXT:    blr
+entry:
+  call void @llvm.ppc.eieio()
+  ret void
+}
+declare void @llvm.ppc.eieio()
+
+define dso_local void @test_builtin_ppc_iospace_eieio() {
+; CHECK-LABEL: test_builtin_ppc_iospace_eieio:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    ori 2, 2, 0
+; CHECK-NEXT:    ori 2, 2, 0
+; CHECK-NEXT:    eieio
+; CHECK-NEXT:    blr
+entry:
+  call void @llvm.ppc.iospace.eieio()
+  ret void
+}
+declare void @llvm.ppc.iospace.eieio()
+
+define dso_local void @test_builtin_ppc_iospace_lwsync() {
+; CHECK-LABEL: test_builtin_ppc_iospace_lwsync:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lwsync
+; CHECK-NEXT:    blr
+entry:
+  call void @llvm.ppc.iospace.lwsync()
+  ret void
+}
+declare void @llvm.ppc.iospace.lwsync()
+
+define dso_local void @test_builtin_ppc_iospace_sync() {
+; CHECK-LABEL: test_builtin_ppc_iospace_sync:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sync
+; CHECK-NEXT:    blr
+entry:
+  call void @llvm.ppc.iospace.sync()
+  ret void
+}
+declare void @llvm.ppc.iospace.sync()
+
+; FIXME: __icbt is only valid for pwr8 and up.
+define dso_local void @test_builtin_ppc_icbt() {
+; CHECK-LABEL: test_builtin_ppc_icbt:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lwz 3, -8(1)
+; CHECK-NEXT:    icbt 0, 0, 3
+; CHECK-NEXT:    blr
+entry:
+  %a = alloca i8*, align 8
+  %0 = load i8*, i8** %a, align 8
+  call void @llvm.ppc.icbt(i8* %0)
+  ret void
+}
+declare void @llvm.ppc.icbt(i8*)

llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-64.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
+; RUN:   --ppc-asm-full-reg-names -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN:   --ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   --ppc-asm-full-reg-names -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX
+
+define dso_local i64 @test_builtin_ppc_popcntb_i64(i64 %a) local_unnamed_addr {
+; CHECK-LABEL: test_builtin_ppc_popcntb_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    popcntb r3, r3
+; CHECK-NEXT:    blr
+;
+; CHECK-AIX-LABEL: test_builtin_ppc_popcntb_i64:
+; CHECK-AIX:       # %bb.0: # %entry
+; CHECK-AIX-NEXT:    popcntb 3, 3
+; CHECK-AIX-NEXT:    blr
+entry:
+  %popcntb = tail call i64 @llvm.ppc.popcntb.i64.i64(i64 %a)
+  ret i64 %popcntb
+}
+declare i64 @llvm.ppc.popcntb.i64.i64(i64)
+
+define dso_local void @test_builtin_ppc_eieio() {
+; CHECK-LABEL: test_builtin_ppc_eieio:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    ori r2, r2, 0
+; CHECK-NEXT:    ori r2, r2, 0
+; CHECK-NEXT:    eieio
+; CHECK-NEXT:    blr
+;
+; CHECK-AIX-LABEL: test_builtin_ppc_eieio:
+; CHECK-AIX:       # %bb.0: # %entry
+; CHECK-AIX-NEXT:    ori 2, 2, 0
+; CHECK-AIX-NEXT:    ori 2, 2, 0
+; CHECK-AIX-NEXT:    eieio
+; CHECK-AIX-NEXT:    blr
+entry:
+  call void @llvm.ppc.eieio()
+  ret void
+}
+declare void @llvm.ppc.eieio()
+
+define dso_local void @test_builtin_ppc_iospace_eieio() {
+; CHECK-LABEL: test_builtin_ppc_iospace_eieio:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    ori r2, r2, 0
+; CHECK-NEXT:    ori r2, r2, 0
+; CHECK-NEXT:    eieio
+; CHECK-NEXT:    blr
+;
+; CHECK-AIX-LABEL: test_builtin_ppc_iospace_eieio:
+; CHECK-AIX:       # %bb.0: # %entry
+; CHECK-AIX-NEXT:    ori 2, 2, 0
+; CHECK-AIX-NEXT:    ori 2, 2, 0
+; CHECK-AIX-NEXT:    eieio
+; CHECK-AIX-NEXT:    blr
+entry:
+  call void @llvm.ppc.iospace.eieio()
+  ret void
+}
+declare void @llvm.ppc.iospace.eieio()
+
+define dso_local void @test_builtin_ppc_iospace_lwsync() {
+; CHECK-LABEL: test_builtin_ppc_iospace_lwsync:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lwsync
+; CHECK-NEXT:    blr
+;
+; CHECK-AIX-LABEL: test_builtin_ppc_iospace_lwsync:
+; CHECK-AIX:       # %bb.0: # %entry
+; CHECK-AIX-NEXT:    lwsync
+; CHECK-AIX-NEXT:    blr
+entry:
+  call void @llvm.ppc.iospace.lwsync()
+  ret void
+}
+declare void @llvm.ppc.iospace.lwsync()
+
+define dso_local void @test_builtin_ppc_iospace_sync() {
+; CHECK-LABEL: test_builtin_ppc_iospace_sync:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sync
+; CHECK-NEXT:    blr
+;
+; CHECK-AIX-LABEL: test_builtin_ppc_iospace_sync:
+; CHECK-AIX:       # %bb.0: # %entry
+; CHECK-AIX-NEXT:    sync
+; CHECK-AIX-NEXT:    blr
+entry:
+  call void @llvm.ppc.iospace.sync()
+  ret void
+}
+declare void @llvm.ppc.iospace.sync()
+
+; FIXME: __icbt is only valid for pwr8 and up.
+define dso_local void @test_builtin_ppc_icbt() {
+; CHECK-LABEL: test_builtin_ppc_icbt:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    ld r3, -8(r1)
+; CHECK-NEXT:    icbt 0, 0, r3
+; CHECK-NEXT:    blr
+;
+; CHECK-AIX-LABEL: test_builtin_ppc_icbt:
+; CHECK-AIX:       # %bb.0: # %entry
+; CHECK-AIX-NEXT:    ld 3, -8(1)
+; CHECK-AIX-NEXT:    icbt 0, 0, 3
+; CHECK-AIX-NEXT:    blr
+entry:
+  %a = alloca i8*, align 8
+  %0 = load i8*, i8** %a, align 8
+  call void @llvm.ppc.icbt(i8* %0)
+  ret void
+}
+declare void @llvm.ppc.icbt(i8*)

llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.ll

-; RUN: llc -verify-machineinstrs -mtriple=powerpcle-unknown-linux-gnu \
-; RUN: -mcpu=pwr8 < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu \
-; RUN: -mcpu=pwr8 < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
-; RUN: -mcpu=pwr8 < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
-; RUN: -mcpu=pwr8 < %s | FileCheck %s
-
-define dso_local void @test_builtin_ppc_eieio() #0 {
-; CHECK-LABEL: test_builtin_ppc_eieio
-
-entry:
-  call void @llvm.ppc.eieio()
-; CHECK: ori 2, 2, 0
-; CHECK-NEXT: ori 2, 2, 0
-; CHECK-NEXT: eieio
- 
-  ret void
-}
-
-declare void @llvm.ppc.eieio() #2
-
-define dso_local void @test_builtin_ppc_iospace_eieio() #0 {
-; CHECK-LABEL: test_builtin_ppc_iospace_eieio
-
-entry:
-  call void @llvm.ppc.iospace.eieio()
-; CHECK: ori 2, 2, 0
-; CHECK-NEXT: ori 2, 2, 0
-; CHECK-NEXT: eieio
- 
-  ret void
-}
-
-declare void @llvm.ppc.iospace.eieio() #2
-
-define dso_local void @test_builtin_ppc_iospace_lwsync() #0 {
-; CHECK-LABEL: test_builtin_ppc_iospace_lwsync
-
-entry:
-  call void @llvm.ppc.iospace.lwsync()
-; CHECK: lwsync
-
-  ret void
-}
-
-declare void @llvm.ppc.iospace.lwsync() #2
-
-define dso_local void @test_builtin_ppc_iospace_sync() #0 {
-; CHECK-LABEL: test_builtin_ppc_iospace_sync
-
-entry:
-  call void @llvm.ppc.iospace.sync()
-; CHECK: sync
-
-  ret void
-}
-
-declare void @llvm.ppc.iospace.sync() #2
-
-define dso_local void @test_builtin_ppc_icbt() #0 {
-; CHECK-LABEL: test_builtin_ppc_icbt
-
-entry:
-  %a = alloca i8*, align 8
-  %0 = load i8*, i8** %a, align 8
-  call void @llvm.ppc.icbt(i8* %0)
-; CHECK: icbt 0, 0, 3
-
-  ret void
-}
-
-declare void @llvm.ppc.icbt(i8*) #2