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Differential D103790

[RISCV][NFC] Add a single space after comma for VType
ClosedPublic

Authored by Jim on Jun 7 2021, 12:01 AM.

Details

Reviewers
kito-cheng
craig.topper
Commits
rG242ddd50897c: [RISCV][NFC] Add a single space after comma for VType
Summary

In most of cases, it has a single space after comma in assembly operands.

Diff Detail

Event Timeline

Jim created this revision.Jun 7 2021, 12:01 AM
Herald added subscribers: vkmr, frasercrmck, evandro and 26 others. · View Herald TranscriptJun 7 2021, 12:01 AM
Jim requested review of this revision.Jun 7 2021, 12:01 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 7 2021, 12:01 AM
Herald added subscribers: llvm-commits, MaskRay. · View Herald Transcript
craig.topper added a reviewer: kito-cheng.Jun 7 2021, 12:17 AM
craig.topper added a subscriber: craig.topper.

The examples in the V spec show no spaces. Are you going to update that too? What about binutils?

Harbormaster completed remote builds in B107914: Diff 350184.Jun 7 2021, 1:18 AM
Jim added a reviewer: craig.topper.Jun 7 2021, 1:57 AM
In D103790#2801845, @craig.topper wrote:

The examples in the V spec show no spaces. Are you going to update that too? What about binutils?

I refer to https://github.com/riscv/riscv-binutils-gdb/blob/c5ef83e53e2528c0737bb0f40e6b77dc8b82eac8/gas/testsuite/gas/riscv/vector-insns.s
It looks that binutils can accept two formats with or without spaces.

I pull a request to update riscv-v-spec.
https://github.com/riscv/riscv-v-spec/pull/693

craig.topper accepted this revision.Jun 7 2021, 10:48 AM

LGTM

This revision is now accepted and ready to land.Jun 7 2021, 10:48 AM
Jim updated this revision to Diff 350768.Jun 8 2021, 8:11 PM

Rebase

Jim added a comment.Jun 8 2021, 8:13 PM
In D103790#2801973, @Jim wrote:
In D103790#2801845, @craig.topper wrote:

The examples in the V spec show no spaces. Are you going to update that too? What about binutils?

I refer to https://github.com/riscv/riscv-binutils-gdb/blob/c5ef83e53e2528c0737bb0f40e6b77dc8b82eac8/gas/testsuite/gas/riscv/vector-insns.s
It looks that binutils can accept two formats with or without spaces.

I pull a request to update riscv-v-spec.
https://github.com/riscv/riscv-v-spec/pull/693

https://github.com/riscv/riscv-v-spec/pull/693 has been merged.

kito-cheng accepted this revision.Jun 8 2021, 8:14 PM

LGTM

This revision was landed with ongoing or failed builds.Jun 8 2021, 8:17 PM
Closed by commit rG242ddd50897c: [RISCV][NFC] Add a single space after comma for VType (authored by Jim). · Explain Why
This revision was automatically updated to reflect the committed changes.
Jim added a commit: rG242ddd50897c: [RISCV][NFC] Add a single space after comma for VType.
Harbormaster completed remote builds in B108328: Diff 350768.Jun 8 2021, 9:09 PM
frasercrmck mentioned this in rG292f4197249b: [RISCV] Fix failing RVV MC tests.Jun 9 2021, 1:55 AM
frasercrmck added a comment.Jun 9 2021, 1:59 AM

Note that I pushed rG292f4197249b to fix the failing tests introduced by this patch. Please check the test results before merging in the future, e.g. https://reviews.llvm.org/B107914 was showing this issue.

Jim added a comment.Jun 9 2021, 2:03 AM

Thanks, I missed to check MC tests.

Large Diff

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Diff 350772

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp

llvm/test/CodeGen/RISCV/rvv/abs-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll

llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll

llvm/test/CodeGen/RISCV/rvv/calling-conv.ll

llvm/test/CodeGen/RISCV/rvv/combine-store-fp.ll

llvm/test/CodeGen/RISCV/rvv/constant-folding.ll

llvm/test/CodeGen/RISCV/rvv/extload-truncstore.ll

llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll

llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv32.ll

llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv64.ll

llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll

llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll

llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast-large-vector.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-emergency-slot.mir

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-splat.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-vrgather.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-i1.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll

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llvm/test/CodeGen/RISCV/rvv/load-mask.ll

llvm/test/CodeGen/RISCV/rvv/localvar.ll

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llvm/test/CodeGen/RISCV/rvv/mask-exts-truncs-rv64.ll

llvm/test/CodeGen/RISCV/rvv/masked-load-fp.ll

llvm/test/CodeGen/RISCV/rvv/masked-load-int.ll

llvm/test/CodeGen/RISCV/rvv/masked-store-fp.ll

llvm/test/CodeGen/RISCV/rvv/masked-store-int.ll

llvm/test/CodeGen/RISCV/rvv/memory-args.ll

llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll

llvm/test/CodeGen/RISCV/rvv/regalloc-fast-crash.ll

llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll

llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll

llvm/test/CodeGen/RISCV/rvv/rv32-vsetvli-intrinsics.ll

llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll

llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll

llvm/test/CodeGen/RISCV/rvv/rv64-vsetvli-intrinsics.ll

llvm/test/CodeGen/RISCV/rvv/rvv-out-arguments.ll

llvm/test/CodeGen/RISCV/rvv/saddo-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/select-fp.ll

llvm/test/CodeGen/RISCV/rvv/select-int.ll

llvm/test/CodeGen/RISCV/rvv/select-sra.ll

llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv32.ll

llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv64.ll

llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv32.ll

llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv64.ll

llvm/test/CodeGen/RISCV/rvv/stepvector.ll

llvm/test/CodeGen/RISCV/rvv/unsupported-calling-conv.ll

llvm/test/CodeGen/RISCV/rvv/vaadd-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vaadd-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vaaddu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vaaddu-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vadc-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vadc-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vadd-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vadd-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vadd-sdnode-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vadd-sdnode-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll

llvm/test/CodeGen/RISCV/rvv/vamoadd-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vamoadd-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vamoand-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vamoand-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vamomax-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vamomax-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vamomaxu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vamomaxu-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vamomin-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vamomin-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vamominu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vamominu-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vamoor-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vamoor-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vamoswap-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vamoswap-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vamoxor-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vamoxor-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vand-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vand-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vand-sdnode-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vand-sdnode-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vand-vp.ll

llvm/test/CodeGen/RISCV/rvv/vasub-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vasub-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vasubu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vasubu-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vcompress-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vcompress-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vdiv-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vdiv-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll

llvm/test/CodeGen/RISCV/rvv/vdivu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vdivu-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv32.ll

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