[PowerPC] Implement trap and conversion builtins for XL compatibility

[Conanap]

Summary

This patch implements trap and FP to and from double conversions. The builtins
generate code that mirror what is generated from the XL compiler. Intrinsics
are named conventionally with builtin_ppc, but are aliased to provide the same
builtin names as the XL compiler.

[Conanap]

Rebase and added 64 bit sema checking

Rebased to include the updated location for the builtin alias
definition location, as well as added 64 bit checking for 64
bit only builtins in sema checking.

[qiucf]

clang/lib/Sema/SemaChecking.cpp

3346

Unnecessary brace?

llvm/include/llvm/IR/IntrinsicsPowerPC.td

115

This comment is little bit confusing: we don't have __builtin_ppc_fcfid in XL. XL has __fcfid instead. What we're doing is to follow Clang's convention to name them __builtin_xxx and defines macros to maintain XL compatibility.

llvm/lib/Target/PowerPC/PPCInstr64Bit.td

1735

Where is trap?

llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-conversionfunc.c

1 ↗

(On Diff #352431)

Please separate front-end and back-end tests. IIRC, LLVM doesn't accept end-to-end tests yet. So it's better to put 'C to IR' test in Clang's codegen, and put 'IR to Assembly' test in llvm/PowerPC's codegen.

Use %clang_cc1 in front-end tests. And also test in back-end if VSX is not available.

[Conanap]

Separated new test cases, rebased for newest changes, different semachecking

[Conanap]

Removed unneccessary brackets

[Conanap]

Addressed comments

[NeHuang]

clang/include/clang/Basic/BuiltinsPPC.def

32

seems like rebase issue that comments got overwritten.

50

definition here not matching prototype in document

void __tdw ( long a, long b, unsigned int TO);

51

prototype

void __tw (int a, int b, unsigned int TO);

why not using Ui for the last arg?

clang/lib/Sema/SemaChecking.cpp

3347

range suppose to be 0 to 31 based on document.

3349

same as above.

clang/test/CodeGen/builtins-ppc-xlcompat-conversionfunc.c

3

are these builtins all pwr9 only?

• If yes, please rename the file.
• If not, please use pwr8 for LE test and pwr7 for BE cases.

10

you can define extern variables here for the bulitins.

clang/test/CodeGen/builtins-ppc-xlcompat-error.c

17

range should be 0 to 31 as described in document.

TO A value of 0 to 31 inclusive. Each bit position, if set, indicates one or more of
the following possible conditions:

19

same as above

clang/test/CodeGen/builtins-ppc-xlcompat-trap.c

3

same as above.

llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-conversionfunc.ll

4

32 bit and 64 bit results look identical, you do not need prefixes.

[amyk]

clang/test/CodeGen/builtins-ppc-xlcompat-error.c

12

nit: Have these variables as extern like the other patches do.

clang/test/CodeGen/builtins-ppc-xlcompat-trap.c

15

nit: Have these variables as extern like the other patches do.

llvm/lib/Target/PowerPC/PPCInstrInfo.td

2233

Are tdne, tweq supposed to be aliases that are intended to be added here, too?

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

2840

Question: Why are these in PPCInstrPrefix.td? Shouldn't they be in PPCInstrInfo.td instead?

[Conanap]

Changed to ForceXForm

[Conanap]

Changed to ForceXForm

[Conanap]

Fixed incorrect diff update

[nemanjai]

It appears that Victor's comments have not been addressed yet and this is not ready for the next round of review. Requesting changes again to take it out of the queue until Victor's comments are addressed.

[Conanap]

Addressed comments, separated 64 bit C test cases.

clang/include/clang/Basic/BuiltinsPPC.def

50

the document had been incorrect; the document is now updated to to long long.

llvm/lib/Target/PowerPC/PPCInstrInfo.td

2233

the compiler seem to already know tdne and tweq so I didn't add those.

[Conanap]

Moved inst alias for 64bit to the 64 bit file

[NeHuang]

clang/test/CodeGen/builtins-ppc-xlcompat-conversionfunc.c

3

Please use pwr7 for BE test and pwr8 for LE test.

clang/test/CodeGen/builtins-ppc-xlcompat-trap-64bit-only.c

8 ↗

(On Diff #356988)

pwr8 -> pwr7

11 ↗

(On Diff #356988)

pwr8 -> pwr7

clang/test/CodeGen/builtins-ppc-xlcompat-trap.c

9

same as above

12

same as above.

llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-conversionfunc.ll

8

same target cpu issue for the aix run lines in back end test cases.

llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll

29

can you add another test case for call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 3) to verify the backend change below:

// tdne
def : Pat<(int_ppc_tdw g8rc:$A, g8rc:$B, 3),
          (TD 24, $A, $B)>;

42

seems the InstAlias defined for td and tw not working as expected

[nemanjai]

llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll

136

Where are the aliases twnei and tdnei coming from? You don't seem to add them.

[Conanap]

Rebased and changed aix test cases to pwr 7

[Conanap]

llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll

136

it should be from the trap extend mnemonics

[Conanap]

Removed inst aliases

[Conanap]

llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll

42

after discussion with Nemanja, we'll leave out the inst alias as that is a very low priority fix.

[Conanap]

Removed some incorrect patterns

[nemanjai]

llvm/lib/Target/PowerPC/PPCInstr64Bit.td

1728

This is supposed to be an unconditional trap and the produced sequence is not that.

[Conanap]

llvm/lib/Target/PowerPC/PPCInstr64Bit.td

1728

this one is quite weird... I see the output on xlC as tdnei:
0b 04 00 00 tdnei r4,0

Also for the tdne pattern that I removed (TD 3, ...), xlC outputs the same encoding for TD 3 and TD 24:

Disassembly of section .text:

0000000000000000 <.yes>:
   0:   7f 03 20 88     tdne    r3,r4
   4:   4e 80 00 20     blr
   8:   00 00 00 00     .long 0x0
   c:   00 00 20 00     .long 0x2000
  10:   00 00 00 00     .long 0x0
  14:   00 00 00 08     .long 0x8
        ...
void yes(long long a, long long b) {
   return __tdw(a, b, 24);
}

and for 3:

Disassembly of section .text:

0000000000000000 <.yes>:
   0:   7f 03 20 88     tdne    r3,r4
   4:   4e 80 00 20     blr
   8:   00 00 00 00     .long 0x0
   c:   00 00 20 00     .long 0x2000
  10:   00 00 00 00     .long 0x0
  14:   00 00 00 08     .long 0x8
        ...
void yes(long long a, long long b) {
   return __tdw(a, b, 3);
}

[Conanap]

Removed TWNE pattern as well

[nemanjai]

LGTM. @NeHuang please have a look to see if your comments are adequately addressed.

[NeHuang]

LGTM. Thanks for addressing the comments!

clang/include/clang/Basic/BuiltinsPPC.def

#   define CUSTOM_BUILTIN(ID, INTR, TYPES, ACCUMULATE) \
       BUILTIN(__builtin_##ID, "i.", "t")
 #elif defined(CUSTOM_BUILTIN) && !defined(BUILTIN)
 #   define BUILTIN(ID, TYPES, ATTRS)
 #endif
 
 #define UNALIASED_CUSTOM_BUILTIN(ID, TYPES, ACCUMULATE) \
    CUSTOM_BUILTIN(ID, ID, TYPES, ACCUMULATE)
 
-// builtins for compatibility with the XL compiler
+// XL Compatibility built-ins
 BUILTIN(__builtin_ppc_popcntb, "ULiULi", "")
 BUILTIN(__builtin_ppc_eieio, "v", "")
 BUILTIN(__builtin_ppc_iospace_eieio, "v", "")
 BUILTIN(__builtin_ppc_isync, "v", "")
 BUILTIN(__builtin_ppc_lwsync, "v", "")
 BUILTIN(__builtin_ppc_iospace_lwsync, "v", "")
 BUILTIN(__builtin_ppc_sync, "v", "")
 BUILTIN(__builtin_ppc_iospace_sync, "v", "")
 BUILTIN(__builtin_ppc_dcbfl, "vvC*", "")
 BUILTIN(__builtin_ppc_dcbflp, "vvC*", "")
 BUILTIN(__builtin_ppc_dcbst, "vvC*", "")
 BUILTIN(__builtin_ppc_dcbt, "vv*", "")
 BUILTIN(__builtin_ppc_dcbtst, "vv*", "")
 BUILTIN(__builtin_ppc_dcbz, "vv*", "")
 BUILTIN(__builtin_ppc_icbt, "vv*", "")
 BUILTIN(__builtin_ppc_compare_and_swap, "iiD*i*i", "")
 BUILTIN(__builtin_ppc_compare_and_swaplp, "iLiD*Li*Li", "")
+BUILTIN(__builtin_ppc_tdw, "vLLiLLiIi", "")
+BUILTIN(__builtin_ppc_tw, "viiIi", "")
+BUILTIN(__builtin_ppc_trap, "vi", "")
+BUILTIN(__builtin_ppc_trapd, "vLi", "")
+BUILTIN(__builtin_ppc_fcfid, "dd", "")
+BUILTIN(__builtin_ppc_fcfud, "dd", "")
+BUILTIN(__builtin_ppc_fctid, "dd", "")
+BUILTIN(__builtin_ppc_fctidz, "dd", "")
+BUILTIN(__builtin_ppc_fctiw, "dd", "")
+BUILTIN(__builtin_ppc_fctiwz, "dd", "")
+BUILTIN(__builtin_ppc_fctudz, "dd", "")
+BUILTIN(__builtin_ppc_fctuwz, "dd", "")
 
 BUILTIN(__builtin_ppc_get_timebase, "ULLi", "n")
 
 // This is just a placeholder, the types and attributes are wrong.
 BUILTIN(__builtin_altivec_vaddcuw, "V4UiV4UiV4Ui", "")
 
 BUILTIN(__builtin_altivec_vaddsbs, "V16ScV16ScV16Sc", "")
 BUILTIN(__builtin_altivec_vaddubs, "V16UcV16UcV16Uc", "")

clang/lib/Basic/Targets/PPC.cpp

static void defineXLCompatMacros(MacroBuilder &Builder) {
   Builder.defineMacro("__dcbst", "__builtin_ppc_dcbst");
   Builder.defineMacro("__dcbt", "__builtin_ppc_dcbt");
   Builder.defineMacro("__dcbtst", "__builtin_ppc_dcbtst");
   Builder.defineMacro("__dcbz", "__builtin_ppc_dcbz");
   Builder.defineMacro("__icbt", "__builtin_ppc_icbt");
   Builder.defineMacro("__compare_and_swap", "__builtin_ppc_compare_and_swap");
   Builder.defineMacro("__compare_and_swaplp",
                       "__builtin_ppc_compare_and_swaplp");
+  Builder.defineMacro("__tdw", "__builtin_ppc_tdw");
+  Builder.defineMacro("__tw", "__builtin_ppc_tw");
+  Builder.defineMacro("__trap", "__builtin_ppc_trap");
+  Builder.defineMacro("__trapd", "__builtin_ppc_trapd");
+  Builder.defineMacro("__fcfid", "__builtin_ppc_fcfid");
+  Builder.defineMacro("__fcfud", "__builtin_ppc_fcfud");
+  Builder.defineMacro("__fctid", "__builtin_ppc_fctid");
+  Builder.defineMacro("__fctidz", "__builtin_ppc_fctidz");
+  Builder.defineMacro("__fctiw", "__builtin_ppc_fctiw");
+  Builder.defineMacro("__fctiwz", "__builtin_ppc_fctiwz");
+  Builder.defineMacro("__fctudz", "__builtin_ppc_fctudz");
+  Builder.defineMacro("__fctuwz", "__builtin_ppc_fctuwz");
 }
 
 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
 /// #defines that are not tied to a specific subtarget.
 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
                                      MacroBuilder &Builder) const {
 
   defineXLCompatMacros(Builder);

clang/lib/Sema/SemaChecking.cpp

 }
 
 static bool isPPC_64Builtin(unsigned BuiltinID) {
   // These builtins only work on PPC 64bit targets.
   switch (BuiltinID) {
   case PPC::BI__builtin_divde:
   case PPC::BI__builtin_divdeu:
   case PPC::BI__builtin_bpermd:
+  case PPC::BI__builtin_ppc_tdw:
+  case PPC::BI__builtin_ppc_trapd:
     return true;
   }
   return false;
 }
 
 static bool SemaFeatureCheck(Sema &S, CallExpr *TheCall,
                              StringRef FeatureToCheck, unsigned DiagID) {
   if (!S.Context.getTargetInfo().hasFeature(FeatureToCheck))
bool Sema::CheckPPCBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID,
   case PPC::BI__builtin_vsx_xxeval:
      return SemaBuiltinConstantArgRange(TheCall, 3, 0, 255);
   case PPC::BI__builtin_altivec_vsldbi:
      return SemaBuiltinConstantArgRange(TheCall, 2, 0, 7);
   case PPC::BI__builtin_altivec_vsrdbi:
      return SemaBuiltinConstantArgRange(TheCall, 2, 0, 7);
   case PPC::BI__builtin_vsx_xxpermx:
      return SemaBuiltinConstantArgRange(TheCall, 3, 0, 7);
+  case PPC::BI__builtin_ppc_tw: {
+    return SemaBuiltinConstantArgRange(TheCall, 2, 1, 31);
+  }
+  case PPC::BI__builtin_ppc_tdw: {
+    return SemaBuiltinConstantArgRange(TheCall, 2, 1, 31);
+  }
 #define CUSTOM_BUILTIN(Name, Intr, Types, Acc) \
   case PPC::BI__builtin_##Name: \
     return SemaBuiltinPPCMMACall(TheCall, Types);
 #include "clang/Basic/BuiltinsPPC.def"
   }
   return SemaBuiltinConstantArgRange(TheCall, i, l, u);
 }
 

clang/test/CodeGen/builtins-ppc-xlcompat-conversionfunc.c

+// RUN: %clang_cc1 -O2 -triple powerpc64-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr9 | FileCheck %s
+// RUN: %clang_cc1 -O2 -triple powerpc64le-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr9 | FileCheck %s
+// RUN: %clang_cc1 -O2 -triple powerpc-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr9 | FileCheck %s
+// RUN: %clang_cc1 -O2 -triple powerpc64-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr9 | FileCheck %s
+
+double test_fcfid(double a) {
+  // CHECK-LABEL: test_fcfid
+  // CHECK-NEXT: entry:
+  // CHECK: double @llvm.ppc.fcfid(double %a)
+  return __builtin_ppc_fcfid(a);
+}
+
+double test_xl_fcfid(double a) {
+  // CHECK-LABEL: test_xl_fcfid
+  // CHECK-NEXT: entry:
+  // CHECK: double @llvm.ppc.fcfid(double %a)
+  return __fcfid(a);
+}
+
+double test_fcfud(double a) {
+  // CHECK-LABEL: test_fcfud
+  // CHECK-NEXT: entry:
+  // CHECK: double @llvm.ppc.fcfud(double %a)
+  return __builtin_ppc_fcfud(a);
+}
+
+double test_xl_fcfud(double a) {
+  // CHECK-LABEL: test_xl_fcfud
+  // CHECK-NEXT: entry:
+  // CHECK: double @llvm.ppc.fcfud(double %a)
+  return __fcfud(a);
+}
+
+double test_fctid(double a) {
+  // CHECK-LABEL: test_fctid
+  // CHECK-NEXT: entry:
+  // CHECK: double @llvm.ppc.fctid(double %a)
+  return __builtin_ppc_fctid(a);
+}
+
+double test_xl_fctid(double a) {
+  // CHECK-LABEL: test_xl_fctid
+  // CHECK-NEXT: entry:
+  // CHECK: double @llvm.ppc.fctid(double %a)
+  return __fctid(a);
+}
+
+double test_fctidz(double a) {
+  // CHECK-LABEL: test_fctidz
+  // CHECK-NEXT: entry:
+  // CHECK: double @llvm.ppc.fctidz(double %a)
+  return __builtin_ppc_fctidz(a);
+}
+
+double test_xl_fctidz(double a) {
+  // CHECK-LABEL: test_xl_fctidz
+  // CHECK-NEXT: entry:
+  // CHECK: double @llvm.ppc.fctidz(double %a)
+  return __fctidz(a);
+}
+
+double test_fctiw(double a) {
+  // CHECK-LABEL: test_fctiw
+  // CHECK-NEXT: entry:
+  // CHECK: double @llvm.ppc.fctiw(double %a)
+  return __builtin_ppc_fctiw(a);
+}
+
+double test_xl_fctiw(double a) {
+  // CHECK-LABEL: test_xl_fctiw
+  // CHECK-NEXT: entry:
+  // CHECK: double @llvm.ppc.fctiw(double %a)
+  return __fctiw(a);
+}
+
+double test_fctiwz(double a) {
+  // CHECK-LABEL: test_fctiwz
+  // CHECK-NEXT: entry:
+  // CHECK: double @llvm.ppc.fctiwz(double %a)
+  return __builtin_ppc_fctiwz(a);
+}
+
+double test_xl_fctiwz(double a) {
+  // CHECK-LABEL: test_xl_fctiwz
+  // CHECK-NEXT: entry:
+  // CHECK: double @llvm.ppc.fctiwz(double %a)
+  return __fctiwz(a);
+}
+
+double test_fctudz(double a) {
+  // CHECK-LABEL: test_fctudz
+  // CHECK-NEXT: entry:
+  // CHECK: double @llvm.ppc.fctudz(double %a)
+  return __builtin_ppc_fctudz(a);
+}
+
+double test_xl_fctudz(double a) {
+  // CHECK-LABEL: test_xl_fctudz
+  // CHECK-NEXT: entry:
+  // CHECK: double @llvm.ppc.fctudz(double %a)
+  return __fctudz(a);
+}
+
+double test_fctuwz(double a) {
+  // CHECK-LABEL: test_fctuwz
+  // CHECK-NEXT: entry:
+  // CHECK: double @llvm.ppc.fctuwz(double %a)
+  return __builtin_ppc_fctuwz(a);
+}
+
+double test_xl_fctuwz(double a) {
+  // CHECK-LABEL: test_xl_fctuwz
+  // CHECK-NEXT: entry:
+  // CHECK: double @llvm.ppc.fctuwz(double %a)
+  return __fctuwz(a);
+}

clang/test/CodeGen/builtins-ppc-xlcompat-error.c

+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -fsyntax-only \
+// RUN:   -Wall -Werror -verify %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -fsyntax-only \
+// RUN:   -Wall -Werror -verify %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix -fsyntax-only \
+// RUN:   -Wall -Werror -verify %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -fsyntax-only \
+// RUN:   -Wall -Werror -verify %s
+
+long long lla, llb;
+int ia, ib;
+
+void test_trap(void) {
+#ifdef __PPC64__
+  __tdw(lla, llb, 50); //expected-error {{argument value 50 is outside the valid range [1, 31]}}
+#endif
+  __tw(ia, ib, 50); //expected-error {{argument value 50 is outside the valid range [1, 31]}}
+}

clang/test/CodeGen/builtins-ppc-xlcompat-trap.c

+// RUN: %clang_cc1 -O2 -triple powerpc64-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr9 | \
+// RUN:  FileCheck %s --check-prefixes=CHECK64,CHECK
+// RUN: %clang_cc1 -O2 -triple powerpc64le-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr9 | \
+// RUN:  FileCheck %s --check-prefixes=CHECK64,CHECK
+// RUN: %clang_cc1 -O2 -triple powerpc-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr9 | \
+// RUN:  FileCheck %s -check-prefixes=CHECK
+// RUN: %clang_cc1 -O2 -triple powerpc64-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr9 | \
+// RUN:  FileCheck %s --check-prefixes=CHECK64,CHECK
+
+long long lla, llb;
+double da;
+int ia, ib;
+
+#ifdef __ppc64__
+// tdw
+void test_xl_tdw(void) {
+// CHECK64: void @llvm.ppc.tdw(i64 %0, i64 %1, i32 1)
+
+  __tdw(lla, llb, 1);
+}
+
+void test_tdw(void) {
+// CHECK64: void @llvm.ppc.tdw(i64 %0, i64 %1, i32 13)
+
+  __builtin_ppc_tdw(lla, llb, 13);
+}
+#endif
+
+// td
+void test_tw(void) {
+// CHECK: void @llvm.ppc.tw(i32 %0, i32 %1, i32 1)
+
+  __builtin_ppc_tw(ia, ib, 1);
+}
+
+void test_xl_tw(void) {
+// CHECK: void @llvm.ppc.tw(i32 %0, i32 %1, i32 1)
+
+  __tw(ia, ib, 1);
+}
+
+// trap
+void test_trap(void) {
+// CHECK: void @llvm.ppc.trap(i32 %0)
+  __builtin_ppc_trap(ia);
+}
+
+void test_xl_trap(void) {
+// CHECK: void @llvm.ppc.trap(i32 %0)
+  __trap(ia);
+}
+
+#ifdef __PPC64__
+// trapd
+void test_trapd(void) {
+// CHECK64: void @llvm.ppc.trapd(i64 %conv)
+  __builtin_ppc_trapd(da);
+}
+
+void test_xl_trapd(void) {
+// CHECK64: void @llvm.ppc.trapd(i64 %conv)
+  __trapd(da);
+}
+#endif

llvm/include/llvm/IR/IntrinsicsPowerPC.td

def int_ppc_fmaf128_round_to_odd
         Intrinsic <[llvm_f128_ty], [llvm_f128_ty,llvm_f128_ty,llvm_f128_ty], [IntrNoMem]>;
   def int_ppc_scalar_extract_expq
       : GCCBuiltin<"__builtin_vsx_scalar_extract_expq">,
         Intrinsic <[llvm_i64_ty], [llvm_f128_ty], [IntrNoMem]>;
   def int_ppc_scalar_insert_exp_qp
       : GCCBuiltin<"__builtin_vsx_scalar_insert_exp_qp">,
         Intrinsic <[llvm_f128_ty], [llvm_f128_ty, llvm_i64_ty], [IntrNoMem]>;
 
+  // Intrinsics defined to maintain XL compatibility
+  def int_ppc_tdw
+      : GCCBuiltin<"__builtin_ppc_tdw">,
+        Intrinsic <[], [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty], [ImmArg<ArgIndex<2>>]>;
+  def int_ppc_tw
+      : GCCBuiltin<"__builtin_ppc_tw">,
+        Intrinsic <[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<2>>]>;
+  def int_ppc_trapd
+      : GCCBuiltin<"__builtin_ppc_trapd">,
+        Intrinsic <[], [llvm_i64_ty], []>;
+  def int_ppc_trap
+      : GCCBuiltin<"__builtin_ppc_trap">,
+        Intrinsic <[], [llvm_i32_ty], []>;
+  def int_ppc_fcfid
+      : GCCBuiltin<"__builtin_ppc_fcfid">,
+        Intrinsic <[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;
+  def int_ppc_fcfud
+      : GCCBuiltin<"__builtin_ppc_fcfud">,
+        Intrinsic <[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;
+  def int_ppc_fctid
+      : GCCBuiltin<"__builtin_ppc_fctid">,
+        Intrinsic <[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;
+  def int_ppc_fctidz
+      : GCCBuiltin<"__builtin_ppc_fctidz">,
+        Intrinsic <[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;
+  def int_ppc_fctiw
+      : GCCBuiltin<"__builtin_ppc_fctiw">,
+        Intrinsic <[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;
+  def int_ppc_fctiwz
+      : GCCBuiltin<"__builtin_ppc_fctiwz">,
+        Intrinsic <[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;
+  def int_ppc_fctudz
+      : GCCBuiltin<"__builtin_ppc_fctudz">,
+        Intrinsic <[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;
+  def int_ppc_fctuwz
+      : GCCBuiltin<"__builtin_ppc_fctuwz">,
+        Intrinsic <[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;
 }
 
-
 let TargetPrefix = "ppc" in {  // All PPC intrinsics start with "llvm.ppc.".
   /// PowerPC_Vec_Intrinsic - Base class for all altivec intrinsics.
   class PowerPC_Vec_Intrinsic<string GCCIntSuffix, list<LLVMType> ret_types,
                               list<LLVMType> param_types,
                               list<IntrinsicProperty> properties>
     : GCCBuiltin<!strconcat("__builtin_altivec_", GCCIntSuffix)>,
       Intrinsic<ret_types, param_types, properties>;
 

llvm/lib/Target/PowerPC/PPCInstr64Bit.td

 
 // SLB Invalidate Entry Global
 def SLBIEG : XForm_26<31, 466, (outs), (ins gprc:$RS, gprc:$RB),
                       "slbieg $RS, $RB", IIC_SprSLBIEG, []>;
 // SLB Synchronize
 def SLBSYNC : XForm_0<31, 338, (outs), (ins), "slbsync", IIC_SprSLBSYNC, []>;
 
 } // IsISA3_0
+
+// tdne
+def : Pat<(int_ppc_tdw g8rc:$A, g8rc:$B, 3),
+          (TD 24, $A, $B)>;
+// tweq, but we can use tdeq instead
+// as XL produces a tweq <regA>, <regA>.
+def : Pat<(int_ppc_tdw g8rc:$A, g8rc:$B, 31),
+          (TD 4, $A, $B)>;
+def : Pat<(int_ppc_tdw g8rc:$A, g8rc:$B, i32:$IMM),
+          (TD $IMM, $A, $B)>;
+
+// trapd
+def : Pat<(int_ppc_trapd g8rc:$A),
+          (TDI 24, $A, 0)>;

llvm/lib/Target/PowerPC/PPCInstrInfo.td

def TWI : DForm_base<3, (outs), (ins u5imm:$to, gprc:$rA, s16imm:$imm),
                      "twi $to, $rA, $imm", IIC_IntTrapW, []>;
 def TW : XForm_1<31, 4, (outs), (ins u5imm:$to, gprc:$rA, gprc:$rB),
                  "tw $to, $rA, $rB", IIC_IntTrapW, []>;
 def TDI : DForm_base<2, (outs), (ins u5imm:$to, g8rc:$rA, s16imm:$imm),
                      "tdi $to, $rA, $imm", IIC_IntTrapD, []>;
 def TD : XForm_1<31, 68, (outs), (ins u5imm:$to, g8rc:$rA, g8rc:$rB),
                  "td $to, $rA, $rB", IIC_IntTrapD, []>;
 
+def : InstAlias<"tdlle $rA, $rB", (TD 6, g8rc:$rA, g8rc:$rB)>;
+def : InstAlias<"tdlge $rA, $rB", (TD 5, g8rc:$rA, g8rc:$rB)>;
+def : InstAlias<"tdge $rA, $rB", (TD 12, g8rc:$rA, g8rc:$rB)>;
+def : InstAlias<"tdle $rA, $rB", (TD 20, g8rc:$rA, g8rc:$rB)>;
+def : InstAlias<"twlle $rA, $rB", (TW 6, gprc:$rA, gprc:$rB)>;
+def : InstAlias<"twlge $rA, $rB", (TW 5, gprc:$rA, gprc:$rB)>;
+def : InstAlias<"twge $rA, $rB", (TW 12, gprc:$rA, gprc:$rB)>;
+def : InstAlias<"twle $rA, $rB", (TW 20, gprc:$rA, gprc:$rB)>;
+
 //===----------------------------------------------------------------------===//
 // PPC32 Load Instructions.
 //
 
 // Unindexed (r+i) Loads.
 let PPC970_Unit = 2 in {
 def LBZ : DForm_1<34, (outs gprc:$rD), (ins memri:$src),
                   "lbz $rD, $src", IIC_LdStLoad,

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

def : Pat<(v4f32 (PPCvecinsertelt v4f32:$vDi, (f32 (load iaddrX34:$rA)), (i64 i))),
               (VINSW $vDi, !mul(i, 4), (PLWZ memri34:$rA))>;
     def : Pat<(v4f32 (PPCvecinsertelt v4f32:$vDi, (f32 (load xaddr:$rA)), (i64 i))),
               (VINSW $vDi, !mul(i, 4), (LWZX memrr:$rA))>;
   }
   foreach i = [0, 1] in
     def : Pat<(v2i64 (PPCvecinsertelt v2i64:$vDi, i64:$rA, (i64 i))),
               (VINSD $vDi, !mul(i, 8), $rA)>;
 }
+
+// XL Compatibility
+// twne
+def : Pat<(int_ppc_tw gprc:$A, gprc:$B, 3),
+          (TW 24, $A, $B)>;
+// tweq
+def : Pat<(int_ppc_tw gprc:$A, gprc:$B, 31),
+          (TW 4, $A, $B)>;
+def : Pat<(int_ppc_tw gprc:$A, gprc:$B, i32:$IMM),
+          (TW $IMM, $A, $B)>;
+def : Pat<(int_ppc_trap gprc:$A),
+          (TWI 24, $A, 0)>;
+
+def : Pat<(int_ppc_fcfid f64:$A),
+        (XSCVSXDDP $A)>;
+def : Pat<(int_ppc_fcfud f64:$A),
+        (XSCVUXDDP $A)>;
+def : Pat<(int_ppc_fctid f64:$A),
+        (FCTID $A)>;
+def : Pat<(int_ppc_fctidz f64:$A),
+        (XSCVDPSXDS $A)>;
+def : Pat<(int_ppc_fctiw f64:$A),
+        (FCTIW $A)>;
+def : Pat<(int_ppc_fctiwz f64:$A),
+        (XSCVDPSXWS $A)>;
+def : Pat<(int_ppc_fctudz f64:$A),
+        (XSCVDPUXDS $A)>;
+def : Pat<(int_ppc_fctuwz f64:$A),
+        (XSCVDPUXWS $A)>;

llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-conversionfunc.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-64
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-64
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-32
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-64
+
+declare double @llvm.ppc.fcfid(double %a)
+define dso_local double @test_fcfid(double %a) {
+; CHECK-64-LABEL: test_fcfid:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    xscvsxddp 1, 1
+; CHECK-64-NEXT:    blr
+;
+; CHECK-32-LABEL: test_fcfid:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    xscvsxddp 1, 1
+; CHECK-32-NEXT:    blr
+  %1 = call double @llvm.ppc.fcfid(double %a)
+  ret double %1
+}
+
+declare double @llvm.ppc.fcfud(double %a)
+define dso_local double @test_fcfud(double %a) {
+; CHECK-64-LABEL: test_fcfud:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    xscvuxddp 1, 1
+; CHECK-64-NEXT:    blr
+;
+; CHECK-32-LABEL: test_fcfud:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    xscvuxddp 1, 1
+; CHECK-32-NEXT:    blr
+  %1 = call double @llvm.ppc.fcfud(double %a)
+  ret double %1
+}
+
+declare double @llvm.ppc.fctid(double %a)
+define dso_local double @test_fctid(double %a) {
+; CHECK-64-LABEL: test_fctid:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    fctid 1, 1
+; CHECK-64-NEXT:    blr
+;
+; CHECK-32-LABEL: test_fctid:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    fctid 1, 1
+; CHECK-32-NEXT:    blr
+  %1 = call double @llvm.ppc.fctid(double %a)
+  ret double %1
+}
+
+declare double @llvm.ppc.fctidz(double %a)
+define dso_local double @test_fctidz(double %a) {
+; CHECK-64-LABEL: test_fctidz:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    fctid 1, 1
+; CHECK-64-NEXT:    blr
+;
+; CHECK-32-LABEL: test_fctidz:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    fctid 1, 1
+; CHECK-32-NEXT:    blr
+  %1 = call double @llvm.ppc.fctid(double %a)
+  ret double %1
+}
+
+declare double @llvm.ppc.fctiw(double %a)
+define dso_local double @test_fctiw(double %a) {
+; CHECK-64-LABEL: test_fctiw:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    fctid 1, 1
+; CHECK-64-NEXT:    blr
+;
+; CHECK-32-LABEL: test_fctiw:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    fctid 1, 1
+; CHECK-32-NEXT:    blr
+  %1 = call double @llvm.ppc.fctid(double %a)
+  ret double %1
+}
+
+declare double @llvm.ppc.fctiwz(double %a)
+define dso_local double @test_fctiwz(double %a) {
+; CHECK-64-LABEL: test_fctiwz:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    fctid 1, 1
+; CHECK-64-NEXT:    blr
+;
+; CHECK-32-LABEL: test_fctiwz:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    fctid 1, 1
+; CHECK-32-NEXT:    blr
+  %1 = call double @llvm.ppc.fctid(double %a)
+  ret double %1
+}
+
+declare double @llvm.ppc.fctudz(double %a)
+define dso_local double @test_fctudz(double %a) {
+; CHECK-64-LABEL: test_fctudz:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    fctid 1, 1
+; CHECK-64-NEXT:    blr
+;
+; CHECK-32-LABEL: test_fctudz:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    fctid 1, 1
+; CHECK-32-NEXT:    blr
+  %1 = call double @llvm.ppc.fctid(double %a)
+  ret double %1
+}
+
+declare double @llvm.ppc.fctuwz(double %a)
+define dso_local double @test_fctuwz(double %a) {
+; CHECK-64-LABEL: test_fctuwz:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    fctid 1, 1
+; CHECK-64-NEXT:    blr
+;
+; CHECK-32-LABEL: test_fctuwz:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    fctid 1, 1
+; CHECK-32-NEXT:    blr
+  %1 = call double @llvm.ppc.fctid(double %a)
+  ret double %1
+}

llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+
+; tdw
+declare void @llvm.ppc.tdw(i64 %a, i64 %b, i32 immarg)
+define dso_local void @test__tdwlgt(i64 %a, i64 %b) {
+; CHECK-LABEL: test__tdwlgt:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    tdlgt 3, 4
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 1)
+  ret void
+}
+
+define dso_local void @test__tdwllt(i64 %a, i64 %b) {
+; CHECK-LABEL: test__tdwllt:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    tdllt 3, 4
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 2)
+  ret void
+}
+
+define dso_local void @test__tdweq(i64 %a, i64 %b) {
+; CHECK-LABEL: test__tdweq:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    tdeq 3, 4
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 4)
+  ret void
+}
+
+define dso_local void @test__tdwlge(i64 %a, i64 %b) {
+; CHECK-LABEL: test__tdwlge:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    td 5, 3, 4
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 5)
+  ret void
+}
+
+define dso_local void @test__tdwlle(i64 %a, i64 %b) {
+; CHECK-LABEL: test__tdwlle:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    td 6, 3, 4
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 6)
+  ret void
+}
+
+define dso_local void @test__tdwgt(i64 %a, i64 %b) {
+; CHECK-LABEL: test__tdwgt:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    tdgt 3, 4
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 8)
+  ret void
+}
+
+define dso_local void @test__tdwge(i64 %a, i64 %b) {
+; CHECK-LABEL: test__tdwge:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    td 12, 3, 4
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 12)
+  ret void
+}
+
+define dso_local void @test__tdwlt(i64 %a, i64 %b) {
+; CHECK-LABEL: test__tdwlt:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    tdlt 3, 4
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 16)
+  ret void
+}
+
+define dso_local void @test__tdwle(i64 %a, i64 %b) {
+; CHECK-LABEL: test__tdwle:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    td 20, 3, 4
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 20)
+  ret void
+}
+
+define dso_local void @test__tdwne24(i64 %a, i64 %b) {
+; CHECK-LABEL: test__tdwne24:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    tdne 3, 4
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 24)
+  ret void
+}
+
+define dso_local void @test__tdweq31(i64 %a, i64 %b) {
+; CHECK-LABEL: test__tdweq31:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    tdeq 3, 4
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 31)
+  ret void
+}
+
+define dso_local void @test__tdw_no_match(i64 %a, i64 %b) {
+; CHECK-LABEL: test__tdw_no_match:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    td 13, 3, 4
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 13)
+  ret void
+}
+
+; trapd
+declare void @llvm.ppc.trapd(i64 %a)
+define dso_local void @test__trapd(i64 %a) {
+; CHECK-LABEL: test__trapd:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    tdnei 3, 0
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.trapd(i64 %a)
+  ret void
+}

llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+
+; tw
+declare void @llvm.ppc.tw(i32 %a, i32 %b, i32 %c)
+define dso_local void @test__twlgt(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twlgt:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    twlgt 3, 4
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 1)
+  ret void
+}
+
+define dso_local void @test__twllt(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twllt:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    twllt 3, 4
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 2)
+  ret void
+}
+
+define dso_local void @test__twne3(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twne3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    twne 3, 4
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 3)
+  ret void
+}
+
+define dso_local void @test__tweq(i32 %a, i32 %b) {
+; CHECK-LABEL: test__tweq:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    tweq 3, 4
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 4)
+  ret void
+}
+
+define dso_local void @test__twlge(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twlge:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    tw 5, 3, 4
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 5)
+  ret void
+}
+
+define dso_local void @test__twlle(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twlle:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    tw 6, 3, 4
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 6)
+  ret void
+}
+
+define dso_local void @test__twgt(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twgt:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    twgt 3, 4
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 8)
+  ret void
+}
+
+define dso_local void @test__twge(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twge:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    tw 12, 3, 4
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 12)
+  ret void
+}
+
+define dso_local void @test__twlt(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twlt:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    twlt 3, 4
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 16)
+  ret void
+}
+
+define dso_local void @test__twle(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twle:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    tw 20, 3, 4
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 20)
+  ret void
+}
+
+define dso_local void @test__twne24(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twne24:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    twne 3, 4
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 24)
+  ret void
+}
+
+define dso_local void @test__tweq31(i32 %a, i32 %b) {
+; CHECK-LABEL: test__tweq31:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    tweq 3, 4
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 31)
+  ret void
+}
+
+define dso_local void @test__tw_no_match(i32 %a, i32 %b) {
+; CHECK-LABEL: test__tw_no_match:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    tw 13, 3, 4
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 13)
+  ret void
+}
+
+; trap
+declare void @llvm.ppc.trap(i32 %a)
+define dso_local void @test__trap(i32 %a) {
+; CHECK-LABEL: test__trap:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    twnei 3, 0
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.trap(i32 %a)
+  ret void
+}