[Clang] Add option to handle behaviour of vector bool/vector pixel.

[stefanp]

Summary

Added the option -altivec-src-compat=[mixed,gcc,xl]. The default at this time is mixed.

The default behavior for clang is for all vector compares to return a scalar unless the vectors being
compared are vector bool or vector pixel. In that case the compare returns a
vector. With the gcc case all vector compares return vectors and in the xl case
all vector compares return scalars.

This patch does not change the default behavior of clang.

This option will be used in future patches to implement behaviour compatibility for the vector bool/pixel types.

[bmahjour]

As far as I can see, there is no good reason for the special treatment of vector bool/pixel going forward. Could we drop this special treatment, or at least change the default to use scalar results across the board (consistent with XL's behaviour and clang's current behaviour for most cases).

clang/include/clang/Driver/Options.td

3826

I'm not sure the term "ABI" is really applicable. Maybe we should call it "vector-compare-compat="

clang/test/CodeGen/vector-compat-pixel-bool-ternary.c

7

I only see the clang FE interface being tested. Does this have to be specified through -Xclang -vector-abi-compat=... or is there a clang driver option for it as well? I think we should have a clang driver option and have at least one test for it.

[stefanp]

In D103615#2799498, @bmahjour wrote:

As far as I can see, there is no good reason for the special treatment of vector bool/pixel going forward. Could we drop this special treatment, or at least change the default to use scalar results across the board (consistent with XL's behaviour and clang's current behaviour for most cases).

We can change this but I am hesitant to make the change immediately. I can leave the default behavior as-is for now and add a warning to say that this feature is going to be deprecated at a later date. After a couple of releases we can then change the default. I don't want to change defaults without giving users some kind of warning first.

As a result of this I'm going to change the name in the enum from Default to Mixed as it does not make sense to have it named Default if it's not going to be default in the long run.

clang/include/clang/Driver/Options.td

3826

Sure. I can change the name to vector-compare-compat.

clang/test/CodeGen/vector-compat-pixel-bool-ternary.c

7

This option works when it is passed immediately to clang.
I will add a couple of RUN lines to test this as well.

[stefanp]

Updated the name of the option to vector-compare compat.
Added clang test lines to the test cases.
Added deprecation warnings to the current default behaviour of vector bool and
vector pixel.

[bmahjour]

clang/include/clang/Basic/LangOptions.h

248

How about adding Default = Mixed at the end and moving the comment with it?

249

Pixel -> pixel

250

[nit] Pixel -> pixel

clang/lib/Sema/SemaExpr.cpp

12232

Check for getLangOpts().AltiVec before the switch?

[stefanp]

Moved if statement out of switch and added the Default=Mixed.

[bmahjour]

Sorry I didn't mention this in my earlier comment about the option name, but I think that all inconsistencies in handling vector bool/pixel types should be controlled by a single compatibility option. For example the current special handling of initialization (splat vs non-splat) for these types should also be option controlled. For that reason we should design and name the option in a more generic way. The same consideration should go into the wording of the deprecation warning.
Some suggestions:

rename -vector-compare-compat to -altivec-compatibility or -altivec-compat or -altivec-bool-pixel-compat or -vector-bool-pixel-compat. (I prefer the last two)
reword the message to:
"Current handling of vector bool and vector pixel types in this context are deprecated. The default behaviour will soon change to that implied by the '-altivec-compat=xl' option"

Please also update the description section of this review.

clang/include/clang/Basic/DiagnosticSemaKinds.td

7447

We need to add a new grouping (see InGroup<...>) for this, otherwise users won't be able to turn this warning off individually. There is also a clang LIT test that would fail if a warning message is added without a grouping specified. Please make sure check-all passes.

clang/include/clang/Basic/LangOptions.def

130

VectorCompareCompatKind::Mixed -> VectorCompareCompatKind::Default

[nemanjai]

I haven't had time to review this yet, but I just wanted to chime in on the option spelling and description. I think we should go with:

-faltivec-src-compat={xl|gcc|mixed}
  Source-level compatibility for Altivec vectors (for PowerPC targets). This
  includes results of vector comparison (scalar for 'xl', vector for 'gcc')
  as well as behavior when initializing with a scalar (splatting for 'xl',
  element zero only for 'gcc'). For 'mixed', the compatibility is as 'gcc' for
  'vector bool/vector pixel' and as 'xl' for other types. Current default is
  'mixed'.

The name makes it clear that this has to do with source compatibility for Altivec vector types. The description is rather verbose - much more so than most options, but I think that is useful for an option such as this - that has a complex set of implications.

[stefanp]

Updated the name of the option to cover all of the inconsistencies for vector
pixel/bool. Future patches will continue to use this option to define the
behaviour of these two types.

Reworded the warning message.
Added InGroup<> to the warning.
Set the default to Default.

[bmahjour]

LGTM

[dblaikie]

As mentioned in the reverting commit - these tests fail in non-asserts builds, because they assume named IR instructions (like the named entry BB label), which aren't provided on a non-asserts build (there's a flag to turn them on - but that's probably not the right fix - making the test resilient to non-asserts IR is probably the right fix).

Leaving non-asserts builds broken for 12 hours (maybe I'm the first one to come across/report it - but I'd expect there are some buildbots that would fail, etc) is quite a while - best to be avoided when possible.

[dyung]

In D103615#2846245, @dblaikie wrote:

As mentioned in the reverting commit - these tests fail in non-asserts builds, because they assume named IR instructions (like the named entry BB label), which aren't provided on a non-asserts build (there's a flag to turn them on - but that's probably not the right fix - making the test resilient to non-asserts IR is probably the right fix).

Leaving non-asserts builds broken for 12 hours (maybe I'm the first one to come across/report it - but I'd expect there are some buildbots that would fail, etc) is quite a while - best to be avoided when possible.

Our internal bot also caught it and I was readying a patch to add "REQUIRES: asserts" to the tests as a workaround.

[dblaikie]

In D103615#2846251, @dyung wrote:

In D103615#2846245, @dblaikie wrote:

As mentioned in the reverting commit - these tests fail in non-asserts builds, because they assume named IR instructions (like the named entry BB label), which aren't provided on a non-asserts build (there's a flag to turn them on - but that's probably not the right fix - making the test resilient to non-asserts IR is probably the right fix).

Leaving non-asserts builds broken for 12 hours (maybe I'm the first one to come across/report it - but I'd expect there are some buildbots that would fail, etc) is quite a while - best to be avoided when possible.

Our internal bot also caught it and I was readying a patch to add "REQUIRES: asserts" to the tests as a workaround.

Thanks for the confirmation! Yeah, I probably could've/should've settled for that narrower solution - good to keep in mind for next time.

[stefanp]

I'm sorry I missed the asserts requirement.
I will recommit this patch after I add REQUIRES: asserts.

[bmahjour]

In D103615#2847047, @stefanp wrote:

I'm sorry I missed the asserts requirement.
I will recommit this patch after I add REQUIRES: asserts.

Instead of disabling the tests for non-assert builds, can we just remove the entry: checks at the beginning of each function? The rest of the IR checks should pass since they use a regexp so they should match for either named or unnamed instructions.

[bmahjour]

In D103615#2846245, @dblaikie wrote:

As mentioned in the reverting commit - these tests fail in non-asserts builds, because they assume named IR instructions (like the named entry BB label), which aren't provided on a non-asserts build (there's a flag to turn them on - but that's probably not the right fix - making the test resilient to non-asserts IR is probably the right fix).

Leaving non-asserts builds broken for 12 hours (maybe I'm the first one to come across/report it - but I'd expect there are some buildbots that would fail, etc) is quite a while - best to be avoided when possible.

This is a bit off topic, but I'm just curious about clang's rationale for producing different IR depending on whether asserts are on/off? Seems strange and undesirable to me.

[dblaikie]

In D103615#2847118, @bmahjour wrote:

In D103615#2847047, @stefanp wrote:

I'm sorry I missed the asserts requirement.
I will recommit this patch after I add REQUIRES: asserts.

Instead of disabling the tests for non-assert builds, can we just remove the entry: checks at the beginning of each function? The rest of the IR checks should pass since they use a regexp so they should match for either named or unnamed instructions.

(generally: disabling the test in non-asserts builds isn't the right path, modifying the test so it doesn't depend on asserts IR naming is the right path)

Yes, probably removing the entry: check would be sufficient - give it a test locally and see how it goes. (it does mean the "CHECK-NEXT" after that (for the first instruction) would have to be a plain "CHECK" - so that the test could pass both in the presence and absence of the entry label.

In D103615#2847124, @bmahjour wrote:

In D103615#2846245, @dblaikie wrote:

As mentioned in the reverting commit - these tests fail in non-asserts builds, because they assume named IR instructions (like the named entry BB label), which aren't provided on a non-asserts build (there's a flag to turn them on - but that's probably not the right fix - making the test resilient to non-asserts IR is probably the right fix).

Leaving non-asserts builds broken for 12 hours (maybe I'm the first one to come across/report it - but I'd expect there are some buildbots that would fail, etc) is quite a while - best to be avoided when possible.

This is a bit off topic, but I'm just curious about clang's rationale for producing different IR depending on whether asserts are on/off? Seems strange and undesirable to me.

Yeah, seems like a weird choice to me too (though has been around a long time, so folks are pretty used to it) - might be worth bringing it up on llvm-dev. I think we now have a flag to enable this functionality that works even in non-asserts builds (maybe?) so maybe if we just change the default for assert builds so it's always opt-in via a flag, then it's consistent between asserts and non-asserts builds.

[bmahjour]

(generally: disabling the test in non-asserts builds isn't the right path, modifying the test so it doesn't depend on asserts IR naming is the right path)

Agreed.

Yes, probably removing the entry: check would be sufficient - give it a test locally and see how it goes. (it does mean the "CHECK-NEXT" after that (for the first instruction) would have to be a plain "CHECK" - so that the test could pass both in the presence and absence of the entry label.

Right.

Yeah, seems like a weird choice to me too (though has been around a long time, so folks are pretty used to it) - might be worth bringing it up on llvm-dev. I think we now have a flag to enable this functionality that works even in non-asserts builds (maybe?) so maybe if we just change the default for assert builds so it's always opt-in via a flag, then it's consistent between asserts and non-asserts builds.

Do you happen to know what that option is? Thanks!

[dblaikie]

In D103615#2847704, @bmahjour wrote:

(generally: disabling the test in non-asserts builds isn't the right path, modifying the test so it doesn't depend on asserts IR naming is the right path)

Agreed.

Yes, probably removing the entry: check would be sufficient - give it a test locally and see how it goes. (it does mean the "CHECK-NEXT" after that (for the first instruction) would have to be a plain "CHECK" - so that the test could pass both in the presence and absence of the entry label.

Right.

Yeah, seems like a weird choice to me too (though has been around a long time, so folks are pretty used to it) - might be worth bringing it up on llvm-dev. I think we now have a flag to enable this functionality that works even in non-asserts builds (maybe?) so maybe if we just change the default for assert builds so it's always opt-in via a flag, then it's consistent between asserts and non-asserts builds.

Do you happen to know what that option is? Thanks!

Generally called "discard value names" - clang has -f{no-}discard-value-names - the various command line tools (opt, llc, etc) have some similar flags with spelling more suitable to the various command line syntaxes, etc...

[stefanp]

In D103615#2847650, @dblaikie wrote:

In D103615#2847118, @bmahjour wrote:

In D103615#2847047, @stefanp wrote:

I'm sorry I missed the asserts requirement.
I will recommit this patch after I add REQUIRES: asserts.

Instead of disabling the tests for non-assert builds, can we just remove the entry: checks at the beginning of each function? The rest of the IR checks should pass since they use a regexp so they should match for either named or unnamed instructions.

(generally: disabling the test in non-asserts builds isn't the right path, modifying the test so it doesn't depend on asserts IR naming is the right path)

Yes, probably removing the entry: check would be sufficient - give it a test locally and see how it goes. (it does mean the "CHECK-NEXT" after that (for the first instruction) would have to be a plain "CHECK" - so that the test could pass both in the presence and absence of the entry label.

I've removed all of the entry: checks and changed for next line to CHECK: and that seems to be working with assertions off. I will recommit the patch like that if this is preferred.

[dblaikie]

In D103615#2847965, @stefanp wrote:

In D103615#2847650, @dblaikie wrote:

In D103615#2847118, @bmahjour wrote:

In D103615#2847047, @stefanp wrote:

I'm sorry I missed the asserts requirement.
I will recommit this patch after I add REQUIRES: asserts.

Instead of disabling the tests for non-assert builds, can we just remove the entry: checks at the beginning of each function? The rest of the IR checks should pass since they use a regexp so they should match for either named or unnamed instructions.

(generally: disabling the test in non-asserts builds isn't the right path, modifying the test so it doesn't depend on asserts IR naming is the right path)

Yes, probably removing the entry: check would be sufficient - give it a test locally and see how it goes. (it does mean the "CHECK-NEXT" after that (for the first instruction) would have to be a plain "CHECK" - so that the test could pass both in the presence and absence of the entry label.

I've removed all of the entry: checks and changed for next line to CHECK: and that seems to be working with assertions off. I will recommit the patch like that if this is preferred.

Sounds alright to me

[stefanp]

Updated test cases to avoid failures on non assert builds.

[stefanp]

Removed the lines that specified that checks were auto generated.

[krasimir]

I'm unfamiliar with the altivec API. What's a reasonable source code update that preserves the current default behavior -altivec-src-compat=mixed under -altivec-src-compat=xl, i.e., under -altivec-src-compat=xl how would we compare vector bool or vector pixel to produce a vector?

[bmahjour]

In D103615#2852430, @krasimir wrote:

I'm unfamiliar with the altivec API. What's a reasonable source code update that preserves the current default behavior -altivec-src-compat=mixed under -altivec-src-compat=xl, i.e., under -altivec-src-compat=xl how would we compare vector bool or vector pixel to produce a vector?

For vector bool comparison one could use vec_cmpeq and vec_compne (see https://www.ibm.com/docs/en/xl-c-and-cpp-linux/16.1.1?topic=functions-vec-cmpeq). However, vec_cmp* interfaces do not currently support vector pixel. Do you have a concrete use case for comparing vector pixels? If so I think we should consider adding corresponding overloads to altivec.h.

[krasimir]

In D103615#2858433, @bmahjour wrote:

In D103615#2852430, @krasimir wrote:

I'm unfamiliar with the altivec API. What's a reasonable source code update that preserves the current default behavior -altivec-src-compat=mixed under -altivec-src-compat=xl, i.e., under -altivec-src-compat=xl how would we compare vector bool or vector pixel to produce a vector?

For vector bool comparison one could use vec_cmpeq and vec_compne (see https://www.ibm.com/docs/en/xl-c-and-cpp-linux/16.1.1?topic=functions-vec-cmpeq). However, vec_cmp* interfaces do not currently support vector pixel. Do you have a concrete use case for comparing vector pixels? If so I think we should consider adding corresponding overloads to altivec.h.

Thank you! I don't have a use case for comparing vector pixels.

clang/include/clang/Basic/DiagnosticSemaKinds.td

def warn_deprecated_volatile_return : Warning<
   InGroup<DeprecatedVolatile>;
 def warn_deprecated_volatile_param : Warning<
   "volatile-qualified parameter type %0 is deprecated">,
   InGroup<DeprecatedVolatile>;
 def warn_deprecated_volatile_structured_binding : Warning<
   "volatile qualifier in structured binding declaration is deprecated">,
   InGroup<DeprecatedVolatile>;
 
+def warn_deprecated_altivec_src_compat : Warning<
+  "Current handling of vector bool and vector pixel types in this context are "
+  "deprecated. The default behaviour will soon change to that implied by the "
+  "'-altivec-compat=xl' option">,
+  InGroup<DiagGroup<"deprecated-altivec-src-compat">>;
+
 def err_catch_incomplete_ptr : Error<
   "cannot catch pointer to incomplete type %0">;
 def err_catch_incomplete_ref : Error<
   "cannot catch reference to incomplete type %0">;
 def err_catch_incomplete : Error<"cannot catch incomplete type %0">;
 def err_catch_sizeless : Error<
   "cannot catch %select{|reference to }0sizeless type %1">;
 def err_catch_rvalue_ref : Error<"cannot catch exceptions by rvalue reference">;

clang/include/clang/Basic/LangOptions.h

enum class LaxVectorConversionKind {
     /// Permit vector bitcasts between integer vectors with different numbers
     /// of elements but the same total bit-width.
     Integer,
     /// Permit vector bitcasts between all vectors with the same total
     /// bit-width.
     All,
   };
 
+  enum class AltivecSrcCompatKind {
+    // All vector compares produce scalars except vector pixel and vector bool.
+    // The types vector pixel and vector bool return vector results.
+    Mixed,
+    // All vector compares produce vector results as in GCC.
+    GCC,
+    // All vector compares produce scalars as in XL.
+    XL,
+    // Default clang behaviour.
+    Default = Mixed,
+  };
+
   enum class SignReturnAddressScopeKind {
     /// No signing for any function.
     None,
     /// Sign the return address of functions that spill LR.
     NonLeaf,
     /// Sign the return address of all functions,
     All
   };

clang/include/clang/Basic/LangOptions.def

 BENIGN_LANGOPT(HexFloats  , 1, C99, "C99 hexadecimal float constants")
 LANGOPT(CXXOperatorNames  , 1, 0, "C++ operator name keywords")
 LANGOPT(AppleKext         , 1, 0, "Apple kext support")
 BENIGN_LANGOPT(PascalStrings, 1, 0, "Pascal string support")
 LANGOPT(WritableStrings   , 1, 0, "writable string support")
 LANGOPT(ConstStrings      , 1, 0, "const-qualified string support")
 ENUM_LANGOPT(LaxVectorConversions, LaxVectorConversionKind, 2,
              LaxVectorConversionKind::All, "lax vector conversions")
+ENUM_LANGOPT(AltivecSrcCompat, AltivecSrcCompatKind, 2,
+             AltivecSrcCompatKind::Default, "Altivec source compatibility")
 LANGOPT(ConvergentFunctions, 1, 1, "Assume convergent functions")
 LANGOPT(AltiVec           , 1, 0, "AltiVec-style vector initializers")
 LANGOPT(ZVector           , 1, 0, "System z vector extensions")
 LANGOPT(Exceptions        , 1, 0, "exception handling")
 LANGOPT(ObjCExceptions    , 1, 0, "Objective-C exceptions")
 LANGOPT(CXXExceptions     , 1, 0, "C++ exceptions")
 LANGOPT(EHAsynch          , 1, 0, "C/C++ EH Asynch exceptions")
 ENUM_LANGOPT(ExceptionHandling, ExceptionHandlingKind, 3,

clang/include/clang/Driver/Options.td

 def undef : Flag<["-"], "undef">, Group<u_Group>, Flags<[CC1Option]>,
   HelpText<"undef all system defines">,
   MarshallingInfoNegativeFlag<PreprocessorOpts<"UsePredefines">>;
 def unexported__symbols__list : Separate<["-"], "unexported_symbols_list">;
 def u : JoinedOrSeparate<["-"], "u">, Group<u_Group>;
 def v : Flag<["-"], "v">, Flags<[CC1Option, CoreOption]>,
   HelpText<"Show commands to run and use verbose output">,
   MarshallingInfoFlag<HeaderSearchOpts<"Verbose">>;
+def altivec_src_compat : Joined<["-"], "faltivec-src-compat=">,
+  Flags<[CC1Option]>, Group<f_Group>,
+  HelpText<"Source-level compatibility for Altivec vectors (for PowerPC "
+           "targets). This includes results of vector comparison (scalar for "
+           "'xl', vector for 'gcc') as well as behavior when initializing with "
+           "a scalar (splatting for 'xl', element zero only for 'gcc'). For "
+           "'mixed', the compatibility is as 'gcc' for 'vector bool/vector "
+           "pixel' and as 'xl' for other types. Current default is 'mixed'.">,
+  Values<"mixed,gcc,xl">,
+  NormalizedValuesScope<"LangOptions::AltivecSrcCompatKind">,
+  NormalizedValues<["Mixed", "GCC", "XL"]>,
+  MarshallingInfoEnum<LangOpts<"AltivecSrcCompat">, "Mixed">;
 def verify_debug_info : Flag<["--"], "verify-debug-info">, Flags<[NoXarchOption]>,
   HelpText<"Verify the binary representation of debug output">;
 def weak_l : Joined<["-"], "weak-l">, Flags<[LinkerInput]>;
 def weak__framework : Separate<["-"], "weak_framework">, Flags<[LinkerInput]>;
 def weak__library : Separate<["-"], "weak_library">, Flags<[LinkerInput]>;
 def weak__reference__mismatches : Separate<["-"], "weak_reference_mismatches">;
 def whatsloaded : Flag<["-"], "whatsloaded">;
 def why_load : Flag<["-"], "why_load">;

clang/lib/Driver/ToolChains/Clang.cpp

if (Arg *A = Args.getLastArg(options::OPT_mrecord_mcount)) {
             << A->getAsString(Args) << TripleStr;
     }
   }
 
   if (Args.getLastArg(options::OPT_fapple_kext) ||
       (Args.hasArg(options::OPT_mkernel) && types::isCXX(InputType)))
     CmdArgs.push_back("-fapple-kext");
 
+  Args.AddLastArg(CmdArgs, options::OPT_altivec_src_compat);
   Args.AddLastArg(CmdArgs, options::OPT_flax_vector_conversions_EQ);
   Args.AddLastArg(CmdArgs, options::OPT_fobjc_sender_dependent_dispatch);
   Args.AddLastArg(CmdArgs, options::OPT_fdiagnostics_print_source_range_info);
   Args.AddLastArg(CmdArgs, options::OPT_fdiagnostics_parseable_fixits);
   Args.AddLastArg(CmdArgs, options::OPT_ftime_report);
   Args.AddLastArg(CmdArgs, options::OPT_ftime_report_EQ);
   Args.AddLastArg(CmdArgs, options::OPT_ftime_trace);
   Args.AddLastArg(CmdArgs, options::OPT_ftime_trace_granularity_EQ);

clang/lib/Sema/SemaExpr.cpp

QualType Sema::CheckVectorCompareOperands(ExprResult &LHS, ExprResult &RHS,
   QualType vType = CheckVectorOperands(LHS, RHS, Loc, /*isCompAssign*/false,
                               /*AllowBothBool*/true,
                               /*AllowBoolConversions*/getLangOpts().ZVector);
   if (vType.isNull())
     return vType;
 
   QualType LHSType = LHS.get()->getType();
 
+  // Determine the return type of a vector compare. By default clang will return
+  // a scalar for all vector compares except vector bool and vector pixel.
+  // With the gcc compiler we will always return a vector type and with the xl
+  // compiler we will always return a scalar type. This switch allows choosing
+  // which behavior is prefered.
+  if (getLangOpts().AltiVec) {
+    switch (getLangOpts().getAltivecSrcCompat()) {
+    case LangOptions::AltivecSrcCompatKind::Mixed:
       // If AltiVec, the comparison results in a numeric type, i.e.
       // bool for C++, int for C
-  if (getLangOpts().AltiVec &&
-      vType->castAs<VectorType>()->getVectorKind() == VectorType::AltiVecVector)
+      if (vType->castAs<VectorType>()->getVectorKind() ==
+          VectorType::AltiVecVector)
         return Context.getLogicalOperationType();
+      else
+        Diag(Loc, diag::warn_deprecated_altivec_src_compat);
+      break;
+    case LangOptions::AltivecSrcCompatKind::GCC:
+      // For GCC we always return the vector type.
+      break;
+    case LangOptions::AltivecSrcCompatKind::XL:
+      return Context.getLogicalOperationType();
+      break;
+    }
+  }
 
   // For non-floating point types, check for self-comparisons of the form
   // x == x, x != x, x < x, etc.  These always evaluate to a constant, and
   // often indicate logic errors in the program.
   diagnoseTautologicalComparison(*this, Loc, LHS.get(), RHS.get(), Opc);
 
   // Check for comparisons of floating point operands using != and ==.
   if (BinaryOperator::isEqualityOp(Opc) &&

clang/test/CodeGen/vector-compat-pixel-bool-ternary.c

+// RUN: not %clang_cc1 -target-feature +altivec -target-feature +vsx \
+// RUN:   -faltivec-src-compat=mixed -triple powerpc-unknown-unknown -S -emit-llvm %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR
+// RUN: not %clang_cc1 -target-feature +altivec -target-feature +vsx \
+// RUN:   -faltivec-src-compat=gcc -triple powerpc-unknown-unknown -S -emit-llvm %s -o - 2>&1| FileCheck %s --check-prefix=ERROR
+// RUN: %clang_cc1 -target-feature +altivec -target-feature +vsx \
+// RUN:   -faltivec-src-compat=xl -triple powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang -mcpu=pwr8 -faltivec-src-compat=xl --target=powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang -mcpu=pwr9 -faltivec-src-compat=xl --target=powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s
+
+// CHECK-LABEL: @bi8(
+// CHECK:         [[A_ADDR:%.*]] = alloca <16 x i8>, align 16
+// CHECK-NEXT:    [[B_ADDR:%.*]] = alloca <16 x i8>, align 16
+// CHECK-NEXT:    store <16 x i8> [[A:%.*]], <16 x i8>* [[A_ADDR]], align 16
+// CHECK-NEXT:    store <16 x i8> [[B:%.*]], <16 x i8>* [[B_ADDR]], align 16
+// CHECK-NEXT:    [[TMP0:%.*]] = load <16 x i8>, <16 x i8>* [[A_ADDR]], align 16
+// CHECK-NEXT:    [[TMP1:%.*]] = load <16 x i8>, <16 x i8>* [[B_ADDR]], align 16
+// CHECK-NEXT:    [[TMP2:%.*]] = call i32 @llvm.ppc.altivec.vcmpequb.p(i32 2, <16 x i8> [[TMP0]], <16 x i8> [[TMP1]])
+// CHECK-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0
+// CHECK-NEXT:    [[TMP3:%.*]] = zext i1 [[TOBOOL]] to i64
+// CHECK-NEXT:    [[COND:%.*]] = select i1 [[TOBOOL]], i32 3, i32 7
+// CHECK-NEXT:    ret i32 [[COND]]
+//
+// ERROR: error: used type '__attribute__((__vector_size__(16 * sizeof(char)))) char' (vector of 16 'char' values) where arithmetic or pointer type is required
+int bi8(vector bool char a, vector bool char b) {
+  return a == b ? 3 : 7;
+}
+
+// CHECK-LABEL: @bi16(
+// CHECK:         [[A_ADDR:%.*]] = alloca <8 x i16>, align 16
+// CHECK-NEXT:    [[B_ADDR:%.*]] = alloca <8 x i16>, align 16
+// CHECK-NEXT:    store <8 x i16> [[A:%.*]], <8 x i16>* [[A_ADDR]], align 16
+// CHECK-NEXT:    store <8 x i16> [[B:%.*]], <8 x i16>* [[B_ADDR]], align 16
+// CHECK-NEXT:    [[TMP0:%.*]] = load <8 x i16>, <8 x i16>* [[A_ADDR]], align 16
+// CHECK-NEXT:    [[TMP1:%.*]] = load <8 x i16>, <8 x i16>* [[B_ADDR]], align 16
+// CHECK-NEXT:    [[TMP2:%.*]] = call i32 @llvm.ppc.altivec.vcmpequh.p(i32 2, <8 x i16> [[TMP0]], <8 x i16> [[TMP1]])
+// CHECK-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0
+// CHECK-NEXT:    [[TMP3:%.*]] = zext i1 [[TOBOOL]] to i64
+// CHECK-NEXT:    [[COND:%.*]] = select i1 [[TOBOOL]], i32 3, i32 7
+// CHECK-NEXT:    ret i32 [[COND]]
+//
+// ERROR: error: used type '__attribute__((__vector_size__(8 * sizeof(short)))) short' (vector of 8 'short' values) where arithmetic or pointer type is required
+int bi16(vector bool short a, vector bool short b) {
+  return a == b ? 3 : 7;
+}
+
+// CHECK-LABEL: @bi32(
+// CHECK:         [[A_ADDR:%.*]] = alloca <4 x i32>, align 16
+// CHECK-NEXT:    [[B_ADDR:%.*]] = alloca <4 x i32>, align 16
+// CHECK-NEXT:    store <4 x i32> [[A:%.*]], <4 x i32>* [[A_ADDR]], align 16
+// CHECK-NEXT:    store <4 x i32> [[B:%.*]], <4 x i32>* [[B_ADDR]], align 16
+// CHECK-NEXT:    [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* [[A_ADDR]], align 16
+// CHECK-NEXT:    [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* [[B_ADDR]], align 16
+// CHECK-NEXT:    [[TMP2:%.*]] = call i32 @llvm.ppc.altivec.vcmpequw.p(i32 2, <4 x i32> [[TMP0]], <4 x i32> [[TMP1]])
+// CHECK-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0
+// CHECK-NEXT:    [[TMP3:%.*]] = zext i1 [[TOBOOL]] to i64
+// CHECK-NEXT:    [[COND:%.*]] = select i1 [[TOBOOL]], i32 3, i32 7
+// CHECK-NEXT:    ret i32 [[COND]]
+//
+// ERROR: error: used type '__attribute__((__vector_size__(4 * sizeof(long)))) long' (vector of 4 'long' values) where arithmetic or pointer type is required
+int bi32(vector bool int a, vector bool int b) {
+  return a == b ? 3 : 7;
+}
+
+// CHECK-LABEL: @bi64(
+// CHECK:         [[A_ADDR:%.*]] = alloca <2 x i64>, align 16
+// CHECK-NEXT:    [[B_ADDR:%.*]] = alloca <2 x i64>, align 16
+// CHECK-NEXT:    store <2 x i64> [[A:%.*]], <2 x i64>* [[A_ADDR]], align 16
+// CHECK-NEXT:    store <2 x i64> [[B:%.*]], <2 x i64>* [[B_ADDR]], align 16
+// CHECK-NEXT:    [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* [[A_ADDR]], align 16
+// CHECK-NEXT:    [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* [[B_ADDR]], align 16
+// CHECK-NEXT:    [[TMP2:%.*]] = call i32 @llvm.ppc.altivec.vcmpequd.p(i32 2, <2 x i64> [[TMP0]], <2 x i64> [[TMP1]])
+// CHECK-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0
+// CHECK-NEXT:    [[TMP3:%.*]] = zext i1 [[TOBOOL]] to i64
+// CHECK-NEXT:    [[COND:%.*]] = select i1 [[TOBOOL]], i32 3, i32 7
+// CHECK-NEXT:    ret i32 [[COND]]
+//
+// ERROR: error: used type '__attribute__((__vector_size__(2 * sizeof(long long)))) long long' (vector of 2 'long long' values) where arithmetic or pointer type is required
+int bi64(vector bool long long a, vector bool long long b) {
+  return a == b ? 3 : 7;
+}
+
+// CHECK-LABEL: @VecPixel(
+// CHECK:         [[A_ADDR:%.*]] = alloca <8 x i16>, align 16
+// CHECK-NEXT:    [[B_ADDR:%.*]] = alloca <8 x i16>, align 16
+// CHECK-NEXT:    store <8 x i16> [[A:%.*]], <8 x i16>* [[A_ADDR]], align 16
+// CHECK-NEXT:    store <8 x i16> [[B:%.*]], <8 x i16>* [[B_ADDR]], align 16
+// CHECK-NEXT:    [[TMP0:%.*]] = load <8 x i16>, <8 x i16>* [[A_ADDR]], align 16
+// CHECK-NEXT:    [[TMP1:%.*]] = load <8 x i16>, <8 x i16>* [[B_ADDR]], align 16
+// CHECK-NEXT:    [[TMP2:%.*]] = call i32 @llvm.ppc.altivec.vcmpequh.p(i32 2, <8 x i16> [[TMP0]], <8 x i16> [[TMP1]])
+// CHECK-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0
+// CHECK-NEXT:    [[TMP3:%.*]] = zext i1 [[TOBOOL]] to i64
+// CHECK-NEXT:    [[COND:%.*]] = select i1 [[TOBOOL]], i32 3, i32 7
+// CHECK-NEXT:    ret i32 [[COND]]
+//
+// ERROR: error: used type '__attribute__((__vector_size__(8 * sizeof(short)))) short' (vector of 8 'short' values) where arithmetic or pointer type is required
+int VecPixel(vector pixel a, vector pixel b) {
+  return a == b ? 3 : 7;
+}

clang/test/CodeGen/vector-compat-pixel-bool.c

+// RUN: %clang_cc1 -target-feature +altivec -target-feature +vsx \
+// RUN:   -faltivec-src-compat=mixed -triple powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -target-feature +altivec -target-feature +vsx \
+// RUN:   -faltivec-src-compat=gcc -triple powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s
+// RUN: not %clang_cc1 -target-feature +altivec -target-feature +vsx \
+// RUN:   -faltivec-src-compat=xl -triple powerpc-unknown-unknown -S -emit-llvm %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR
+// RUN: %clang -mcpu=pwr8 -faltivec-src-compat=gcc --target=powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang -mcpu=pwr9 -faltivec-src-compat=gcc --target=powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s
+
+// CHECK-LABEL: @bi8(
+// CHECK:         [[A_ADDR:%.*]] = alloca <16 x i8>, align 16
+// CHECK-NEXT:    [[B_ADDR:%.*]] = alloca <16 x i8>, align 16
+// CHECK-NEXT:    store <16 x i8> [[A:%.*]], <16 x i8>* [[A_ADDR]], align 16
+// CHECK-NEXT:    store <16 x i8> [[B:%.*]], <16 x i8>* [[B_ADDR]], align 16
+// CHECK-NEXT:    [[TMP0:%.*]] = load <16 x i8>, <16 x i8>* [[A_ADDR]], align 16
+// CHECK-NEXT:    [[TMP1:%.*]] = load <16 x i8>, <16 x i8>* [[B_ADDR]], align 16
+// CHECK-NEXT:    [[CMP:%.*]] = icmp eq <16 x i8> [[TMP0]], [[TMP1]]
+// CHECK-NEXT:    [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i8>
+// CHECK-NEXT:    ret <16 x i8> [[SEXT]]
+//
+// ERROR: returning 'int' from a function with incompatible result type
+vector unsigned char bi8(vector bool char a, vector bool char b) {
+  return a == b;
+}
+
+// CHECK-LABEL: @bi16(
+// CHECK:         [[A_ADDR:%.*]] = alloca <8 x i16>, align 16
+// CHECK-NEXT:    [[B_ADDR:%.*]] = alloca <8 x i16>, align 16
+// CHECK-NEXT:    store <8 x i16> [[A:%.*]], <8 x i16>* [[A_ADDR]], align 16
+// CHECK-NEXT:    store <8 x i16> [[B:%.*]], <8 x i16>* [[B_ADDR]], align 16
+// CHECK-NEXT:    [[TMP0:%.*]] = load <8 x i16>, <8 x i16>* [[A_ADDR]], align 16
+// CHECK-NEXT:    [[TMP1:%.*]] = load <8 x i16>, <8 x i16>* [[B_ADDR]], align 16
+// CHECK-NEXT:    [[CMP:%.*]] = icmp eq <8 x i16> [[TMP0]], [[TMP1]]
+// CHECK-NEXT:    [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i16>
+// CHECK-NEXT:    ret <8 x i16> [[SEXT]]
+//
+// ERROR: returning 'int' from a function with incompatible result type
+vector bool short bi16(vector bool short a, vector bool short b) {
+  return a == b;
+}
+
+// CHECK-LABEL: @bi32(
+// CHECK:         [[A_ADDR:%.*]] = alloca <4 x i32>, align 16
+// CHECK-NEXT:    [[B_ADDR:%.*]] = alloca <4 x i32>, align 16
+// CHECK-NEXT:    store <4 x i32> [[A:%.*]], <4 x i32>* [[A_ADDR]], align 16
+// CHECK-NEXT:    store <4 x i32> [[B:%.*]], <4 x i32>* [[B_ADDR]], align 16
+// CHECK-NEXT:    [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* [[A_ADDR]], align 16
+// CHECK-NEXT:    [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* [[B_ADDR]], align 16
+// CHECK-NEXT:    [[CMP:%.*]] = icmp eq <4 x i32> [[TMP0]], [[TMP1]]
+// CHECK-NEXT:    [[SEXT:%.*]] = sext <4 x i1> [[CMP]] to <4 x i32>
+// CHECK-NEXT:    ret <4 x i32> [[SEXT]]
+//
+// ERROR: returning 'int' from a function with incompatible result type
+vector bool int bi32(vector bool int a, vector bool int b) {
+  return a == b;
+}
+
+// CHECK-LABEL: @bi64(
+// CHECK:         [[A_ADDR:%.*]] = alloca <2 x i64>, align 16
+// CHECK-NEXT:    [[B_ADDR:%.*]] = alloca <2 x i64>, align 16
+// CHECK-NEXT:    store <2 x i64> [[A:%.*]], <2 x i64>* [[A_ADDR]], align 16
+// CHECK-NEXT:    store <2 x i64> [[B:%.*]], <2 x i64>* [[B_ADDR]], align 16
+// CHECK-NEXT:    [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* [[A_ADDR]], align 16
+// CHECK-NEXT:    [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* [[B_ADDR]], align 16
+// CHECK-NEXT:    [[CMP:%.*]] = icmp eq <2 x i64> [[TMP0]], [[TMP1]]
+// CHECK-NEXT:    [[SEXT:%.*]] = sext <2 x i1> [[CMP]] to <2 x i64>
+// CHECK-NEXT:    ret <2 x i64> [[SEXT]]
+//
+// ERROR: returning 'int' from a function with incompatible result type
+vector long long bi64(vector bool long long a, vector bool long long b) {
+  return a == b;
+}
+
+// CHECK-LABEL: @VecPixel(
+// CHECK:         [[A_ADDR:%.*]] = alloca <8 x i16>, align 16
+// CHECK-NEXT:    [[B_ADDR:%.*]] = alloca <8 x i16>, align 16
+// CHECK-NEXT:    store <8 x i16> [[A:%.*]], <8 x i16>* [[A_ADDR]], align 16
+// CHECK-NEXT:    store <8 x i16> [[B:%.*]], <8 x i16>* [[B_ADDR]], align 16
+// CHECK-NEXT:    [[TMP0:%.*]] = load <8 x i16>, <8 x i16>* [[A_ADDR]], align 16
+// CHECK-NEXT:    [[TMP1:%.*]] = load <8 x i16>, <8 x i16>* [[B_ADDR]], align 16
+// CHECK-NEXT:    [[CMP:%.*]] = icmp eq <8 x i16> [[TMP0]], [[TMP1]]
+// CHECK-NEXT:    [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i16>
+// CHECK-NEXT:    ret <8 x i16> [[SEXT]]
+//
+// ERROR: returning 'int' from a function with incompatible result type
+vector pixel VecPixel(vector pixel a, vector pixel b) {
+  return a == b;
+}

clang/test/CodeGen/vector-compat-ternary.c

+// RUN: %clang_cc1 -target-feature +altivec -target-feature +vsx \
+// RUN:   -faltivec-src-compat=mixed -triple powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s
+// RUN: not %clang_cc1 -target-feature +altivec -target-feature +vsx \
+// RUN:   -faltivec-src-compat=gcc -triple powerpc-unknown-unknown -S -emit-llvm %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR
+// RUN: %clang_cc1 -target-feature +altivec -target-feature +vsx \
+// RUN:   -faltivec-src-compat=xl -triple powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang -mcpu=pwr8 -faltivec-src-compat=xl --target=powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang -mcpu=pwr9 -faltivec-src-compat=xl --target=powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s
+
+// CHECK-LABEL: @ui8(
+// CHECK:         [[A_ADDR:%.*]] = alloca <16 x i8>, align 16
+// CHECK-NEXT:    [[B_ADDR:%.*]] = alloca <16 x i8>, align 16
+// CHECK-NEXT:    store <16 x i8> [[A:%.*]], <16 x i8>* [[A_ADDR]], align 16
+// CHECK-NEXT:    store <16 x i8> [[B:%.*]], <16 x i8>* [[B_ADDR]], align 16
+// CHECK-NEXT:    [[TMP0:%.*]] = load <16 x i8>, <16 x i8>* [[A_ADDR]], align 16
+// CHECK-NEXT:    [[TMP1:%.*]] = load <16 x i8>, <16 x i8>* [[B_ADDR]], align 16
+// CHECK-NEXT:    [[TMP2:%.*]] = call i32 @llvm.ppc.altivec.vcmpequb.p(i32 2, <16 x i8> [[TMP0]], <16 x i8> [[TMP1]])
+// CHECK-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0
+// CHECK-NEXT:    [[TMP3:%.*]] = zext i1 [[TOBOOL]] to i64
+// CHECK-NEXT:    [[COND:%.*]] = select i1 [[TOBOOL]], i32 3, i32 7
+// CHECK-NEXT:    ret i32 [[COND]]
+//
+// ERROR: error: used type '__attribute__((__vector_size__(16 * sizeof(char)))) char' (vector of 16 'char' values) where arithmetic or pointer type is required
+int ui8(vector unsigned char a, vector unsigned char b) {
+  return a == b ? 3 : 7;
+}
+
+// CHECK-LABEL: @si8(
+// CHECK:         [[A_ADDR:%.*]] = alloca <16 x i8>, align 16
+// CHECK-NEXT:    [[B_ADDR:%.*]] = alloca <16 x i8>, align 16
+// CHECK-NEXT:    store <16 x i8> [[A:%.*]], <16 x i8>* [[A_ADDR]], align 16
+// CHECK-NEXT:    store <16 x i8> [[B:%.*]], <16 x i8>* [[B_ADDR]], align 16
+// CHECK-NEXT:    [[TMP0:%.*]] = load <16 x i8>, <16 x i8>* [[A_ADDR]], align 16
+// CHECK-NEXT:    [[TMP1:%.*]] = load <16 x i8>, <16 x i8>* [[B_ADDR]], align 16
+// CHECK-NEXT:    [[TMP2:%.*]] = call i32 @llvm.ppc.altivec.vcmpequb.p(i32 2, <16 x i8> [[TMP0]], <16 x i8> [[TMP1]])
+// CHECK-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0
+// CHECK-NEXT:    [[TMP3:%.*]] = zext i1 [[TOBOOL]] to i64
+// CHECK-NEXT:    [[COND:%.*]] = select i1 [[TOBOOL]], i32 3, i32 7
+// CHECK-NEXT:    ret i32 [[COND]]
+//
+// ERROR: error: used type '__attribute__((__vector_size__(16 * sizeof(char)))) char' (vector of 16 'char' values) where arithmetic or pointer type is required
+int si8(vector signed char a, vector signed char b) {
+  return a == b ? 3 : 7;
+}
+
+// CHECK-LABEL: @ui16(
+// CHECK:         [[A_ADDR:%.*]] = alloca <8 x i16>, align 16
+// CHECK-NEXT:    [[B_ADDR:%.*]] = alloca <8 x i16>, align 16
+// CHECK-NEXT:    store <8 x i16> [[A:%.*]], <8 x i16>* [[A_ADDR]], align 16
+// CHECK-NEXT:    store <8 x i16> [[B:%.*]], <8 x i16>* [[B_ADDR]], align 16
+// CHECK-NEXT:    [[TMP0:%.*]] = load <8 x i16>, <8 x i16>* [[A_ADDR]], align 16
+// CHECK-NEXT:    [[TMP1:%.*]] = load <8 x i16>, <8 x i16>* [[B_ADDR]], align 16
+// CHECK-NEXT:    [[TMP2:%.*]] = call i32 @llvm.ppc.altivec.vcmpequh.p(i32 2, <8 x i16> [[TMP0]], <8 x i16> [[TMP1]])
+// CHECK-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0
+// CHECK-NEXT:    [[TMP3:%.*]] = zext i1 [[TOBOOL]] to i64
+// CHECK-NEXT:    [[COND:%.*]] = select i1 [[TOBOOL]], i32 3, i32 7
+// CHECK-NEXT:    ret i32 [[COND]]
+//
+// ERROR: error: used type '__attribute__((__vector_size__(8 * sizeof(short)))) short' (vector of 8 'short' values) where arithmetic or pointer type is required
+int ui16(vector unsigned short a, vector unsigned short b) {
+  return a == b ? 3 : 7;
+}
+
+// CHECK-LABEL: @si16(
+// CHECK:         [[A_ADDR:%.*]] = alloca <8 x i16>, align 16
+// CHECK-NEXT:    [[B_ADDR:%.*]] = alloca <8 x i16>, align 16
+// CHECK-NEXT:    store <8 x i16> [[A:%.*]], <8 x i16>* [[A_ADDR]], align 16
+// CHECK-NEXT:    store <8 x i16> [[B:%.*]], <8 x i16>* [[B_ADDR]], align 16
+// CHECK-NEXT:    [[TMP0:%.*]] = load <8 x i16>, <8 x i16>* [[A_ADDR]], align 16
+// CHECK-NEXT:    [[TMP1:%.*]] = load <8 x i16>, <8 x i16>* [[B_ADDR]], align 16
+// CHECK-NEXT:    [[TMP2:%.*]] = call i32 @llvm.ppc.altivec.vcmpequh.p(i32 2, <8 x i16> [[TMP0]], <8 x i16> [[TMP1]])
+// CHECK-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0
+// CHECK-NEXT:    [[TMP3:%.*]] = zext i1 [[TOBOOL]] to i64
+// CHECK-NEXT:    [[COND:%.*]] = select i1 [[TOBOOL]], i32 3, i32 7
+// CHECK-NEXT:    ret i32 [[COND]]
+//
+// ERROR: error: used type '__attribute__((__vector_size__(8 * sizeof(short)))) short' (vector of 8 'short' values) where arithmetic or pointer type is required
+int si16(vector signed short a, vector signed short b) {
+  return a == b ? 3 : 7;
+}
+
+// CHECK-LABEL: @ui32(
+// CHECK:         [[A_ADDR:%.*]] = alloca <4 x i32>, align 16
+// CHECK-NEXT:    [[B_ADDR:%.*]] = alloca <4 x i32>, align 16
+// CHECK-NEXT:    store <4 x i32> [[A:%.*]], <4 x i32>* [[A_ADDR]], align 16
+// CHECK-NEXT:    store <4 x i32> [[B:%.*]], <4 x i32>* [[B_ADDR]], align 16
+// CHECK-NEXT:    [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* [[A_ADDR]], align 16
+// CHECK-NEXT:    [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* [[B_ADDR]], align 16
+// CHECK-NEXT:    [[TMP2:%.*]] = call i32 @llvm.ppc.altivec.vcmpequw.p(i32 2, <4 x i32> [[TMP0]], <4 x i32> [[TMP1]])
+// CHECK-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0
+// CHECK-NEXT:    [[TMP3:%.*]] = zext i1 [[TOBOOL]] to i64
+// CHECK-NEXT:    [[COND:%.*]] = select i1 [[TOBOOL]], i32 3, i32 7
+// CHECK-NEXT:    ret i32 [[COND]]
+//
+// ERROR: error: used type '__attribute__((__vector_size__(4 * sizeof(long)))) long' (vector of 4 'long' values) where arithmetic or pointer type is required
+int ui32(vector unsigned int a, vector unsigned int b) {
+  return a == b ? 3 : 7;
+}
+
+// CHECK-LABEL: @si32(
+// CHECK:         [[A_ADDR:%.*]] = alloca <4 x i32>, align 16
+// CHECK-NEXT:    [[B_ADDR:%.*]] = alloca <4 x i32>, align 16
+// CHECK-NEXT:    store <4 x i32> [[A:%.*]], <4 x i32>* [[A_ADDR]], align 16
+// CHECK-NEXT:    store <4 x i32> [[B:%.*]], <4 x i32>* [[B_ADDR]], align 16
+// CHECK-NEXT:    [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* [[A_ADDR]], align 16
+// CHECK-NEXT:    [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* [[B_ADDR]], align 16
+// CHECK-NEXT:    [[TMP2:%.*]] = call i32 @llvm.ppc.altivec.vcmpequw.p(i32 2, <4 x i32> [[TMP0]], <4 x i32> [[TMP1]])
+// CHECK-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0
+// CHECK-NEXT:    [[TMP3:%.*]] = zext i1 [[TOBOOL]] to i64
+// CHECK-NEXT:    [[COND:%.*]] = select i1 [[TOBOOL]], i32 3, i32 7
+// CHECK-NEXT:    ret i32 [[COND]]
+//
+// ERROR: error: used type '__attribute__((__vector_size__(4 * sizeof(long)))) long' (vector of 4 'long' values) where arithmetic or pointer type is required
+int si32(vector signed int a, vector signed int b) {
+  return a == b ? 3 : 7;
+}
+
+// CHECK-LABEL: @si64(
+// CHECK:         [[A_ADDR:%.*]] = alloca <2 x i64>, align 16
+// CHECK-NEXT:    [[B_ADDR:%.*]] = alloca <2 x i64>, align 16
+// CHECK-NEXT:    store <2 x i64> [[A:%.*]], <2 x i64>* [[A_ADDR]], align 16
+// CHECK-NEXT:    store <2 x i64> [[B:%.*]], <2 x i64>* [[B_ADDR]], align 16
+// CHECK-NEXT:    [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* [[A_ADDR]], align 16
+// CHECK-NEXT:    [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* [[B_ADDR]], align 16
+// CHECK-NEXT:    [[TMP2:%.*]] = call i32 @llvm.ppc.altivec.vcmpequd.p(i32 2, <2 x i64> [[TMP0]], <2 x i64> [[TMP1]])
+// CHECK-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0
+// CHECK-NEXT:    [[TMP3:%.*]] = zext i1 [[TOBOOL]] to i64
+// CHECK-NEXT:    [[COND:%.*]] = select i1 [[TOBOOL]], i32 3, i32 7
+// CHECK-NEXT:    ret i32 [[COND]]
+//
+// ERROR: error: used type '__attribute__((__vector_size__(2 * sizeof(long long)))) long long' (vector of 2 'long long' values) where arithmetic or pointer type is required
+int si64(vector long long a, vector long long b) {
+  return a == b ? 3 : 7;
+}
+
+// CHECK-LABEL: @f32(
+// CHECK:         [[A_ADDR:%.*]] = alloca <4 x float>, align 16
+// CHECK-NEXT:    [[B_ADDR:%.*]] = alloca <4 x float>, align 16
+// CHECK-NEXT:    store <4 x float> [[A:%.*]], <4 x float>* [[A_ADDR]], align 16
+// CHECK-NEXT:    store <4 x float> [[B:%.*]], <4 x float>* [[B_ADDR]], align 16
+// CHECK-NEXT:    [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[A_ADDR]], align 16
+// CHECK-NEXT:    [[TMP1:%.*]] = load <4 x float>, <4 x float>* [[B_ADDR]], align 16
+// CHECK-NEXT:    [[TMP2:%.*]] = call i32 @llvm.ppc.altivec.vcmpeqfp.p(i32 2, <4 x float> [[TMP0]], <4 x float> [[TMP1]])
+// CHECK-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0
+// CHECK-NEXT:    [[TMP3:%.*]] = zext i1 [[TOBOOL]] to i64
+// CHECK-NEXT:    [[COND:%.*]] = select i1 [[TOBOOL]], i32 3, i32 7
+// CHECK-NEXT:    ret i32 [[COND]]
+//
+// ERROR: error: used type '__attribute__((__vector_size__(4 * sizeof(long)))) long' (vector of 4 'long' values) where arithmetic or pointer type is required
+int f32(vector float a, vector float b) {
+  return a == b ? 3 : 7;
+}
+
+// CHECK-LABEL: @f64(
+// CHECK:         [[A_ADDR:%.*]] = alloca <2 x double>, align 16
+// CHECK-NEXT:    [[B_ADDR:%.*]] = alloca <2 x double>, align 16
+// CHECK-NEXT:    store <2 x double> [[A:%.*]], <2 x double>* [[A_ADDR]], align 16
+// CHECK-NEXT:    store <2 x double> [[B:%.*]], <2 x double>* [[B_ADDR]], align 16
+// CHECK-NEXT:    [[TMP0:%.*]] = load <2 x double>, <2 x double>* [[A_ADDR]], align 16
+// CHECK-NEXT:    [[TMP1:%.*]] = load <2 x double>, <2 x double>* [[B_ADDR]], align 16
+// CHECK-NEXT:    [[TMP2:%.*]] = call i32 @llvm.ppc.vsx.xvcmpeqdp.p(i32 2, <2 x double> [[TMP0]], <2 x double> [[TMP1]])
+// CHECK-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0
+// CHECK-NEXT:    [[TMP3:%.*]] = zext i1 [[TOBOOL]] to i64
+// CHECK-NEXT:    [[COND:%.*]] = select i1 [[TOBOOL]], i32 3, i32 7
+// CHECK-NEXT:    ret i32 [[COND]]
+//
+// ERROR: error: used type '__attribute__((__vector_size__(2 * sizeof(long long)))) long long' (vector of 2 'long long' values) where arithmetic or pointer type is required
+int f64(vector double a, vector double b) {
+  return a == b ? 3 : 7;
+}

clang/test/CodeGen/vector-compat.c

+// RUN: not %clang_cc1 -target-feature +altivec -target-feature +vsx \
+// RUN:   -faltivec-src-compat=mixed -triple powerpc-unknown-unknown -S -emit-llvm %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR
+// RUN: %clang_cc1 -target-feature +altivec -target-feature +vsx \
+// RUN:   -faltivec-src-compat=gcc -triple powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s
+// RUN: not %clang_cc1 -target-feature +altivec -target-feature +vsx \
+// RUN:   -faltivec-src-compat=xl -triple powerpc-unknown-unknown -S -emit-llvm %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR
+// RUN: %clang -mcpu=pwr8 -faltivec-src-compat=gcc --target=powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang -mcpu=pwr9 -faltivec-src-compat=gcc --target=powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s
+
+// CHECK-LABEL: @ui8(
+// CHECK:         [[A_ADDR:%.*]] = alloca <16 x i8>, align 16
+// CHECK-NEXT:    [[B_ADDR:%.*]] = alloca <16 x i8>, align 16
+// CHECK-NEXT:    store <16 x i8> [[A:%.*]], <16 x i8>* [[A_ADDR]], align 16
+// CHECK-NEXT:    store <16 x i8> [[B:%.*]], <16 x i8>* [[B_ADDR]], align 16
+// CHECK-NEXT:    [[TMP0:%.*]] = load <16 x i8>, <16 x i8>* [[A_ADDR]], align 16
+// CHECK-NEXT:    [[TMP1:%.*]] = load <16 x i8>, <16 x i8>* [[B_ADDR]], align 16
+// CHECK-NEXT:    [[CMP:%.*]] = icmp eq <16 x i8> [[TMP0]], [[TMP1]]
+// CHECK-NEXT:    [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i8>
+// CHECK-NEXT:    ret <16 x i8> [[SEXT]]
+//
+// ERROR: returning 'int' from a function with incompatible result type
+vector unsigned char ui8(vector unsigned char a, vector unsigned char b) {
+  return a == b;
+}
+
+// CHECK-LABEL: @si8(
+// CHECK:         [[A_ADDR:%.*]] = alloca <16 x i8>, align 16
+// CHECK-NEXT:    [[B_ADDR:%.*]] = alloca <16 x i8>, align 16
+// CHECK-NEXT:    store <16 x i8> [[A:%.*]], <16 x i8>* [[A_ADDR]], align 16
+// CHECK-NEXT:    store <16 x i8> [[B:%.*]], <16 x i8>* [[B_ADDR]], align 16
+// CHECK-NEXT:    [[TMP0:%.*]] = load <16 x i8>, <16 x i8>* [[A_ADDR]], align 16
+// CHECK-NEXT:    [[TMP1:%.*]] = load <16 x i8>, <16 x i8>* [[B_ADDR]], align 16
+// CHECK-NEXT:    [[CMP:%.*]] = icmp eq <16 x i8> [[TMP0]], [[TMP1]]
+// CHECK-NEXT:    [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i8>
+// CHECK-NEXT:    ret <16 x i8> [[SEXT]]
+//
+// ERROR: returning 'int' from a function with incompatible result type
+vector signed char si8(vector signed char a, vector signed char b) {
+  return a == b;
+}
+
+// CHECK-LABEL: @ui16(
+// CHECK:         [[A_ADDR:%.*]] = alloca <8 x i16>, align 16
+// CHECK-NEXT:    [[B_ADDR:%.*]] = alloca <8 x i16>, align 16
+// CHECK-NEXT:    store <8 x i16> [[A:%.*]], <8 x i16>* [[A_ADDR]], align 16
+// CHECK-NEXT:    store <8 x i16> [[B:%.*]], <8 x i16>* [[B_ADDR]], align 16
+// CHECK-NEXT:    [[TMP0:%.*]] = load <8 x i16>, <8 x i16>* [[A_ADDR]], align 16
+// CHECK-NEXT:    [[TMP1:%.*]] = load <8 x i16>, <8 x i16>* [[B_ADDR]], align 16
+// CHECK-NEXT:    [[CMP:%.*]] = icmp eq <8 x i16> [[TMP0]], [[TMP1]]
+// CHECK-NEXT:    [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i16>
+// CHECK-NEXT:    ret <8 x i16> [[SEXT]]
+//
+// ERROR: returning 'int' from a function with incompatible result type
+vector unsigned short ui16(vector unsigned short a, vector unsigned short b) {
+  return a == b;
+}
+
+// CHECK-LABEL: @si16(
+// CHECK:         [[A_ADDR:%.*]] = alloca <8 x i16>, align 16
+// CHECK-NEXT:    [[B_ADDR:%.*]] = alloca <8 x i16>, align 16
+// CHECK-NEXT:    store <8 x i16> [[A:%.*]], <8 x i16>* [[A_ADDR]], align 16
+// CHECK-NEXT:    store <8 x i16> [[B:%.*]], <8 x i16>* [[B_ADDR]], align 16
+// CHECK-NEXT:    [[TMP0:%.*]] = load <8 x i16>, <8 x i16>* [[A_ADDR]], align 16
+// CHECK-NEXT:    [[TMP1:%.*]] = load <8 x i16>, <8 x i16>* [[B_ADDR]], align 16
+// CHECK-NEXT:    [[CMP:%.*]] = icmp eq <8 x i16> [[TMP0]], [[TMP1]]
+// CHECK-NEXT:    [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i16>
+// CHECK-NEXT:    ret <8 x i16> [[SEXT]]
+//
+// ERROR: returning 'int' from a function with incompatible result type
+vector signed short si16(vector signed short a, vector signed short b) {
+  return a == b;
+}
+
+// CHECK-LABEL: @ui32(
+// CHECK:         [[A_ADDR:%.*]] = alloca <4 x i32>, align 16
+// CHECK-NEXT:    [[B_ADDR:%.*]] = alloca <4 x i32>, align 16
+// CHECK-NEXT:    store <4 x i32> [[A:%.*]], <4 x i32>* [[A_ADDR]], align 16
+// CHECK-NEXT:    store <4 x i32> [[B:%.*]], <4 x i32>* [[B_ADDR]], align 16
+// CHECK-NEXT:    [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* [[A_ADDR]], align 16
+// CHECK-NEXT:    [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* [[B_ADDR]], align 16
+// CHECK-NEXT:    [[CMP:%.*]] = icmp eq <4 x i32> [[TMP0]], [[TMP1]]
+// CHECK-NEXT:    [[SEXT:%.*]] = sext <4 x i1> [[CMP]] to <4 x i32>
+// CHECK-NEXT:    ret <4 x i32> [[SEXT]]
+//
+// ERROR: returning 'int' from a function with incompatible result type
+vector unsigned int ui32(vector unsigned int a, vector unsigned int b) {
+  return a == b;
+}
+
+// CHECK-LABEL: @si32(
+// CHECK:         [[A_ADDR:%.*]] = alloca <4 x i32>, align 16
+// CHECK-NEXT:    [[B_ADDR:%.*]] = alloca <4 x i32>, align 16
+// CHECK-NEXT:    store <4 x i32> [[A:%.*]], <4 x i32>* [[A_ADDR]], align 16
+// CHECK-NEXT:    store <4 x i32> [[B:%.*]], <4 x i32>* [[B_ADDR]], align 16
+// CHECK-NEXT:    [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* [[A_ADDR]], align 16
+// CHECK-NEXT:    [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* [[B_ADDR]], align 16
+// CHECK-NEXT:    [[CMP:%.*]] = icmp eq <4 x i32> [[TMP0]], [[TMP1]]
+// CHECK-NEXT:    [[SEXT:%.*]] = sext <4 x i1> [[CMP]] to <4 x i32>
+// CHECK-NEXT:    ret <4 x i32> [[SEXT]]
+//
+// ERROR: returning 'int' from a function with incompatible result type
+vector signed int si32(vector signed int a, vector signed int b) {
+  return a == b;
+}
+
+// CHECK-LABEL: @si64(
+// CHECK:         [[A_ADDR:%.*]] = alloca <2 x i64>, align 16
+// CHECK-NEXT:    [[B_ADDR:%.*]] = alloca <2 x i64>, align 16
+// CHECK-NEXT:    store <2 x i64> [[A:%.*]], <2 x i64>* [[A_ADDR]], align 16
+// CHECK-NEXT:    store <2 x i64> [[B:%.*]], <2 x i64>* [[B_ADDR]], align 16
+// CHECK-NEXT:    [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* [[A_ADDR]], align 16
+// CHECK-NEXT:    [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* [[B_ADDR]], align 16
+// CHECK-NEXT:    [[CMP:%.*]] = icmp eq <2 x i64> [[TMP0]], [[TMP1]]
+// CHECK-NEXT:    [[SEXT:%.*]] = sext <2 x i1> [[CMP]] to <2 x i64>
+// CHECK-NEXT:    ret <2 x i64> [[SEXT]]
+//
+// ERROR: returning 'int' from a function with incompatible result type
+vector long long si64(vector long long a, vector long long b) {
+  return a == b;
+}
+
+// CHECK-LABEL: @f32(
+// CHECK:         [[A_ADDR:%.*]] = alloca <4 x float>, align 16
+// CHECK-NEXT:    [[B_ADDR:%.*]] = alloca <4 x float>, align 16
+// CHECK-NEXT:    store <4 x float> [[A:%.*]], <4 x float>* [[A_ADDR]], align 16
+// CHECK-NEXT:    store <4 x float> [[B:%.*]], <4 x float>* [[B_ADDR]], align 16
+// CHECK-NEXT:    [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[A_ADDR]], align 16
+// CHECK-NEXT:    [[TMP1:%.*]] = load <4 x float>, <4 x float>* [[B_ADDR]], align 16
+// CHECK-NEXT:    [[CMP:%.*]] = fcmp oeq <4 x float> [[TMP0]], [[TMP1]]
+// CHECK-NEXT:    [[SEXT:%.*]] = sext <4 x i1> [[CMP]] to <4 x i32>
+// CHECK-NEXT:    ret <4 x i32> [[SEXT]]
+//
+// ERROR: returning 'int' from a function with incompatible result type
+vector int f32(vector float a, vector float b) {
+  return a == b;
+}
+
+// CHECK-LABEL: @f64(
+// CHECK:         [[A_ADDR:%.*]] = alloca <2 x double>, align 16
+// CHECK-NEXT:    [[B_ADDR:%.*]] = alloca <2 x double>, align 16
+// CHECK-NEXT:    store <2 x double> [[A:%.*]], <2 x double>* [[A_ADDR]], align 16
+// CHECK-NEXT:    store <2 x double> [[B:%.*]], <2 x double>* [[B_ADDR]], align 16
+// CHECK-NEXT:    [[TMP0:%.*]] = load <2 x double>, <2 x double>* [[A_ADDR]], align 16
+// CHECK-NEXT:    [[TMP1:%.*]] = load <2 x double>, <2 x double>* [[B_ADDR]], align 16
+// CHECK-NEXT:    [[CMP:%.*]] = fcmp oeq <2 x double> [[TMP0]], [[TMP1]]
+// CHECK-NEXT:    [[SEXT:%.*]] = sext <2 x i1> [[CMP]] to <2 x i64>
+// CHECK-NEXT:    ret <2 x i64> [[SEXT]]
+//
+// ERROR: returning 'int' from a function with incompatible result type
+vector long long f64(vector double a, vector double b) {
+  return a == b;
+}