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Differential D103215

[RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed.
ClosedPublic

Authored by craig.topper on May 26 2021, 4:44 PM.

Details

Reviewers
arcbbb
khchen
frasercrmck
HsiangKai
evandro
rogfer01
Commits
rG527cd013144d: [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that…
Summary

This can help avoid needing a virtual register for the vsetvl output
when the AVL is X0. For other register AVLs it can shorter the live
range of the AVL register if it isn't needed later.

There's probably no advantage when AVL is a 5 bit immediate that
can use vsetivli. But do it anyway for consistency.

Diff Detail

Event Timeline

craig.topper created this revision.May 26 2021, 4:44 PM
Herald added subscribers: StephenFan, vkmr, luismarques and 23 others. · View Herald TranscriptMay 26 2021, 4:44 PM
craig.topper requested review of this revision.May 26 2021, 4:44 PM
Herald added a project: Restricted Project. · View Herald TranscriptMay 26 2021, 4:44 PM
Herald added a subscriber: MaskRay. · View Herald Transcript
Harbormaster completed remote builds in B106409: Diff 348125.May 26 2021, 5:24 PM
rogfer01 accepted this revision.May 27 2021, 5:06 AM

LGTM. Thanks!

This revision is now accepted and ready to land.May 27 2021, 5:06 AM
Closed by commit rG527cd013144d: [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that… (authored by craig.topper). · Explain WhyMay 27 2021, 10:15 AM
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rG527cd013144d: [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that….

Large Diff

This large diff affects 108 files. Files without inline comments have been collapsed. Expand All Files

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Diff 348321

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp

llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

llvm/test/CodeGen/RISCV/rvv/extload-truncstore.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-i1.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll

llvm/test/CodeGen/RISCV/rvv/interleave-crash.ll

llvm/test/CodeGen/RISCV/rvv/legalize-scalable-vectortype.ll

llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll

llvm/test/CodeGen/RISCV/rvv/saddo-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv32.ll

llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vaadd-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vaaddu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vadd-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vand-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vasub-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vasubu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vdiv-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vdivu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vfpext-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vfptrunc-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vlseg-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vlseg-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vlsseg-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vlsseg-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmacc-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmadd-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmax-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmaxu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmfeq-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmfeq-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmfge-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmfge-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmfgt-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmfgt-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmfle-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmfle-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmflt-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmflt-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmfne-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmfne-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmin-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vminu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmseq-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmseq-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmsge-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmsge-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmsgt-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmsle-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmsle-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmsleu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmsleu-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmslt-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmsltu-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmsne-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmul-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmulh-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmulhu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vnmsac-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vnmsub-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vor-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vrem-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vremu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vrsub-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vsadd-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vsaddu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir

llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir

llvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vssub-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vssubu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vsub-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vxor-rv32.ll

llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll