[RISCV] [1/2] Add IR intrinsic for Zbm extension

[LevyHsu]

Summary

RV64 ONLY:

bmator
bmatxor
bmatflip

[craig.topper]

clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbm.c

16

clmul?

[LevyHsu]

1. clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbm.c
   • All test cases renamed

[craig.topper]

LGTM

clang/include/clang/Basic/BuiltinsRISCV.def

 TARGET_BUILTIN(__builtin_riscv_orc_b_32, "ZiZi", "nc", "experimental-zbb")
 TARGET_BUILTIN(__builtin_riscv_orc_b_64, "WiWi", "nc", "experimental-zbb,64bit")
 
 // Zbc extension
 TARGET_BUILTIN(__builtin_riscv_clmul, "LiLiLi", "nc", "experimental-zbc")
 TARGET_BUILTIN(__builtin_riscv_clmulh, "LiLiLi", "nc", "experimental-zbc")
 TARGET_BUILTIN(__builtin_riscv_clmulr, "LiLiLi", "nc", "experimental-zbc")
 
+// Zbm extension
+TARGET_BUILTIN(__builtin_riscv_bmator, "WiWiWi", "nc","experimental-zbm,64bit")
+TARGET_BUILTIN(__builtin_riscv_bmatxor, "WiWiWi", "nc", "experimental-zbm,64bit")
+TARGET_BUILTIN(__builtin_riscv_bmatflip, "WiWi", "nc", "experimental-zbm,64bit")
+
 // Zbp extension
 TARGET_BUILTIN(__builtin_riscv_grev_32, "ZiZiZi", "nc", "experimental-zbp")
 TARGET_BUILTIN(__builtin_riscv_grev_64, "WiWiWi", "nc", "experimental-zbp,64bit")
 TARGET_BUILTIN(__builtin_riscv_gorc_32, "ZiZiZi", "nc", "experimental-zbp")
 TARGET_BUILTIN(__builtin_riscv_gorc_64, "WiWiWi", "nc", "experimental-zbp,64bit")
 TARGET_BUILTIN(__builtin_riscv_shfl_32, "ZiZiZi", "nc", "experimental-zbp")
 TARGET_BUILTIN(__builtin_riscv_shfl_64, "WiWiWi", "nc", "experimental-zbp,64bit")
 TARGET_BUILTIN(__builtin_riscv_unshfl_32, "ZiZiZi", "nc", "experimental-zbp")

clang/lib/CodeGen/CGBuiltin.cpp

Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
   llvm::SmallVector<llvm::Type *, 2> IntrinsicTypes;
   switch (BuiltinID) {
   default: llvm_unreachable("unexpected builtin ID");
   case RISCV::BI__builtin_riscv_orc_b_32:
   case RISCV::BI__builtin_riscv_orc_b_64:
   case RISCV::BI__builtin_riscv_clmul:
   case RISCV::BI__builtin_riscv_clmulh:
   case RISCV::BI__builtin_riscv_clmulr:
+  case RISCV::BI__builtin_riscv_bmator:
+  case RISCV::BI__builtin_riscv_bmatxor:
+  case RISCV::BI__builtin_riscv_bmatflip:
   case RISCV::BI__builtin_riscv_grev_32:
   case RISCV::BI__builtin_riscv_grev_64:
   case RISCV::BI__builtin_riscv_gorc_32:
   case RISCV::BI__builtin_riscv_gorc_64:
   case RISCV::BI__builtin_riscv_shfl_32:
   case RISCV::BI__builtin_riscv_shfl_64:
   case RISCV::BI__builtin_riscv_unshfl_32:
   case RISCV::BI__builtin_riscv_unshfl_64:
case RISCV::BI__builtin_riscv_clmul:
       break;
     case RISCV::BI__builtin_riscv_clmulh:
       ID = Intrinsic::riscv_clmulh;
       break;
     case RISCV::BI__builtin_riscv_clmulr:
       ID = Intrinsic::riscv_clmulr;
       break;
 
+    // Zbm
+    case RISCV::BI__builtin_riscv_bmator:
+      ID = Intrinsic::riscv_bmator;
+      break;
+    case RISCV::BI__builtin_riscv_bmatxor:
+      ID = Intrinsic::riscv_bmatxor;
+      break;
+    case RISCV::BI__builtin_riscv_bmatflip:
+      ID = Intrinsic::riscv_bmatflip;
+      break;
+
     // Zbp
     case RISCV::BI__builtin_riscv_grev_32:
     case RISCV::BI__builtin_riscv_grev_64:
       ID = Intrinsic::riscv_grev;
       break;
     case RISCV::BI__builtin_riscv_gorc_32:
     case RISCV::BI__builtin_riscv_gorc_64:
       ID = Intrinsic::riscv_gorc;

clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbm.c

+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zbm -emit-llvm %s -o - \
+// RUN:     | FileCheck %s  -check-prefix=RV64ZBM
+
+// RV64ZBM-LABEL: @clmul(
+// RV64ZBM-NEXT:  entry:
+// RV64ZBM-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBM-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBM-NEXT:    store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBM-NEXT:    store i64 [[B:%.*]], i64* [[B_ADDR]], align 8
+// RV64ZBM-NEXT:    [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBM-NEXT:    [[TMP1:%.*]] = load i64, i64* [[B_ADDR]], align 8
+// RV64ZBM-NEXT:    [[TMP2:%.*]] = call i64 @llvm.riscv.bmator.i64(i64 [[TMP0]], i64 [[TMP1]])
+// RV64ZBM-NEXT:    ret i64 [[TMP2]]
+//
+long clmul(long a, long b) {
+  return __builtin_riscv_bmator(a, b);
+}
+
+// RV64ZBM-LABEL: @clmulh(
+// RV64ZBM-NEXT:  entry:
+// RV64ZBM-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBM-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBM-NEXT:    store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBM-NEXT:    store i64 [[B:%.*]], i64* [[B_ADDR]], align 8
+// RV64ZBM-NEXT:    [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBM-NEXT:    [[TMP1:%.*]] = load i64, i64* [[B_ADDR]], align 8
+// RV64ZBM-NEXT:    [[TMP2:%.*]] = call i64 @llvm.riscv.bmatxor.i64(i64 [[TMP0]], i64 [[TMP1]])
+// RV64ZBM-NEXT:    ret i64 [[TMP2]]
+//
+long clmulh(long a, long b) {
+  return __builtin_riscv_bmatxor(a, b);
+}
+
+// RV64ZBM-LABEL: @clmulr(
+// RV64ZBM-NEXT:  entry:
+// RV64ZBM-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBM-NEXT:    store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBM-NEXT:    [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBM-NEXT:    [[TMP1:%.*]] = call i64 @llvm.riscv.bmatflip.i64(i64 [[TMP0]])
+// RV64ZBM-NEXT:    ret i64 [[TMP1]]
+//
+long clmulr(long a) {
+  return __builtin_riscv_bmatflip(a);
+}

llvm/include/llvm/IR/IntrinsicsRISCV.td

let TargetPrefix = "riscv" in {
   // Zbb
   def int_riscv_orc_b : BitManipGPRIntrinsics;
 
   // Zbc
   def int_riscv_clmul  : BitManipGPRGPRIntrinsics;
   def int_riscv_clmulh : BitManipGPRGPRIntrinsics;
   def int_riscv_clmulr : BitManipGPRGPRIntrinsics;
 
+  // Zbm
+  def int_riscv_bmator   : BitManipGPRGPRIntrinsics;
+  def int_riscv_bmatxor  : BitManipGPRGPRIntrinsics;
+  def int_riscv_bmatflip : BitManipGPRIntrinsics;
+
   // Zbp
   def int_riscv_grev  : BitManipGPRGPRIntrinsics;
   def int_riscv_gorc  : BitManipGPRGPRIntrinsics;
   def int_riscv_shfl  : BitManipGPRGPRIntrinsics;
   def int_riscv_unshfl  : BitManipGPRGPRIntrinsics;
   def int_riscv_xperm_n  : BitManipGPRGPRIntrinsics;
   def int_riscv_xperm_b  : BitManipGPRGPRIntrinsics;
   def int_riscv_xperm_h  : BitManipGPRGPRIntrinsics;

llvm/lib/Target/RISCV/RISCVInstrInfoB.td

 } // Predicates = [HasStdExtZbp, IsRV64]
 
 let Predicates = [HasStdExtZbc] in {
 def : PatGprGpr<int_riscv_clmul, CLMUL>;
 def : PatGprGpr<int_riscv_clmulh, CLMULH>;
 def : PatGprGpr<int_riscv_clmulr, CLMULR>;
 } // Predicates = [HasStdExtZbc]
 
+let Predicates = [HasStdExtZbm, IsRV64] in {
+def : PatGprGpr<int_riscv_bmator, BMATOR>;
+def : PatGprGpr<int_riscv_bmatxor, BMATXOR>;
+def : PatGpr<int_riscv_bmatflip, BMATFLIP>;
+} // Predicates = [HasStdExtZbm, IsRV64]
+
 let Predicates = [HasStdExtZbr] in {
 def : PatGpr<int_riscv_crc32_b, CRC32B>;
 def : PatGpr<int_riscv_crc32_h, CRC32H>;
 def : PatGpr<int_riscv_crc32_w, CRC32W>;
 def : PatGpr<int_riscv_crc32c_b, CRC32CB>;
 def : PatGpr<int_riscv_crc32c_h, CRC32CH>;
 def : PatGpr<int_riscv_crc32c_w, CRC32CW>;
 } // Predicates = [HasStdExtZbr]
 
 let Predicates = [HasStdExtZbr, IsRV64] in {
 def : PatGpr<int_riscv_crc32_d, CRC32D>;
 def : PatGpr<int_riscv_crc32c_d, CRC32CD>;
 } // Predicates = [HasStdExtZbr, IsRV64]

llvm/test/CodeGen/RISCV/rv64zbm-intrinsic.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64IB
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbm -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64IBM
+
+declare i64 @llvm.riscv.bmator.i64(i64 %a, i64 %b)
+
+define i64 @bmator64(i64 %a, i64 %b) nounwind {
+; RV64IB-LABEL: bmator64:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    bmator a0, a0, a1
+; RV64IB-NEXT:    ret
+;
+; RV64IBM-LABEL: bmator64:
+; RV64IBM:       # %bb.0:
+; RV64IBM-NEXT:    bmator a0, a0, a1
+; RV64IBM-NEXT:    ret
+  %tmp = call i64 @llvm.riscv.bmator.i64(i64 %a, i64 %b)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.bmatxor.i64(i64 %a, i64 %b)
+
+define i64 @bmatxor64(i64 %a, i64 %b) nounwind {
+; RV64IB-LABEL: bmatxor64:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    bmatxor a0, a0, a1
+; RV64IB-NEXT:    ret
+;
+; RV64IBM-LABEL: bmatxor64:
+; RV64IBM:       # %bb.0:
+; RV64IBM-NEXT:    bmatxor a0, a0, a1
+; RV64IBM-NEXT:    ret
+  %tmp = call i64 @llvm.riscv.bmatxor.i64(i64 %a, i64 %b)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.bmatflip.i64(i64 %a)
+
+define i64 @bmatflip64(i64 %a) nounwind {
+; RV64IB-LABEL: bmatflip64:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    bmatflip a0, a0
+; RV64IB-NEXT:    ret
+;
+; RV64IBM-LABEL: bmatflip64:
+; RV64IBM:       # %bb.0:
+; RV64IBM-NEXT:    bmatflip a0, a0
+; RV64IBM-NEXT:    ret
+  %tmp = call i64 @llvm.riscv.bmatflip.i64(i64 %a)
+ ret i64 %tmp
+}