[InstCombine] Fully disable select to and/or i1 folding

[aqjune]

Summary

This is a patch that disables the poison-unsafe select -> and/or i1 folding.

It has been blocking D72396 and also has been the source of a few miscompilations
described in llvm.org/pr49688 .
D99674 conditionally blocked this folding and successfully fixed the latter one.
The former one was still blocked, and this patch addresses it.

Note that a few test functions that has _logical suffix are now deoptimized.
These are created by @nikic to check the impact of disabling this optimization
by copying existing original functions and replacing and/or with select.

I can see that most of these are poison-unsafe; they can be revived by introducing
freeze instruction. I left comments at fcmp + select optimizations (or-fcmp.ll, and-fcmp.ll)
because I think they are good targets for freeze fix.

[nikic]

llvm/test/Transforms/InstCombine/logical-select.ll

385

It looks like this fold could be salvaged, if we wanted to: https://alive2.llvm.org/ce/z/TpsYAj

[aqjune]

Salvage a few select transformations

[aqjune]

llvm/test/Transforms/InstCombine/logical-select.ll

385

Thx, I added the transformation.
If the transformations look good, I'll make it as a separate commit with tests and push it.

[aqjune]

llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp

2723

I guess isImpliedCondition is assuming that LHS and RHS are never poison, but this transformation is still correct even if c or b is poison.

[nikic]

llvm/test/Transforms/InstCombine/logical-select.ll

385

Could you please split it off into a separate review? Hard to understand impact as part of this change.

[spatel]

llvm/test/Transforms/PhaseOrdering/X86/vector-reductions.ll

282

I don't think we need to worry about regressing this. It's not ideal before or after, but we probably have a better chance of getting to the goal by making instcombine/simplifycfg correct and consistent.

[spatel]

llvm/test/Transforms/PhaseOrdering/unsigned-multiply-overflow-check.ll

20

Any ideas about what it will take to get those argument attributes for the C++ source example shown in the code comment?

SDAG is still going to convert the select to and, so we can probably avoid regressions by replicating InstSimplify's omitCheckForZeroBeforeMulWithOverflow() as a DAG combine. Let me know if I should do that.

[aqjune]

llvm/test/Transforms/InstCombine/logical-select.ll

385

It is splitted into D101375

llvm/test/Transforms/PhaseOrdering/unsigned-multiply-overflow-check.ll

20

I promised to do the patch at D82317, but these days I'm occupied with other things, so it might not be a recent future (not in a month at least)...

I think it is a good chance to use freeze here: We can add

%cond = icmp ne %x, 0
%v = call @llvm.umul.with.overflow(%x, %y)
%ov = extractvalue %v, 1
%res = select i1 %cond, %ov, false
  =>
%y.fr = freeze %y
%v = call @llvm.umul.with.overflow(%x, %y.fr)
%ov = extractvalue %v, 1
%res = %ov

into CodeGenPrepare.
What do you think? CodeGenPrepare is already using freeze for a few transformations.

[aqjune]

llvm/test/Transforms/PhaseOrdering/unsigned-multiply-overflow-check.ll

20

Alive2 proof: https://alive2.llvm.org/ce/z/zgPUGT

[spatel]

llvm/test/Transforms/PhaseOrdering/unsigned-multiply-overflow-check.ll

20

I don't think we want to add code to CGP if we can avoid it. CGP is supposed to be a temporary hack that is not needed with GlobalISel. I do acknowledge that "temporary" in the code may outlive the people working on it today (!).

If we don't care about undef correctness in codegen (in other words, the select->and transform will live on in codegen forever), then we might as well add a DAG combine. Alternatively, are we comfortable creating freeze in instcombine for rare code like umul.with.ov?

[nikic]

llvm/test/Transforms/PhaseOrdering/unsigned-multiply-overflow-check.ll

20

I think this is one of the rare cases where inserting Freeze in InstCombine makes sense. There's not much (any?) further optimization opportunities for a umul.with.overflow with non-constant operands.

[aqjune]

llvm/test/Transforms/PhaseOrdering/unsigned-multiply-overflow-check.ll

20

InstCombine sounds good as well!

[spatel]

llvm/test/Transforms/PhaseOrdering/unsigned-multiply-overflow-check.ll

20

For reference, that part is D101423, and it will be a preliminary patch before this one.

[aqjune]

Rebase on D101375

[aqjune]

ctpop is splitted out

[aqjune]

rebase to reduce diffs

[aqjune]

remove the noundef comment

[aqjune]

I found that there are a few more patterns that can be salvaged. Will create a patch for them.

llvm/test/Transforms/InstCombine/and.ll

898

This can be resurrected.

1033

This can be resurrected as well.

llvm/test/Transforms/InstCombine/and2.ll

51

This one too

llvm/test/Transforms/PGOProfile/chr.ll

1374

This one as well

[aqjune]

I made D101720 to cover the remaining cases except Transforms/InstCombine/and2.ll.
Supporting and2.ll doesn't seem super-straightforward, but maybe some minor tweaks can make it.

[aqjune]

(BTW, if the patch is reviewed, then I believe we are finally ready to land this patch.)

[aqjune]

Rebase to D101720

[nikic]

Went through all the tests again, looks like there's three patterns that could still be handled. I think the last one of them should be handled, and for the other two it's fine to just open an issue.

llvm/test/Transforms/InstCombine/and2.ll

51

Looks like we still miss this one (https://alive2.llvm.org/ce/z/E_F768).

llvm/test/Transforms/InstCombine/logical-select-inseltpoison.ll

450

Looks like this could be salvaged: https://alive2.llvm.org/ce/z/YQUQew

Doesn't seem important though.

llvm/test/Transforms/InstCombine/or.ll

1102

Can be salvaged: https://alive2.llvm.org/ce/z/-STJ2d

I thought this was already covered by one of the folds though...

[aqjune]

llvm/test/Transforms/InstCombine/or.ll

1102

No, it didn't exist.
I think there are too many possible combinations here. It should be reduced into more compact code someday...
Made a patch here: D101807

[aqjune]

Rebase onto D101807

[aqjune]

llvm/test/Transforms/InstCombine/or.ll

1139

This can be salvaged as well:
https://alive2.llvm.org/ce/z/yXF96T

But I think there are more patterns that are missing. I'll leave them as missing optimization opportunities at bugzilla after this patch is reviewed.

[aqjune]

Rebase

[aqjune]

I think this patch is ready to go: running the test-suite on an ARM machine didn't complain anything.

Well, but one thing that I'm concerned about is that from tomorrow I'll not be online for about three weeks. :(

I'd like to find someone who reverts this patch if there is any serious problem.

llvm/test/Transforms/InstCombine/or.ll

1139

Addressed via D101801

[nikic]

LGTM. I can take care of reverting if there are issues.

[aqjune]

In D101191#2738130, @nikic wrote:

LGTM. I can take care of reverting if there are issues.

Thanks!

[sanwou01]

Hi, we've got a ~6% regression in SPEC INT 2006 462.libquantum on AArch64 (both -flto and -Ofast) that comes back to this change. See here for a reproducer https://godbolt.org/z/dq98Gqqxn (-fno-vectorize is not strictly necessary, but it does make the difference easier to spot). @dmgreen mentioned to me that we could probably fix this up in the AArch64 backend, but a fix in the mid-end might be more generally useful too.

[nikic]

In D101191#2751002, @sanwou01 wrote:

Hi, we've got a ~6% regression in SPEC INT 2006 462.libquantum on AArch64 (both -flto and -Ofast) that comes back to this change. See here for a reproducer https://godbolt.org/z/dq98Gqqxn (-fno-vectorize is not strictly necessary, but it does make the difference easier to spot). @dmgreen mentioned to me that we could probably fix this up in the AArch64 backend, but a fix in the mid-end might be more generally useful too.

Thanks for the report! This looks like the "one hot merge" optimization, which is indeed disabled by this patch, because it is incorrect in the current form (onehot_merge.ll). We can bring back this optimization in InstCombine, but need to freeze one of the operands (c2 in your example).

[fhahn]

Looks like this is causing an infinite loop in instcombine: https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=34661

Reproducer test case: https://oss-fuzz.com/download?testcase_id=6383789942112256 , hangs with opt -instcombine, terminates with the patch reverted.

[spatel]

In D101191#2779007, @fhahn wrote:

Looks like this is causing an infinite loop in instcombine: https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=34661

This seems likely to be another partial undef/poison vector problem ( 1894c6c59e ). I'll take a look.

[spatel]

In D101191#2779631, @spatel wrote:

In D101191#2779007, @fhahn wrote:

Looks like this is causing an infinite loop in instcombine: https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=34661

This seems likely to be another partial undef/poison vector problem ( 1894c6c59e ). I'll take a look.

The fuzzer test can be reduced to a single line. I committed a minimal fix here:
ae1bc9ebf3
...but some follow-up seems necessary.

[rupprecht]

FYI, I'm seeing what I think is a miscompile that bisects to this patch. Greatly simplified, the problematic snippet is this:

struct Stats {
  int a;
  int b;
  int a_or_b;
};

bool x = ...
bool y = ...
Stats stats;
stats.a = x ? 1 : 0;
stats.b = y ? 1 : 0;
stats.a_or_b = (x || y) ? 1 : 0;

What we see is that when x is false and y is true, a is 0 (expected), b is 1 (expected), but a_or_b is 0 (unexpected).

[rupprecht]

The issue I'm seeing seems more directly caused by SLP vectorization, as it goes away with -fno-slp-vectorize. This patch merely unblocks that bad optimization AFAICT.

[rupprecht]

In D101191#2782963, @rupprecht wrote:

The issue I'm seeing seems more directly caused by SLP vectorization, as it goes away with -fno-slp-vectorize. This patch merely unblocks that bad optimization AFAICT.

Filed as http://llvm.org/PR50500

[spatel]

In D101191#2783570, @rupprecht wrote:

In D101191#2782963, @rupprecht wrote:

The issue I'm seeing seems more directly caused by SLP vectorization, as it goes away with -fno-slp-vectorize. This patch merely unblocks that bad optimization AFAICT.

Filed as http://llvm.org/PR50500

We needed SLP to get to the problem state in that example, but the bug was in instcombine/instsimplify.
Should be fixed with:
7bb8bfa0622b

[rupprecht]

In D101191#2788596, @spatel wrote:

In D101191#2783570, @rupprecht wrote:

In D101191#2782963, @rupprecht wrote:

The issue I'm seeing seems more directly caused by SLP vectorization, as it goes away with -fno-slp-vectorize. This patch merely unblocks that bad optimization AFAICT.

Filed as http://llvm.org/PR50500

We needed SLP to get to the problem state in that example, but the bug was in instcombine/instsimplify.
Should be fixed with:
7bb8bfa0622b

Thanks Sanjay! This fixes the unreduced miscompile we're seeing.

clang/test/CodeGenOpenCL/amdgpu-nullptr.cl

 int test_not_local_ptr(local char* p) {
   return !p;
 }
 
 
 // CHECK-LABEL: test_and_ptr
 // CHECK: %[[tobool:.*]] = icmp ne i8 addrspace(5)* %p1, addrspacecast (i8* null to i8 addrspace(5)*)
 // CHECK: %[[tobool1:.*]] = icmp ne i8 addrspace(3)* %p2, addrspacecast (i8* null to i8 addrspace(3)*)
-// CHECK: %[[res:.*]] = and i1 %[[tobool]], %[[tobool1]]
+// CHECK: %[[res:.*]] = select i1 %[[tobool]], i1 %[[tobool1]], i1 false
 // CHECK: %[[land_ext:.*]] = zext i1 %[[res]] to i32
 // CHECK: ret i32 %[[land_ext]]
 int test_and_ptr(private char* p1, local char* p2) {
   return p1 && p2;
 }
 
 // Test folding of null pointer in function scope.
 // NOOPT-LABEL: test_fold_private

llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp

 //===- InstCombineSelect.cpp ----------------------------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //

 #include <cassert>
 #include <utility>
 
 using namespace llvm;
 using namespace PatternMatch;
 
 #define DEBUG_TYPE "instcombine"
 
-/// FIXME: Enabled by default until the pattern is supported well.
-static cl::opt<bool> EnableUnsafeSelectTransform(
-    "instcombine-unsafe-select-transform", cl::init(true),
-    cl::desc("Enable poison-unsafe select to and/or transform"));
-
 static Value *createMinMax(InstCombiner::BuilderTy &Builder,
                            SelectPatternFlavor SPF, Value *A, Value *B) {
   CmpInst::Predicate Pred = getMinMaxPred(SPF);
   assert(CmpInst::isIntPredicate(Pred) && "Expected integer predicate");
   return Builder.CreateSelect(Builder.CreateICmp(Pred, A, B), A, B);
 }
 
 /// Replace a select operand based on an equality comparison with the identity
Instruction *InstCombinerImpl::visitSelectInst(SelectInst &SI) {
 
   if (Instruction *I = canonicalizeScalarSelectOfVecs(SI, *this))
     return I;
 
   CmpInst::Predicate Pred;
 
   if (SelType->isIntOrIntVectorTy(1) &&
       TrueVal->getType() == CondVal->getType()) {
-    auto IsSafeToConvert = [&](Value *OtherVal) {
-      if (impliesPoison(OtherVal, CondVal))
-        return true;
-
-      if (!EnableUnsafeSelectTransform)
-        return false;
-
-      // We block this transformation if OtherVal or its operand can create
-      // poison. See PR49688
-      if (auto *Op = dyn_cast<Operator>(OtherVal)) {
-        if (canCreatePoison(Op))
-          return false;
-        if (propagatesPoison(Op) &&
-            llvm::any_of(Op->operand_values(), [](Value *V) {
-              return isa<Operator>(V) ? canCreatePoison(cast<Operator>(V))
-                                      : false;
-            }))
-          return false;
-      }
-      return true;
-    };
-    if (match(TrueVal, m_One()) && IsSafeToConvert(FalseVal)) {
+    // Folding select to and/or i1 isn't poison safe in general. impliesPoison
+    // checks whether folding it does not convert a well-defined value into
+    // poison.
+    if (match(TrueVal, m_One()) && impliesPoison(FalseVal, CondVal)) {
       // Change: A = select B, true, C --> A = or B, C
       return BinaryOperator::CreateOr(CondVal, FalseVal);
     }
-    if (match(FalseVal, m_Zero()) && IsSafeToConvert(TrueVal)) {
+    if (match(FalseVal, m_Zero()) && impliesPoison(TrueVal, CondVal)) {
       // Change: A = select B, C, false --> A = and B, C
       return BinaryOperator::CreateAnd(CondVal, TrueVal);
     }
 
     auto *One = ConstantInt::getTrue(SelType);
     auto *Zero = ConstantInt::getFalse(SelType);
 
     // We match the "full" 0 or 1 constant here to avoid a potential infinite
if (Value *S = SimplifyWithOpReplaced(TrueVal, CondVal, One, SQ,
                                           /* AllowRefinement */ true))
       return replaceOperand(SI, 1, S);
     if (Value *S = SimplifyWithOpReplaced(FalseVal, CondVal, Zero, SQ,
                                           /* AllowRefinement */ true))
       return replaceOperand(SI, 2, S);
 
     if (match(FalseVal, m_Zero()) || match(TrueVal, m_One())) {
       Use *Y = nullptr;
       bool IsAnd = match(FalseVal, m_Zero()) ? true : false;
       Value *Op1 = IsAnd ? TrueVal : FalseVal;
       if (isCheckForZeroAndMulWithOverflow(CondVal, Op1, IsAnd, Y)) {
         auto *FI = new FreezeInst(*Y, (*Y)->getName() + ".fr");
         InsertNewInstBefore(FI, *cast<Instruction>(Y->getUser()));
         replaceUse(*Y, FI);
         return replaceInstUsesWith(SI, Op1);
       }
 

llvm/test/Transforms/InstCombine/2008-02-28-OrFCmpCrash.ll

bb80:   ; preds = %entry
   ret float 0.000000e+00
 }
 
 define float @test_logical(float %x, x86_fp80 %y) nounwind readonly  {
 ; CHECK-LABEL: @test_logical(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP67:%.*]] = fcmp uno x86_fp80 [[Y:%.*]], 0xK00000000000000000000
 ; CHECK-NEXT:    [[TMP71:%.*]] = fcmp uno float [[X:%.*]], 0.000000e+00
-; CHECK-NEXT:    [[BOTHCOND:%.*]] = or i1 [[TMP67]], [[TMP71]]
+; CHECK-NEXT:    [[BOTHCOND:%.*]] = select i1 [[TMP67]], i1 true, i1 [[TMP71]]
 ; CHECK-NEXT:    br i1 [[BOTHCOND]], label [[BB74:%.*]], label [[BB80:%.*]]
 ; CHECK:       bb74:
 ; CHECK-NEXT:    ret float 0.000000e+00
 ; CHECK:       bb80:
 ; CHECK-NEXT:    ret float 0.000000e+00
 ;
 entry:
   %tmp67 = fcmp uno x86_fp80 %y, 0xK00000000000000000000    ; <i1> [#uses=1]

llvm/test/Transforms/InstCombine/2012-03-10-InstCombine.ll

 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[D:%.*]] = alloca i8, align 1
 ; CHECK-NEXT:    store i8 0, i8* [[D]], align 1
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp ugt i8* [[D]], [[C:%.*]]
 ; CHECK-NEXT:    br i1 [[CMP]], label [[IF_ELSE:%.*]], label [[IF_THEN:%.*]]
 ; CHECK:       if.then:
 ; CHECK-NEXT:    [[CMP2:%.*]] = icmp ule i8* [[D]], [[F:%.*]]
 ; CHECK-NEXT:    [[NOT_CMP1:%.*]] = icmp uge i8* [[C]], [[F]]
-; CHECK-NEXT:    [[DOTCMP2:%.*]] = and i1 [[CMP2]], [[NOT_CMP1]]
+; CHECK-NEXT:    [[DOTCMP2:%.*]] = select i1 [[CMP2]], i1 [[NOT_CMP1]], i1 false
 ; CHECK-NEXT:    br label [[RETURN:%.*]]
 ; CHECK:       if.else:
 ; CHECK-NEXT:    [[CMP5:%.*]] = icmp uge i8* [[D]], [[F]]
 ; CHECK-NEXT:    [[NOT_CMP3:%.*]] = icmp ule i8* [[C]], [[F]]
-; CHECK-NEXT:    [[DOTCMP5:%.*]] = and i1 [[CMP5]], [[NOT_CMP3]]
+; CHECK-NEXT:    [[DOTCMP5:%.*]] = select i1 [[CMP5]], i1 [[NOT_CMP3]], i1 false
 ; CHECK-NEXT:    br label [[RETURN]]
 ; CHECK:       return:
 ; CHECK-NEXT:    [[RETVAL_0_IN:%.*]] = phi i1 [ [[DOTCMP2]], [[IF_THEN]] ], [ [[DOTCMP5]], [[IF_ELSE]] ]
 ; CHECK-NEXT:    [[RETVAL_0:%.*]] = zext i1 [[RETVAL_0_IN]] to i32
 ; CHECK-NEXT:    ret i32 [[RETVAL_0]]
 ;
 entry:
   %d = alloca i8, align 1

llvm/test/Transforms/InstCombine/and-fcmp.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -instcombine -S | FileCheck %s
 
 define i1 @PR1738(double %x, double %y) {
 ; CHECK-LABEL: @PR1738(
 ; CHECK-NEXT:    [[TMP1:%.*]] = fcmp ord double [[X:%.*]], [[Y:%.*]]
 ; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
   %cmp1 = fcmp ord double %x, 0.0
   %cmp2 = fcmp ord double %y, 0.0
   %and = and i1 %cmp1, %cmp2
   ret i1 %and
 }
 
+; TODO: this can be supported by freezing %y
 define i1 @PR1738_logical(double %x, double %y) {
 ; CHECK-LABEL: @PR1738_logical(
+; CHECK-NEXT:    [[CMP1:%.*]] = fcmp ord double [[X:%.*]], 0.000000e+00
+; CHECK-NEXT:    [[CMP2:%.*]] = fcmp ord double [[Y:%.*]], 0.000000e+00
+; CHECK-NEXT:    [[AND:%.*]] = select i1 [[CMP1]], i1 [[CMP2]], i1 false
+; CHECK-NEXT:    ret i1 [[AND]]
+;
+  %cmp1 = fcmp ord double %x, 0.0
+  %cmp2 = fcmp ord double %y, 0.0
+  %and = select i1 %cmp1, i1 %cmp2, i1 false
+  ret i1 %and
+}
+
+define i1 @PR1738_logical_noundef(double %x, double noundef %y) {
+; CHECK-LABEL: @PR1738_logical_noundef(
 ; CHECK-NEXT:    [[TMP1:%.*]] = fcmp ord double [[X:%.*]], [[Y:%.*]]
 ; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
   %cmp1 = fcmp ord double %x, 0.0
   %cmp2 = fcmp ord double %y, 0.0
   %and = select i1 %cmp1, i1 %cmp2, i1 false
   ret i1 %and
 }

 ;
   %ord1 = fcmp arcp ord float %c, 0.0
   %and = and i1 %ord1, %z
   %ord2 = fcmp afn ord float %d, 0.0
   %r = and i1 %and, %ord2
   ret i1 %r
 }
 
+; FIXME: this can be supported by freezing %d
 define i1 @PR41069_logical(i1 %z, float %c, float %d) {
 ; CHECK-LABEL: @PR41069_logical(
-; CHECK-NEXT:    [[TMP1:%.*]] = fcmp ord float [[D:%.*]], [[C:%.*]]
-; CHECK-NEXT:    [[R:%.*]] = and i1 [[TMP1]], [[Z:%.*]]
+; CHECK-NEXT:    [[ORD1:%.*]] = fcmp arcp ord float [[C:%.*]], 0.000000e+00
+; CHECK-NEXT:    [[AND:%.*]] = select i1 [[ORD1]], i1 [[Z:%.*]], i1 false
+; CHECK-NEXT:    [[ORD2:%.*]] = fcmp afn ord float [[D:%.*]], 0.000000e+00
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[AND]], i1 [[ORD2]], i1 false
 ; CHECK-NEXT:    ret i1 [[R]]
 ;
   %ord1 = fcmp arcp ord float %c, 0.0
   %and = select i1 %ord1, i1 %z, i1 false
   %ord2 = fcmp afn ord float %d, 0.0
   %r = select i1 %and, i1 %ord2, i1 false
   ret i1 %r
 }
;
   %r = and i1 %ord2, %and
   ret i1 %r
 }
 
 ; TODO: this should be fixed using freeze
 define i1 @PR41069_commute_logical(i1 %z, float %c, float %d) {
 ; CHECK-LABEL: @PR41069_commute_logical(
 ; CHECK-NEXT:    [[ORD1:%.*]] = fcmp ninf ord float [[C:%.*]], 0.000000e+00
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[ORD1]], [[Z:%.*]]
 ; CHECK-NEXT:    [[ORD2:%.*]] = fcmp reassoc ninf ord float [[D:%.*]], 0.000000e+00
-; CHECK-NEXT:    [[R:%.*]] = select i1 [[ORD2]], i1 [[AND]], i1 false
+; CHECK-NEXT:    [[TMP1:%.*]] = select i1 [[ORD2]], i1 [[ORD1]], i1 false
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[TMP1]], i1 [[Z:%.*]], i1 false
 ; CHECK-NEXT:    ret i1 [[R]]
 ;
   %ord1 = fcmp ninf ord float %c, 0.0
   %and = select i1 %ord1, i1 %z, i1 false
   %ord2 = fcmp ninf reassoc ord float %d, 0.0
   %r = select i1 %ord2, i1 %and, i1 false
   ret i1 %r
 }
;
   %and = and i1 %cmp, %cmp1
   ret i1 %and
 }
 
 define i1 @PR15737_logical(float %a, double %b) {
 ; CHECK-LABEL: @PR15737_logical(
 ; CHECK-NEXT:    [[CMP:%.*]] = fcmp ord float [[A:%.*]], 0.000000e+00
 ; CHECK-NEXT:    [[CMP1:%.*]] = fcmp ord double [[B:%.*]], 0.000000e+00
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[CMP]], [[CMP1]]
+; CHECK-NEXT:    [[AND:%.*]] = select i1 [[CMP]], i1 [[CMP1]], i1 false
 ; CHECK-NEXT:    ret i1 [[AND]]
 ;
   %cmp = fcmp ord float %a, 0.000000e+00
   %cmp1 = fcmp ord double %b, 0.000000e+00
   %and = select i1 %cmp, i1 %cmp1, i1 false
   ret i1 %and
 }
 

 ; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
   %cmp1 = fcmp ord float %x, 1.0
   %cmp2 = fcmp ord float %y, 2.0
   %and = and i1 %cmp1, %cmp2
   ret i1 %and
 }
 
+; TODO: this can be supported by freezing %y
 define i1 @fcmp_ord_nonzero_logical(float %x, float %y) {
 ; CHECK-LABEL: @fcmp_ord_nonzero_logical(
-; CHECK-NEXT:    [[TMP1:%.*]] = fcmp ord float [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT:    ret i1 [[TMP1]]
+; CHECK-NEXT:    [[CMP1:%.*]] = fcmp ord float [[X:%.*]], 0.000000e+00
+; CHECK-NEXT:    [[CMP2:%.*]] = fcmp ord float [[Y:%.*]], 0.000000e+00
+; CHECK-NEXT:    [[AND:%.*]] = select i1 [[CMP1]], i1 [[CMP2]], i1 false
+; CHECK-NEXT:    ret i1 [[AND]]
 ;
   %cmp1 = fcmp ord float %x, 1.0
   %cmp2 = fcmp ord float %y, 2.0
   %and = select i1 %cmp1, i1 %cmp2, i1 false
   ret i1 %and
 }
 
 define <3 x i1> @fcmp_ord_nonzero_vec(<3 x float> %x, <3 x float> %y) {

llvm/test/Transforms/InstCombine/and-or-icmp-min-max.ll

;
   %cmpeq = icmp eq i8 %x, 127
   %r = or i1 %cmpeq, %cmp
   ret i1 %r
 }
 
 define i1 @sge_or_max_commute_logical(i8 %x, i8 %y)  {
 ; CHECK-LABEL: @sge_or_max_commute_logical(
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp sge i8 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT:    ret i1 [[CMP]]
+; CHECK-NEXT:    [[CMPEQ:%.*]] = icmp eq i8 [[X]], 127
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[CMPEQ]], i1 true, i1 [[CMP]]
+; CHECK-NEXT:    ret i1 [[R]]
 ;
   %cmp = icmp sge i8 %x, %y
   %cmpeq = icmp eq i8 %x, 127
   %r = select i1 %cmpeq, i1 true, i1 %cmp
   ret i1 %r
 }
 
 define i1 @sge_swap_or_max(i8 %x, i8 %y)  {
;
   %cmpeq = icmp eq i8 %x, 127
   %r = or i1 %cmpeq, %cmp
   ret i1 %r
 }
 
 define i1 @sge_swap_or_max_commute_logical(i8 %x, i8 %y)  {
 ; CHECK-LABEL: @sge_swap_or_max_commute_logical(
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp sle i8 [[Y:%.*]], [[X:%.*]]
-; CHECK-NEXT:    ret i1 [[CMP]]
+; CHECK-NEXT:    [[CMPEQ:%.*]] = icmp eq i8 [[X]], 127
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[CMPEQ]], i1 true, i1 [[CMP]]
+; CHECK-NEXT:    ret i1 [[R]]
 ;
   %cmp = icmp sle i8 %y, %x
   %cmpeq = icmp eq i8 %x, 127
   %r = select i1 %cmpeq, i1 true, i1 %cmp
   ret i1 %r
 }
 
 define i1 @uge_or_max(i8 %x, i8 %y)  {
;
   %cmpeq = icmp eq i8 %x, 255
   %r = or i1 %cmpeq, %cmp
   ret i1 %r
 }
 
 define i1 @uge_or_max_commute_logical(i8 %x, i8 %y)  {
 ; CHECK-LABEL: @uge_or_max_commute_logical(
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp uge i8 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT:    ret i1 [[CMP]]
+; CHECK-NEXT:    [[CMPEQ:%.*]] = icmp eq i8 [[X]], -1
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[CMPEQ]], i1 true, i1 [[CMP]]
+; CHECK-NEXT:    ret i1 [[R]]
 ;
   %cmp = icmp uge i8 %x, %y
   %cmpeq = icmp eq i8 %x, 255
   %r = select i1 %cmpeq, i1 true, i1 %cmp
   ret i1 %r
 }
 
 define i1 @uge_swap_or_max(i8 %x, i8 %y)  {
;
   %cmpeq = icmp eq i8 %x, 255
   %r = or i1 %cmpeq, %cmp
   ret i1 %r
 }
 
 define i1 @uge_swap_or_max_commute_logical(i8 %x, i8 %y)  {
 ; CHECK-LABEL: @uge_swap_or_max_commute_logical(
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp ule i8 [[Y:%.*]], [[X:%.*]]
-; CHECK-NEXT:    ret i1 [[CMP]]
+; CHECK-NEXT:    [[CMPEQ:%.*]] = icmp eq i8 [[X]], -1
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[CMPEQ]], i1 true, i1 [[CMP]]
+; CHECK-NEXT:    ret i1 [[R]]
 ;
   %cmp = icmp ule i8 %y, %x
   %cmpeq = icmp eq i8 %x, 255
   %r = select i1 %cmpeq, i1 true, i1 %cmp
   ret i1 %r
 }
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
   %cmpeq = icmp eq i8 %x, 128
   %r = or i1 %cmpeq, %cmp
   ret i1 %r
 }
 
 define i1 @sle_or_min_commute_logical(i8 %x, i8 %y)  {
 ; CHECK-LABEL: @sle_or_min_commute_logical(
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp sle i8 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT:    ret i1 [[CMP]]
+; CHECK-NEXT:    [[CMPEQ:%.*]] = icmp eq i8 [[X]], -128
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[CMPEQ]], i1 true, i1 [[CMP]]
+; CHECK-NEXT:    ret i1 [[R]]
 ;
   %cmp = icmp sle i8 %x, %y
   %cmpeq = icmp eq i8 %x, 128
   %r = select i1 %cmpeq, i1 true, i1 %cmp
   ret i1 %r
 }
 
 define i1 @sle_swap_or_min(i8 %x, i8 %y)  {
;
   %cmpeq = icmp eq i8 %x, 128
   %r = or i1 %cmpeq, %cmp
   ret i1 %r
 }
 
 define i1 @sle_swap_or_min_commute_logical(i8 %x, i8 %y)  {
 ; CHECK-LABEL: @sle_swap_or_min_commute_logical(
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp sge i8 [[Y:%.*]], [[X:%.*]]
-; CHECK-NEXT:    ret i1 [[CMP]]
+; CHECK-NEXT:    [[CMPEQ:%.*]] = icmp eq i8 [[X]], -128
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[CMPEQ]], i1 true, i1 [[CMP]]
+; CHECK-NEXT:    ret i1 [[R]]
 ;
   %cmp = icmp sge i8 %y, %x
   %cmpeq = icmp eq i8 %x, 128
   %r = select i1 %cmpeq, i1 true, i1 %cmp
   ret i1 %r
 }
 
 define i1 @ule_or_min(i8 %x, i8 %y)  {
;
   %cmpeq = icmp eq i8 %x, 0
   %r = or i1 %cmpeq, %cmp
   ret i1 %r
 }
 
 define i1 @ule_or_min_commute_logical(i8 %x, i8 %y)  {
 ; CHECK-LABEL: @ule_or_min_commute_logical(
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp ule i8 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT:    ret i1 [[CMP]]
+; CHECK-NEXT:    [[CMPEQ:%.*]] = icmp eq i8 [[X]], 0
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[CMPEQ]], i1 true, i1 [[CMP]]
+; CHECK-NEXT:    ret i1 [[R]]
 ;
   %cmp = icmp ule i8 %x, %y
   %cmpeq = icmp eq i8 %x, 0
   %r = select i1 %cmpeq, i1 true, i1 %cmp
   ret i1 %r
 }
 
 define i1 @ule_swap_or_min(i8 %x, i8 %y)  {
;
   %cmpeq = icmp eq i8 %x, 0
   %r = or i1 %cmpeq, %cmp
   ret i1 %r
 }
 
 define i1 @ule_swap_or_min_commute_logical(i8 %x, i8 %y)  {
 ; CHECK-LABEL: @ule_swap_or_min_commute_logical(
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp uge i8 [[Y:%.*]], [[X:%.*]]
-; CHECK-NEXT:    ret i1 [[CMP]]
+; CHECK-NEXT:    [[CMPEQ:%.*]] = icmp eq i8 [[X]], 0
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[CMPEQ]], i1 true, i1 [[CMP]]
+; CHECK-NEXT:    ret i1 [[R]]
 ;
   %cmp = icmp uge i8 %y, %x
   %cmpeq = icmp eq i8 %x, 0
   %r = select i1 %cmpeq, i1 true, i1 %cmp
   ret i1 %r
 }
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
   %cmpeq = icmp ne i8 %x, 127
   %r = and i1 %cmpeq, %cmp
   ret i1 %r
 }
 
 define i1 @slt_and_not_max_commute_logical(i8 %x, i8 %y)  {
 ; CHECK-LABEL: @slt_and_not_max_commute_logical(
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i8 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT:    ret i1 [[CMP]]
+; CHECK-NEXT:    [[CMPEQ:%.*]] = icmp ne i8 [[X]], 127
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[CMPEQ]], i1 [[CMP]], i1 false
+; CHECK-NEXT:    ret i1 [[R]]
 ;
   %cmp = icmp slt i8 %x, %y
   %cmpeq = icmp ne i8 %x, 127
   %r = select i1 %cmpeq, i1 %cmp, i1 false
   ret i1 %r
 }
 
 define i1 @slt_swap_and_not_max(i8 %x, i8 %y)  {
;
   %cmpeq = icmp ne i8 %x, 127
   %r = and i1 %cmpeq, %cmp
   ret i1 %r
 }
 
 define i1 @slt_swap_and_not_max_commute_logical(i8 %x, i8 %y)  {
 ; CHECK-LABEL: @slt_swap_and_not_max_commute_logical(
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt i8 [[Y:%.*]], [[X:%.*]]
-; CHECK-NEXT:    ret i1 [[CMP]]
+; CHECK-NEXT:    [[CMPEQ:%.*]] = icmp ne i8 [[X]], 127
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[CMPEQ]], i1 [[CMP]], i1 false
+; CHECK-NEXT:    ret i1 [[R]]
 ;
   %cmp = icmp sgt i8 %y, %x
   %cmpeq = icmp ne i8 %x, 127
   %r = select i1 %cmpeq, i1 %cmp, i1 false
   ret i1 %r
 }
 
 define i1 @ult_and_not_max(i8 %x, i8 %y)  {
;
   %cmpeq = icmp ne i8 %x, 255
   %r = and i1 %cmpeq, %cmp
   ret i1 %r
 }
 
 define i1 @ult_and_not_max_commute_logical(i8 %x, i8 %y)  {
 ; CHECK-LABEL: @ult_and_not_max_commute_logical(
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i8 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT:    ret i1 [[CMP]]
+; CHECK-NEXT:    [[CMPEQ:%.*]] = icmp ne i8 [[X]], -1
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[CMPEQ]], i1 [[CMP]], i1 false
+; CHECK-NEXT:    ret i1 [[R]]
 ;
   %cmp = icmp ult i8 %x, %y
   %cmpeq = icmp ne i8 %x, 255
   %r = select i1 %cmpeq, i1 %cmp, i1 false
   ret i1 %r
 }
 
 define i1 @ult_swap_and_not_max(i8 %x, i8 %y)  {
;
   %cmpeq = icmp ne i8 %x, 255
   %r = and i1 %cmpeq, %cmp
   ret i1 %r
 }
 
 define i1 @ult_swap_and_not_max_commute_logical(i8 %x, i8 %y)  {
 ; CHECK-LABEL: @ult_swap_and_not_max_commute_logical(
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp ugt i8 [[Y:%.*]], [[X:%.*]]
-; CHECK-NEXT:    ret i1 [[CMP]]
+; CHECK-NEXT:    [[CMPEQ:%.*]] = icmp ne i8 [[X]], -1
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[CMPEQ]], i1 [[CMP]], i1 false
+; CHECK-NEXT:    ret i1 [[R]]
 ;
   %cmp = icmp ugt i8 %y, %x
   %cmpeq = icmp ne i8 %x, 255
   %r = select i1 %cmpeq, i1 %cmp, i1 false
   ret i1 %r
 }
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
   %cmpeq = icmp ne i8 %x, 128
   %r = and i1 %cmpeq, %cmp
   ret i1 %r
 }
 
 define i1 @sgt_and_not_min_commute_logical(i8 %x, i8 %y)  {
 ; CHECK-LABEL: @sgt_and_not_min_commute_logical(
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt i8 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT:    ret i1 [[CMP]]
+; CHECK-NEXT:    [[CMPEQ:%.*]] = icmp ne i8 [[X]], -128
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[CMPEQ]], i1 [[CMP]], i1 false
+; CHECK-NEXT:    ret i1 [[R]]
 ;
   %cmp = icmp sgt i8 %x, %y
   %cmpeq = icmp ne i8 %x, 128
   %r = select i1 %cmpeq, i1 %cmp, i1 false
   ret i1 %r
 }
 
 define i1 @sgt_swap_and_not_min(i8 %x, i8 %y)  {
;
   %cmpeq = icmp ne i8 %x, 128
   %r = and i1 %cmpeq, %cmp
   ret i1 %r
 }
 
 define i1 @sgt_swap_and_not_min_commute_logical(i8 %x, i8 %y)  {
 ; CHECK-LABEL: @sgt_swap_and_not_min_commute_logical(
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i8 [[Y:%.*]], [[X:%.*]]
-; CHECK-NEXT:    ret i1 [[CMP]]
+; CHECK-NEXT:    [[CMPEQ:%.*]] = icmp ne i8 [[X]], -128
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[CMPEQ]], i1 [[CMP]], i1 false
+; CHECK-NEXT:    ret i1 [[R]]
 ;
   %cmp = icmp slt i8 %y, %x
   %cmpeq = icmp ne i8 %x, 128
   %r = select i1 %cmpeq, i1 %cmp, i1 false
   ret i1 %r
 }
 
 define i1 @ugt_and_not_min(i8 %x, i8 %y)  {
;
   %cmpeq = icmp ne i8 %x, 0
   %r = and i1 %cmpeq, %cmp
   ret i1 %r
 }
 
 define i1 @ugt_and_not_min_commute_logical(i8 %x, i8 %y)  {
 ; CHECK-LABEL: @ugt_and_not_min_commute_logical(
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp ugt i8 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT:    ret i1 [[CMP]]
+; CHECK-NEXT:    [[CMPEQ:%.*]] = icmp ne i8 [[X]], 0
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[CMPEQ]], i1 [[CMP]], i1 false
+; CHECK-NEXT:    ret i1 [[R]]
 ;
   %cmp = icmp ugt i8 %x, %y
   %cmpeq = icmp ne i8 %x, 0
   %r = select i1 %cmpeq, i1 %cmp, i1 false
   ret i1 %r
 }
 
 define i1 @ugt_swap_and_not_min(i8 %x, i8 %y)  {
;
   %cmpeq = icmp ne i8 %x, 0
   %r = and i1 %cmpeq, %cmp
   ret i1 %r
 }
 
 define i1 @ugt_swap_and_not_min_commute_logical(i8 %x, i8 %y)  {
 ; CHECK-LABEL: @ugt_swap_and_not_min_commute_logical(
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i8 [[Y:%.*]], [[X:%.*]]
-; CHECK-NEXT:    ret i1 [[CMP]]
+; CHECK-NEXT:    [[CMPEQ:%.*]] = icmp ne i8 [[X]], 0
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[CMPEQ]], i1 [[CMP]], i1 false
+; CHECK-NEXT:    ret i1 [[R]]
 ;
   %cmp = icmp ult i8 %y, %x
   %cmpeq = icmp ne i8 %x, 0
   %r = select i1 %cmpeq, i1 %cmp, i1 false
   ret i1 %r
 }
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

llvm/test/Transforms/InstCombine/and-or-icmp-nullptr.ll

;
   %cmpeq = icmp eq i8* %x, null
   %r = or i1 %cmpeq, %cmp
   ret i1 %r
 }
 
 define i1 @ule_or_min_commute_logical(i8* %x, i8* %y)  {
 ; CHECK-LABEL: @ule_or_min_commute_logical(
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp ule i8* [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT:    ret i1 [[CMP]]
+; CHECK-NEXT:    [[CMPEQ:%.*]] = icmp eq i8* [[X]], null
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[CMPEQ]], i1 true, i1 [[CMP]]
+; CHECK-NEXT:    ret i1 [[R]]
 ;
   %cmp = icmp ule i8* %x, %y
   %cmpeq = icmp eq i8* %x, null
   %r = select i1 %cmpeq, i1 true, i1 %cmp
   ret i1 %r
 }
 
 define i1 @ule_swap_or_min(i8* %x, i8* %y)  {
;
   %cmpeq = icmp eq i8* %x, null
   %r = or i1 %cmpeq, %cmp
   ret i1 %r
 }
 
 define i1 @ule_swap_or_min_commute_logical(i8* %x, i8* %y)  {
 ; CHECK-LABEL: @ule_swap_or_min_commute_logical(
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp uge i8* [[Y:%.*]], [[X:%.*]]
-; CHECK-NEXT:    ret i1 [[CMP]]
+; CHECK-NEXT:    [[CMPEQ:%.*]] = icmp eq i8* [[X]], null
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[CMPEQ]], i1 true, i1 [[CMP]]
+; CHECK-NEXT:    ret i1 [[R]]
 ;
   %cmp = icmp uge i8* %y, %x
   %cmpeq = icmp eq i8* %x, null
   %r = select i1 %cmpeq, i1 true, i1 %cmp
   ret i1 %r
 }
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
   %cmpeq = icmp ne i8* %x, null
   %r = and i1 %cmpeq, %cmp
   ret i1 %r
 }
 
 define i1 @ugt_and_not_min_commute_logical(i8* %x, i8* %y)  {
 ; CHECK-LABEL: @ugt_and_not_min_commute_logical(
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp ugt i8* [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT:    ret i1 [[CMP]]
+; CHECK-NEXT:    [[CMPEQ:%.*]] = icmp ne i8* [[X]], null
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[CMPEQ]], i1 [[CMP]], i1 false
+; CHECK-NEXT:    ret i1 [[R]]
 ;
   %cmp = icmp ugt i8* %x, %y
   %cmpeq = icmp ne i8* %x, null
   %r = select i1 %cmpeq, i1 %cmp, i1 false
   ret i1 %r
 }
 
 define i1 @ugt_swap_and_not_min(i8* %x, i8* %y)  {
;
   %cmpeq = icmp ne i8* %x, null
   %r = and i1 %cmpeq, %cmp
   ret i1 %r
 }
 
 define i1 @ugt_swap_and_not_min_commute_logical(i8* %x, i8* %y)  {
 ; CHECK-LABEL: @ugt_swap_and_not_min_commute_logical(
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i8* [[Y:%.*]], [[X:%.*]]
-; CHECK-NEXT:    ret i1 [[CMP]]
+; CHECK-NEXT:    [[CMPEQ:%.*]] = icmp ne i8* [[X]], null
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[CMPEQ]], i1 [[CMP]], i1 false
+; CHECK-NEXT:    ret i1 [[R]]
 ;
   %cmp = icmp ult i8* %y, %x
   %cmpeq = icmp ne i8* %x, null
   %r = select i1 %cmpeq, i1 %cmp, i1 false
   ret i1 %r
 }
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
   %cmp = icmp slt i8* %a, %b
   %r = and i1 %cmpeq, %cmp
   ret i1 %r
 }
 
 define i1 @slt_and_min_logical(i8* %a, i8* %b) {
 ; CHECK-LABEL: @slt_and_min_logical(
 ; CHECK-NEXT:    [[CMPEQ:%.*]] = icmp eq i8* [[A:%.*]], null
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt i8* [[B:%.*]], null
-; CHECK-NEXT:    [[TMP2:%.*]] = and i1 [[CMPEQ]], [[TMP1]]
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt i8* [[B:%.*]], null
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[CMPEQ]], i1 [[CMP]], i1 false
+; CHECK-NEXT:    ret i1 [[R]]
 ;
   %cmpeq = icmp eq i8* %a, null
   %cmp = icmp slt i8* %a, %b
   %r = select i1 %cmpeq, i1 %cmp, i1 false
   ret i1 %r
 }

llvm/test/Transforms/InstCombine/and-or-icmps.ll

;
   %cmp1 = icmp ult i32 %a, 8
   %cmp2 = icmp ult i32 %b, 8
   %and = and i1 %cmp2, %cmp1
   ret i1 %and
 }
 
 define i1 @PR2330_logical(i32 %a, i32 %b) {
 ; CHECK-LABEL: @PR2330_logical(
-; CHECK-NEXT:    [[TMP1:%.*]] = or i32 [[B:%.*]], [[A:%.*]]
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp ult i32 [[TMP1]], 8
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp ult i32 [[A:%.*]], 8
+; CHECK-NEXT:    [[CMP2:%.*]] = icmp ult i32 [[B:%.*]], 8
+; CHECK-NEXT:    [[AND:%.*]] = select i1 [[CMP2]], i1 [[CMP1]], i1 false
+; CHECK-NEXT:    ret i1 [[AND]]
 ;
   %cmp1 = icmp ult i32 %a, 8
   %cmp2 = icmp ult i32 %b, 8
   %and = select i1 %cmp2, i1 %cmp1, i1 false
   ret i1 %and
 }
 
 ; if LHSC and RHSC differ only by one bit:
;
   %c2 = icmp eq i8 %x, %y
   %r = and i1 %c1, %c2
   ret i1 %r
 }
 
 define i1 @substitute_constant_and_eq_eq_logical(i8 %x, i8 %y) {
 ; CHECK-LABEL: @substitute_constant_and_eq_eq_logical(
 ; CHECK-NEXT:    [[C1:%.*]] = icmp eq i8 [[X:%.*]], 42
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq i8 [[Y:%.*]], 42
-; CHECK-NEXT:    [[TMP2:%.*]] = and i1 [[C1]], [[TMP1]]
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[C2:%.*]] = icmp eq i8 [[Y:%.*]], 42
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[C1]], i1 [[C2]], i1 false
+; CHECK-NEXT:    ret i1 [[R]]
 ;
   %c1 = icmp eq i8 %x, 42
   %c2 = icmp eq i8 %x, %y
   %r = select i1 %c1, i1 %c2, i1 false
   ret i1 %r
 }
 
 define i1 @substitute_constant_and_eq_eq_commute(i8 %x, i8 %y) {
;
   %c2 = icmp sle i8 %y, %x
   %r = or i1 %c1, %c2
   ret i1 %r
 }
 
 define i1 @substitute_constant_or_ne_swap_sle_logical(i8 %x, i8 %y) {
 ; CHECK-LABEL: @substitute_constant_or_ne_swap_sle_logical(
 ; CHECK-NEXT:    [[C1:%.*]] = icmp ne i8 [[X:%.*]], 42
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i8 [[Y:%.*]], 43
-; CHECK-NEXT:    [[TMP2:%.*]] = or i1 [[C1]], [[TMP1]]
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[C2:%.*]] = icmp slt i8 [[Y:%.*]], 43
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[C1]], i1 true, i1 [[C2]]
+; CHECK-NEXT:    ret i1 [[R]]
 ;
   %c1 = icmp ne i8 %x, 42
   %c2 = icmp sle i8 %y, %x
   %r = select i1 %c1, i1 true, i1 %c2
   ret i1 %r
 }
 
 define i1 @substitute_constant_or_ne_uge_commute(i8 %x, i8 %y) {
;
   %r = or i1 %c1, %c2
   ret i1 %r
 }
 
 define i1 @substitute_constant_or_eq_swap_ne_logical(i8 %x, i8 %y) {
 ; CHECK-LABEL: @substitute_constant_or_eq_swap_ne_logical(
 ; CHECK-NEXT:    [[C1:%.*]] = icmp eq i8 [[X:%.*]], 42
 ; CHECK-NEXT:    [[C2:%.*]] = icmp ne i8 [[Y:%.*]], [[X]]
-; CHECK-NEXT:    [[R:%.*]] = or i1 [[C1]], [[C2]]
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[C1]], i1 true, i1 [[C2]]
 ; CHECK-NEXT:    ret i1 [[R]]
 ;
   %c1 = icmp eq i8 %x, 42
   %c2 = icmp ne i8 %y, %x
   %r = select i1 %c1, i1 true, i1 %c2
   ret i1 %r
 }
 

llvm/test/Transforms/InstCombine/and.ll

;
   %and = and i1 %x, %or
   ret i1 %and
 }
 
 define i1 @and_orn_cmp_1_logical(i32 %a, i32 %b, i32 %c) {
 ; CHECK-LABEL: @and_orn_cmp_1_logical(
 ; CHECK-NEXT:    [[X:%.*]] = icmp sgt i32 [[A:%.*]], [[B:%.*]]
 ; CHECK-NEXT:    [[Y:%.*]] = icmp ugt i32 [[C:%.*]], 42
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[X]], [[Y]]
+; CHECK-NEXT:    [[AND:%.*]] = select i1 [[X]], i1 [[Y]], i1 false
 ; CHECK-NEXT:    ret i1 [[AND]]
 ;
   %x = icmp sgt i32 %a, %b
   %x_inv = icmp sle i32 %a, %b
   %y = icmp ugt i32 %c, 42      ; thwart complexity-based ordering
   %or = select i1 %y, i1 true, i1 %x_inv
   %and = select i1 %x, i1 %or, i1 false
   ret i1 %and
;
   %and = and i1 %x, %or
   ret i1 %and
 }
 
 define i1 @and_orn_cmp_3_logical(i72 %a, i72 %b, i72 %c) {
 ; CHECK-LABEL: @and_orn_cmp_3_logical(
 ; CHECK-NEXT:    [[X:%.*]] = icmp ugt i72 [[A:%.*]], [[B:%.*]]
 ; CHECK-NEXT:    [[Y:%.*]] = icmp ugt i72 [[C:%.*]], 42
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[X]], [[Y]]
+; CHECK-NEXT:    [[AND:%.*]] = select i1 [[X]], i1 [[Y]], i1 false
 ; CHECK-NEXT:    ret i1 [[AND]]
 ;
   %x = icmp ugt i72 %a, %b
   %x_inv = icmp ule i72 %a, %b
   %y = icmp ugt i72 %c, 42      ; thwart complexity-based ordering
   %or = select i1 %x_inv, i1 true, i1 %y
   %and = select i1 %x, i1 %or, i1 false
   ret i1 %and
;
   %and = and i1 %x_inv, %or
   ret i1 %and
 }
 
 define i1 @andn_or_cmp_1_logical(i37 %a, i37 %b, i37 %c) {
 ; CHECK-LABEL: @andn_or_cmp_1_logical(
 ; CHECK-NEXT:    [[X_INV:%.*]] = icmp sle i37 [[A:%.*]], [[B:%.*]]
 ; CHECK-NEXT:    [[Y:%.*]] = icmp ugt i37 [[C:%.*]], 42
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[X_INV]], [[Y]]
+; CHECK-NEXT:    [[AND:%.*]] = select i1 [[X_INV]], i1 [[Y]], i1 false
 ; CHECK-NEXT:    ret i1 [[AND]]
 ;
   %x = icmp sgt i37 %a, %b
   %x_inv = icmp sle i37 %a, %b
   %y = icmp ugt i37 %c, 42      ; thwart complexity-based ordering
   %or = select i1 %y, i1 true, i1 %x
   %and = select i1 %x_inv, i1 %or, i1 false
   ret i1 %and
;
   %and = and i1 %or, %x_inv
   ret i1 %and
 }
 
 define i1 @andn_or_cmp_2_logical(i16 %a, i16 %b, i16 %c) {
 ; CHECK-LABEL: @andn_or_cmp_2_logical(
 ; CHECK-NEXT:    [[X_INV:%.*]] = icmp slt i16 [[A:%.*]], [[B:%.*]]
 ; CHECK-NEXT:    [[Y:%.*]] = icmp ugt i16 [[C:%.*]], 42
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[Y]], [[X_INV]]
+; CHECK-NEXT:    [[AND:%.*]] = select i1 [[Y]], i1 [[X_INV]], i1 false
 ; CHECK-NEXT:    ret i1 [[AND]]
 ;
   %x = icmp sge i16 %a, %b
   %x_inv = icmp slt i16 %a, %b
   %y = icmp ugt i16 %c, 42      ; thwart complexity-based ordering
   %or = select i1 %y, i1 true, i1 %x
   %and = select i1 %or, i1 %x_inv, i1 false
   ret i1 %and
;
   %and = and i1 %or, %x_inv
   ret i1 %and
 }
 
 define i1 @andn_or_cmp_4_logical(i32 %a, i32 %b, i32 %c) {
 ; CHECK-LABEL: @andn_or_cmp_4_logical(
 ; CHECK-NEXT:    [[X_INV:%.*]] = icmp ne i32 [[A:%.*]], [[B:%.*]]
 ; CHECK-NEXT:    [[Y:%.*]] = icmp ugt i32 [[C:%.*]], 42
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[Y]], [[X_INV]]
+; CHECK-NEXT:    [[AND:%.*]] = select i1 [[X_INV]], i1 [[Y]], i1 false
 ; CHECK-NEXT:    ret i1 [[AND]]
 ;
   %x = icmp eq i32 %a, %b
   %x_inv = icmp ne i32 %a, %b
   %y = icmp ugt i32 %c, 42      ; thwart complexity-based ordering
   %or = select i1 %x, i1 true, i1 %y
   %and = select i1 %or, i1 %x_inv, i1 false
   ret i1 %and

llvm/test/Transforms/InstCombine/and2.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -instcombine -S | FileCheck %s
 
 define i1 @test2(i1 %X, i1 %Y) {
 ; CHECK-LABEL: @test2(
 ; CHECK-NEXT:    [[A:%.*]] = and i1 [[X:%.*]], [[Y:%.*]]
 ; CHECK-NEXT:    ret i1 [[A]]
 ;
   %a = and i1 %X, %Y
   %b = and i1 %a, %X
   ret i1 %b
 }
 
 define i1 @test2_logical(i1 %X, i1 %Y) {
 ; CHECK-LABEL: @test2_logical(
-; CHECK-NEXT:    [[A:%.*]] = and i1 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[A:%.*]] = select i1 [[X:%.*]], i1 [[Y:%.*]], i1 false
 ; CHECK-NEXT:    ret i1 [[A]]
 ;
   %a = select i1 %X, i1 %Y, i1 false
   %b = select i1 %a, i1 %X, i1 false
   ret i1 %b
 }
 
 define i32 @test3(i32 %X, i32 %Y) {
;
   %cmp2 = icmp sgt i32 %i, -1
   %and1 = and i1 %cmp1, %b
   %and2 = and i1 %and1, %cmp2
   ret i1 %and2
 }
 
 define i1 @test7_logical(i32 %i, i1 %b) {
 ; CHECK-LABEL: @test7_logical(
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq i32 [[I:%.*]], 0
-; CHECK-NEXT:    [[TMP2:%.*]] = and i1 [[TMP1]], [[B:%.*]]
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp slt i32 [[I:%.*]], 1
+; CHECK-NEXT:    [[CMP2:%.*]] = icmp sgt i32 [[I]], -1
+; CHECK-NEXT:    [[AND1:%.*]] = select i1 [[CMP1]], i1 [[B:%.*]], i1 false
+; CHECK-NEXT:    [[AND2:%.*]] = and i1 [[AND1]], [[CMP2]]
+; CHECK-NEXT:    ret i1 [[AND2]]
 ;
   %cmp1 = icmp slt i32 %i, 1
   %cmp2 = icmp sgt i32 %i, -1
   %and1 = select i1 %cmp1, i1 %b, i1 false
   %and2 = select i1 %and1, i1 %cmp2, i1 false
   ret i1 %and2
 }
 

llvm/test/Transforms/InstCombine/assume.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt < %s -instcombine -S  -instcombine-infinite-loop-threshold=2  -instcombine-unsafe-select-transform=0 | FileCheck --check-prefixes=CHECK,DEFAULT %s
-; RUN: opt < %s -instcombine --enable-knowledge-retention -S  -instcombine-infinite-loop-threshold=2  -instcombine-unsafe-select-transform=0 | FileCheck --check-prefixes=CHECK,BUNDLES %s
+; RUN: opt < %s -instcombine -S  -instcombine-infinite-loop-threshold=2  | FileCheck --check-prefixes=CHECK,DEFAULT %s
+; RUN: opt < %s -instcombine --enable-knowledge-retention -S  -instcombine-infinite-loop-threshold=2  | FileCheck --check-prefixes=CHECK,BUNDLES %s
 
 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-unknown-linux-gnu"
 
 declare void @llvm.assume(i1) #1
 
 ; Check that the alignment has been upgraded and that the assume has not
 ; been removed:

llvm/test/Transforms/InstCombine/bit-checks.ll

;
   %tobool3 = icmp eq i32 %and2, 0
   %and.cond = and i1 %tobool, %tobool3
   %storemerge = select i1 %and.cond, i32 0, i32 1
   ret i32 %storemerge
 }
 
 define i32 @main3e_like_logical(i32 %argc, i32 %argc2, i32 %argc3) {
 ; CHECK-LABEL: @main3e_like_logical(
-; CHECK-NEXT:    [[TMP1:%.*]] = or i32 [[ARGC2:%.*]], [[ARGC3:%.*]]
-; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], [[ARGC:%.*]]
-; CHECK-NEXT:    [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
-; CHECK-NEXT:    [[STOREMERGE:%.*]] = zext i1 [[TMP3]] to i32
+; CHECK-NEXT:    [[AND:%.*]] = and i32 [[ARGC:%.*]], [[ARGC2:%.*]]
+; CHECK-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[AND]], 0
+; CHECK-NEXT:    [[AND2:%.*]] = and i32 [[ARGC]], [[ARGC3:%.*]]
+; CHECK-NEXT:    [[TOBOOL3:%.*]] = icmp ne i32 [[AND2]], 0
+; CHECK-NEXT:    [[AND_COND:%.*]] = select i1 [[TOBOOL]], i1 true, i1 [[TOBOOL3]]
+; CHECK-NEXT:    [[STOREMERGE:%.*]] = zext i1 [[AND_COND]] to i32
 ; CHECK-NEXT:    ret i32 [[STOREMERGE]]
 ;
   %and = and i32 %argc, %argc2
   %tobool = icmp eq i32 %and, 0
   %and2 = and i32 %argc, %argc3
   %tobool3 = icmp eq i32 %and2, 0
   %and.cond = select i1 %tobool, i1 %tobool3, i1 false
   %storemerge = select i1 %and.cond, i32 0, i32 1
;
   %tobool3 = icmp ne i32 %and2, 0
   %or.cond = or i1 %tobool, %tobool3
   %storemerge = select i1 %or.cond, i32 0, i32 1
   ret i32 %storemerge
 }
 
 define i32 @main3f_like_logical(i32 %argc, i32 %argc2, i32 %argc3) {
 ; CHECK-LABEL: @main3f_like_logical(
-; CHECK-NEXT:    [[TMP1:%.*]] = or i32 [[ARGC2:%.*]], [[ARGC3:%.*]]
-; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], [[ARGC:%.*]]
-; CHECK-NEXT:    [[DOTNOT:%.*]] = icmp eq i32 [[TMP2]], 0
-; CHECK-NEXT:    [[STOREMERGE:%.*]] = zext i1 [[DOTNOT]] to i32
+; CHECK-NEXT:    [[AND:%.*]] = and i32 [[ARGC:%.*]], [[ARGC2:%.*]]
+; CHECK-NEXT:    [[TOBOOL:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT:    [[AND2:%.*]] = and i32 [[ARGC]], [[ARGC3:%.*]]
+; CHECK-NEXT:    [[TOBOOL3:%.*]] = icmp eq i32 [[AND2]], 0
+; CHECK-NEXT:    [[OR_COND:%.*]] = select i1 [[TOBOOL]], i1 [[TOBOOL3]], i1 false
+; CHECK-NEXT:    [[STOREMERGE:%.*]] = zext i1 [[OR_COND]] to i32
 ; CHECK-NEXT:    ret i32 [[STOREMERGE]]
 ;
   %and = and i32 %argc, %argc2
   %tobool = icmp ne i32 %and, 0
   %and2 = and i32 %argc, %argc3
   %tobool3 = icmp ne i32 %and2, 0
   %or.cond = select i1 %tobool, i1 true, i1 %tobool3
   %storemerge = select i1 %or.cond, i32 0, i32 1
;
   %tobool3 = icmp eq i32 %and2, %argc3
   %and.cond = and i1 %tobool, %tobool3
   %storemerge = select i1 %and.cond, i32 0, i32 1
   ret i32 %storemerge
 }
 
 define i32 @main4e_like_logical(i32 %argc, i32 %argc2, i32 %argc3) {
 ; CHECK-LABEL: @main4e_like_logical(
-; CHECK-NEXT:    [[TMP1:%.*]] = or i32 [[ARGC2:%.*]], [[ARGC3:%.*]]
-; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], [[ARGC:%.*]]
-; CHECK-NEXT:    [[TMP3:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]]
-; CHECK-NEXT:    [[STOREMERGE:%.*]] = zext i1 [[TMP3]] to i32
+; CHECK-NEXT:    [[AND:%.*]] = and i32 [[ARGC:%.*]], [[ARGC2:%.*]]
+; CHECK-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[AND]], [[ARGC2]]
+; CHECK-NEXT:    [[AND2:%.*]] = and i32 [[ARGC]], [[ARGC3:%.*]]
+; CHECK-NEXT:    [[TOBOOL3:%.*]] = icmp ne i32 [[AND2]], [[ARGC3]]
+; CHECK-NEXT:    [[AND_COND:%.*]] = select i1 [[TOBOOL]], i1 true, i1 [[TOBOOL3]]
+; CHECK-NEXT:    [[STOREMERGE:%.*]] = zext i1 [[AND_COND]] to i32
 ; CHECK-NEXT:    ret i32 [[STOREMERGE]]
 ;
   %and = and i32 %argc, %argc2
   %tobool = icmp eq i32 %and, %argc2
   %and2 = and i32 %argc, %argc3
   %tobool3 = icmp eq i32 %and2, %argc3
   %and.cond = select i1 %tobool, i1 %tobool3, i1 false
   %storemerge = select i1 %and.cond, i32 0, i32 1
;
   %tobool3 = icmp ne i32 %and2, %argc3
   %or.cond = or i1 %tobool, %tobool3
   %storemerge = select i1 %or.cond, i32 0, i32 1
   ret i32 %storemerge
 }
 
 define i32 @main4f_like_logical(i32 %argc, i32 %argc2, i32 %argc3) {
 ; CHECK-LABEL: @main4f_like_logical(
-; CHECK-NEXT:    [[TMP1:%.*]] = or i32 [[ARGC2:%.*]], [[ARGC3:%.*]]
-; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], [[ARGC:%.*]]
-; CHECK-NEXT:    [[DOTNOT:%.*]] = icmp eq i32 [[TMP2]], [[TMP1]]
-; CHECK-NEXT:    [[STOREMERGE:%.*]] = zext i1 [[DOTNOT]] to i32
+; CHECK-NEXT:    [[AND:%.*]] = and i32 [[ARGC:%.*]], [[ARGC2:%.*]]
+; CHECK-NEXT:    [[TOBOOL:%.*]] = icmp eq i32 [[AND]], [[ARGC2]]
+; CHECK-NEXT:    [[AND2:%.*]] = and i32 [[ARGC]], [[ARGC3:%.*]]
+; CHECK-NEXT:    [[TOBOOL3:%.*]] = icmp eq i32 [[AND2]], [[ARGC3]]
+; CHECK-NEXT:    [[OR_COND:%.*]] = select i1 [[TOBOOL]], i1 [[TOBOOL3]], i1 false
+; CHECK-NEXT:    [[STOREMERGE:%.*]] = zext i1 [[OR_COND]] to i32
 ; CHECK-NEXT:    ret i32 [[STOREMERGE]]
 ;
   %and = and i32 %argc, %argc2
   %tobool = icmp ne i32 %and, %argc2
   %and2 = and i32 %argc, %argc3
   %tobool3 = icmp ne i32 %and2, %argc3
   %or.cond = select i1 %tobool, i1 true, i1 %tobool3
   %storemerge = select i1 %or.cond, i32 0, i32 1
;
   %tobool3 = icmp eq i32 %and2, 7
   %and.cond = and i1 %tobool, %tobool3
   %storemerge = select i1 %and.cond, i32 0, i32 1
   ret i32 %storemerge
 }
 
 define i32 @main5_like_logical(i32 %argc, i32 %argc2) {
 ; CHECK-LABEL: @main5_like_logical(
-; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[ARGC:%.*]], [[ARGC2:%.*]]
-; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], 7
-; CHECK-NEXT:    [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 7
-; CHECK-NEXT:    [[STOREMERGE:%.*]] = zext i1 [[TMP3]] to i32
+; CHECK-NEXT:    [[AND:%.*]] = and i32 [[ARGC:%.*]], 7
+; CHECK-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[AND]], 7
+; CHECK-NEXT:    [[AND2:%.*]] = and i32 [[ARGC2:%.*]], 7
+; CHECK-NEXT:    [[TOBOOL3:%.*]] = icmp ne i32 [[AND2]], 7
+; CHECK-NEXT:    [[AND_COND:%.*]] = select i1 [[TOBOOL]], i1 true, i1 [[TOBOOL3]]
+; CHECK-NEXT:    [[STOREMERGE:%.*]] = zext i1 [[AND_COND]] to i32
 ; CHECK-NEXT:    ret i32 [[STOREMERGE]]
 ;
   %and = and i32 %argc, 7
   %tobool = icmp eq i32 %and, 7
   %and2 = and i32 %argc2, 7
   %tobool3 = icmp eq i32 %and2, 7
   %and.cond = select i1 %tobool, i1 %tobool3, i1 false
   %storemerge = select i1 %and.cond, i32 0, i32 1
;
   %tobool3 = icmp eq i32 %and2, %argc
   %and.cond = and i1 %tobool, %tobool3
   %storemerge = select i1 %and.cond, i32 0, i32 1
   ret i32 %storemerge
 }
 
 define i32 @main5e_like_logical(i32 %argc, i32 %argc2, i32 %argc3) {
 ; CHECK-LABEL: @main5e_like_logical(
-; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[ARGC2:%.*]], [[ARGC3:%.*]]
-; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], [[ARGC:%.*]]
-; CHECK-NEXT:    [[TMP3:%.*]] = icmp ne i32 [[TMP2]], [[ARGC]]
-; CHECK-NEXT:    [[STOREMERGE:%.*]] = zext i1 [[TMP3]] to i32
+; CHECK-NEXT:    [[AND:%.*]] = and i32 [[ARGC:%.*]], [[ARGC2:%.*]]
+; CHECK-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[AND]], [[ARGC]]
+; CHECK-NEXT:    [[AND2:%.*]] = and i32 [[ARGC]], [[ARGC3:%.*]]
+; CHECK-NEXT:    [[TOBOOL3:%.*]] = icmp ne i32 [[AND2]], [[ARGC]]
+; CHECK-NEXT:    [[AND_COND:%.*]] = select i1 [[TOBOOL]], i1 true, i1 [[TOBOOL3]]
+; CHECK-NEXT:    [[STOREMERGE:%.*]] = zext i1 [[AND_COND]] to i32
 ; CHECK-NEXT:    ret i32 [[STOREMERGE]]
 ;
   %and = and i32 %argc, %argc2
   %tobool = icmp eq i32 %and, %argc
   %and2 = and i32 %argc, %argc3
   %tobool3 = icmp eq i32 %and2, %argc
   %and.cond = select i1 %tobool, i1 %tobool3, i1 false
   %storemerge = select i1 %and.cond, i32 0, i32 1
;
   %tobool3 = icmp ne i32 %and2, 7
   %or.cond = or i1 %tobool, %tobool3
   %storemerge = select i1 %or.cond, i32 0, i32 1
   ret i32 %storemerge
 }
 
 define i32 @main5c_like_logical(i32 %argc, i32 %argc2) {
 ; CHECK-LABEL: @main5c_like_logical(
-; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[ARGC:%.*]], [[ARGC2:%.*]]
-; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], 7
-; CHECK-NEXT:    [[DOTNOT:%.*]] = icmp eq i32 [[TMP2]], 7
-; CHECK-NEXT:    [[STOREMERGE:%.*]] = zext i1 [[DOTNOT]] to i32
+; CHECK-NEXT:    [[AND:%.*]] = and i32 [[ARGC:%.*]], 7
+; CHECK-NEXT:    [[TOBOOL:%.*]] = icmp eq i32 [[AND]], 7
+; CHECK-NEXT:    [[AND2:%.*]] = and i32 [[ARGC2:%.*]], 7
+; CHECK-NEXT:    [[TOBOOL3:%.*]] = icmp eq i32 [[AND2]], 7
+; CHECK-NEXT:    [[OR_COND:%.*]] = select i1 [[TOBOOL]], i1 [[TOBOOL3]], i1 false
+; CHECK-NEXT:    [[STOREMERGE:%.*]] = zext i1 [[OR_COND]] to i32
 ; CHECK-NEXT:    ret i32 [[STOREMERGE]]
 ;
   %and = and i32 %argc, 7
   %tobool = icmp ne i32 %and, 7
   %and2 = and i32 %argc2, 7
   %tobool3 = icmp ne i32 %and2, 7
   %or.cond = select i1 %tobool, i1 true, i1 %tobool3
   %storemerge = select i1 %or.cond, i32 0, i32 1
;
   %tobool3 = icmp ne i32 %and2, %argc
   %or.cond = or i1 %tobool, %tobool3
   %storemerge = select i1 %or.cond, i32 0, i32 1
   ret i32 %storemerge
 }
 
 define i32 @main5f_like_logical(i32 %argc, i32 %argc2, i32 %argc3) {
 ; CHECK-LABEL: @main5f_like_logical(
-; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[ARGC2:%.*]], [[ARGC3:%.*]]
-; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], [[ARGC:%.*]]
-; CHECK-NEXT:    [[DOTNOT:%.*]] = icmp eq i32 [[TMP2]], [[ARGC]]
-; CHECK-NEXT:    [[STOREMERGE:%.*]] = zext i1 [[DOTNOT]] to i32
+; CHECK-NEXT:    [[AND:%.*]] = and i32 [[ARGC:%.*]], [[ARGC2:%.*]]
+; CHECK-NEXT:    [[TOBOOL:%.*]] = icmp eq i32 [[AND]], [[ARGC]]
+; CHECK-NEXT:    [[AND2:%.*]] = and i32 [[ARGC]], [[ARGC3:%.*]]
+; CHECK-NEXT:    [[TOBOOL3:%.*]] = icmp eq i32 [[AND2]], [[ARGC]]
+; CHECK-NEXT:    [[OR_COND:%.*]] = select i1 [[TOBOOL]], i1 [[TOBOOL3]], i1 false
+; CHECK-NEXT:    [[STOREMERGE:%.*]] = zext i1 [[OR_COND]] to i32
 ; CHECK-NEXT:    ret i32 [[STOREMERGE]]
 ;
   %and = and i32 %argc, %argc2
   %tobool = icmp ne i32 %and, %argc
   %and2 = and i32 %argc, %argc3
   %tobool3 = icmp ne i32 %and2, %argc
   %or.cond = select i1 %tobool, i1 true, i1 %tobool3
   %storemerge = select i1 %or.cond, i32 0, i32 1
;
   %tobool3 = icmp eq i32 %and2, %argc3
   %and.cond = and i1 %tobool, %tobool3
   %storemerge = select i1 %and.cond, i32 0, i32 1
   ret i32 %storemerge
 }
 
 define i32 @main7a_logical(i32 %argc, i32 %argc2, i32 %argc3) {
 ; CHECK-LABEL: @main7a_logical(
-; CHECK-NEXT:    [[TMP1:%.*]] = or i32 [[ARGC2:%.*]], [[ARGC3:%.*]]
-; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], [[ARGC:%.*]]
-; CHECK-NEXT:    [[TMP3:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]]
-; CHECK-NEXT:    [[STOREMERGE:%.*]] = zext i1 [[TMP3]] to i32
+; CHECK-NEXT:    [[AND1:%.*]] = and i32 [[ARGC2:%.*]], [[ARGC:%.*]]
+; CHECK-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[AND1]], [[ARGC2]]
+; CHECK-NEXT:    [[AND2:%.*]] = and i32 [[ARGC3:%.*]], [[ARGC]]
+; CHECK-NEXT:    [[TOBOOL3:%.*]] = icmp ne i32 [[AND2]], [[ARGC3]]
+; CHECK-NEXT:    [[AND_COND:%.*]] = select i1 [[TOBOOL]], i1 true, i1 [[TOBOOL3]]
+; CHECK-NEXT:    [[STOREMERGE:%.*]] = zext i1 [[AND_COND]] to i32
 ; CHECK-NEXT:    ret i32 [[STOREMERGE]]
 ;
   %and1 = and i32 %argc2, %argc
   %tobool = icmp eq i32 %and1, %argc2
   %and2 = and i32 %argc3, %argc
   %tobool3 = icmp eq i32 %and2, %argc3
   %and.cond = select i1 %tobool, i1 %tobool3, i1 false
   %storemerge = select i1 %and.cond, i32 0, i32 1
;
   %tobool3 = icmp eq i32 %argc3, %and2
   %and.cond = and i1 %tobool, %tobool3
   %storemerge = select i1 %and.cond, i32 0, i32 1
   ret i32 %storemerge
 }
 
 define i32 @main7b_logical(i32 %argc, i32 %argc2, i32 %argc3) {
 ; CHECK-LABEL: @main7b_logical(
-; CHECK-NEXT:    [[TMP1:%.*]] = or i32 [[ARGC2:%.*]], [[ARGC3:%.*]]
-; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], [[ARGC:%.*]]
-; CHECK-NEXT:    [[TMP3:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]]
-; CHECK-NEXT:    [[STOREMERGE:%.*]] = zext i1 [[TMP3]] to i32
+; CHECK-NEXT:    [[AND1:%.*]] = and i32 [[ARGC:%.*]], [[ARGC2:%.*]]
+; CHECK-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[AND1]], [[ARGC2]]
+; CHECK-NEXT:    [[AND2:%.*]] = and i32 [[ARGC]], [[ARGC3:%.*]]
+; CHECK-NEXT:    [[TOBOOL3:%.*]] = icmp ne i32 [[AND2]], [[ARGC3]]
+; CHECK-NEXT:    [[AND_COND:%.*]] = select i1 [[TOBOOL]], i1 true, i1 [[TOBOOL3]]
+; CHECK-NEXT:    [[STOREMERGE:%.*]] = zext i1 [[AND_COND]] to i32
 ; CHECK-NEXT:    ret i32 [[STOREMERGE]]
 ;
   %and1 = and i32 %argc, %argc2
   %tobool = icmp eq i32 %argc2, %and1
   %and2 = and i32 %argc, %argc3
   %tobool3 = icmp eq i32 %argc3, %and2
   %and.cond = select i1 %tobool, i1 %tobool3, i1 false
   %storemerge = select i1 %and.cond, i32 0, i32 1
;
   %tobool3 = icmp eq i32 %argc3, %and2
   %and.cond = and i1 %tobool, %tobool3
   %storemerge = select i1 %and.cond, i32 0, i32 1
   ret i32 %storemerge
 }
 
 define i32 @main7c_logical(i32 %argc, i32 %argc2, i32 %argc3) {
 ; CHECK-LABEL: @main7c_logical(
-; CHECK-NEXT:    [[TMP1:%.*]] = or i32 [[ARGC2:%.*]], [[ARGC3:%.*]]
-; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], [[ARGC:%.*]]
-; CHECK-NEXT:    [[TMP3:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]]
-; CHECK-NEXT:    [[STOREMERGE:%.*]] = zext i1 [[TMP3]] to i32
+; CHECK-NEXT:    [[AND1:%.*]] = and i32 [[ARGC2:%.*]], [[ARGC:%.*]]
+; CHECK-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[AND1]], [[ARGC2]]
+; CHECK-NEXT:    [[AND2:%.*]] = and i32 [[ARGC3:%.*]], [[ARGC]]
+; CHECK-NEXT:    [[TOBOOL3:%.*]] = icmp ne i32 [[AND2]], [[ARGC3]]
+; CHECK-NEXT:    [[AND_COND:%.*]] = select i1 [[TOBOOL]], i1 true, i1 [[TOBOOL3]]
+; CHECK-NEXT:    [[STOREMERGE:%.*]] = zext i1 [[AND_COND]] to i32
 ; CHECK-NEXT:    ret i32 [[STOREMERGE]]
 ;
   %and1 = and i32 %argc2, %argc
   %tobool = icmp eq i32 %argc2, %and1
   %and2 = and i32 %argc3, %argc
   %tobool3 = icmp eq i32 %argc3, %and2
   %and.cond = select i1 %tobool, i1 %tobool3, i1 false
   %storemerge = select i1 %and.cond, i32 0, i32 1
;
   %storemerge = select i1 %and.cond, i32 0, i32 1
   ret i32 %storemerge
 }
 
 define i32 @main7d_logical(i32 %argc, i32 %argc2, i32 %argc3, i32 %argc4, i32 %argc5) {
 ; CHECK-LABEL: @main7d_logical(
 ; CHECK-NEXT:    [[BC:%.*]] = and i32 [[ARGC2:%.*]], [[ARGC4:%.*]]
 ; CHECK-NEXT:    [[DE:%.*]] = and i32 [[ARGC3:%.*]], [[ARGC5:%.*]]
-; CHECK-NEXT:    [[TMP1:%.*]] = or i32 [[BC]], [[DE]]
-; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], [[ARGC:%.*]]
-; CHECK-NEXT:    [[TMP3:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]]
-; CHECK-NEXT:    [[STOREMERGE:%.*]] = zext i1 [[TMP3]] to i32
+; CHECK-NEXT:    [[AND1:%.*]] = and i32 [[BC]], [[ARGC:%.*]]
+; CHECK-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[AND1]], [[BC]]
+; CHECK-NEXT:    [[AND2:%.*]] = and i32 [[DE]], [[ARGC]]
+; CHECK-NEXT:    [[TOBOOL3:%.*]] = icmp ne i32 [[AND2]], [[DE]]
+; CHECK-NEXT:    [[AND_COND:%.*]] = select i1 [[TOBOOL]], i1 true, i1 [[TOBOOL3]]
+; CHECK-NEXT:    [[STOREMERGE:%.*]] = zext i1 [[AND_COND]] to i32
 ; CHECK-NEXT:    ret i32 [[STOREMERGE]]
 ;
   %bc = and i32 %argc2, %argc4
   %de = and i32 %argc3, %argc5
   %and1 = and i32 %argc, %bc
   %tobool = icmp eq i32 %and1, %bc
   %and2 = and i32 %argc, %de
   %tobool3 = icmp eq i32 %and2, %de
;
   %storemerge = select i1 %and.cond, i32 0, i32 1
   ret i32 %storemerge
 }
 
 define i32 @main7e_logical(i32 %argc, i32 %argc2, i32 %argc3, i32 %argc4, i32 %argc5) {
 ; CHECK-LABEL: @main7e_logical(
 ; CHECK-NEXT:    [[BC:%.*]] = and i32 [[ARGC2:%.*]], [[ARGC4:%.*]]
 ; CHECK-NEXT:    [[DE:%.*]] = and i32 [[ARGC3:%.*]], [[ARGC5:%.*]]
-; CHECK-NEXT:    [[TMP1:%.*]] = or i32 [[BC]], [[DE]]
-; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], [[ARGC:%.*]]
-; CHECK-NEXT:    [[TMP3:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]]
-; CHECK-NEXT:    [[STOREMERGE:%.*]] = zext i1 [[TMP3]] to i32
+; CHECK-NEXT:    [[AND1:%.*]] = and i32 [[BC]], [[ARGC:%.*]]
+; CHECK-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[AND1]], [[BC]]
+; CHECK-NEXT:    [[AND2:%.*]] = and i32 [[DE]], [[ARGC]]
+; CHECK-NEXT:    [[TOBOOL3:%.*]] = icmp ne i32 [[AND2]], [[DE]]
+; CHECK-NEXT:    [[AND_COND:%.*]] = select i1 [[TOBOOL]], i1 true, i1 [[TOBOOL3]]
+; CHECK-NEXT:    [[STOREMERGE:%.*]] = zext i1 [[AND_COND]] to i32
 ; CHECK-NEXT:    ret i32 [[STOREMERGE]]
 ;
   %bc = and i32 %argc2, %argc4
   %de = and i32 %argc3, %argc5
   %and1 = and i32 %bc, %argc
   %tobool = icmp eq i32 %and1, %bc
   %and2 = and i32 %de, %argc
   %tobool3 = icmp eq i32 %and2, %de
;
   %storemerge = select i1 %and.cond, i32 0, i32 1
   ret i32 %storemerge
 }
 
 define i32 @main7f_logical(i32 %argc, i32 %argc2, i32 %argc3, i32 %argc4, i32 %argc5) {
 ; CHECK-LABEL: @main7f_logical(
 ; CHECK-NEXT:    [[BC:%.*]] = and i32 [[ARGC2:%.*]], [[ARGC4:%.*]]
 ; CHECK-NEXT:    [[DE:%.*]] = and i32 [[ARGC3:%.*]], [[ARGC5:%.*]]
-; CHECK-NEXT:    [[TMP1:%.*]] = or i32 [[BC]], [[DE]]
-; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], [[ARGC:%.*]]
-; CHECK-NEXT:    [[TMP3:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]]
-; CHECK-NEXT:    [[STOREMERGE:%.*]] = zext i1 [[TMP3]] to i32
+; CHECK-NEXT:    [[AND1:%.*]] = and i32 [[BC]], [[ARGC:%.*]]
+; CHECK-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[BC]], [[AND1]]
+; CHECK-NEXT:    [[AND2:%.*]] = and i32 [[DE]], [[ARGC]]
+; CHECK-NEXT:    [[TOBOOL3:%.*]] = icmp ne i32 [[DE]], [[AND2]]
+; CHECK-NEXT:    [[AND_COND:%.*]] = select i1 [[TOBOOL]], i1 true, i1 [[TOBOOL3]]
+; CHECK-NEXT:    [[STOREMERGE:%.*]] = zext i1 [[AND_COND]] to i32
 ; CHECK-NEXT:    ret i32 [[STOREMERGE]]
 ;
   %bc = and i32 %argc2, %argc4
   %de = and i32 %argc3, %argc5
   %and1 = and i32 %argc, %bc
   %tobool = icmp eq i32 %bc, %and1
   %and2 = and i32 %argc, %de
   %tobool3 = icmp eq i32 %de, %and2
;
   %storemerge = select i1 %and.cond, i32 0, i32 1
   ret i32 %storemerge
 }
 
 define i32 @main7g_logical(i32 %argc, i32 %argc2, i32 %argc3, i32 %argc4, i32 %argc5) {
 ; CHECK-LABEL: @main7g_logical(
 ; CHECK-NEXT:    [[BC:%.*]] = and i32 [[ARGC2:%.*]], [[ARGC4:%.*]]
 ; CHECK-NEXT:    [[DE:%.*]] = and i32 [[ARGC3:%.*]], [[ARGC5:%.*]]
-; CHECK-NEXT:    [[TMP1:%.*]] = or i32 [[BC]], [[DE]]
-; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], [[ARGC:%.*]]
-; CHECK-NEXT:    [[TMP3:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]]
-; CHECK-NEXT:    [[STOREMERGE:%.*]] = zext i1 [[TMP3]] to i32
+; CHECK-NEXT:    [[AND1:%.*]] = and i32 [[BC]], [[ARGC:%.*]]
+; CHECK-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[BC]], [[AND1]]
+; CHECK-NEXT:    [[AND2:%.*]] = and i32 [[DE]], [[ARGC]]
+; CHECK-NEXT:    [[TOBOOL3:%.*]] = icmp ne i32 [[DE]], [[AND2]]
+; CHECK-NEXT:    [[AND_COND:%.*]] = select i1 [[TOBOOL]], i1 true, i1 [[TOBOOL3]]
+; CHECK-NEXT:    [[STOREMERGE:%.*]] = zext i1 [[AND_COND]] to i32
 ; CHECK-NEXT:    ret i32 [[STOREMERGE]]
 ;
   %bc = and i32 %argc2, %argc4
   %de = and i32 %argc3, %argc5
   %and1 = and i32 %bc, %argc
   %tobool = icmp eq i32 %bc, %and1
   %and2 = and i32 %de, %argc
   %tobool3 = icmp eq i32 %de, %and2

llvm/test/Transforms/InstCombine/demorgan.ll

;
   %cond = xor i32 %zext, 1
   ret i32 %cond
 }
 
 define i32 @PR28476_logical(i32 %x, i32 %y) {
 ; CHECK-LABEL: @PR28476_logical(
 ; CHECK-NEXT:    [[CMP0:%.*]] = icmp eq i32 [[X:%.*]], 0
 ; CHECK-NEXT:    [[CMP1:%.*]] = icmp eq i32 [[Y:%.*]], 0
-; CHECK-NEXT:    [[TMP1:%.*]] = or i1 [[CMP0]], [[CMP1]]
-; CHECK-NEXT:    [[COND:%.*]] = zext i1 [[TMP1]] to i32
+; CHECK-NEXT:    [[AND:%.*]] = select i1 [[CMP0]], i1 true, i1 [[CMP1]]
+; CHECK-NEXT:    [[COND:%.*]] = zext i1 [[AND]] to i32
 ; CHECK-NEXT:    ret i32 [[COND]]
 ;
   %cmp0 = icmp ne i32 %x, 0
   %cmp1 = icmp ne i32 %y, 0
   %and = select i1 %cmp0, i1 %cmp1, i1 false
   %zext = zext i1 %and to i32
   %cond = xor i32 %zext, 1
   ret i32 %cond

llvm/test/Transforms/InstCombine/div-by-0-guard-before-smul_ov-not.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt %s -instcombine -S -instcombine-unsafe-select-transform=0 | FileCheck %s
+; RUN: opt %s -instcombine -S | FileCheck %s
 
 declare { i4, i1 } @llvm.smul.with.overflow.i4(i4, i4) #1
 
 define i1 @t0_umul(i4 %size, i4 %nmemb) {
 ; CHECK-LABEL: @t0_umul(
 ; CHECK-NEXT:    [[NMEMB_FR:%.*]] = freeze i4 [[NMEMB:%.*]]
 ; CHECK-NEXT:    [[SMUL:%.*]] = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 [[SIZE:%.*]], i4 [[NMEMB_FR]])
 ; CHECK-NEXT:    [[SMUL_OV:%.*]] = extractvalue { i4, i1 } [[SMUL]], 1

llvm/test/Transforms/InstCombine/div-by-0-guard-before-smul_ov.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt %s -instcombine -S -instcombine-unsafe-select-transform=0 | FileCheck %s
+; RUN: opt %s -instcombine -S | FileCheck %s
 
 declare { i4, i1 } @llvm.smul.with.overflow.i4(i4, i4) #1
 
 define i1 @t0_smul(i4 %size, i4 %nmemb) {
 ; CHECK-LABEL: @t0_smul(
 ; CHECK-NEXT:    [[SMUL:%.*]] = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 [[SIZE:%.*]], i4 [[NMEMB:%.*]])
 ; CHECK-NEXT:    [[SMUL_OV:%.*]] = extractvalue { i4, i1 } [[SMUL]], 1
 ; CHECK-NEXT:    ret i1 [[SMUL_OV]]

llvm/test/Transforms/InstCombine/div-by-0-guard-before-umul_ov-not.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt %s -instcombine -S -instcombine-unsafe-select-transform=0 | FileCheck %s
+; RUN: opt %s -instcombine -S | FileCheck %s
 
 declare { i4, i1 } @llvm.umul.with.overflow.i4(i4, i4) #1
 
 define i1 @t0_umul(i4 %size, i4 %nmemb) {
 ; CHECK-LABEL: @t0_umul(
 ; CHECK-NEXT:    [[NMEMB_FR:%.*]] = freeze i4 [[NMEMB:%.*]]
 ; CHECK-NEXT:    [[UMUL:%.*]] = tail call { i4, i1 } @llvm.umul.with.overflow.i4(i4 [[SIZE:%.*]], i4 [[NMEMB_FR]])
 ; CHECK-NEXT:    [[UMUL_OV:%.*]] = extractvalue { i4, i1 } [[UMUL]], 1

llvm/test/Transforms/InstCombine/div-by-0-guard-before-umul_ov.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt %s -instcombine -S -instcombine-unsafe-select-transform=0 | FileCheck %s
+; RUN: opt %s -instcombine -S | FileCheck %s
 
 declare { i4, i1 } @llvm.umul.with.overflow.i4(i4, i4) #1
 
 define i1 @t0_umul(i4 %size, i4 %nmemb) {
 ; CHECK-LABEL: @t0_umul(
 ; CHECK-NEXT:    [[UMUL:%.*]] = tail call { i4, i1 } @llvm.umul.with.overflow.i4(i4 [[SIZE:%.*]], i4 [[NMEMB:%.*]])
 ; CHECK-NEXT:    [[UMUL_OV:%.*]] = extractvalue { i4, i1 } [[UMUL]], 1
 ; CHECK-NEXT:    ret i1 [[UMUL_OV]]

llvm/test/Transforms/InstCombine/dont-distribute-phi.ll

 ; CHECK-NEXT:    call void @bar()
 ; CHECK-NEXT:    br label [[BB_EXIT:%.*]]
 ; CHECK:       bb_else:
 ; CHECK-NEXT:    [[CMP2:%.*]] = icmp slt i32 [[ARG]], 17
 ; CHECK-NEXT:    br label [[BB_EXIT]]
 ; CHECK:       bb_exit:
 ; CHECK-NEXT:    [[PHI1:%.*]] = phi i1 [ [[CMP2]], [[BB_ELSE]] ], [ undef, [[BB_THEN]] ]
 ; CHECK-NEXT:    [[XOR1:%.*]] = xor i1 [[CMP1]], true
-; CHECK-NEXT:    [[AND1:%.*]] = and i1 [[PHI1]], [[XOR1]]
+; CHECK-NEXT:    [[AND1:%.*]] = select i1 [[PHI1]], i1 [[XOR1]], i1 false
 ; CHECK-NEXT:    ret i1 [[AND1]]
 ;
 
 entry:
   %cmp1 = icmp eq i32 %arg, 37
   br i1 %cmp1, label %bb_then, label %bb_else
 
 bb_then:

llvm/test/Transforms/InstCombine/icmp.ll

;
   %1 = icmp eq i64 %b, 0
   %2 = icmp ult i64 %a, %b
   %3 = or i1 %1, %2
   ret i1 %3
 }
 
 define i1 @or_icmp_eq_B_0_icmp_ult_A_B_logical(i64 %a, i64 %b) {
 ; CHECK-LABEL: @or_icmp_eq_B_0_icmp_ult_A_B_logical(
-; CHECK-NEXT:    [[TMP1:%.*]] = add i64 [[B:%.*]], -1
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp uge i64 [[TMP1]], [[A:%.*]]
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq i64 [[B:%.*]], 0
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp ult i64 [[A:%.*]], [[B]]
+; CHECK-NEXT:    [[TMP3:%.*]] = select i1 [[TMP1]], i1 true, i1 [[TMP2]]
+; CHECK-NEXT:    ret i1 [[TMP3]]
 ;
   %1 = icmp eq i64 %b, 0
   %2 = icmp ult i64 %a, %b
   %3 = select i1 %1, i1 true, i1 %2
   ret i1 %3
 }
 
 define <2 x i1> @or_icmp_eq_B_0_icmp_ult_A_B_uniform(<2 x i64> %a, <2 x i64> %b) {
;
   %1 = icmp ne i64 %a, 0
   %2 = icmp ne i64 %b, 0
   %3 = or i1 %1, %2
   ret i1 %3
 }
 
 define i1 @or_icmp_ne_A_0_icmp_ne_B_0_logical(i64 %a, i64 %b) {
 ; CHECK-LABEL: @or_icmp_ne_A_0_icmp_ne_B_0_logical(
-; CHECK-NEXT:    [[TMP1:%.*]] = or i64 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp ne i64 [[TMP1]], 0
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp ne i64 [[A:%.*]], 0
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp ne i64 [[B:%.*]], 0
+; CHECK-NEXT:    [[TMP3:%.*]] = select i1 [[TMP1]], i1 true, i1 [[TMP2]]
+; CHECK-NEXT:    ret i1 [[TMP3]]
 ;
   %1 = icmp ne i64 %a, 0
   %2 = icmp ne i64 %b, 0
   %3 = select i1 %1, i1 true, i1 %2
   ret i1 %3
 }
 
 define <2 x i1> @or_icmp_ne_A_0_icmp_ne_B_0_uniform(<2 x i64> %a, <2 x i64> %b) {

llvm/test/Transforms/InstCombine/logical-select-inseltpoison.ll

;
   %and1 = and i1 %not, %a
   %and2 = and i1 %c, %b
   %or = or i1 %and1, %and2
   ret i1 %or
 }
 
 define i1 @bools_logical(i1 %a, i1 %b, i1 %c) {
 ; CHECK-LABEL: @bools_logical(
-; CHECK-NEXT:    [[TMP1:%.*]] = select i1 [[C:%.*]], i1 [[B:%.*]], i1 [[A:%.*]]
-; CHECK-NEXT:    ret i1 [[TMP1]]
+; CHECK-NEXT:    [[OR:%.*]] = select i1 [[C:%.*]], i1 [[B:%.*]], i1 [[A:%.*]]
+; CHECK-NEXT:    ret i1 [[OR]]
 ;
   %not = xor i1 %c, -1
   %and1 = select i1 %not, i1 %a, i1 false
   %and2 = select i1 %c, i1 %b, i1 false
   %or = select i1 %and1, i1 true, i1 %and2
   ret i1 %or
 }
 
;
   %or = or i1 %and1, %and2
   %xor = xor i1 %or, %and1
   ret i1 %xor
 }
 
 define i1 @bools_multi_uses1_logical(i1 %a, i1 %b, i1 %c) {
 ; CHECK-LABEL: @bools_multi_uses1_logical(
 ; CHECK-NEXT:    [[NOT:%.*]] = xor i1 [[C:%.*]], true
-; CHECK-NEXT:    [[AND1:%.*]] = and i1 [[NOT]], [[A:%.*]]
-; CHECK-NEXT:    [[TMP1:%.*]] = select i1 [[C]], i1 [[B:%.*]], i1 [[A]]
-; CHECK-NEXT:    [[XOR:%.*]] = xor i1 [[TMP1]], [[AND1]]
+; CHECK-NEXT:    [[AND1:%.*]] = select i1 [[NOT]], i1 [[A:%.*]], i1 false
+; CHECK-NEXT:    [[OR:%.*]] = select i1 [[C]], i1 [[B:%.*]], i1 [[A]]
+; CHECK-NEXT:    [[XOR:%.*]] = xor i1 [[OR]], [[AND1]]
 ; CHECK-NEXT:    ret i1 [[XOR]]
 ;
   %not = xor i1 %c, -1
   %and1 = select i1 %not, i1 %a, i1 false
   %and2 = select i1 %c, i1 %b, i1 false
   %or = select i1 %and1, i1 true, i1 %and2
   %xor = xor i1 %or, %and1
   ret i1 %xor
;
   %or = or i1 %and1, %and2
   %add = add i1 %and1, %and2
   %and3 = and i1 %or, %add
   ret i1 %and3
 }
 
 define i1 @bools_multi_uses2_logical(i1 %a, i1 %b, i1 %c) {
 ; CHECK-LABEL: @bools_multi_uses2_logical(
-; CHECK-NEXT:    [[TMP1:%.*]] = select i1 [[C:%.*]], i1 [[B:%.*]], i1 [[A:%.*]]
-; CHECK-NEXT:    ret i1 [[TMP1]]
+; CHECK-NEXT:    [[NOT:%.*]] = xor i1 [[C:%.*]], true
+; CHECK-NEXT:    [[AND1:%.*]] = select i1 [[NOT]], i1 [[A:%.*]], i1 false
+; CHECK-NEXT:    [[AND2:%.*]] = select i1 [[C]], i1 [[B:%.*]], i1 false
+; CHECK-NEXT:    [[OR:%.*]] = select i1 [[C]], i1 [[B]], i1 [[A]]
+; CHECK-NEXT:    [[ADD:%.*]] = xor i1 [[AND1]], [[AND2]]
+; CHECK-NEXT:    [[AND3:%.*]] = select i1 [[OR]], i1 [[ADD]], i1 false
+; CHECK-NEXT:    ret i1 [[AND3]]
 ;
   %not = xor i1 %c, -1
   %and1 = select i1 %not, i1 %a, i1 false
   %and2 = select i1 %c, i1 %b, i1 false
   %or = select i1 %and1, i1 true, i1 %and2
   %add = add i1 %and1, %and2
   %and3 = select i1 %or, i1 %add, i1 false
   ret i1 %and3

llvm/test/Transforms/InstCombine/logical-select.ll

;
   %and1 = and i1 %not, %a
   %and2 = and i1 %c, %b
   %or = or i1 %and1, %and2
   ret i1 %or
 }
 
 define i1 @bools_logical(i1 %a, i1 %b, i1 %c) {
 ; CHECK-LABEL: @bools_logical(
-; CHECK-NEXT:    [[TMP1:%.*]] = select i1 [[C:%.*]], i1 [[B:%.*]], i1 [[A:%.*]]
-; CHECK-NEXT:    ret i1 [[TMP1]]
+; CHECK-NEXT:    [[OR:%.*]] = select i1 [[C:%.*]], i1 [[B:%.*]], i1 [[A:%.*]]
+; CHECK-NEXT:    ret i1 [[OR]]
 ;
   %not = xor i1 %c, -1
   %and1 = select i1 %not, i1 %a, i1 false
   %and2 = select i1 %c, i1 %b, i1 false
   %or = select i1 %and1, i1 true, i1 %and2
   ret i1 %or
 }
 
 ; Form a select if we know we can get replace 2 simple logic ops.
 
 define i1 @bools_multi_uses1(i1 %a, i1 %b, i1 %c) {
;
   %or = or i1 %and1, %and2
   %xor = xor i1 %or, %and1
   ret i1 %xor
 }
 
 define i1 @bools_multi_uses1_logical(i1 %a, i1 %b, i1 %c) {
 ; CHECK-LABEL: @bools_multi_uses1_logical(
 ; CHECK-NEXT:    [[NOT:%.*]] = xor i1 [[C:%.*]], true
-; CHECK-NEXT:    [[AND1:%.*]] = and i1 [[NOT]], [[A:%.*]]
-; CHECK-NEXT:    [[TMP1:%.*]] = select i1 [[C]], i1 [[B:%.*]], i1 [[A]]
-; CHECK-NEXT:    [[XOR:%.*]] = xor i1 [[TMP1]], [[AND1]]
+; CHECK-NEXT:    [[AND1:%.*]] = select i1 [[NOT]], i1 [[A:%.*]], i1 false
+; CHECK-NEXT:    [[OR:%.*]] = select i1 [[C]], i1 [[B:%.*]], i1 [[A]]
+; CHECK-NEXT:    [[XOR:%.*]] = xor i1 [[OR]], [[AND1]]
 ; CHECK-NEXT:    ret i1 [[XOR]]
 ;
   %not = xor i1 %c, -1
   %and1 = select i1 %not, i1 %a, i1 false
   %and2 = select i1 %c, i1 %b, i1 false
   %or = select i1 %and1, i1 true, i1 %and2
   %xor = xor i1 %or, %and1
   ret i1 %xor
;
   %or = or i1 %and1, %and2
   %add = add i1 %and1, %and2
   %and3 = and i1 %or, %add
   ret i1 %and3
 }
 
 define i1 @bools_multi_uses2_logical(i1 %a, i1 %b, i1 %c) {
 ; CHECK-LABEL: @bools_multi_uses2_logical(
-; CHECK-NEXT:    [[TMP1:%.*]] = select i1 [[C:%.*]], i1 [[B:%.*]], i1 [[A:%.*]]
-; CHECK-NEXT:    ret i1 [[TMP1]]
+; CHECK-NEXT:    [[NOT:%.*]] = xor i1 [[C:%.*]], true
+; CHECK-NEXT:    [[AND1:%.*]] = select i1 [[NOT]], i1 [[A:%.*]], i1 false
+; CHECK-NEXT:    [[AND2:%.*]] = select i1 [[C]], i1 [[B:%.*]], i1 false
+; CHECK-NEXT:    [[OR:%.*]] = select i1 [[C]], i1 [[B]], i1 [[A]]
+; CHECK-NEXT:    [[ADD:%.*]] = xor i1 [[AND1]], [[AND2]]
+; CHECK-NEXT:    [[AND3:%.*]] = select i1 [[OR]], i1 [[ADD]], i1 false
+; CHECK-NEXT:    ret i1 [[AND3]]
 ;
   %not = xor i1 %c, -1
   %and1 = select i1 %not, i1 %a, i1 false
   %and2 = select i1 %c, i1 %b, i1 false
   %or = select i1 %and1, i1 true, i1 %and2
   %add = add i1 %and1, %and2
   %and3 = select i1 %or, i1 %add, i1 false
   ret i1 %and3

llvm/test/Transforms/InstCombine/onehot_merge.ll

;
   %or = or i1 %t2, %t6
   ret i1 %or
 }
 
 define i1 @foo1_and_logical(i32 %k, i32 %c1, i32 %c2) {
 ; CHECK-LABEL: @foo1_and_logical(
 ; CHECK-NEXT:    [[T:%.*]] = shl i32 1, [[C1:%.*]]
 ; CHECK-NEXT:    [[T4:%.*]] = shl i32 1, [[C2:%.*]]
-; CHECK-NEXT:    [[TMP1:%.*]] = or i32 [[T]], [[T4]]
-; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], [[K:%.*]]
-; CHECK-NEXT:    [[TMP3:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]]
-; CHECK-NEXT:    ret i1 [[TMP3]]
+; CHECK-NEXT:    [[T1:%.*]] = and i32 [[T]], [[K:%.*]]
+; CHECK-NEXT:    [[T2:%.*]] = icmp eq i32 [[T1]], 0
+; CHECK-NEXT:    [[T5:%.*]] = and i32 [[T4]], [[K]]
+; CHECK-NEXT:    [[T6:%.*]] = icmp eq i32 [[T5]], 0
+; CHECK-NEXT:    [[OR:%.*]] = select i1 [[T2]], i1 true, i1 [[T6]]
+; CHECK-NEXT:    ret i1 [[OR]]
 ;
   %t = shl i32 1, %c1
   %t4 = shl i32 1, %c2
   %t1 = and i32 %t, %k
   %t2 = icmp eq i32 %t1, 0
   %t5 = and i32 %t4, %k
   %t6 = icmp eq i32 %t5, 0
   %or = select i1 %t2, i1 true, i1 %t6
;
   ret i1 %or
 }
 
 define i1 @foo1_and_commuted_logical(i32 %k, i32 %c1, i32 %c2) {
 ; CHECK-LABEL: @foo1_and_commuted_logical(
 ; CHECK-NEXT:    [[K2:%.*]] = mul i32 [[K:%.*]], [[K]]
 ; CHECK-NEXT:    [[T:%.*]] = shl i32 1, [[C1:%.*]]
 ; CHECK-NEXT:    [[T4:%.*]] = shl i32 1, [[C2:%.*]]
-; CHECK-NEXT:    [[TMP1:%.*]] = or i32 [[T]], [[T4]]
-; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[K2]], [[TMP1]]
-; CHECK-NEXT:    [[TMP3:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]]
-; CHECK-NEXT:    ret i1 [[TMP3]]
+; CHECK-NEXT:    [[T1:%.*]] = and i32 [[K2]], [[T]]
+; CHECK-NEXT:    [[T2:%.*]] = icmp eq i32 [[T1]], 0
+; CHECK-NEXT:    [[T5:%.*]] = and i32 [[T4]], [[K2]]
+; CHECK-NEXT:    [[T6:%.*]] = icmp eq i32 [[T5]], 0
+; CHECK-NEXT:    [[OR:%.*]] = select i1 [[T2]], i1 true, i1 [[T6]]
+; CHECK-NEXT:    ret i1 [[OR]]
 ;
   %k2 = mul i32 %k, %k ; to trick the complexity sorting
   %t = shl i32 1, %c1
   %t4 = shl i32 1, %c2
   %t1 = and i32 %k2, %t
   %t2 = icmp eq i32 %t1, 0
   %t5 = and i32 %t4, %k2
   %t6 = icmp eq i32 %t5, 0
;
   %or = and i1 %t2, %t6
   ret i1 %or
 }
 
 define i1 @foo1_or_logical(i32 %k, i32 %c1, i32 %c2) {
 ; CHECK-LABEL: @foo1_or_logical(
 ; CHECK-NEXT:    [[T:%.*]] = shl i32 1, [[C1:%.*]]
 ; CHECK-NEXT:    [[T4:%.*]] = shl i32 1, [[C2:%.*]]
-; CHECK-NEXT:    [[TMP1:%.*]] = or i32 [[T]], [[T4]]
-; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], [[K:%.*]]
-; CHECK-NEXT:    [[TMP3:%.*]] = icmp eq i32 [[TMP2]], [[TMP1]]
-; CHECK-NEXT:    ret i1 [[TMP3]]
+; CHECK-NEXT:    [[T1:%.*]] = and i32 [[T]], [[K:%.*]]
+; CHECK-NEXT:    [[T2:%.*]] = icmp ne i32 [[T1]], 0
+; CHECK-NEXT:    [[T5:%.*]] = and i32 [[T4]], [[K]]
+; CHECK-NEXT:    [[T6:%.*]] = icmp ne i32 [[T5]], 0
+; CHECK-NEXT:    [[OR:%.*]] = select i1 [[T2]], i1 [[T6]], i1 false
+; CHECK-NEXT:    ret i1 [[OR]]
 ;
   %t = shl i32 1, %c1
   %t4 = shl i32 1, %c2
   %t1 = and i32 %t, %k
   %t2 = icmp ne i32 %t1, 0
   %t5 = and i32 %t4, %k
   %t6 = icmp ne i32 %t5, 0
   %or = select i1 %t2, i1 %t6, i1 false
;
   ret i1 %or
 }
 
 define i1 @foo1_or_commuted_logical(i32 %k, i32 %c1, i32 %c2) {
 ; CHECK-LABEL: @foo1_or_commuted_logical(
 ; CHECK-NEXT:    [[K2:%.*]] = mul i32 [[K:%.*]], [[K]]
 ; CHECK-NEXT:    [[T:%.*]] = shl i32 1, [[C1:%.*]]
 ; CHECK-NEXT:    [[T4:%.*]] = shl i32 1, [[C2:%.*]]
-; CHECK-NEXT:    [[TMP1:%.*]] = or i32 [[T]], [[T4]]
-; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[K2]], [[TMP1]]
-; CHECK-NEXT:    [[TMP3:%.*]] = icmp eq i32 [[TMP2]], [[TMP1]]
-; CHECK-NEXT:    ret i1 [[TMP3]]
+; CHECK-NEXT:    [[T1:%.*]] = and i32 [[K2]], [[T]]
+; CHECK-NEXT:    [[T2:%.*]] = icmp ne i32 [[T1]], 0
+; CHECK-NEXT:    [[T5:%.*]] = and i32 [[T4]], [[K2]]
+; CHECK-NEXT:    [[T6:%.*]] = icmp ne i32 [[T5]], 0
+; CHECK-NEXT:    [[OR:%.*]] = select i1 [[T2]], i1 [[T6]], i1 false
+; CHECK-NEXT:    ret i1 [[OR]]
 ;
   %k2 = mul i32 %k, %k ; to trick the complexity sorting
   %t = shl i32 1, %c1
   %t4 = shl i32 1, %c2
   %t1 = and i32 %k2, %t
   %t2 = icmp ne i32 %t1, 0
   %t5 = and i32 %t4, %k2
   %t6 = icmp ne i32 %t5, 0
;
   %or = or i1 %t2, %t6
   ret i1 %or
 }
 
 define i1 @foo1_and_signbit_lshr_logical(i32 %k, i32 %c1, i32 %c2) {
 ; CHECK-LABEL: @foo1_and_signbit_lshr_logical(
 ; CHECK-NEXT:    [[T:%.*]] = shl i32 1, [[C1:%.*]]
 ; CHECK-NEXT:    [[T4:%.*]] = lshr i32 -2147483648, [[C2:%.*]]
-; CHECK-NEXT:    [[TMP1:%.*]] = or i32 [[T]], [[T4]]
-; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], [[K:%.*]]
-; CHECK-NEXT:    [[TMP3:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]]
-; CHECK-NEXT:    ret i1 [[TMP3]]
+; CHECK-NEXT:    [[T1:%.*]] = and i32 [[T]], [[K:%.*]]
+; CHECK-NEXT:    [[T2:%.*]] = icmp eq i32 [[T1]], 0
+; CHECK-NEXT:    [[T5:%.*]] = and i32 [[T4]], [[K]]
+; CHECK-NEXT:    [[T6:%.*]] = icmp eq i32 [[T5]], 0
+; CHECK-NEXT:    [[OR:%.*]] = select i1 [[T2]], i1 true, i1 [[T6]]
+; CHECK-NEXT:    ret i1 [[OR]]
 ;
   %t = shl i32 1, %c1
   %t4 = lshr i32 -2147483648, %c2
   %t1 = and i32 %t, %k
   %t2 = icmp eq i32 %t1, 0
   %t5 = and i32 %t4, %k
   %t6 = icmp eq i32 %t5, 0
   %or = select i1 %t2, i1 true, i1 %t6
;
   %or = and i1 %t2, %t6
   ret i1 %or
 }
 
 define i1 @foo1_or_signbit_lshr_logical(i32 %k, i32 %c1, i32 %c2) {
 ; CHECK-LABEL: @foo1_or_signbit_lshr_logical(
 ; CHECK-NEXT:    [[T:%.*]] = shl i32 1, [[C1:%.*]]
 ; CHECK-NEXT:    [[T4:%.*]] = lshr i32 -2147483648, [[C2:%.*]]
-; CHECK-NEXT:    [[TMP1:%.*]] = or i32 [[T]], [[T4]]
-; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], [[K:%.*]]
-; CHECK-NEXT:    [[TMP3:%.*]] = icmp eq i32 [[TMP2]], [[TMP1]]
-; CHECK-NEXT:    ret i1 [[TMP3]]
+; CHECK-NEXT:    [[T1:%.*]] = and i32 [[T]], [[K:%.*]]
+; CHECK-NEXT:    [[T2:%.*]] = icmp ne i32 [[T1]], 0
+; CHECK-NEXT:    [[T5:%.*]] = and i32 [[T4]], [[K]]
+; CHECK-NEXT:    [[T6:%.*]] = icmp ne i32 [[T5]], 0
+; CHECK-NEXT:    [[OR:%.*]] = select i1 [[T2]], i1 [[T6]], i1 false
+; CHECK-NEXT:    ret i1 [[OR]]
 ;
   %t = shl i32 1, %c1
   %t4 = lshr i32 -2147483648, %c2
   %t1 = and i32 %t, %k
   %t2 = icmp ne i32 %t1, 0
   %t5 = and i32 %t4, %k
   %t6 = icmp ne i32 %t5, 0
   %or = select i1 %t2, i1 %t6, i1 false
;
   ret i1 %or
 }
 
 define i1 @foo1_and_extra_use_shl_logical(i32 %k, i32 %c1, i32 %c2, i32* %p) {
 ; CHECK-LABEL: @foo1_and_extra_use_shl_logical(
 ; CHECK-NEXT:    [[T0:%.*]] = shl i32 1, [[C1:%.*]]
 ; CHECK-NEXT:    store i32 [[T0]], i32* [[P:%.*]], align 4
 ; CHECK-NEXT:    [[T1:%.*]] = shl i32 1, [[C2:%.*]]
-; CHECK-NEXT:    [[TMP1:%.*]] = or i32 [[T0]], [[T1]]
-; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], [[K:%.*]]
-; CHECK-NEXT:    [[TMP3:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]]
-; CHECK-NEXT:    ret i1 [[TMP3]]
+; CHECK-NEXT:    [[T2:%.*]] = and i32 [[T0]], [[K:%.*]]
+; CHECK-NEXT:    [[T3:%.*]] = icmp eq i32 [[T2]], 0
+; CHECK-NEXT:    [[T4:%.*]] = and i32 [[T1]], [[K]]
+; CHECK-NEXT:    [[T5:%.*]] = icmp eq i32 [[T4]], 0
+; CHECK-NEXT:    [[OR:%.*]] = select i1 [[T3]], i1 true, i1 [[T5]]
+; CHECK-NEXT:    ret i1 [[OR]]
 ;
   %t0 = shl i32 1, %c1
   store i32 %t0, i32* %p  ; extra use of shl
   %t1 = shl i32 1, %c2
   %t2 = and i32 %t0, %k
   %t3 = icmp eq i32 %t2, 0
   %t4 = and i32 %t1, %k
   %t5 = icmp eq i32 %t4, 0

 }
 
 define i1 @foo1_and_extra_use_and_logical(i32 %k, i32 %c1, i32 %c2, i32* %p) {
 ; CHECK-LABEL: @foo1_and_extra_use_and_logical(
 ; CHECK-NEXT:    [[T0:%.*]] = shl i32 1, [[C1:%.*]]
 ; CHECK-NEXT:    [[T1:%.*]] = shl i32 1, [[C2:%.*]]
 ; CHECK-NEXT:    [[T2:%.*]] = and i32 [[T0]], [[K:%.*]]
 ; CHECK-NEXT:    store i32 [[T2]], i32* [[P:%.*]], align 4
-; CHECK-NEXT:    [[TMP1:%.*]] = or i32 [[T0]], [[T1]]
-; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], [[K]]
-; CHECK-NEXT:    [[TMP3:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]]
-; CHECK-NEXT:    ret i1 [[TMP3]]
+; CHECK-NEXT:    [[T3:%.*]] = icmp eq i32 [[T2]], 0
+; CHECK-NEXT:    [[T4:%.*]] = and i32 [[T1]], [[K]]
+; CHECK-NEXT:    [[T5:%.*]] = icmp eq i32 [[T4]], 0
+; CHECK-NEXT:    [[OR:%.*]] = select i1 [[T3]], i1 true, i1 [[T5]]
+; CHECK-NEXT:    ret i1 [[OR]]
 ;
   %t0 = shl i32 1, %c1
   %t1 = shl i32 1, %c2
   %t2 = and i32 %t0, %k
   store i32 %t2, i32* %p  ; extra use of and
   %t3 = icmp eq i32 %t2, 0
   %t4 = and i32 %t1, %k
   %t5 = icmp eq i32 %t4, 0

 
 define i1 @foo1_and_extra_use_cmp_logical(i32 %k, i32 %c1, i32 %c2, i1* %p) {
 ; CHECK-LABEL: @foo1_and_extra_use_cmp_logical(
 ; CHECK-NEXT:    [[T0:%.*]] = shl i32 1, [[C1:%.*]]
 ; CHECK-NEXT:    [[T1:%.*]] = shl i32 1, [[C2:%.*]]
 ; CHECK-NEXT:    [[T2:%.*]] = and i32 [[T0]], [[K:%.*]]
 ; CHECK-NEXT:    [[T3:%.*]] = icmp eq i32 [[T2]], 0
 ; CHECK-NEXT:    store i1 [[T3]], i1* [[P:%.*]], align 1
-; CHECK-NEXT:    [[TMP1:%.*]] = or i32 [[T0]], [[T1]]
-; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], [[K]]
-; CHECK-NEXT:    [[TMP3:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]]
-; CHECK-NEXT:    ret i1 [[TMP3]]
+; CHECK-NEXT:    [[T4:%.*]] = and i32 [[T1]], [[K]]
+; CHECK-NEXT:    [[T5:%.*]] = icmp eq i32 [[T4]], 0
+; CHECK-NEXT:    [[OR:%.*]] = select i1 [[T3]], i1 true, i1 [[T5]]
+; CHECK-NEXT:    ret i1 [[OR]]
 ;
   %t0 = shl i32 1, %c1
   %t1 = shl i32 1, %c2
   %t2 = and i32 %t0, %k
   %t3 = icmp eq i32 %t2, 0
   store i1 %t3, i1* %p  ; extra use of cmp
   %t4 = and i32 %t1, %k
   %t5 = icmp eq i32 %t4, 0
;
   ret i1 %or
 }
 
 define i1 @foo1_and_extra_use_shl2_logical(i32 %k, i32 %c1, i32 %c2, i32* %p) {
 ; CHECK-LABEL: @foo1_and_extra_use_shl2_logical(
 ; CHECK-NEXT:    [[T0:%.*]] = shl i32 1, [[C1:%.*]]
 ; CHECK-NEXT:    [[T1:%.*]] = shl i32 1, [[C2:%.*]]
 ; CHECK-NEXT:    store i32 [[T1]], i32* [[P:%.*]], align 4
-; CHECK-NEXT:    [[TMP1:%.*]] = or i32 [[T0]], [[T1]]
-; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], [[K:%.*]]
-; CHECK-NEXT:    [[TMP3:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]]
-; CHECK-NEXT:    ret i1 [[TMP3]]
+; CHECK-NEXT:    [[T2:%.*]] = and i32 [[T0]], [[K:%.*]]
+; CHECK-NEXT:    [[T3:%.*]] = icmp eq i32 [[T2]], 0
+; CHECK-NEXT:    [[T4:%.*]] = and i32 [[T1]], [[K]]
+; CHECK-NEXT:    [[T5:%.*]] = icmp eq i32 [[T4]], 0
+; CHECK-NEXT:    [[OR:%.*]] = select i1 [[T3]], i1 true, i1 [[T5]]
+; CHECK-NEXT:    ret i1 [[OR]]
 ;
   %t0 = shl i32 1, %c1
   %t1 = shl i32 1, %c2
   store i32 %t1, i32* %p  ; extra use of shl
   %t2 = and i32 %t0, %k
   %t3 = icmp eq i32 %t2, 0
   %t4 = and i32 %t1, %k
   %t5 = icmp eq i32 %t4, 0
;
   %or = or i1 %t3, %t5
   ret i1 %or
 }
 
 define i1 @foo1_and_extra_use_and2_logical(i32 %k, i32 %c1, i32 %c2, i32* %p) {
 ; CHECK-LABEL: @foo1_and_extra_use_and2_logical(
 ; CHECK-NEXT:    [[T0:%.*]] = shl i32 1, [[C1:%.*]]
 ; CHECK-NEXT:    [[T1:%.*]] = shl i32 1, [[C2:%.*]]
-; CHECK-NEXT:    [[T4:%.*]] = and i32 [[T1]], [[K:%.*]]
+; CHECK-NEXT:    [[T2:%.*]] = and i32 [[T0]], [[K:%.*]]
+; CHECK-NEXT:    [[T3:%.*]] = icmp eq i32 [[T2]], 0
+; CHECK-NEXT:    [[T4:%.*]] = and i32 [[T1]], [[K]]
 ; CHECK-NEXT:    store i32 [[T4]], i32* [[P:%.*]], align 4
-; CHECK-NEXT:    [[TMP1:%.*]] = or i32 [[T0]], [[T1]]
-; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], [[K]]
-; CHECK-NEXT:    [[TMP3:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]]
-; CHECK-NEXT:    ret i1 [[TMP3]]
+; CHECK-NEXT:    [[T5:%.*]] = icmp eq i32 [[T4]], 0
+; CHECK-NEXT:    [[OR:%.*]] = select i1 [[T3]], i1 true, i1 [[T5]]
+; CHECK-NEXT:    ret i1 [[OR]]
 ;
   %t0 = shl i32 1, %c1
   %t1 = shl i32 1, %c2
   %t2 = and i32 %t0, %k
   %t3 = icmp eq i32 %t2, 0
   %t4 = and i32 %t1, %k
   store i32 %t4, i32* %p  ; extra use of and
   %t5 = icmp eq i32 %t4, 0
;
   %or = or i1 %t3, %t5
   ret i1 %or
 }
 
 define i1 @foo1_and_extra_use_cmp2_logical(i32 %k, i32 %c1, i32 %c2, i1* %p) {
 ; CHECK-LABEL: @foo1_and_extra_use_cmp2_logical(
 ; CHECK-NEXT:    [[T0:%.*]] = shl i32 1, [[C1:%.*]]
 ; CHECK-NEXT:    [[T1:%.*]] = shl i32 1, [[C2:%.*]]
-; CHECK-NEXT:    [[T4:%.*]] = and i32 [[T1]], [[K:%.*]]
+; CHECK-NEXT:    [[T2:%.*]] = and i32 [[T0]], [[K:%.*]]
+; CHECK-NEXT:    [[T3:%.*]] = icmp eq i32 [[T2]], 0
+; CHECK-NEXT:    [[T4:%.*]] = and i32 [[T1]], [[K]]
 ; CHECK-NEXT:    [[T5:%.*]] = icmp eq i32 [[T4]], 0
 ; CHECK-NEXT:    store i1 [[T5]], i1* [[P:%.*]], align 1
-; CHECK-NEXT:    [[TMP1:%.*]] = or i32 [[T0]], [[T1]]
-; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], [[K]]
-; CHECK-NEXT:    [[TMP3:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]]
-; CHECK-NEXT:    ret i1 [[TMP3]]
+; CHECK-NEXT:    [[OR:%.*]] = select i1 [[T3]], i1 true, i1 [[T5]]
+; CHECK-NEXT:    ret i1 [[OR]]
 ;
   %t0 = shl i32 1, %c1
   %t1 = shl i32 1, %c2
   %t2 = and i32 %t0, %k
   %t3 = icmp eq i32 %t2, 0
   %t4 = and i32 %t1, %k
   %t5 = icmp eq i32 %t4, 0
   store i1 %t5, i1* %p  ; extra use of cmp

llvm/test/Transforms/InstCombine/or-fcmp.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -instcombine -S | FileCheck %s
 
 define i1 @PR1738(double %x, double %y) {
 ; CHECK-LABEL: @PR1738(
 ; CHECK-NEXT:    [[TMP1:%.*]] = fcmp uno double [[X:%.*]], [[Y:%.*]]
 ; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
   %cmp1 = fcmp uno double %x, 0.0
   %cmp2 = fcmp uno double %y, 0.0
   %or = or i1 %cmp1, %cmp2
   ret i1 %or
 }
 
+; TODO: this can be fixed by freezing %y
 define i1 @PR1738_logical(double %x, double %y) {
 ; CHECK-LABEL: @PR1738_logical(
-; CHECK-NEXT:    [[TMP1:%.*]] = fcmp uno double [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT:    ret i1 [[TMP1]]
+; CHECK-NEXT:    [[CMP1:%.*]] = fcmp uno double [[X:%.*]], 0.000000e+00
+; CHECK-NEXT:    [[CMP2:%.*]] = fcmp uno double [[Y:%.*]], 0.000000e+00
+; CHECK-NEXT:    [[OR:%.*]] = select i1 [[CMP1]], i1 true, i1 [[CMP2]]
+; CHECK-NEXT:    ret i1 [[OR]]
 ;
   %cmp1 = fcmp uno double %x, 0.0
   %cmp2 = fcmp uno double %y, 0.0
   %or = select i1 %cmp1, i1 true, i1 %cmp2
   ret i1 %or
 }
 
 define <2 x i1> @PR1738_vec_undef(<2 x double> %x, <2 x double> %y) {
;
   %uno1 = fcmp uno double %a, %b
   %uno2 = fcmp uno double %c, 0.0
   %or = or i1 %uno1, %uno2
   %uno3 = fcmp uno double %d, 0.0
   %r = or i1 %or, %uno3
   ret i1 %r
 }
 
+; TODO: this can be fixed by freezing %c and %d
 define i1 @PR41069_logical(double %a, double %b, double %c, double %d) {
 ; CHECK-LABEL: @PR41069_logical(
 ; CHECK-NEXT:    [[UNO1:%.*]] = fcmp uno double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT:    [[TMP1:%.*]] = fcmp uno double [[D:%.*]], [[C:%.*]]
-; CHECK-NEXT:    [[R:%.*]] = or i1 [[TMP1]], [[UNO1]]
+; CHECK-NEXT:    [[UNO2:%.*]] = fcmp uno double [[C:%.*]], 0.000000e+00
+; CHECK-NEXT:    [[OR:%.*]] = select i1 [[UNO1]], i1 true, i1 [[UNO2]]
+; CHECK-NEXT:    [[UNO3:%.*]] = fcmp uno double [[D:%.*]], 0.000000e+00
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[OR]], i1 true, i1 [[UNO3]]
 ; CHECK-NEXT:    ret i1 [[R]]
 ;
   %uno1 = fcmp uno double %a, %b
   %uno2 = fcmp uno double %c, 0.0
   %or = select i1 %uno1, i1 true, i1 %uno2
   %uno3 = fcmp uno double %d, 0.0
   %r = select i1 %or, i1 true, i1 %uno3
   ret i1 %r
;
   %uno1 = fcmp uno double %a, %b
   %uno2 = fcmp uno double %c, 0.0
   %or = or i1 %uno1, %uno2
   %uno3 = fcmp uno double %d, 0.0
   %r = or i1 %uno3, %or
   ret i1 %r
 }
 
+; TODO: this can be fixed by freezing %c and %d
 define i1 @PR41069_commute_logical(double %a, double %b, double %c, double %d) {
 ; CHECK-LABEL: @PR41069_commute_logical(
 ; CHECK-NEXT:    [[UNO1:%.*]] = fcmp uno double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT:    [[TMP1:%.*]] = fcmp uno double [[D:%.*]], [[C:%.*]]
-; CHECK-NEXT:    [[R:%.*]] = or i1 [[TMP1]], [[UNO1]]
+; CHECK-NEXT:    [[UNO2:%.*]] = fcmp uno double [[C:%.*]], 0.000000e+00
+; CHECK-NEXT:    [[UNO3:%.*]] = fcmp uno double [[D:%.*]], 0.000000e+00
+; CHECK-NEXT:    [[TMP1:%.*]] = select i1 [[UNO3]], i1 true, i1 [[UNO1]]
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[TMP1]], i1 true, i1 [[UNO2]]
 ; CHECK-NEXT:    ret i1 [[R]]
 ;
   %uno1 = fcmp uno double %a, %b
   %uno2 = fcmp uno double %c, 0.0
   %or = select i1 %uno1, i1 true, i1 %uno2
   %uno3 = fcmp uno double %d, 0.0
   %r = select i1 %uno3, i1 true, i1 %or
   ret i1 %r

 ; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
   %cmp1 = fcmp uno float %x, 1.0
   %cmp2 = fcmp uno float %y, 2.0
   %or = or i1 %cmp1, %cmp2
   ret i1 %or
 }
 
+; TODO: this can be fixed by freezing %y
 define i1 @fcmp_uno_nonzero_logical(float %x, float %y) {
 ; CHECK-LABEL: @fcmp_uno_nonzero_logical(
-; CHECK-NEXT:    [[TMP1:%.*]] = fcmp uno float [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT:    ret i1 [[TMP1]]
+; CHECK-NEXT:    [[CMP1:%.*]] = fcmp uno float [[X:%.*]], 0.000000e+00
+; CHECK-NEXT:    [[CMP2:%.*]] = fcmp uno float [[Y:%.*]], 0.000000e+00
+; CHECK-NEXT:    [[OR:%.*]] = select i1 [[CMP1]], i1 true, i1 [[CMP2]]
+; CHECK-NEXT:    ret i1 [[OR]]
 ;
   %cmp1 = fcmp uno float %x, 1.0
   %cmp2 = fcmp uno float %y, 2.0
   %or = select i1 %cmp1, i1 true, i1 %cmp2
   ret i1 %or
 }
 
 define <3 x i1> @fcmp_uno_nonzero_vec(<3 x float> %x, <3 x float> %y) {

llvm/test/Transforms/InstCombine/or.ll

;
   %F = xor i1 %E, -1
   ret i1 %F
 }
 
 define i1 @test25_logical(i32 %A, i32 %B) {
 ; CHECK-LABEL: @test25_logical(
 ; CHECK-NEXT:    [[C:%.*]] = icmp ne i32 [[A:%.*]], 0
 ; CHECK-NEXT:    [[D:%.*]] = icmp ne i32 [[B:%.*]], 57
-; CHECK-NEXT:    [[F:%.*]] = and i1 [[C]], [[D]]
-; CHECK-NEXT:    ret i1 [[F]]
+; CHECK-NEXT:    [[E:%.*]] = select i1 [[C]], i1 [[D]], i1 false
+; CHECK-NEXT:    ret i1 [[E]]
 ;
   %C = icmp eq i32 %A, 0
   %D = icmp eq i32 %B, 57
   %E = select i1 %C, i1 true, i1 %D
   %F = xor i1 %E, -1
   ret i1 %F
 }
 
 ; PR5634
 define i1 @test26(i32 %A, i32 %B) {
 ; CHECK-LABEL: @test26(
 ; CHECK-NEXT:    [[TMP1:%.*]] = or i32 [[A:%.*]], [[B:%.*]]
 ; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 0
 ; CHECK-NEXT:    ret i1 [[TMP2]]
 ;
   %C1 = icmp eq i32 %A, 0
   %C2 = icmp eq i32 %B, 0
   ; (A == 0) & (A == 0)   -->   (A|B) == 0
   %D = and i1 %C1, %C2
   ret i1 %D
 }
 
 define i1 @test26_logical(i32 %A, i32 %B) {
 ; CHECK-LABEL: @test26_logical(
-; CHECK-NEXT:    [[TMP1:%.*]] = or i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 0
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[C1:%.*]] = icmp eq i32 [[A:%.*]], 0
+; CHECK-NEXT:    [[C2:%.*]] = icmp eq i32 [[B:%.*]], 0
+; CHECK-NEXT:    [[D:%.*]] = select i1 [[C1]], i1 [[C2]], i1 false
+; CHECK-NEXT:    ret i1 [[D]]
 ;
   %C1 = icmp eq i32 %A, 0
   %C2 = icmp eq i32 %B, 0
   ; (A == 0) & (A == 0)   -->   (A|B) == 0
   %D = select i1 %C1, i1 %C2, i1 false
   ret i1 %D
 }
 
;
   %C2 = icmp ne i32 %B, 0
   ; (A != 0) | (A != 0)   -->   (A|B) != 0
   %D = or i1 %C1, %C2
   ret i1 %D
 }
 
 define i1 @test28_logical(i32 %A, i32 %B) {
 ; CHECK-LABEL: @test28_logical(
-; CHECK-NEXT:    [[TMP1:%.*]] = or i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[C1:%.*]] = icmp ne i32 [[A:%.*]], 0
+; CHECK-NEXT:    [[C2:%.*]] = icmp ne i32 [[B:%.*]], 0
+; CHECK-NEXT:    [[D:%.*]] = select i1 [[C1]], i1 true, i1 [[C2]]
+; CHECK-NEXT:    ret i1 [[D]]
 ;
   %C1 = icmp ne i32 %A, 0
   %C2 = icmp ne i32 %B, 0
   ; (A != 0) | (A != 0)   -->   (A|B) != 0
   %D = select i1 %C1, i1 true, i1 %C2
   ret i1 %D
 }
 

 ;
   %a = or i1 %X, %Y
   %b = or i1 %a, %X
   ret i1 %b
 }
 
 define i1 @test33_logical(i1 %X, i1 %Y) {
 ; CHECK-LABEL: @test33_logical(
-; CHECK-NEXT:    [[A:%.*]] = or i1 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[A:%.*]] = select i1 [[X:%.*]], i1 true, i1 [[Y:%.*]]
 ; CHECK-NEXT:    ret i1 [[A]]
 ;
   %a = select i1 %X, i1 true, i1 %Y
   %b = select i1 %a, i1 true, i1 %X
   ret i1 %b
 }
 
 define i32 @test34(i32 %X, i32 %Y) {
;
   %and = and i1 %y, %x_inv
   %or = or i1 %x, %and
   ret i1 %or
 }
 
 define i1 @or_andn_cmp_1_logical(i32 %a, i32 %b, i32 %c) {
 ; CHECK-LABEL: @or_andn_cmp_1_logical(
 ; CHECK-NEXT:    [[X:%.*]] = icmp sgt i32 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[X_INV:%.*]] = icmp sle i32 [[A]], [[B]]
 ; CHECK-NEXT:    [[Y:%.*]] = icmp ugt i32 [[C:%.*]], 42
-; CHECK-NEXT:    [[OR:%.*]] = or i1 [[X]], [[Y]]
+; CHECK-NEXT:    [[AND:%.*]] = select i1 [[Y]], i1 [[X_INV]], i1 false
+; CHECK-NEXT:    [[OR:%.*]] = select i1 [[X]], i1 true, i1 [[AND]]
 ; CHECK-NEXT:    ret i1 [[OR]]
 ;
   %x = icmp sgt i32 %a, %b
   %x_inv = icmp sle i32 %a, %b
   %y = icmp ugt i32 %c, 42      ; thwart complexity-based ordering
   %and = select i1 %y, i1 %x_inv, i1 false
   %or = select i1 %x, i1 true, i1 %and
   ret i1 %or
;
   %or = or i1 %x, %and
   ret i1 %or
 }
 
 define i1 @or_andn_cmp_3_logical(i72 %a, i72 %b, i72 %c) {
 ; CHECK-LABEL: @or_andn_cmp_3_logical(
 ; CHECK-NEXT:    [[X:%.*]] = icmp ugt i72 [[A:%.*]], [[B:%.*]]
 ; CHECK-NEXT:    [[Y:%.*]] = icmp ugt i72 [[C:%.*]], 42
-; CHECK-NEXT:    [[OR:%.*]] = or i1 [[X]], [[Y]]
+; CHECK-NEXT:    [[OR:%.*]] = select i1 [[X]], i1 true, i1 [[Y]]
 ; CHECK-NEXT:    ret i1 [[OR]]
 ;
   %x = icmp ugt i72 %a, %b
   %x_inv = icmp ule i72 %a, %b
   %y = icmp ugt i72 %c, 42      ; thwart complexity-based ordering
   %and = select i1 %x_inv, i1 %y, i1 false
   %or = select i1 %x, i1 true, i1 %and
   ret i1 %or
;
   %y = icmp ugt i37 %c, 42      ; thwart complexity-based ordering
   %and = and i1 %y, %x
   %or = or i1 %x_inv, %and
   ret i1 %or
 }
 
 define i1 @orn_and_cmp_1_logical(i37 %a, i37 %b, i37 %c) {
 ; CHECK-LABEL: @orn_and_cmp_1_logical(
-; CHECK-NEXT:    [[X_INV:%.*]] = icmp sle i37 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[X:%.*]] = icmp sgt i37 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[X_INV:%.*]] = icmp sle i37 [[A]], [[B]]
 ; CHECK-NEXT:    [[Y:%.*]] = icmp ugt i37 [[C:%.*]], 42
-; CHECK-NEXT:    [[OR:%.*]] = or i1 [[X_INV]], [[Y]]
+; CHECK-NEXT:    [[AND:%.*]] = select i1 [[Y]], i1 [[X]], i1 false
+; CHECK-NEXT:    [[OR:%.*]] = select i1 [[X_INV]], i1 true, i1 [[AND]]
 ; CHECK-NEXT:    ret i1 [[OR]]
 ;
   %x = icmp sgt i37 %a, %b
   %x_inv = icmp sle i37 %a, %b
   %y = icmp ugt i37 %c, 42      ; thwart complexity-based ordering
   %and = select i1 %y, i1 %x, i1 false
   %or = select i1 %x_inv, i1 true, i1 %and
   ret i1 %or
;
   %y = icmp ugt i16 %c, 42      ; thwart complexity-based ordering
   %and = and i1 %y, %x
   %or = or i1 %and, %x_inv
   ret i1 %or
 }
 
 define i1 @orn_and_cmp_2_logical(i16 %a, i16 %b, i16 %c) {
 ; CHECK-LABEL: @orn_and_cmp_2_logical(
-; CHECK-NEXT:    [[X_INV:%.*]] = icmp slt i16 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[X:%.*]] = icmp sge i16 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[X_INV:%.*]] = icmp slt i16 [[A]], [[B]]
 ; CHECK-NEXT:    [[Y:%.*]] = icmp ugt i16 [[C:%.*]], 42
-; CHECK-NEXT:    [[OR:%.*]] = or i1 [[Y]], [[X_INV]]
+; CHECK-NEXT:    [[AND:%.*]] = select i1 [[Y]], i1 [[X]], i1 false
+; CHECK-NEXT:    [[OR:%.*]] = select i1 [[AND]], i1 true, i1 [[X_INV]]
 ; CHECK-NEXT:    ret i1 [[OR]]
 ;
   %x = icmp sge i16 %a, %b
   %x_inv = icmp slt i16 %a, %b
   %y = icmp ugt i16 %c, 42      ; thwart complexity-based ordering
   %and = select i1 %y, i1 %x, i1 false
   %or = select i1 %and, i1 true, i1 %x_inv
   ret i1 %or
 }
 
;
   %or = or i1 %and, %x_inv
   ret i1 %or
 }
 
 define i1 @orn_and_cmp_4_logical(i32 %a, i32 %b, i32 %c) {
 ; CHECK-LABEL: @orn_and_cmp_4_logical(
 ; CHECK-NEXT:    [[X_INV:%.*]] = icmp ne i32 [[A:%.*]], [[B:%.*]]
 ; CHECK-NEXT:    [[Y:%.*]] = icmp ugt i32 [[C:%.*]], 42
-; CHECK-NEXT:    [[OR:%.*]] = or i1 [[Y]], [[X_INV]]
+; CHECK-NEXT:    [[OR:%.*]] = select i1 [[X_INV]], i1 true, i1 [[Y]]
 ; CHECK-NEXT:    ret i1 [[OR]]
 ;
   %x = icmp eq i32 %a, %b
   %x_inv = icmp ne i32 %a, %b
   %y = icmp ugt i32 %c, 42      ; thwart complexity-based ordering
   %and = select i1 %x, i1 %y, i1 false
   %or = select i1 %and, i1 true, i1 %x_inv
   ret i1 %or

llvm/test/Transforms/InstCombine/prevent-cmp-merge.ll

;
   ret i1 %sel
 }
 
 define zeroext i1 @test1_logical(i32 %lhs, i32 %rhs) {
 ; CHECK-LABEL: @test1_logical(
 ; CHECK-NEXT:    [[XOR:%.*]] = xor i32 [[LHS:%.*]], 5
 ; CHECK-NEXT:    [[CMP1:%.*]] = icmp eq i32 [[XOR]], 10
 ; CHECK-NEXT:    [[CMP2:%.*]] = icmp eq i32 [[XOR]], [[RHS:%.*]]
-; CHECK-NEXT:    [[SEL:%.*]] = or i1 [[CMP1]], [[CMP2]]
+; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP1]], i1 true, i1 [[CMP2]]
 ; CHECK-NEXT:    ret i1 [[SEL]]
 ;
 
   %xor = xor i32 %lhs, 5
   %cmp1 = icmp eq i32 %xor, 10
   %cmp2 = icmp eq i32 %xor, %rhs
   %sel = select i1 %cmp1, i1 true, i1 %cmp2
   ret i1 %sel

llvm/test/Transforms/InstCombine/range-check.ll

;
   %b = icmp slt i32 %x, %nn
   %c = and i1 %a, %b
   ret i1 %c
 }
 
 define i1 @test_and1_logical(i32 %x, i32 %n) {
 ; CHECK-LABEL: @test_and1_logical(
 ; CHECK-NEXT:    [[NN:%.*]] = and i32 [[N:%.*]], 2147483647
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp ugt i32 [[NN]], [[X:%.*]]
-; CHECK-NEXT:    ret i1 [[TMP1]]
+; CHECK-NEXT:    [[A:%.*]] = icmp sgt i32 [[X:%.*]], -1
+; CHECK-NEXT:    [[B:%.*]] = icmp sgt i32 [[NN]], [[X]]
+; CHECK-NEXT:    [[C:%.*]] = select i1 [[A]], i1 [[B]], i1 false
+; CHECK-NEXT:    ret i1 [[C]]
 ;
   %nn = and i32 %n, 2147483647
   %a = icmp sge i32 %x, 0
   %b = icmp slt i32 %x, %nn
   %c = select i1 %a, i1 %b, i1 false
   ret i1 %c
 }
 
 define i1 @test_and2(i32 %x, i32 %n) {
 ; CHECK-LABEL: @test_and2(
 ; CHECK-NEXT:    [[NN:%.*]] = and i32 [[N:%.*]], 2147483647
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp uge i32 [[NN]], [[X:%.*]]
 ; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
   %nn = and i32 %n, 2147483647
   %a = icmp sgt i32 %x, -1
   %b = icmp sle i32 %x, %nn
   %c = and i1 %a, %b
   ret i1 %c
 }
 
 define i1 @test_and2_logical(i32 %x, i32 %n) {
 ; CHECK-LABEL: @test_and2_logical(
 ; CHECK-NEXT:    [[NN:%.*]] = and i32 [[N:%.*]], 2147483647
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp uge i32 [[NN]], [[X:%.*]]
-; CHECK-NEXT:    ret i1 [[TMP1]]
+; CHECK-NEXT:    [[A:%.*]] = icmp sgt i32 [[X:%.*]], -1
+; CHECK-NEXT:    [[B:%.*]] = icmp sge i32 [[NN]], [[X]]
+; CHECK-NEXT:    [[C:%.*]] = select i1 [[A]], i1 [[B]], i1 false
+; CHECK-NEXT:    ret i1 [[C]]
 ;
   %nn = and i32 %n, 2147483647
   %a = icmp sgt i32 %x, -1
   %b = icmp sle i32 %x, %nn
   %c = select i1 %a, i1 %b, i1 false
   ret i1 %c
 }
 
;
   %b = icmp sge i32 %x, %nn
   %c = or i1 %a, %b
   ret i1 %c
 }
 
 define i1 @test_or1_logical(i32 %x, i32 %n) {
 ; CHECK-LABEL: @test_or1_logical(
 ; CHECK-NEXT:    [[NN:%.*]] = and i32 [[N:%.*]], 2147483647
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp ule i32 [[NN]], [[X:%.*]]
-; CHECK-NEXT:    ret i1 [[TMP1]]
+; CHECK-NEXT:    [[A:%.*]] = icmp slt i32 [[X:%.*]], 0
+; CHECK-NEXT:    [[B:%.*]] = icmp sle i32 [[NN]], [[X]]
+; CHECK-NEXT:    [[C:%.*]] = select i1 [[A]], i1 true, i1 [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
 ;
   %nn = and i32 %n, 2147483647
   %a = icmp slt i32 %x, 0
   %b = icmp sge i32 %x, %nn
   %c = select i1 %a, i1 true, i1 %b
   ret i1 %c
 }
 
 define i1 @test_or2(i32 %x, i32 %n) {
 ; CHECK-LABEL: @test_or2(
 ; CHECK-NEXT:    [[NN:%.*]] = and i32 [[N:%.*]], 2147483647
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp ult i32 [[NN]], [[X:%.*]]
 ; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
   %nn = and i32 %n, 2147483647
   %a = icmp sle i32 %x, -1
   %b = icmp sgt i32 %x, %nn
   %c = or i1 %a, %b
   ret i1 %c
 }
 
 define i1 @test_or2_logical(i32 %x, i32 %n) {
 ; CHECK-LABEL: @test_or2_logical(
 ; CHECK-NEXT:    [[NN:%.*]] = and i32 [[N:%.*]], 2147483647
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp ult i32 [[NN]], [[X:%.*]]
-; CHECK-NEXT:    ret i1 [[TMP1]]
+; CHECK-NEXT:    [[A:%.*]] = icmp slt i32 [[X:%.*]], 0
+; CHECK-NEXT:    [[B:%.*]] = icmp slt i32 [[NN]], [[X]]
+; CHECK-NEXT:    [[C:%.*]] = select i1 [[A]], i1 true, i1 [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
 ;
   %nn = and i32 %n, 2147483647
   %a = icmp sle i32 %x, -1
   %b = icmp sgt i32 %x, %nn
   %c = select i1 %a, i1 true, i1 %b
   ret i1 %c
 }
 
;
   ret i1 %c
 }
 
 define i1 @negative3_logical(i32 %x, i32 %y, i32 %n) {
 ; CHECK-LABEL: @negative3_logical(
 ; CHECK-NEXT:    [[NN:%.*]] = and i32 [[N:%.*]], 2147483647
 ; CHECK-NEXT:    [[A:%.*]] = icmp sgt i32 [[NN]], [[X:%.*]]
 ; CHECK-NEXT:    [[B:%.*]] = icmp sgt i32 [[Y:%.*]], -1
-; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    [[C:%.*]] = select i1 [[A]], i1 [[B]], i1 false
 ; CHECK-NEXT:    ret i1 [[C]]
 ;
   %nn = and i32 %n, 2147483647
   %a = icmp slt i32 %x, %nn
   %b = icmp sge i32 %y, 0      ; should compare %x and not %y
   %c = select i1 %a, i1 %b, i1 false
   ret i1 %c
 }

llvm/test/Transforms/InstCombine/select-and-or.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -S -instcombine -instcombine-unsafe-select-transform=0 < %s | FileCheck %s
+; RUN: opt -S -instcombine < %s | FileCheck %s
 
 ; Should not be converted to "and", which has different poison semantics.
 define i1 @logical_and(i1 %a, i1 %b) {
 ; CHECK-LABEL: @logical_and(
 ; CHECK-NEXT:    [[RES:%.*]] = select i1 [[A:%.*]], i1 [[B:%.*]], i1 false
 ; CHECK-NEXT:    ret i1 [[RES]]
 ;
   %res = select i1 %a, i1 %b, i1 false

llvm/test/Transforms/InstCombine/select-bitext.ll

;
   %trunc = fptrunc <2 x float> %a to <2 x half>
   %sel = select <2 x i1> %cmp, <2 x half> %trunc, <2 x half> <half 42.0, half 43.0>
   %ext = fpext <2 x half> %sel to <2 x float>
   ret <2 x float> %ext
 }
 
 define i32 @test_sext1(i1 %cca, i1 %ccb) {
 ; CHECK-LABEL: @test_sext1(
-; CHECK-NEXT:    [[NARROW:%.*]] = and i1 [[CCB:%.*]], [[CCA:%.*]]
+; CHECK-NEXT:    [[NARROW:%.*]] = select i1 [[CCB:%.*]], i1 [[CCA:%.*]], i1 false
 ; CHECK-NEXT:    [[R:%.*]] = sext i1 [[NARROW]] to i32
 ; CHECK-NEXT:    ret i32 [[R]]
 ;
   %ccax = sext i1 %cca to i32
   %r = select i1 %ccb, i32 %ccax, i32 0
   ret i32 %r
 }
 
 define i32 @test_sext2(i1 %cca, i1 %ccb) {
 ; CHECK-LABEL: @test_sext2(
-; CHECK-NEXT:    [[NARROW:%.*]] = or i1 [[CCB:%.*]], [[CCA:%.*]]
+; CHECK-NEXT:    [[NARROW:%.*]] = select i1 [[CCB:%.*]], i1 true, i1 [[CCA:%.*]]
 ; CHECK-NEXT:    [[R:%.*]] = sext i1 [[NARROW]] to i32
 ; CHECK-NEXT:    ret i32 [[R]]
 ;
   %ccax = sext i1 %cca to i32
   %r = select i1 %ccb, i32 -1, i32 %ccax
   ret i32 %r
 }
 
 define i32 @test_sext3(i1 %cca, i1 %ccb) {
 ; CHECK-LABEL: @test_sext3(
 ; CHECK-NEXT:    [[NOT_CCB:%.*]] = xor i1 [[CCB:%.*]], true
-; CHECK-NEXT:    [[NARROW:%.*]] = and i1 [[NOT_CCB]], [[CCA:%.*]]
+; CHECK-NEXT:    [[NARROW:%.*]] = select i1 [[NOT_CCB]], i1 [[CCA:%.*]], i1 false
 ; CHECK-NEXT:    [[R:%.*]] = sext i1 [[NARROW]] to i32
 ; CHECK-NEXT:    ret i32 [[R]]
 ;
   %ccax = sext i1 %cca to i32
   %r = select i1 %ccb, i32 0, i32 %ccax
   ret i32 %r
 }
 
 define i32 @test_sext4(i1 %cca, i1 %ccb) {
 ; CHECK-LABEL: @test_sext4(
 ; CHECK-NEXT:    [[NOT_CCB:%.*]] = xor i1 [[CCB:%.*]], true
-; CHECK-NEXT:    [[NARROW:%.*]] = or i1 [[NOT_CCB]], [[CCA:%.*]]
+; CHECK-NEXT:    [[NARROW:%.*]] = select i1 [[NOT_CCB]], i1 true, i1 [[CCA:%.*]]
 ; CHECK-NEXT:    [[R:%.*]] = sext i1 [[NARROW]] to i32
 ; CHECK-NEXT:    ret i32 [[R]]
 ;
   %ccax = sext i1 %cca to i32
   %r = select i1 %ccb, i32 %ccax, i32 -1
   ret i32 %r
 }
 
 define i32 @test_zext1(i1 %cca, i1 %ccb) {
 ; CHECK-LABEL: @test_zext1(
-; CHECK-NEXT:    [[NARROW:%.*]] = and i1 [[CCB:%.*]], [[CCA:%.*]]
+; CHECK-NEXT:    [[NARROW:%.*]] = select i1 [[CCB:%.*]], i1 [[CCA:%.*]], i1 false
 ; CHECK-NEXT:    [[R:%.*]] = zext i1 [[NARROW]] to i32
 ; CHECK-NEXT:    ret i32 [[R]]
 ;
   %ccax = zext i1 %cca to i32
   %r = select i1 %ccb, i32 %ccax, i32 0
   ret i32 %r
 }
 
 define i32 @test_zext2(i1 %cca, i1 %ccb) {
 ; CHECK-LABEL: @test_zext2(
-; CHECK-NEXT:    [[NARROW:%.*]] = or i1 [[CCB:%.*]], [[CCA:%.*]]
+; CHECK-NEXT:    [[NARROW:%.*]] = select i1 [[CCB:%.*]], i1 true, i1 [[CCA:%.*]]
 ; CHECK-NEXT:    [[R:%.*]] = zext i1 [[NARROW]] to i32
 ; CHECK-NEXT:    ret i32 [[R]]
 ;
   %ccax = zext i1 %cca to i32
   %r = select i1 %ccb, i32 1, i32 %ccax
   ret i32 %r
 }
 
 define i32 @test_zext3(i1 %cca, i1 %ccb) {
 ; CHECK-LABEL: @test_zext3(
 ; CHECK-NEXT:    [[NOT_CCB:%.*]] = xor i1 [[CCB:%.*]], true
-; CHECK-NEXT:    [[NARROW:%.*]] = and i1 [[NOT_CCB]], [[CCA:%.*]]
+; CHECK-NEXT:    [[NARROW:%.*]] = select i1 [[NOT_CCB]], i1 [[CCA:%.*]], i1 false
 ; CHECK-NEXT:    [[R:%.*]] = zext i1 [[NARROW]] to i32
 ; CHECK-NEXT:    ret i32 [[R]]
 ;
   %ccax = zext i1 %cca to i32
   %r = select i1 %ccb, i32 0, i32 %ccax
   ret i32 %r
 }
 
 define i32 @test_zext4(i1 %cca, i1 %ccb) {
 ; CHECK-LABEL: @test_zext4(
 ; CHECK-NEXT:    [[NOT_CCB:%.*]] = xor i1 [[CCB:%.*]], true
-; CHECK-NEXT:    [[NARROW:%.*]] = or i1 [[NOT_CCB]], [[CCA:%.*]]
+; CHECK-NEXT:    [[NARROW:%.*]] = select i1 [[NOT_CCB]], i1 true, i1 [[CCA:%.*]]
 ; CHECK-NEXT:    [[R:%.*]] = zext i1 [[NARROW]] to i32
 ; CHECK-NEXT:    ret i32 [[R]]
 ;
   %ccax = zext i1 %cca to i32
   %r = select i1 %ccb, i32 %ccax, i32 1
   ret i32 %r
 }
 
;
   %ccbx = sext i1 %ccb to i32
   %ccc = icmp sgt i32 %c, 0
   %r = select i1 %ccc, i32 %ccax, i32 %ccbx
   ret i32 %r
 }
 
 define <2 x i32> @test_vectors_sext(<2 x i1> %cca, <2 x i1> %ccb) {
 ; CHECK-LABEL: @test_vectors_sext(
-; CHECK-NEXT:    [[NARROW:%.*]] = and <2 x i1> [[CCB:%.*]], [[CCA:%.*]]
+; CHECK-NEXT:    [[NARROW:%.*]] = select <2 x i1> [[CCB:%.*]], <2 x i1> [[CCA:%.*]], <2 x i1> zeroinitializer
 ; CHECK-NEXT:    [[R:%.*]] = sext <2 x i1> [[NARROW]] to <2 x i32>
 ; CHECK-NEXT:    ret <2 x i32> [[R]]
 ;
   %ccax = sext <2 x i1> %cca to <2 x i32>
   %r = select <2 x i1> %ccb, <2 x i32> %ccax, <2 x i32> <i32 0, i32 0>
   ret <2 x i32> %r
 }
 
 define <2 x i32> @test_vectors_sext_nonsplat(<2 x i1> %cca, <2 x i1> %ccb) {
 ; CHECK-LABEL: @test_vectors_sext_nonsplat(
 ; CHECK-NEXT:    [[NARROW:%.*]] = select <2 x i1> [[CCB:%.*]], <2 x i1> [[CCA:%.*]], <2 x i1> <i1 false, i1 true>
 ; CHECK-NEXT:    [[R:%.*]] = sext <2 x i1> [[NARROW]] to <2 x i32>
 ; CHECK-NEXT:    ret <2 x i32> [[R]]
 ;
   %ccax = sext <2 x i1> %cca to <2 x i32>
   %r = select <2 x i1> %ccb, <2 x i32> %ccax, <2 x i32> <i32 0, i32 -1>
   ret <2 x i32> %r
 }
 
 define <2 x i32> @test_vectors_zext(<2 x i1> %cca, <2 x i1> %ccb) {
 ; CHECK-LABEL: @test_vectors_zext(
-; CHECK-NEXT:    [[NARROW:%.*]] = and <2 x i1> [[CCB:%.*]], [[CCA:%.*]]
+; CHECK-NEXT:    [[NARROW:%.*]] = select <2 x i1> [[CCB:%.*]], <2 x i1> [[CCA:%.*]], <2 x i1> zeroinitializer
 ; CHECK-NEXT:    [[R:%.*]] = zext <2 x i1> [[NARROW]] to <2 x i32>
 ; CHECK-NEXT:    ret <2 x i32> [[R]]
 ;
   %ccax = zext <2 x i1> %cca to <2 x i32>
   %r = select <2 x i1> %ccb, <2 x i32> %ccax, <2 x i32> <i32 0, i32 0>
   ret <2 x i32> %r
 }
 

llvm/test/Transforms/InstCombine/select-cmp-br.ll

 ; CHECK-LABEL: @test1(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP:%.*]] = getelementptr inbounds [[C:%.*]], %C* [[ARG:%.*]], i64 0, i32 0, i32 0
 ; CHECK-NEXT:    [[M:%.*]] = load i64*, i64** [[TMP]], align 8
 ; CHECK-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [[C]], %C* [[ARG]], i64 1, i32 0, i32 0
 ; CHECK-NEXT:    [[N:%.*]] = load i64*, i64** [[TMP1]], align 8
 ; CHECK-NEXT:    [[TMP5:%.*]] = icmp ne i64* [[M]], [[N]]
 ; CHECK-NEXT:    [[TMP71:%.*]] = icmp eq %C* [[ARG]], null
-; CHECK-NEXT:    [[TMP7:%.*]] = or i1 [[TMP5]], [[TMP71]]
+; CHECK-NEXT:    [[TMP7:%.*]] = select i1 [[TMP5]], i1 true, i1 [[TMP71]]
 ; CHECK-NEXT:    br i1 [[TMP7]], label [[BB10:%.*]], label [[BB8:%.*]]
 ; CHECK:       bb:
 ; CHECK-NEXT:    ret void
 ; CHECK:       bb8:
 ; CHECK-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[C]], %C* [[ARG]], i64 0, i32 0
 ; CHECK-NEXT:    tail call void @bar(%struct.S* [[TMP9]])
 ; CHECK-NEXT:    br label [[BB:%.*]]
 ; CHECK:       bb10:

 ; CHECK-LABEL: @test2(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP:%.*]] = getelementptr inbounds [[C:%.*]], %C* [[ARG:%.*]], i64 0, i32 0, i32 0
 ; CHECK-NEXT:    [[M:%.*]] = load i64*, i64** [[TMP]], align 8
 ; CHECK-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [[C]], %C* [[ARG]], i64 1, i32 0, i32 0
 ; CHECK-NEXT:    [[N:%.*]] = load i64*, i64** [[TMP1]], align 8
 ; CHECK-NEXT:    [[TMP5:%.*]] = icmp eq i64* [[M]], [[N]]
 ; CHECK-NEXT:    [[TMP71:%.*]] = icmp eq %C* [[ARG]], null
-; CHECK-NEXT:    [[TMP7:%.*]] = or i1 [[TMP5]], [[TMP71]]
+; CHECK-NEXT:    [[TMP7:%.*]] = select i1 [[TMP5]], i1 true, i1 [[TMP71]]
 ; CHECK-NEXT:    br i1 [[TMP7]], label [[BB10:%.*]], label [[BB8:%.*]]
 ; CHECK:       bb:
 ; CHECK-NEXT:    ret void
 ; CHECK:       bb8:
 ; CHECK-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[C]], %C* [[ARG]], i64 0, i32 0
 ; CHECK-NEXT:    tail call void @bar(%struct.S* [[TMP9]])
 ; CHECK-NEXT:    br label [[BB:%.*]]
 ; CHECK:       bb10:

 ; CHECK-LABEL: @test3(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP:%.*]] = getelementptr inbounds [[C:%.*]], %C* [[ARG:%.*]], i64 0, i32 0, i32 0
 ; CHECK-NEXT:    [[M:%.*]] = load i64*, i64** [[TMP]], align 8
 ; CHECK-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [[C]], %C* [[ARG]], i64 1, i32 0, i32 0
 ; CHECK-NEXT:    [[N:%.*]] = load i64*, i64** [[TMP1]], align 8
 ; CHECK-NEXT:    [[TMP5:%.*]] = icmp ne i64* [[M]], [[N]]
 ; CHECK-NEXT:    [[TMP7_NOT1:%.*]] = icmp eq %C* [[ARG]], null
-; CHECK-NEXT:    [[TMP7_NOT:%.*]] = or i1 [[TMP5]], [[TMP7_NOT1]]
+; CHECK-NEXT:    [[TMP7_NOT:%.*]] = select i1 [[TMP5]], i1 true, i1 [[TMP7_NOT1]]
 ; CHECK-NEXT:    br i1 [[TMP7_NOT]], label [[BB10:%.*]], label [[BB8:%.*]]
 ; CHECK:       bb:
 ; CHECK-NEXT:    ret void
 ; CHECK:       bb8:
 ; CHECK-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[C]], %C* [[ARG]], i64 0, i32 0
 ; CHECK-NEXT:    tail call void @bar(%struct.S* [[TMP9]])
 ; CHECK-NEXT:    br label [[BB:%.*]]
 ; CHECK:       bb10:

 ; CHECK-LABEL: @test4(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP:%.*]] = getelementptr inbounds [[C:%.*]], %C* [[ARG:%.*]], i64 0, i32 0, i32 0
 ; CHECK-NEXT:    [[M:%.*]] = load i64*, i64** [[TMP]], align 8
 ; CHECK-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [[C]], %C* [[ARG]], i64 1, i32 0, i32 0
 ; CHECK-NEXT:    [[N:%.*]] = load i64*, i64** [[TMP1]], align 8
 ; CHECK-NEXT:    [[TMP5:%.*]] = icmp eq i64* [[M]], [[N]]
 ; CHECK-NEXT:    [[TMP7_NOT1:%.*]] = icmp eq %C* [[ARG]], null
-; CHECK-NEXT:    [[TMP7_NOT:%.*]] = or i1 [[TMP5]], [[TMP7_NOT1]]
+; CHECK-NEXT:    [[TMP7_NOT:%.*]] = select i1 [[TMP5]], i1 true, i1 [[TMP7_NOT1]]
 ; CHECK-NEXT:    br i1 [[TMP7_NOT]], label [[BB10:%.*]], label [[BB8:%.*]]
 ; CHECK:       bb:
 ; CHECK-NEXT:    ret void
 ; CHECK:       bb8:
 ; CHECK-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[C]], %C* [[ARG]], i64 0, i32 0
 ; CHECK-NEXT:    tail call void @bar(%struct.S* [[TMP9]])
 ; CHECK-NEXT:    br label [[BB:%.*]]
 ; CHECK:       bb10:
bb10:                                             ; preds = %entry
   %tmp11 = tail call i64 %tmp4(%C* %arg)
   br label %bb
 }
 
 define void @test5(%C* %arg, i1 %arg1) {
 ; CHECK-LABEL: @test5(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP2_NOT1:%.*]] = icmp eq %C* [[ARG:%.*]], null
-; CHECK-NEXT:    [[TMP2_NOT:%.*]] = or i1 [[TMP2_NOT1]], [[ARG1:%.*]]
+; CHECK-NEXT:    [[TMP2_NOT:%.*]] = select i1 [[ARG1:%.*]], i1 true, i1 [[TMP2_NOT1]]
 ; CHECK-NEXT:    br i1 [[TMP2_NOT]], label [[BB5:%.*]], label [[BB3:%.*]]
 ; CHECK:       bb:
 ; CHECK-NEXT:    ret void
 ; CHECK:       bb3:
 ; CHECK-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[C:%.*]], %C* [[ARG]], i64 0, i32 0
 ; CHECK-NEXT:    tail call void @bar(%struct.S* [[TMP4]])
 ; CHECK-NEXT:    br label [[BB:%.*]]
 ; CHECK:       bb5:

llvm/test/Transforms/InstCombine/select-safe-bool-transforms.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt < %s -instcombine-unsafe-select-transform=0 -instcombine -S | FileCheck %s
+; RUN: opt < %s -instcombine -S | FileCheck %s
 
 ; TODO: All of these should be optimized to less than or equal to a single
 ; instruction of select/and/or.
 
 ; --- (A op B) op' A   /   (B op A) op' A ---
 
 ; (A land B) land A
 define i1 @land_land_left1(i1 %A, i1 %B) {

llvm/test/Transforms/InstCombine/select-safe-impliedcond-transforms.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt < %s -instcombine-unsafe-select-transform=0 -instcombine -S | FileCheck %s
+; RUN: opt < %s -instcombine -S | FileCheck %s
 
 define i1 @a_true_implies_b_true(i8 %z, i1 %X, i1 %Y) {
 ; CHECK-LABEL: @a_true_implies_b_true(
 ; CHECK-NEXT:    [[A:%.*]] = icmp ugt i8 [[Z:%.*]], 20
 ; CHECK-NEXT:    [[RES:%.*]] = select i1 [[A]], i1 [[X:%.*]], i1 false
 ; CHECK-NEXT:    ret i1 [[RES]]
 ;
   %a = icmp ugt i8 %z, 20

llvm/test/Transforms/InstCombine/select-safe-transforms.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt < %s -instcombine-unsafe-select-transform=0 -instcombine -S | FileCheck %s
+; RUN: opt < %s -instcombine -S | FileCheck %s
 
 define i1 @cond_eq_and(i8 %X, i8 %Y, i8 noundef %C) {
 ; CHECK-LABEL: @cond_eq_and(
 ; CHECK-NEXT:    [[COND:%.*]] = icmp eq i8 [[X:%.*]], [[C:%.*]]
 ; CHECK-NEXT:    [[LHS:%.*]] = icmp ult i8 [[X]], [[Y:%.*]]
 ; CHECK-NEXT:    [[RES:%.*]] = select i1 [[COND]], i1 [[LHS]], i1 false
 ; CHECK-NEXT:    ret i1 [[RES]]
 ;

llvm/test/Transforms/InstCombine/select.ll

 ; CHECK-NEXT:    ret i32 [[V]]
 ;
   %V = select i1 %C, i32 1, i32 0
   ret i32 %V
 }
 
 define i1 @trueval_is_true(i1 %C, i1 %X) {
 ; CHECK-LABEL: @trueval_is_true(
-; CHECK-NEXT:    [[R:%.*]] = or i1 [[C:%.*]], [[X:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[C:%.*]], i1 true, i1 [[X:%.*]]
 ; CHECK-NEXT:    ret i1 [[R]]
 ;
   %R = select i1 %C, i1 true, i1 %X
   ret i1 %R
 }
 
 define <2 x i1> @trueval_is_true_vec(<2 x i1> %C, <2 x i1> %X) {
 ; CHECK-LABEL: @trueval_is_true_vec(
-; CHECK-NEXT:    [[R:%.*]] = or <2 x i1> [[C:%.*]], [[X:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = select <2 x i1> [[C:%.*]], <2 x i1> <i1 true, i1 true>, <2 x i1> [[X:%.*]]
 ; CHECK-NEXT:    ret <2 x i1> [[R]]
 ;
   %R = select <2 x i1> %C, <2 x i1> <i1 true, i1 true>, <2 x i1> %X
   ret <2 x i1> %R
 }
 
 define <2 x i1> @trueval_is_true_vec_undef_elt(<2 x i1> %C, <2 x i1> %X) {
 ; CHECK-LABEL: @trueval_is_true_vec_undef_elt(
-; CHECK-NEXT:    [[R:%.*]] = or <2 x i1> [[C:%.*]], [[X:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = select <2 x i1> [[C:%.*]], <2 x i1> <i1 undef, i1 true>, <2 x i1> [[X:%.*]]
 ; CHECK-NEXT:    ret <2 x i1> [[R]]
 ;
   %R = select <2 x i1> %C, <2 x i1> <i1 undef, i1 true>, <2 x i1> %X
   ret <2 x i1> %R
 }
 
 define i1 @test8(i1 %C, i1 %X) {
 ; CHECK-LABEL: @test8(
-; CHECK-NEXT:    [[R:%.*]] = and i1 [[C:%.*]], [[X:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[C:%.*]], i1 [[X:%.*]], i1 false
 ; CHECK-NEXT:    ret i1 [[R]]
 ;
   %R = select i1 %C, i1 %X, i1 false
   ret i1 %R
 }
 
 define <2 x i1> @test8vec(<2 x i1> %C, <2 x i1> %X) {
 ; CHECK-LABEL: @test8vec(
-; CHECK-NEXT:    [[R:%.*]] = and <2 x i1> [[C:%.*]], [[X:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = select <2 x i1> [[C:%.*]], <2 x i1> [[X:%.*]], <2 x i1> zeroinitializer
 ; CHECK-NEXT:    ret <2 x i1> [[R]]
 ;
   %R = select <2 x i1> %C, <2 x i1> %X, <2 x i1> <i1 false, i1 false>
   ret <2 x i1> %R
 }
 
 define <vscale x 2 x i1> @test8vvec(<vscale x 2 x i1> %C, <vscale x 2 x i1> %X) {
 ; CHECK-LABEL: @test8vvec(
-; CHECK-NEXT:    [[R:%.*]] = and <vscale x 2 x i1> [[C:%.*]], [[X:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = select <vscale x 2 x i1> [[C:%.*]], <vscale x 2 x i1> [[X:%.*]], <vscale x 2 x i1> zeroinitializer
 ; CHECK-NEXT:    ret <vscale x 2 x i1> [[R]]
 ;
   %R = select <vscale x 2 x i1> %C, <vscale x 2 x i1> %X, <vscale x 2 x i1> zeroinitializer
   ret <vscale x 2 x i1> %R
 }
 
 define i1 @test9(i1 %C, i1 %X) {
 ; CHECK-LABEL: @test9(
 ; CHECK-NEXT:    [[NOT_C:%.*]] = xor i1 [[C:%.*]], true
-; CHECK-NEXT:    [[R:%.*]] = and i1 [[NOT_C]], [[X:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[NOT_C]], i1 [[X:%.*]], i1 false
 ; CHECK-NEXT:    ret i1 [[R]]
 ;
   %R = select i1 %C, i1 false, i1 %X
   ret i1 %R
 }
 
 define <2 x i1> @test9vec(<2 x i1> %C, <2 x i1> %X) {
 ; CHECK-LABEL: @test9vec(
 ; CHECK-NEXT:    [[NOT_C:%.*]] = xor <2 x i1> [[C:%.*]], <i1 true, i1 true>
-; CHECK-NEXT:    [[R:%.*]] = and <2 x i1> [[NOT_C]], [[X:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = select <2 x i1> [[NOT_C]], <2 x i1> [[X:%.*]], <2 x i1> zeroinitializer
 ; CHECK-NEXT:    ret <2 x i1> [[R]]
 ;
   %R = select <2 x i1> %C, <2 x i1> <i1 false, i1 false>, <2 x i1> %X
   ret <2 x i1> %R
 }
 
 define <vscale x 2 x i1> @test9vvec(<vscale x 2 x i1> %C, <vscale x 2 x i1> %X) {
 ; CHECK-LABEL: @test9vvec(
 ; CHECK-NEXT:    [[NOT_C:%.*]] = xor <vscale x 2 x i1> [[C:%.*]], shufflevector (<vscale x 2 x i1> insertelement (<vscale x 2 x i1> undef, i1 true, i32 0), <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer)
-; CHECK-NEXT:    [[R:%.*]] = and <vscale x 2 x i1> [[NOT_C]], [[X:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = select <vscale x 2 x i1> [[NOT_C]], <vscale x 2 x i1> [[X:%.*]], <vscale x 2 x i1> zeroinitializer
 ; CHECK-NEXT:    ret <vscale x 2 x i1> [[R]]
 ;
   %R = select <vscale x 2 x i1> %C, <vscale x 2 x i1> zeroinitializer, <vscale x 2 x i1> %X
   ret <vscale x 2 x i1> %R
 }
 
 define i1 @test10(i1 %C, i1 %X) {
 ; CHECK-LABEL: @test10(
 ; CHECK-NEXT:    [[NOT_C:%.*]] = xor i1 [[C:%.*]], true
-; CHECK-NEXT:    [[R:%.*]] = or i1 [[NOT_C]], [[X:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[NOT_C]], i1 true, i1 [[X:%.*]]
 ; CHECK-NEXT:    ret i1 [[R]]
 ;
   %R = select i1 %C, i1 %X, i1 true
   ret i1 %R
 }
 
 define <2 x i1> @test10vec(<2 x i1> %C, <2 x i1> %X) {
 ; CHECK-LABEL: @test10vec(
 ; CHECK-NEXT:    [[NOT_C:%.*]] = xor <2 x i1> [[C:%.*]], <i1 true, i1 true>
-; CHECK-NEXT:    [[R:%.*]] = or <2 x i1> [[NOT_C]], [[X:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = select <2 x i1> [[NOT_C]], <2 x i1> <i1 true, i1 true>, <2 x i1> [[X:%.*]]
 ; CHECK-NEXT:    ret <2 x i1> [[R]]
 ;
   %R = select <2 x i1> %C, <2 x i1> %X, <2 x i1> <i1 true, i1 true>
   ret <2 x i1> %R
 }
 
 define i1 @test23(i1 %a, i1 %b) {
 ; CHECK-LABEL: @test23(
-; CHECK-NEXT:    [[C:%.*]] = and i1 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[C:%.*]] = select i1 [[A:%.*]], i1 [[B:%.*]], i1 false
 ; CHECK-NEXT:    ret i1 [[C]]
 ;
   %c = select i1 %a, i1 %b, i1 %a
   ret i1 %c
 }
 
 define <2 x i1> @test23vec(<2 x i1> %a, <2 x i1> %b) {
 ; CHECK-LABEL: @test23vec(
-; CHECK-NEXT:    [[C:%.*]] = and <2 x i1> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[C:%.*]] = select <2 x i1> [[A:%.*]], <2 x i1> [[B:%.*]], <2 x i1> zeroinitializer
 ; CHECK-NEXT:    ret <2 x i1> [[C]]
 ;
   %c = select <2 x i1> %a, <2 x i1> %b, <2 x i1> %a
   ret <2 x i1> %c
 }
 
 define i1 @test24(i1 %a, i1 %b) {
 ; CHECK-LABEL: @test24(
-; CHECK-NEXT:    [[C:%.*]] = or i1 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[C:%.*]] = select i1 [[A:%.*]], i1 true, i1 [[B:%.*]]
 ; CHECK-NEXT:    ret i1 [[C]]
 ;
   %c = select i1 %a, i1 %a, i1 %b
   ret i1 %c
 }
 
 define <2 x i1> @test24vec(<2 x i1> %a, <2 x i1> %b) {
 ; CHECK-LABEL: @test24vec(
-; CHECK-NEXT:    [[C:%.*]] = or <2 x i1> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[C:%.*]] = select <2 x i1> [[A:%.*]], <2 x i1> <i1 true, i1 true>, <2 x i1> [[B:%.*]]
 ; CHECK-NEXT:    ret <2 x i1> [[C]]
 ;
   %c = select <2 x i1> %a, <2 x i1> %a, <2 x i1> %b
   ret <2 x i1> %c
 }
 
 define i1 @test62(i1 %A, i1 %B) {
 ; CHECK-LABEL: @test62(
 ; CHECK-NEXT:    [[NOT:%.*]] = xor i1 [[A:%.*]], true
-; CHECK-NEXT:    [[C:%.*]] = and i1 [[NOT]], [[B:%.*]]
+; CHECK-NEXT:    [[C:%.*]] = select i1 [[NOT]], i1 [[B:%.*]], i1 false
 ; CHECK-NEXT:    ret i1 [[C]]
 ;
   %not = xor i1 %A, true
   %C = select i1 %A, i1 %not, i1 %B
   ret i1 %C
 }
 
 define <2 x i1> @test62vec(<2 x i1> %A, <2 x i1> %B) {
 ; CHECK-LABEL: @test62vec(
 ; CHECK-NEXT:    [[NOT:%.*]] = xor <2 x i1> [[A:%.*]], <i1 true, i1 true>
-; CHECK-NEXT:    [[C:%.*]] = and <2 x i1> [[NOT]], [[B:%.*]]
+; CHECK-NEXT:    [[C:%.*]] = select <2 x i1> [[NOT]], <2 x i1> [[B:%.*]], <2 x i1> zeroinitializer
 ; CHECK-NEXT:    ret <2 x i1> [[C]]
 ;
   %not = xor <2 x i1> %A, <i1 true, i1 true>
   %C = select <2 x i1> %A, <2 x i1> %not, <2 x i1> %B
   ret <2 x i1> %C
 }
 
 define i1 @test63(i1 %A, i1 %B) {
 ; CHECK-LABEL: @test63(
 ; CHECK-NEXT:    [[NOT:%.*]] = xor i1 [[A:%.*]], true
-; CHECK-NEXT:    [[C:%.*]] = or i1 [[NOT]], [[B:%.*]]
+; CHECK-NEXT:    [[C:%.*]] = select i1 [[NOT]], i1 true, i1 [[B:%.*]]
 ; CHECK-NEXT:    ret i1 [[C]]
 ;
   %not = xor i1 %A, true
   %C = select i1 %A, i1 %B, i1 %not
   ret i1 %C
 }
 
 define <2 x i1> @test63vec(<2 x i1> %A, <2 x i1> %B) {
 ; CHECK-LABEL: @test63vec(
 ; CHECK-NEXT:    [[NOT:%.*]] = xor <2 x i1> [[A:%.*]], <i1 true, i1 true>
-; CHECK-NEXT:    [[C:%.*]] = or <2 x i1> [[NOT]], [[B:%.*]]
+; CHECK-NEXT:    [[C:%.*]] = select <2 x i1> [[NOT]], <2 x i1> <i1 true, i1 true>, <2 x i1> [[B:%.*]]
 ; CHECK-NEXT:    ret <2 x i1> [[C]]
 ;
   %not = xor <2 x i1> %A, <i1 true, i1 true>
   %C = select <2 x i1> %A, <2 x i1> %B, <2 x i1> %not
   ret <2 x i1> %C
 }
 
 define i32 @test11(i32 %a) {
;
   %V = select i1 %C, i32 %b, i32 %a
   ret i32 %V
 }
 
 define i1 @test14a(i1 %C, i32 %X) {
 ; CHECK-LABEL: @test14a(
 ; CHECK-NEXT:    [[R1:%.*]] = icmp slt i32 [[X:%.*]], 1
 ; CHECK-NEXT:    [[NOT_C:%.*]] = xor i1 [[C:%.*]], true
-; CHECK-NEXT:    [[R:%.*]] = or i1 [[R1]], [[NOT_C]]
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[NOT_C]], i1 true, i1 [[R1]]
 ; CHECK-NEXT:    ret i1 [[R]]
 ;
   %V = select i1 %C, i32 %X, i32 0
   ; (X < 1) | !C
   %R = icmp slt i32 %V, 1
   ret i1 %R
 }
 
 define i1 @test14b(i1 %C, i32 %X) {
 ; CHECK-LABEL: @test14b(
 ; CHECK-NEXT:    [[R1:%.*]] = icmp slt i32 [[X:%.*]], 1
-; CHECK-NEXT:    [[R:%.*]] = or i1 [[R1]], [[C:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[C:%.*]], i1 true, i1 [[R1]]
 ; CHECK-NEXT:    ret i1 [[R]]
 ;
   %V = select i1 %C, i32 0, i32 %X
   ; (X < 1) | C
   %R = icmp slt i32 %V, 1
   ret i1 %R
 }
 

 }
 
 attributes #0 = { null_pointer_is_valid }
 
 define i1 @test17(i32* %X, i1 %C) {
 ; CHECK-LABEL: @test17(
 ; CHECK-NEXT:    [[RV1:%.*]] = icmp eq i32* [[X:%.*]], null
 ; CHECK-NEXT:    [[NOT_C:%.*]] = xor i1 [[C:%.*]], true
-; CHECK-NEXT:    [[RV:%.*]] = or i1 [[RV1]], [[NOT_C]]
+; CHECK-NEXT:    [[RV:%.*]] = select i1 [[NOT_C]], i1 true, i1 [[RV1]]
 ; CHECK-NEXT:    ret i1 [[RV]]
 ;
   %R = select i1 %C, i32* %X, i32* null
   %RV = icmp eq i32* %R, null
   ret i1 %RV
 }
 
 define i32 @test18(i32 %X, i32 %Y, i1 %C) {

llvm/test/Transforms/InstCombine/sign-test-and-or.ll

;
   %1 = icmp slt i32 %a, 0
   %2 = icmp slt i32 %b, 0
   %or.cond = or i1 %1, %2
   ret i1 %or.cond
 }
 
 define i1 @test1_logical(i32 %a, i32 %b) {
 ; CHECK-LABEL: @test1_logical(
-; CHECK-NEXT:    [[TMP1:%.*]] = or i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp slt i32 [[TMP1]], 0
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i32 [[A:%.*]], 0
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp slt i32 [[B:%.*]], 0
+; CHECK-NEXT:    [[OR_COND:%.*]] = select i1 [[TMP1]], i1 true, i1 [[TMP2]]
+; CHECK-NEXT:    ret i1 [[OR_COND]]
 ;
   %1 = icmp slt i32 %a, 0
   %2 = icmp slt i32 %b, 0
   %or.cond = select i1 %1, i1 true, i1 %2
   ret i1 %or.cond
 }
 
 define i1 @test2(i32 %a, i32 %b) {
 ; CHECK-LABEL: @test2(
 ; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[A:%.*]], [[B:%.*]]
 ; CHECK-NEXT:    [[TMP2:%.*]] = icmp sgt i32 [[TMP1]], -1
 ; CHECK-NEXT:    ret i1 [[TMP2]]
 ;
   %1 = icmp sgt i32 %a, -1
   %2 = icmp sgt i32 %b, -1
   %or.cond = or i1 %1, %2
   ret i1 %or.cond
 }
 
 define i1 @test2_logical(i32 %a, i32 %b) {
 ; CHECK-LABEL: @test2_logical(
-; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp sgt i32 [[TMP1]], -1
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt i32 [[A:%.*]], -1
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp sgt i32 [[B:%.*]], -1
+; CHECK-NEXT:    [[OR_COND:%.*]] = select i1 [[TMP1]], i1 true, i1 [[TMP2]]
+; CHECK-NEXT:    ret i1 [[OR_COND]]
 ;
   %1 = icmp sgt i32 %a, -1
   %2 = icmp sgt i32 %b, -1
   %or.cond = select i1 %1, i1 true, i1 %2
   ret i1 %or.cond
 }
 
 define i1 @test3(i32 %a, i32 %b) {
 ; CHECK-LABEL: @test3(
 ; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[A:%.*]], [[B:%.*]]
 ; CHECK-NEXT:    [[TMP2:%.*]] = icmp slt i32 [[TMP1]], 0
 ; CHECK-NEXT:    ret i1 [[TMP2]]
 ;
   %1 = icmp slt i32 %a, 0
   %2 = icmp slt i32 %b, 0
   %or.cond = and i1 %1, %2
   ret i1 %or.cond
 }
 
 define i1 @test3_logical(i32 %a, i32 %b) {
 ; CHECK-LABEL: @test3_logical(
-; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp slt i32 [[TMP1]], 0
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i32 [[A:%.*]], 0
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp slt i32 [[B:%.*]], 0
+; CHECK-NEXT:    [[OR_COND:%.*]] = select i1 [[TMP1]], i1 [[TMP2]], i1 false
+; CHECK-NEXT:    ret i1 [[OR_COND]]
 ;
   %1 = icmp slt i32 %a, 0
   %2 = icmp slt i32 %b, 0
   %or.cond = select i1 %1, i1 %2, i1 false
   ret i1 %or.cond
 }
 
 define i1 @test4(i32 %a, i32 %b) {
 ; CHECK-LABEL: @test4(
 ; CHECK-NEXT:    [[TMP1:%.*]] = or i32 [[A:%.*]], [[B:%.*]]
 ; CHECK-NEXT:    [[TMP2:%.*]] = icmp sgt i32 [[TMP1]], -1
 ; CHECK-NEXT:    ret i1 [[TMP2]]
 ;
   %1 = icmp sgt i32 %a, -1
   %2 = icmp sgt i32 %b, -1
   %or.cond = and i1 %1, %2
   ret i1 %or.cond
 }
 
 define i1 @test4_logical(i32 %a, i32 %b) {
 ; CHECK-LABEL: @test4_logical(
-; CHECK-NEXT:    [[TMP1:%.*]] = or i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp sgt i32 [[TMP1]], -1
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt i32 [[A:%.*]], -1
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp sgt i32 [[B:%.*]], -1
+; CHECK-NEXT:    [[OR_COND:%.*]] = select i1 [[TMP1]], i1 [[TMP2]], i1 false
+; CHECK-NEXT:    ret i1 [[OR_COND]]
 ;
   %1 = icmp sgt i32 %a, -1
   %2 = icmp sgt i32 %b, -1
   %or.cond = select i1 %1, i1 %2, i1 false
   ret i1 %or.cond
 }
 
 define void @test5(i32 %a) {

llvm/test/Transforms/InstCombine/signed-truncation-check.ll

;
   %t3 = icmp ult i32 %t2, 256
   %t4 = and i1 %t1, %z
   %t5 = and i1 %t3, %t4
   ret i1 %t5
 }
 
 define i1 @positive_with_extra_and_logical(i32 %arg, i1 %z) {
 ; CHECK-LABEL: @positive_with_extra_and_logical(
-; CHECK-NEXT:    [[T5_SIMPLIFIED:%.*]] = icmp ult i32 [[ARG:%.*]], 128
-; CHECK-NEXT:    [[TMP1:%.*]] = and i1 [[T5_SIMPLIFIED]], [[Z:%.*]]
-; CHECK-NEXT:    ret i1 [[TMP1]]
+; CHECK-NEXT:    [[DOTSIMPLIFIED:%.*]] = icmp ult i32 [[ARG:%.*]], 128
+; CHECK-NEXT:    [[T5:%.*]] = select i1 [[DOTSIMPLIFIED]], i1 [[Z:%.*]], i1 false
+; CHECK-NEXT:    ret i1 [[T5]]
 ;
   %t1 = icmp sgt i32 %arg, -1
   %t2 = add i32 %arg, 128
   %t3 = icmp ult i32 %t2, 256
   %t4 = select i1 %t1, i1 %z, i1 false
   %t5 = select i1 %t3, i1 %t4, i1 false
   ret i1 %t5
 }

 
 define i1 @positive_different_trunc_both_logical(i32 %arg) {
 ; CHECK-LABEL: @positive_different_trunc_both_logical(
 ; CHECK-NEXT:    [[T1:%.*]] = trunc i32 [[ARG:%.*]] to i15
 ; CHECK-NEXT:    [[T2:%.*]] = icmp sgt i15 [[T1]], -1
 ; CHECK-NEXT:    [[T3:%.*]] = trunc i32 [[ARG]] to i16
 ; CHECK-NEXT:    [[T4:%.*]] = add i16 [[T3]], 128
 ; CHECK-NEXT:    [[T5:%.*]] = icmp ult i16 [[T4]], 256
-; CHECK-NEXT:    [[T6:%.*]] = and i1 [[T2]], [[T5]]
+; CHECK-NEXT:    [[T6:%.*]] = select i1 [[T2]], i1 [[T5]], i1 false
 ; CHECK-NEXT:    ret i1 [[T6]]
 ;
   %t1 = trunc i32 %arg to i15
   %t2 = icmp sgt i15 %t1, -1
   %t3 = trunc i32 %arg to i16
   %t4 = add i16 %t3, 128
   %t5 = icmp ult i16 %t4, 256
   %t6 = select i1 %t2, i1 %t5, i1 false

 ; CHECK-NEXT:    [[T2:%.*]] = icmp sgt i8 [[T1]], -1
 ; CHECK-NEXT:    call void @use1(i1 [[T2]])
 ; CHECK-NEXT:    [[T3:%.*]] = trunc i32 [[ARG]] to i8
 ; CHECK-NEXT:    call void @use8(i8 [[T3]])
 ; CHECK-NEXT:    [[T4:%.*]] = sext i8 [[T3]] to i32
 ; CHECK-NEXT:    call void @use32(i32 [[T4]])
 ; CHECK-NEXT:    [[T5:%.*]] = icmp eq i32 [[T4]], [[ARG]]
 ; CHECK-NEXT:    call void @use1(i1 [[T5]])
-; CHECK-NEXT:    [[T6:%.*]] = and i1 [[T2]], [[T5]]
+; CHECK-NEXT:    [[T6:%.*]] = select i1 [[T2]], i1 [[T5]], i1 false
 ; CHECK-NEXT:    ret i1 [[T6]]
 ;
   %t1 = trunc i32 %arg to i8
   call void @use8(i8 %t1)
   %t2 = icmp sgt i8 %t1, -1
   call void @use1(i1 %t2)
   %t3 = trunc i32 %arg to i8
   call void @use8(i8 %t3)
;
   ret i1 %t4
 }
 
 define i1 @negative_not_arg_logical(i32 %arg, i32 %arg2) {
 ; CHECK-LABEL: @negative_not_arg_logical(
 ; CHECK-NEXT:    [[T1:%.*]] = icmp sgt i32 [[ARG:%.*]], -1
 ; CHECK-NEXT:    [[T2:%.*]] = add i32 [[ARG2:%.*]], 128
 ; CHECK-NEXT:    [[T3:%.*]] = icmp ult i32 [[T2]], 256
-; CHECK-NEXT:    [[T4:%.*]] = and i1 [[T1]], [[T3]]
+; CHECK-NEXT:    [[T4:%.*]] = select i1 [[T1]], i1 [[T3]], i1 false
 ; CHECK-NEXT:    ret i1 [[T4]]
 ;
   %t1 = icmp sgt i32 %arg, -1
   %t2 = add i32 %arg2, 128 ; not %arg
   %t3 = icmp ult i32 %t2, 256
   %t4 = select i1 %t1, i1 %t3, i1 false
   ret i1 %t4
 }

 }
 
 define i1 @negative_trunc_not_arg_logical(i32 %arg, i32 %arg2) {
 ; CHECK-LABEL: @negative_trunc_not_arg_logical(
 ; CHECK-NEXT:    [[T1:%.*]] = trunc i32 [[ARG:%.*]] to i8
 ; CHECK-NEXT:    [[T2:%.*]] = icmp sgt i8 [[T1]], -1
 ; CHECK-NEXT:    [[T3:%.*]] = add i32 [[ARG2:%.*]], 128
 ; CHECK-NEXT:    [[T4:%.*]] = icmp ult i32 [[T3]], 256
-; CHECK-NEXT:    [[T5:%.*]] = and i1 [[T2]], [[T4]]
+; CHECK-NEXT:    [[T5:%.*]] = select i1 [[T2]], i1 [[T4]], i1 false
 ; CHECK-NEXT:    ret i1 [[T5]]
 ;
   %t1 = trunc i32 %arg to i8
   %t2 = icmp sgt i8 %t1, -1
   %t3 = add i32 %arg2, 128 ; not %arg
   %t4 = icmp ult i32 %t3, 256
   %t5 = select i1 %t2, i1 %t4, i1 false
   ret i1 %t5

 }
 
 define i1 @positive_with_mask_not_arg_logical(i32 %arg, i32 %arg2) {
 ; CHECK-LABEL: @positive_with_mask_not_arg_logical(
 ; CHECK-NEXT:    [[T1:%.*]] = and i32 [[ARG:%.*]], 1140850688
 ; CHECK-NEXT:    [[T2:%.*]] = icmp eq i32 [[T1]], 0
 ; CHECK-NEXT:    [[T3:%.*]] = add i32 [[ARG2:%.*]], 128
 ; CHECK-NEXT:    [[T4:%.*]] = icmp ult i32 [[T3]], 256
-; CHECK-NEXT:    [[T5:%.*]] = and i1 [[T2]], [[T4]]
+; CHECK-NEXT:    [[T5:%.*]] = select i1 [[T2]], i1 [[T4]], i1 false
 ; CHECK-NEXT:    ret i1 [[T5]]
 ;
   %t1 = and i32 %arg, 1140850688
   %t2 = icmp eq i32 %t1, 0
   %t3 = add i32 %arg2, 128 ; not %arg
   %t4 = icmp ult i32 %t3, 256
   %t5 = select i1 %t2, i1 %t4, i1 false
   ret i1 %t5

 }
 
 define i1 @bad_trunc_stc_logical(i32 %arg) {
 ; CHECK-LABEL: @bad_trunc_stc_logical(
 ; CHECK-NEXT:    [[T1:%.*]] = icmp sgt i32 [[ARG:%.*]], -1
 ; CHECK-NEXT:    [[T2:%.*]] = trunc i32 [[ARG]] to i16
 ; CHECK-NEXT:    [[T3:%.*]] = add i16 [[T2]], 128
 ; CHECK-NEXT:    [[T4:%.*]] = icmp ult i16 [[T3]], 256
-; CHECK-NEXT:    [[T5:%.*]] = and i1 [[T1]], [[T4]]
+; CHECK-NEXT:    [[T5:%.*]] = select i1 [[T1]], i1 [[T4]], i1 false
 ; CHECK-NEXT:    ret i1 [[T5]]
 ;
   %t1 = icmp sgt i32 %arg, -1 ; checks a bit outside of the i16
   %t2 = trunc i32 %arg to i16
   %t3 = add i16 %t2, 128
   %t4 = icmp ult i16 %t3, 256
   %t5 = select i1 %t1, i1 %t4, i1 false
   ret i1 %t5
 }

llvm/test/Transforms/InstCombine/umul-sign-check.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -instcombine -S %s | FileCheck %s
-; RUN: opt -instcombine -instcombine-unsafe-select-transform=0 -S %s | FileCheck %s
 
 ; Check that we simplify llvm.umul.with.overflow, if the overflow check is
 ; weakened by or (icmp ne %res, 0) %overflow. This is generated by code using
 ; __builtin_mul_overflow with negative integer constants, e.g.
 
 ;   bool test(unsigned long long v, unsigned long long *res) {
 ;     return __builtin_mul_overflow(v, -4775807LL, res);
 ;   }

llvm/test/Transforms/InstCombine/usub-overflow-known-by-implied-cond.ll

 
 bb3:
   ret i32 0
 }
 
 define i32 @test9_logical(i32 %a, i32 %b, i1 %cond2) {
 ; CHECK-LABEL: @test9_logical(
 ; CHECK-NEXT:    [[COND:%.*]] = icmp ugt i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[COND]], [[COND2:%.*]]
+; CHECK-NEXT:    [[AND:%.*]] = select i1 [[COND]], i1 [[COND2:%.*]], i1 false
 ; CHECK-NEXT:    br i1 [[AND]], label [[BB1:%.*]], label [[BB3:%.*]]
 ; CHECK:       bb1:
 ; CHECK-NEXT:    br i1 false, label [[BB3]], label [[BB2:%.*]]
 ; CHECK:       bb2:
 ; CHECK-NEXT:    [[SUB1:%.*]] = sub nuw i32 [[A]], [[B]]
 ; CHECK-NEXT:    ret i32 [[SUB1]]
 ; CHECK:       bb3:
 ; CHECK-NEXT:    ret i32 0

 
 bb3:
   ret i32 0
 }
 
 define i32 @test10_logical(i32 %a, i32 %b, i1 %cond2) {
 ; CHECK-LABEL: @test10_logical(
 ; CHECK-NEXT:    [[COND:%.*]] = icmp ugt i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[COND]], [[COND2:%.*]]
+; CHECK-NEXT:    [[AND:%.*]] = select i1 [[COND]], i1 [[COND2:%.*]], i1 false
 ; CHECK-NEXT:    br i1 [[AND]], label [[BB3:%.*]], label [[BB1:%.*]]
 ; CHECK:       bb1:
 ; CHECK-NEXT:    [[SUB1:%.*]] = call { i32, i1 } @llvm.usub.with.overflow.i32(i32 [[A]], i32 [[B]])
 ; CHECK-NEXT:    [[C1:%.*]] = extractvalue { i32, i1 } [[SUB1]], 1
 ; CHECK-NEXT:    br i1 [[C1]], label [[BB3]], label [[BB2:%.*]]
 ; CHECK:       bb2:
 ; CHECK-NEXT:    [[R1:%.*]] = extractvalue { i32, i1 } [[SUB1]], 0
 ; CHECK-NEXT:    ret i32 [[R1]]

 
 bb3:
   ret i32 0
 }
 
 define i32 @test11_logical(i32 %a, i32 %b, i1 %cond2) {
 ; CHECK-LABEL: @test11_logical(
 ; CHECK-NEXT:    [[COND:%.*]] = icmp ugt i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT:    [[OR:%.*]] = or i1 [[COND]], [[COND2:%.*]]
+; CHECK-NEXT:    [[OR:%.*]] = select i1 [[COND]], i1 true, i1 [[COND2:%.*]]
 ; CHECK-NEXT:    br i1 [[OR]], label [[BB1:%.*]], label [[BB3:%.*]]
 ; CHECK:       bb1:
 ; CHECK-NEXT:    [[SUB1:%.*]] = call { i32, i1 } @llvm.usub.with.overflow.i32(i32 [[A]], i32 [[B]])
 ; CHECK-NEXT:    [[C1:%.*]] = extractvalue { i32, i1 } [[SUB1]], 1
 ; CHECK-NEXT:    br i1 [[C1]], label [[BB3]], label [[BB2:%.*]]
 ; CHECK:       bb2:
 ; CHECK-NEXT:    [[R1:%.*]] = extractvalue { i32, i1 } [[SUB1]], 0
 ; CHECK-NEXT:    ret i32 [[R1]]

 
 bb3:
   ret i32 0
 }
 
 define i32 @test12_logical(i32 %a, i32 %b, i1 %cond2) {
 ; CHECK-LABEL: @test12_logical(
 ; CHECK-NEXT:    [[COND:%.*]] = icmp ugt i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT:    [[OR:%.*]] = or i1 [[COND]], [[COND2:%.*]]
+; CHECK-NEXT:    [[OR:%.*]] = select i1 [[COND]], i1 true, i1 [[COND2:%.*]]
 ; CHECK-NEXT:    br i1 [[OR]], label [[BB3:%.*]], label [[BB1:%.*]]
 ; CHECK:       bb1:
 ; CHECK-NEXT:    [[SUB1:%.*]] = call { i32, i1 } @llvm.usub.with.overflow.i32(i32 [[A]], i32 [[B]])
 ; CHECK-NEXT:    [[C1:%.*]] = extractvalue { i32, i1 } [[SUB1]], 1
 ; CHECK-NEXT:    br i1 [[C1]], label [[BB3]], label [[BB2:%.*]]
 ; CHECK:       bb2:
 ; CHECK-NEXT:    [[R1:%.*]] = extractvalue { i32, i1 } [[SUB1]], 0
 ; CHECK-NEXT:    ret i32 [[R1]]

llvm/test/Transforms/InstCombine/widenable-conditions.ll

;
   %and = and i1 %lhs, %a
   ret i1 %and
 }
 
 define i1 @test1_logical(i1 %a, i1 %b) {
 ; CHECK-LABEL: @test1_logical(
 ; CHECK-NEXT:    [[WC:%.*]] = call i1 @llvm.experimental.widenable.condition()
 ; CHECK-NEXT:    [[LHS:%.*]] = select i1 [[B:%.*]], i1 [[WC]], i1 false
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[LHS]], [[A:%.*]]
+; CHECK-NEXT:    [[AND:%.*]] = select i1 [[LHS]], i1 [[A:%.*]], i1 false
 ; CHECK-NEXT:    ret i1 [[AND]]
 ;
   %wc = call i1 @llvm.experimental.widenable.condition()
   %lhs = select i1 %b, i1 %wc, i1 false
   %and = select i1 %lhs, i1 %a, i1 false
   ret i1 %and
 }
 
;
   ret i1 %and
 }
 
 define i1 @test1b_logical(i1 %a, i1 %b) {
 ; CHECK-LABEL: @test1b_logical(
 ; CHECK-NEXT:    [[WC:%.*]] = call i1 @llvm.experimental.widenable.condition()
 ; CHECK-NEXT:    [[LHS:%.*]] = select i1 [[B:%.*]], i1 [[WC]], i1 false
 ; CHECK-NEXT:    call void @use(i1 [[LHS]])
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[LHS]], [[A:%.*]]
+; CHECK-NEXT:    [[AND:%.*]] = select i1 [[LHS]], i1 [[A:%.*]], i1 false
 ; CHECK-NEXT:    ret i1 [[AND]]
 ;
   %wc = call i1 @llvm.experimental.widenable.condition()
   %lhs = select i1 %b, i1 %wc, i1 false
   call void @use(i1 %lhs)
   %and = select i1 %lhs, i1 %a, i1 false
   ret i1 %and
 }

 
 define i1 @test1c_logical(i1 %a, i1 %b) {
 ; CHECK-LABEL: @test1c_logical(
 ; CHECK-NEXT:    call void @use(i1 [[A:%.*]])
 ; CHECK-NEXT:    call void @use(i1 [[B:%.*]])
 ; CHECK-NEXT:    [[WC:%.*]] = call i1 @llvm.experimental.widenable.condition()
 ; CHECK-NEXT:    call void @use(i1 [[WC]])
 ; CHECK-NEXT:    [[LHS:%.*]] = select i1 [[B]], i1 [[WC]], i1 false
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[LHS]], [[A]]
+; CHECK-NEXT:    [[AND:%.*]] = select i1 [[LHS]], i1 [[A]], i1 false
 ; CHECK-NEXT:    ret i1 [[AND]]
 ;
   call void @use(i1 %a)
   call void @use(i1 %b)
   %wc = call i1 @llvm.experimental.widenable.condition()
   call void @use(i1 %wc)
   %lhs = select i1 %b, i1 %wc, i1 false
   %and = select i1 %lhs, i1 %a, i1 false
;
   %lhs = and i1 %wc, %b
   %and = and i1 %lhs, %a
   ret i1 %and
 }
 
 define i1 @test2_logical(i1 %a, i1 %b) {
 ; CHECK-LABEL: @test2_logical(
 ; CHECK-NEXT:    [[WC:%.*]] = call i1 @llvm.experimental.widenable.condition()
-; CHECK-NEXT:    [[LHS:%.*]] = and i1 [[WC]], [[B:%.*]]
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[LHS]], [[A:%.*]]
+; CHECK-NEXT:    [[LHS:%.*]] = select i1 [[WC]], i1 [[B:%.*]], i1 false
+; CHECK-NEXT:    [[AND:%.*]] = select i1 [[LHS]], i1 [[A:%.*]], i1 false
 ; CHECK-NEXT:    ret i1 [[AND]]
 ;
   %wc = call i1 @llvm.experimental.widenable.condition()
   %lhs = select i1 %wc, i1 %b, i1 false
   %and = select i1 %lhs, i1 %a, i1 false
   ret i1 %and
 }
 
;
   %rhs = and i1 %c, %wc
   %and = and i1 %lhs, %rhs
   ret i1 %and
 }
 
 define i1 @test3_logical(i1 %a, i1 %b, i1 %c) {
 ; CHECK-LABEL: @test3_logical(
 ; CHECK-NEXT:    [[WC:%.*]] = call i1 @llvm.experimental.widenable.condition()
-; CHECK-NEXT:    [[LHS:%.*]] = and i1 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT:    [[RHS:%.*]] = select i1 [[C:%.*]], i1 [[WC]], i1 false
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[LHS]], [[RHS]]
+; CHECK-NEXT:    [[LHS:%.*]] = select i1 [[A:%.*]], i1 [[B:%.*]], i1 false
+; CHECK-NEXT:    [[TMP1:%.*]] = select i1 [[LHS]], i1 [[C:%.*]], i1 false
+; CHECK-NEXT:    [[AND:%.*]] = select i1 [[TMP1]], i1 [[WC]], i1 false
 ; CHECK-NEXT:    ret i1 [[AND]]
 ;
   %wc = call i1 @llvm.experimental.widenable.condition()
   %lhs = select i1 %a, i1 %b, i1 false
   %rhs = select i1 %c, i1 %wc, i1 false
   %and = select i1 %lhs, i1 %rhs, i1 false
   ret i1 %and
 }
;
   %rhs = and i1 %wc, %c
   %and = and i1 %lhs, %rhs
   ret i1 %and
 }
 
 define i1 @test4_logical(i1 %a, i1 %b, i1 %c) {
 ; CHECK-LABEL: @test4_logical(
 ; CHECK-NEXT:    [[WC:%.*]] = call i1 @llvm.experimental.widenable.condition()
-; CHECK-NEXT:    [[LHS:%.*]] = and i1 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT:    [[RHS:%.*]] = and i1 [[WC]], [[C:%.*]]
-; CHECK-NEXT:    [[AND:%.*]] = select i1 [[LHS]], i1 [[RHS]], i1 false
+; CHECK-NEXT:    [[LHS:%.*]] = select i1 [[A:%.*]], i1 [[B:%.*]], i1 false
+; CHECK-NEXT:    [[TMP1:%.*]] = select i1 [[LHS]], i1 [[WC]], i1 false
+; CHECK-NEXT:    [[AND:%.*]] = select i1 [[TMP1]], i1 [[C:%.*]], i1 false
 ; CHECK-NEXT:    ret i1 [[AND]]
 ;
   %wc = call i1 @llvm.experimental.widenable.condition()
   %lhs = select i1 %a, i1 %b, i1 false
   %rhs = select i1 %wc, i1 %c, i1 false
   %and = select i1 %lhs, i1 %rhs, i1 false
   ret i1 %and
 }

llvm/test/Transforms/InstCombine/zext-or-icmp.ll

;
   %bothCond = or i1 %toBool1, %toBool2
   %zext = zext i1 %bothCond to i8
   ret i8 %zext
 }
 
 define i8 @zext_or_icmp_icmp_logical(i8 %a, i8 %b) {
 ; CHECK-LABEL: @zext_or_icmp_icmp_logical(
 ; CHECK-NEXT:    [[MASK:%.*]] = and i8 [[A:%.*]], 1
+; CHECK-NEXT:    [[TOBOOL1:%.*]] = icmp eq i8 [[MASK]], 0
 ; CHECK-NEXT:    [[TOBOOL2:%.*]] = icmp eq i8 [[B:%.*]], 0
-; CHECK-NEXT:    [[TOBOOL22:%.*]] = zext i1 [[TOBOOL2]] to i8
-; CHECK-NEXT:    [[TMP1:%.*]] = xor i8 [[MASK]], 1
-; CHECK-NEXT:    [[ZEXT3:%.*]] = or i8 [[TMP1]], [[TOBOOL22]]
-; CHECK-NEXT:    ret i8 [[ZEXT3]]
+; CHECK-NEXT:    [[BOTHCOND:%.*]] = select i1 [[TOBOOL1]], i1 true, i1 [[TOBOOL2]]
+; CHECK-NEXT:    [[ZEXT:%.*]] = zext i1 [[BOTHCOND]] to i8
+; CHECK-NEXT:    ret i8 [[ZEXT]]
 ;
   %mask = and i8 %a, 1
   %toBool1 = icmp eq i8 %mask, 0
   %toBool2 = icmp eq i8 %b, 0
   %bothCond = select i1 %toBool1, i1 true, i1 %toBool2
   %zext = zext i1 %bothCond to i8
   ret i8 %zext
 }

llvm/test/Transforms/LoopSimplify/merge-exits.ll

 ; CHECK-NEXT:    [[T3:%.*]] = load float, float* [[T2]], align 4
 ; CHECK-NEXT:    [[T4]] = fadd float [[T3]], [[DISTERBHI_04]]
 ; CHECK-NEXT:    [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
 ; CHECK-NEXT:    [[T7:%.*]] = getelementptr float, float* [[PEAKWEIGHT]], i64 [[INDVARS_IV_NEXT]]
 ; CHECK-NEXT:    [[T8:%.*]] = load float, float* [[T7]], align 4
 ; CHECK-NEXT:    [[T9]] = fadd float [[T8]], [[PEAKCOUNT_02]]
 ; CHECK-NEXT:    [[T10:%.*]] = fcmp olt float [[T4]], 2.500000e+00
 ; CHECK-NEXT:    [[T12:%.*]] = icmp sgt i64 [[TMP0]], [[INDVARS_IV_NEXT]]
-; CHECK-NEXT:    [[OR_COND:%.*]] = and i1 [[T10]], [[T12]]
+; CHECK-NEXT:    [[OR_COND:%.*]] = select i1 [[T10]], i1 [[T12]], i1 false
 ; CHECK-NEXT:    br i1 [[OR_COND]], label [[BB]], label [[BB1_BB3_CRIT_EDGE:%.*]]
 ; CHECK:       bb1.bb3_crit_edge:
 ; CHECK-NEXT:    [[T4_LCSSA:%.*]] = phi float [ [[T4]], [[BB]] ]
 ; CHECK-NEXT:    [[T9_LCSSA:%.*]] = phi float [ [[T9]], [[BB]] ]
 ; CHECK-NEXT:    br label [[BB3]]
 ; CHECK:       bb3:
 ; CHECK-NEXT:    [[PEAKCOUNT_0_LCSSA:%.*]] = phi float [ [[T9_LCSSA]], [[BB1_BB3_CRIT_EDGE]] ], [ [[T0]], [[ENTRY:%.*]] ]
 ; CHECK-NEXT:    [[DISTERBHI_0_LCSSA:%.*]] = phi float [ [[T4_LCSSA]], [[BB1_BB3_CRIT_EDGE]] ], [ 0.000000e+00, [[ENTRY]] ]

 ; CHECK-NEXT:    [[T3:%.*]] = load float, float* [[T2]], align 4
 ; CHECK-NEXT:    [[T4]] = fadd float [[T3]], [[DISTERBHI_04]]
 ; CHECK-NEXT:    [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
 ; CHECK-NEXT:    [[T7:%.*]] = getelementptr float, float* [[PEAKWEIGHT]], i64 [[INDVARS_IV_NEXT]]
 ; CHECK-NEXT:    [[T8:%.*]] = load float, float* [[T7]], align 4
 ; CHECK-NEXT:    [[T9]] = fadd float [[T8]], [[PEAKCOUNT_02]]
 ; CHECK-NEXT:    [[T10:%.*]] = fcmp olt float [[T4]], 2.500000e+00
 ; CHECK-NEXT:    [[T12:%.*]] = icmp sgt i64 [[TMP0]], [[INDVARS_IV_NEXT]]
-; CHECK-NEXT:    [[OR_COND:%.*]] = and i1 [[T10]], [[T12]]
+; CHECK-NEXT:    [[OR_COND:%.*]] = select i1 [[T10]], i1 [[T12]], i1 false
 ; CHECK-NEXT:    br i1 [[OR_COND]], label [[BB]], label [[BB1_BB3_CRIT_EDGE:%.*]], !prof !0
 ; CHECK:       bb1.bb3_crit_edge:
 ; CHECK-NEXT:    [[T4_LCSSA:%.*]] = phi float [ [[T4]], [[BB]] ]
 ; CHECK-NEXT:    [[T9_LCSSA:%.*]] = phi float [ [[T9]], [[BB]] ]
 ; CHECK-NEXT:    br label [[BB3]]
 ; CHECK:       bb3:
 ; CHECK-NEXT:    [[PEAKCOUNT_0_LCSSA:%.*]] = phi float [ [[T9_LCSSA]], [[BB1_BB3_CRIT_EDGE]] ], [ [[T0]], [[ENTRY:%.*]] ]
 ; CHECK-NEXT:    [[DISTERBHI_0_LCSSA:%.*]] = phi float [ [[T4_LCSSA]], [[BB1_BB3_CRIT_EDGE]] ], [ 0.000000e+00, [[ENTRY]] ]

llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-accesses-masked-group.ll

 ; DISABLED_MASKED_STRIDED-NEXT:    [[BROADCAST_SPLAT2:%.*]] = shufflevector <8 x i32> [[BROADCAST_SPLATINSERT1]], <8 x i32> poison, <8 x i32> zeroinitializer
 ; DISABLED_MASKED_STRIDED-NEXT:    br label [[VECTOR_BODY:%.*]]
 ; DISABLED_MASKED_STRIDED:       vector.body:
 ; DISABLED_MASKED_STRIDED-NEXT:    [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_LOAD_CONTINUE16:%.*]] ]
 ; DISABLED_MASKED_STRIDED-NEXT:    [[VEC_IND:%.*]] = phi <8 x i32> [ <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[PRED_LOAD_CONTINUE16]] ]
 ; DISABLED_MASKED_STRIDED-NEXT:    [[TMP0:%.*]] = icmp ugt <8 x i32> [[VEC_IND]], [[BROADCAST_SPLAT2]]
 ; DISABLED_MASKED_STRIDED-NEXT:    [[TMP1:%.*]] = icmp ule <8 x i32> [[VEC_IND]], [[BROADCAST_SPLAT]]
 ; DISABLED_MASKED_STRIDED-NEXT:    [[TMP2:%.*]] = shl nuw nsw <8 x i32> [[VEC_IND]], <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
-; DISABLED_MASKED_STRIDED-NEXT:    [[TMP3:%.*]] = and <8 x i1> [[TMP1]], [[TMP0]]
+; DISABLED_MASKED_STRIDED-NEXT:    [[TMP3:%.*]] = select <8 x i1> [[TMP1]], <8 x i1> [[TMP0]], <8 x i1> zeroinitializer
 ; DISABLED_MASKED_STRIDED-NEXT:    [[TMP4:%.*]] = extractelement <8 x i1> [[TMP3]], i32 0
 ; DISABLED_MASKED_STRIDED-NEXT:    br i1 [[TMP4]], label [[PRED_LOAD_IF:%.*]], label [[PRED_LOAD_CONTINUE:%.*]]
 ; DISABLED_MASKED_STRIDED:       pred.load.if:
 ; DISABLED_MASKED_STRIDED-NEXT:    [[TMP5:%.*]] = extractelement <8 x i32> [[TMP2]], i32 0
 ; DISABLED_MASKED_STRIDED-NEXT:    [[TMP6:%.*]] = getelementptr inbounds i8, i8* [[P:%.*]], i32 [[TMP5]]
 ; DISABLED_MASKED_STRIDED-NEXT:    [[TMP7:%.*]] = load i8, i8* [[TMP6]], align 1
 ; DISABLED_MASKED_STRIDED-NEXT:    [[TMP8:%.*]] = insertelement <8 x i8> poison, i8 [[TMP7]], i32 0
 ; DISABLED_MASKED_STRIDED-NEXT:    br label [[PRED_LOAD_CONTINUE]]

 ; ENABLED_MASKED_STRIDED-NEXT:    br label [[VECTOR_BODY:%.*]]
 ; ENABLED_MASKED_STRIDED:       vector.body:
 ; ENABLED_MASKED_STRIDED-NEXT:    [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
 ; ENABLED_MASKED_STRIDED-NEXT:    [[VEC_IND:%.*]] = phi <8 x i32> [ <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ]
 ; ENABLED_MASKED_STRIDED-NEXT:    [[TMP0:%.*]] = icmp ugt <8 x i32> [[VEC_IND]], [[BROADCAST_SPLAT2]]
 ; ENABLED_MASKED_STRIDED-NEXT:    [[TMP1:%.*]] = icmp ule <8 x i32> [[VEC_IND]], [[BROADCAST_SPLAT]]
 ; ENABLED_MASKED_STRIDED-NEXT:    [[TMP2:%.*]] = shl nuw nsw i32 [[INDEX]], 1
 ; ENABLED_MASKED_STRIDED-NEXT:    [[TMP3:%.*]] = getelementptr inbounds i8, i8* [[P:%.*]], i32 [[TMP2]]
-; ENABLED_MASKED_STRIDED-NEXT:    [[TMP4:%.*]] = and <8 x i1> [[TMP1]], [[TMP0]]
+; ENABLED_MASKED_STRIDED-NEXT:    [[TMP4:%.*]] = select <8 x i1> [[TMP1]], <8 x i1> [[TMP0]], <8 x i1> zeroinitializer
 ; ENABLED_MASKED_STRIDED-NEXT:    [[TMP5:%.*]] = bitcast i8* [[TMP3]] to <16 x i8>*
 ; ENABLED_MASKED_STRIDED-NEXT:    [[INTERLEAVED_MASK:%.*]] = shufflevector <8 x i1> [[TMP4]], <8 x i1> poison, <16 x i32> <i32 0, i32 0, i32 1, i32 1, i32 2, i32 2, i32 3, i32 3, i32 4, i32 4, i32 5, i32 5, i32 6, i32 6, i32 7, i32 7>
 ; ENABLED_MASKED_STRIDED-NEXT:    [[TMP6:%.*]] = and <16 x i1> [[INTERLEAVED_MASK]], <i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false>
 ; ENABLED_MASKED_STRIDED-NEXT:    [[WIDE_MASKED_VEC:%.*]] = call <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>* [[TMP5]], i32 1, <16 x i1> [[TMP6]], <16 x i8> poison)
 ; ENABLED_MASKED_STRIDED-NEXT:    [[STRIDED_VEC:%.*]] = shufflevector <16 x i8> [[WIDE_MASKED_VEC]], <16 x i8> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
 ; ENABLED_MASKED_STRIDED-NEXT:    [[TMP7:%.*]] = getelementptr inbounds i8, i8* [[Q:%.*]], i32 [[INDEX]]
 ; ENABLED_MASKED_STRIDED-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP7]] to <8 x i8>*
 ; ENABLED_MASKED_STRIDED-NEXT:    call void @llvm.masked.store.v8i8.p0v8i8(<8 x i8> [[STRIDED_VEC]], <8 x i8>* [[TMP8]], i32 1, <8 x i1> [[TMP4]])

 ; DISABLED_MASKED_STRIDED-NEXT:    [[BROADCAST_SPLAT2:%.*]] = shufflevector <8 x i32> [[BROADCAST_SPLATINSERT1]], <8 x i32> poison, <8 x i32> zeroinitializer
 ; DISABLED_MASKED_STRIDED-NEXT:    br label [[VECTOR_BODY:%.*]]
 ; DISABLED_MASKED_STRIDED:       vector.body:
 ; DISABLED_MASKED_STRIDED-NEXT:    [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_LOAD_CONTINUE16:%.*]] ]
 ; DISABLED_MASKED_STRIDED-NEXT:    [[VEC_IND:%.*]] = phi <8 x i32> [ <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[PRED_LOAD_CONTINUE16]] ]
 ; DISABLED_MASKED_STRIDED-NEXT:    [[TMP0:%.*]] = icmp ugt <8 x i32> [[VEC_IND]], [[BROADCAST_SPLAT2]]
 ; DISABLED_MASKED_STRIDED-NEXT:    [[TMP1:%.*]] = icmp ule <8 x i32> [[VEC_IND]], [[BROADCAST_SPLAT]]
 ; DISABLED_MASKED_STRIDED-NEXT:    [[TMP2:%.*]] = mul nsw <8 x i32> [[VEC_IND]], <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
-; DISABLED_MASKED_STRIDED-NEXT:    [[TMP3:%.*]] = and <8 x i1> [[TMP1]], [[TMP0]]
+; DISABLED_MASKED_STRIDED-NEXT:    [[TMP3:%.*]] = select <8 x i1> [[TMP1]], <8 x i1> [[TMP0]], <8 x i1> zeroinitializer
 ; DISABLED_MASKED_STRIDED-NEXT:    [[TMP4:%.*]] = extractelement <8 x i1> [[TMP3]], i32 0
 ; DISABLED_MASKED_STRIDED-NEXT:    br i1 [[TMP4]], label [[PRED_LOAD_IF:%.*]], label [[PRED_LOAD_CONTINUE:%.*]]
 ; DISABLED_MASKED_STRIDED:       pred.load.if:
 ; DISABLED_MASKED_STRIDED-NEXT:    [[TMP5:%.*]] = extractelement <8 x i32> [[TMP2]], i32 0
 ; DISABLED_MASKED_STRIDED-NEXT:    [[TMP6:%.*]] = getelementptr inbounds i8, i8* [[P:%.*]], i32 [[TMP5]]
 ; DISABLED_MASKED_STRIDED-NEXT:    [[TMP7:%.*]] = load i8, i8* [[TMP6]], align 1
 ; DISABLED_MASKED_STRIDED-NEXT:    [[TMP8:%.*]] = insertelement <8 x i8> poison, i8 [[TMP7]], i32 0
 ; DISABLED_MASKED_STRIDED-NEXT:    br label [[PRED_LOAD_CONTINUE]]

 ; ENABLED_MASKED_STRIDED-NEXT:    br label [[VECTOR_BODY:%.*]]
 ; ENABLED_MASKED_STRIDED:       vector.body:
 ; ENABLED_MASKED_STRIDED-NEXT:    [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
 ; ENABLED_MASKED_STRIDED-NEXT:    [[VEC_IND:%.*]] = phi <8 x i32> [ <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ]
 ; ENABLED_MASKED_STRIDED-NEXT:    [[TMP0:%.*]] = icmp ugt <8 x i32> [[VEC_IND]], [[BROADCAST_SPLAT2]]
 ; ENABLED_MASKED_STRIDED-NEXT:    [[TMP1:%.*]] = icmp ule <8 x i32> [[VEC_IND]], [[BROADCAST_SPLAT]]
 ; ENABLED_MASKED_STRIDED-NEXT:    [[TMP2:%.*]] = mul nsw i32 [[INDEX]], 3
 ; ENABLED_MASKED_STRIDED-NEXT:    [[TMP3:%.*]] = getelementptr inbounds i8, i8* [[P:%.*]], i32 [[TMP2]]
-; ENABLED_MASKED_STRIDED-NEXT:    [[TMP4:%.*]] = and <8 x i1> [[TMP1]], [[TMP0]]
+; ENABLED_MASKED_STRIDED-NEXT:    [[TMP4:%.*]] = select <8 x i1> [[TMP1]], <8 x i1> [[TMP0]], <8 x i1> zeroinitializer
 ; ENABLED_MASKED_STRIDED-NEXT:    [[TMP5:%.*]] = bitcast i8* [[TMP3]] to <24 x i8>*
 ; ENABLED_MASKED_STRIDED-NEXT:    [[INTERLEAVED_MASK:%.*]] = shufflevector <8 x i1> [[TMP4]], <8 x i1> poison, <24 x i32> <i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 2, i32 2, i32 2, i32 3, i32 3, i32 3, i32 4, i32 4, i32 4, i32 5, i32 5, i32 5, i32 6, i32 6, i32 6, i32 7, i32 7, i32 7>
 ; ENABLED_MASKED_STRIDED-NEXT:    [[TMP6:%.*]] = and <24 x i1> [[INTERLEAVED_MASK]], <i1 true, i1 false, i1 false, i1 true, i1 false, i1 false, i1 true, i1 false, i1 false, i1 true, i1 false, i1 false, i1 true, i1 false, i1 false, i1 true, i1 false, i1 false, i1 true, i1 false, i1 false, i1 true, i1 false, i1 false>
 ; ENABLED_MASKED_STRIDED-NEXT:    [[WIDE_MASKED_VEC:%.*]] = call <24 x i8> @llvm.masked.load.v24i8.p0v24i8(<24 x i8>* [[TMP5]], i32 1, <24 x i1> [[TMP6]], <24 x i8> poison)
 ; ENABLED_MASKED_STRIDED-NEXT:    [[STRIDED_VEC:%.*]] = shufflevector <24 x i8> [[WIDE_MASKED_VEC]], <24 x i8> poison, <8 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21>
 ; ENABLED_MASKED_STRIDED-NEXT:    [[TMP7:%.*]] = getelementptr inbounds i8, i8* [[Q:%.*]], i32 [[INDEX]]
 ; ENABLED_MASKED_STRIDED-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP7]] to <8 x i8>*
 ; ENABLED_MASKED_STRIDED-NEXT:    call void @llvm.masked.store.v8i8.p0v8i8(<8 x i8> [[STRIDED_VEC]], <8 x i8>* [[TMP8]], i32 1, <8 x i1> [[TMP4]])

 ; DISABLED_MASKED_STRIDED-NEXT:    [[BROADCAST_SPLAT2:%.*]] = shufflevector <8 x i32> [[BROADCAST_SPLATINSERT1]], <8 x i32> poison, <8 x i32> zeroinitializer
 ; DISABLED_MASKED_STRIDED-NEXT:    br label [[VECTOR_BODY:%.*]]
 ; DISABLED_MASKED_STRIDED:       vector.body:
 ; DISABLED_MASKED_STRIDED-NEXT:    [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE62:%.*]] ]
 ; DISABLED_MASKED_STRIDED-NEXT:    [[VEC_IND:%.*]] = phi <8 x i32> [ <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[PRED_STORE_CONTINUE62]] ]
 ; DISABLED_MASKED_STRIDED-NEXT:    [[TMP0:%.*]] = icmp sgt <8 x i32> [[VEC_IND]], [[BROADCAST_SPLAT2]]
 ; DISABLED_MASKED_STRIDED-NEXT:    [[TMP1:%.*]] = icmp ule <8 x i32> [[VEC_IND]], [[BROADCAST_SPLAT]]
 ; DISABLED_MASKED_STRIDED-NEXT:    [[TMP2:%.*]] = shl nuw nsw <8 x i32> [[VEC_IND]], <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
-; DISABLED_MASKED_STRIDED-NEXT:    [[TMP3:%.*]] = and <8 x i1> [[TMP1]], [[TMP0]]
+; DISABLED_MASKED_STRIDED-NEXT:    [[TMP3:%.*]] = select <8 x i1> [[TMP1]], <8 x i1> [[TMP0]], <8 x i1> zeroinitializer
 ; DISABLED_MASKED_STRIDED-NEXT:    [[TMP4:%.*]] = extractelement <8 x i1> [[TMP3]], i32 0
 ; DISABLED_MASKED_STRIDED-NEXT:    br i1 [[TMP4]], label [[PRED_LOAD_IF:%.*]], label [[PRED_LOAD_CONTINUE:%.*]]
 ; DISABLED_MASKED_STRIDED:       pred.load.if:
 ; DISABLED_MASKED_STRIDED-NEXT:    [[TMP5:%.*]] = extractelement <8 x i32> [[TMP2]], i32 0
 ; DISABLED_MASKED_STRIDED-NEXT:    [[TMP6:%.*]] = getelementptr inbounds i8, i8* [[P:%.*]], i32 [[TMP5]]
 ; DISABLED_MASKED_STRIDED-NEXT:    [[TMP7:%.*]] = load i8, i8* [[TMP6]], align 1
 ; DISABLED_MASKED_STRIDED-NEXT:    [[TMP8:%.*]] = insertelement <8 x i8> poison, i8 [[TMP7]], i32 0
 ; DISABLED_MASKED_STRIDED-NEXT:    br label [[PRED_LOAD_CONTINUE]]

 ; ENABLED_MASKED_STRIDED-NEXT:    br label [[VECTOR_BODY:%.*]]
 ; ENABLED_MASKED_STRIDED:       vector.body:
 ; ENABLED_MASKED_STRIDED-NEXT:    [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
 ; ENABLED_MASKED_STRIDED-NEXT:    [[VEC_IND:%.*]] = phi <8 x i32> [ <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ]
 ; ENABLED_MASKED_STRIDED-NEXT:    [[TMP0:%.*]] = icmp sgt <8 x i32> [[VEC_IND]], [[BROADCAST_SPLAT2]]
 ; ENABLED_MASKED_STRIDED-NEXT:    [[TMP1:%.*]] = icmp ule <8 x i32> [[VEC_IND]], [[BROADCAST_SPLAT]]
 ; ENABLED_MASKED_STRIDED-NEXT:    [[TMP2:%.*]] = shl nuw nsw i32 [[INDEX]], 1
 ; ENABLED_MASKED_STRIDED-NEXT:    [[TMP3:%.*]] = getelementptr inbounds i8, i8* [[P:%.*]], i32 [[TMP2]]
-; ENABLED_MASKED_STRIDED-NEXT:    [[TMP4:%.*]] = and <8 x i1> [[TMP1]], [[TMP0]]
+; ENABLED_MASKED_STRIDED-NEXT:    [[TMP4:%.*]] = select <8 x i1> [[TMP1]], <8 x i1> [[TMP0]], <8 x i1> zeroinitializer
 ; ENABLED_MASKED_STRIDED-NEXT:    [[TMP5:%.*]] = bitcast i8* [[TMP3]] to <16 x i8>*
 ; ENABLED_MASKED_STRIDED-NEXT:    [[INTERLEAVED_MASK:%.*]] = shufflevector <8 x i1> [[TMP4]], <8 x i1> poison, <16 x i32> <i32 0, i32 0, i32 1, i32 1, i32 2, i32 2, i32 3, i32 3, i32 4, i32 4, i32 5, i32 5, i32 6, i32 6, i32 7, i32 7>
 ; ENABLED_MASKED_STRIDED-NEXT:    [[WIDE_MASKED_VEC:%.*]] = call <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>* [[TMP5]], i32 1, <16 x i1> [[INTERLEAVED_MASK]], <16 x i8> poison)
 ; ENABLED_MASKED_STRIDED-NEXT:    [[STRIDED_VEC:%.*]] = shufflevector <16 x i8> [[WIDE_MASKED_VEC]], <16 x i8> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
 ; ENABLED_MASKED_STRIDED-NEXT:    [[STRIDED_VEC3:%.*]] = shufflevector <16 x i8> [[WIDE_MASKED_VEC]], <16 x i8> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
 ; ENABLED_MASKED_STRIDED-NEXT:    [[TMP6:%.*]] = or i32 [[TMP2]], 1
 ; ENABLED_MASKED_STRIDED-NEXT:    [[TMP7:%.*]] = icmp slt <8 x i8> [[STRIDED_VEC]], [[STRIDED_VEC3]]
 ; ENABLED_MASKED_STRIDED-NEXT:    [[TMP8:%.*]] = select <8 x i1> [[TMP7]], <8 x i8> [[STRIDED_VEC3]], <8 x i8> [[STRIDED_VEC]]

llvm/test/Transforms/LoopVectorize/reduction-inloop-pred.ll

 ; CHECK-NEXT:    [[TMP7:%.*]] = fcmp ogt <4 x float> [[WIDE_LOAD]], <float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00>
 ; CHECK-NEXT:    [[TMP8:%.*]] = and <4 x i1> [[TMP5]], [[TMP6]]
 ; CHECK-NEXT:    [[TMP9:%.*]] = and <4 x i1> [[TMP8]], [[TMP7]]
 ; CHECK-NEXT:    [[TMP10:%.*]] = xor <4 x i1> [[TMP7]], <i1 true, i1 true, i1 true, i1 true>
 ; CHECK-NEXT:    [[TMP11:%.*]] = and <4 x i1> [[TMP8]], [[TMP10]]
 ; CHECK-NEXT:    [[TMP12:%.*]] = xor <4 x i1> [[TMP5]], <i1 true, i1 true, i1 true, i1 true>
 ; CHECK-NEXT:    [[PREDPHI_V:%.*]] = select <4 x i1> [[TMP9]], <4 x float> [[WIDE_LOAD1]], <4 x float> [[WIDE_LOAD]]
 ; CHECK-NEXT:    [[PREDPHI:%.*]] = fadd fast <4 x float> [[VEC_PHI]], [[PREDPHI_V]]
-; CHECK-NEXT:    [[TMP13:%.*]] = or <4 x i1> [[TMP11]], [[TMP12]]
+; CHECK-NEXT:    [[TMP13:%.*]] = select <4 x i1> [[TMP12]], <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i1> [[TMP11]]
 ; CHECK-NEXT:    [[PREDPHI3]] = select <4 x i1> [[TMP13]], <4 x float> [[VEC_PHI]], <4 x float> [[PREDPHI]]
 ; CHECK-NEXT:    [[INDEX_NEXT]] = add i64 [[INDEX]], 4
 ; CHECK-NEXT:    [[TMP14:%.*]] = icmp eq i64 [[INDEX_NEXT]], 128
 ; CHECK-NEXT:    br i1 [[TMP14]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP28:![0-9]+]]
 ; CHECK:       middle.block:
 ; CHECK-NEXT:    [[TMP15:%.*]] = call fast float @llvm.vector.reduce.fadd.v4f32(float -0.000000e+00, <4 x float> [[PREDPHI3]])
 ; CHECK-NEXT:    br i1 true, label [[FOR_END:%.*]], label [[SCALAR_PH]]
 ; CHECK:       scalar.ph:

llvm/test/Transforms/LoopVectorize/reduction-inloop.ll

 ; CHECK-NEXT:    [[TMP7:%.*]] = fcmp ogt <4 x float> [[WIDE_LOAD]], <float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00>
 ; CHECK-NEXT:    [[TMP8:%.*]] = and <4 x i1> [[TMP5]], [[TMP6]]
 ; CHECK-NEXT:    [[TMP9:%.*]] = and <4 x i1> [[TMP8]], [[TMP7]]
 ; CHECK-NEXT:    [[TMP10:%.*]] = xor <4 x i1> [[TMP7]], <i1 true, i1 true, i1 true, i1 true>
 ; CHECK-NEXT:    [[TMP11:%.*]] = and <4 x i1> [[TMP8]], [[TMP10]]
 ; CHECK-NEXT:    [[TMP12:%.*]] = xor <4 x i1> [[TMP5]], <i1 true, i1 true, i1 true, i1 true>
 ; CHECK-NEXT:    [[PREDPHI_V:%.*]] = select <4 x i1> [[TMP9]], <4 x float> [[WIDE_LOAD1]], <4 x float> [[WIDE_LOAD]]
 ; CHECK-NEXT:    [[PREDPHI:%.*]] = fadd fast <4 x float> [[VEC_PHI]], [[PREDPHI_V]]
-; CHECK-NEXT:    [[TMP13:%.*]] = or <4 x i1> [[TMP11]], [[TMP12]]
+; CHECK-NEXT:    [[TMP13:%.*]] = select <4 x i1> [[TMP12]], <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i1> [[TMP11]]
 ; CHECK-NEXT:    [[PREDPHI3]] = select <4 x i1> [[TMP13]], <4 x float> [[VEC_PHI]], <4 x float> [[PREDPHI]]
 ; CHECK-NEXT:    [[INDEX_NEXT]] = add i64 [[INDEX]], 4
 ; CHECK-NEXT:    [[TMP14:%.*]] = icmp eq i64 [[INDEX_NEXT]], 128
 ; CHECK-NEXT:    br i1 [[TMP14]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP32:![0-9]+]]
 ; CHECK:       middle.block:
 ; CHECK-NEXT:    [[TMP15:%.*]] = call fast float @llvm.vector.reduce.fadd.v4f32(float -0.000000e+00, <4 x float> [[PREDPHI3]])
 ; CHECK-NEXT:    br i1 true, label [[FOR_END:%.*]], label [[SCALAR_PH]]
 ; CHECK:       scalar.ph:

llvm/test/Transforms/PGOProfile/chr.ll

 ; return i0 + sum3
 ; ->
 ; (no change)
 define i32 @test_chr_15(i32* %i, i32* %j, i32 %sum0, i1 %pred, i32 %z) !prof !14 {
 ; CHECK-LABEL: @test_chr_15(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[I0:%.*]] = load i32, i32* [[I:%.*]], align 4
 ; CHECK-NEXT:    [[V0:%.*]] = icmp eq i32 [[Z:%.*]], 0
-; CHECK-NEXT:    [[V3:%.*]] = and i1 [[V0]], [[PRED:%.*]]
+; CHECK-NEXT:    [[V3:%.*]] = select i1 [[V0]], i1 [[PRED:%.*]], i1 false
 ; CHECK-NEXT:    br i1 [[V3]], label [[BB0:%.*]], label [[BB1:%.*]], !prof !16
 ; CHECK:       bb0:
 ; CHECK-NEXT:    call void @foo()
 ; CHECK-NEXT:    br label [[BB1]]
 ; CHECK:       bb1:
 ; CHECK-NEXT:    [[J0:%.*]] = load i32, i32* [[J:%.*]], align 4
 ; CHECK-NEXT:    [[V6:%.*]] = and i32 [[I0]], 2
 ; CHECK-NEXT:    [[V4:%.*]] = icmp eq i32 [[V6]], [[J0]]

llvm/test/Transforms/PhaseOrdering/X86/vector-reductions.ll

for.end:
   %cmp3 = fcmp fast ole float %sum.0, %Tolerance
   %2 = zext i1 %cmp3 to i64
   %cond = select i1 %cmp3, i32 1, i32 0
   ret i32 %cond
 }
 
 ; PR43745 - https://bugs.llvm.org/show_bug.cgi?id=43745
 
+; FIXME: this should be vectorized
 define i1 @cmp_lt_gt(double %a, double %b, double %c) {
 ; CHECK-LABEL: @cmp_lt_gt(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[FNEG:%.*]] = fneg double [[B:%.*]]
+; CHECK-NEXT:    [[ADD:%.*]] = fsub double [[C:%.*]], [[B]]
 ; CHECK-NEXT:    [[MUL:%.*]] = fmul double [[A:%.*]], 2.000000e+00
-; CHECK-NEXT:    [[TMP0:%.*]] = insertelement <2 x double> poison, double [[C:%.*]], i32 0
-; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> [[TMP0]], double [[FNEG]], i32 1
-; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <2 x double> poison, double [[B]], i32 0
-; CHECK-NEXT:    [[TMP3:%.*]] = insertelement <2 x double> [[TMP2]], double [[C]], i32 1
-; CHECK-NEXT:    [[TMP4:%.*]] = fsub <2 x double> [[TMP1]], [[TMP3]]
-; CHECK-NEXT:    [[TMP5:%.*]] = insertelement <2 x double> poison, double [[MUL]], i32 0
-; CHECK-NEXT:    [[TMP6:%.*]] = shufflevector <2 x double> [[TMP5]], <2 x double> undef, <2 x i32> zeroinitializer
-; CHECK-NEXT:    [[TMP7:%.*]] = fdiv <2 x double> [[TMP4]], [[TMP6]]
-; CHECK-NEXT:    [[TMP8:%.*]] = fcmp olt <2 x double> [[TMP7]], <double 0x3EB0C6F7A0B5ED8D, double 0x3EB0C6F7A0B5ED8D>
-; CHECK-NEXT:    [[SHIFT:%.*]] = shufflevector <2 x i1> [[TMP8]], <2 x i1> poison, <2 x i32> <i32 1, i32 undef>
-; CHECK-NEXT:    [[TMP9:%.*]] = and <2 x i1> [[TMP8]], [[SHIFT]]
-; CHECK-NEXT:    [[OR_COND:%.*]] = extractelement <2 x i1> [[TMP9]], i64 0
+; CHECK-NEXT:    [[DIV:%.*]] = fdiv double [[ADD]], [[MUL]]
+; CHECK-NEXT:    [[SUB:%.*]] = fsub double [[FNEG]], [[C]]
+; CHECK-NEXT:    [[DIV3:%.*]] = fdiv double [[SUB]], [[MUL]]
+; CHECK-NEXT:    [[CMP:%.*]] = fcmp olt double [[DIV]], 0x3EB0C6F7A0B5ED8D
+; CHECK-NEXT:    [[CMP4:%.*]] = fcmp olt double [[DIV3]], 0x3EB0C6F7A0B5ED8D
+; CHECK-NEXT:    [[OR_COND:%.*]] = select i1 [[CMP]], i1 [[CMP4]], i1 false
 ; CHECK-NEXT:    br i1 [[OR_COND]], label [[CLEANUP:%.*]], label [[LOR_LHS_FALSE:%.*]]
 ; CHECK:       lor.lhs.false:
-; CHECK-NEXT:    [[TMP10:%.*]] = fcmp ule <2 x double> [[TMP7]], <double 1.000000e+00, double 1.000000e+00>
-; CHECK-NEXT:    [[SHIFT2:%.*]] = shufflevector <2 x i1> [[TMP10]], <2 x i1> poison, <2 x i32> <i32 1, i32 undef>
-; CHECK-NEXT:    [[TMP11:%.*]] = or <2 x i1> [[TMP10]], [[SHIFT2]]
-; CHECK-NEXT:    [[NOT_OR_COND1:%.*]] = extractelement <2 x i1> [[TMP11]], i32 0
-; CHECK-NEXT:    ret i1 [[NOT_OR_COND1]]
+; CHECK-NEXT:    [[CMP5:%.*]] = fcmp ule double [[DIV]], 1.000000e+00
+; CHECK-NEXT:    [[CMP7:%.*]] = fcmp ule double [[DIV3]], 1.000000e+00
+; CHECK-NEXT:    [[OR_COND1:%.*]] = select i1 [[CMP5]], i1 true, i1 [[CMP7]]
+; CHECK-NEXT:    ret i1 [[OR_COND1]]
 ; CHECK:       cleanup:
 ; CHECK-NEXT:    ret i1 false
 ;
 entry:
   %fneg = fneg double %b
   %add = fadd double %fneg, %c
   %mul = fmul double 2.0, %a
   %div = fdiv double %add, %mul

llvm/test/Transforms/PhaseOrdering/unsigned-multiply-overflow-check.ll

 ; #include <limits>
 ; #include <cstdint>
 ;
 ; using size_type = std::size_t;
 ; bool will_not_overflow(size_type size, size_type nmemb) {
 ;   return (size != 0 && (nmemb > std::numeric_limits<size_type>::max() / size));
 ; }
 
 define i1 @will_not_overflow(i64 %arg, i64 %arg1) {
 ; SIMPLIFYCFG-LABEL: @will_not_overflow(
 ; SIMPLIFYCFG-NEXT:  bb:
 ; SIMPLIFYCFG-NEXT:    [[T0:%.*]] = icmp eq i64 [[ARG:%.*]], 0
 ; SIMPLIFYCFG-NEXT:    br i1 [[T0]], label [[BB5:%.*]], label [[BB2:%.*]]
 ; SIMPLIFYCFG:       bb2:
 ; SIMPLIFYCFG-NEXT:    [[T3:%.*]] = udiv i64 -1, [[ARG]]
 ; SIMPLIFYCFG-NEXT:    [[T4:%.*]] = icmp ult i64 [[T3]], [[ARG1:%.*]]
 ; SIMPLIFYCFG-NEXT:    br label [[BB5]]

 ; INSTCOMBINESIMPLIFYCFGONLY-NEXT:    [[T0:%.*]] = icmp eq i64 [[ARG:%.*]], 0
 ; INSTCOMBINESIMPLIFYCFGONLY-NEXT:    [[UMUL:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 [[ARG]], i64 [[ARG1:%.*]])
 ; INSTCOMBINESIMPLIFYCFGONLY-NEXT:    [[UMUL_OV:%.*]] = extractvalue { i64, i1 } [[UMUL]], 1
 ; INSTCOMBINESIMPLIFYCFGONLY-NEXT:    [[T6:%.*]] = select i1 [[T0]], i1 false, i1 [[UMUL_OV]]
 ; INSTCOMBINESIMPLIFYCFGONLY-NEXT:    ret i1 [[T6]]
 ;
 ; INSTCOMBINESIMPLIFYCFGINSTCOMBINE-LABEL: @will_not_overflow(
 ; INSTCOMBINESIMPLIFYCFGINSTCOMBINE-NEXT:  bb:
-; INSTCOMBINESIMPLIFYCFGINSTCOMBINE-NEXT:    [[UMUL:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 [[ARG:%.*]], i64 [[ARG1:%.*]])
+; INSTCOMBINESIMPLIFYCFGINSTCOMBINE-NEXT:    [[ARG1_FR:%.*]] = freeze i64 [[ARG1:%.*]]
+; INSTCOMBINESIMPLIFYCFGINSTCOMBINE-NEXT:    [[UMUL:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 [[ARG:%.*]], i64 [[ARG1_FR]])
 ; INSTCOMBINESIMPLIFYCFGINSTCOMBINE-NEXT:    [[UMUL_OV:%.*]] = extractvalue { i64, i1 } [[UMUL]], 1
 ; INSTCOMBINESIMPLIFYCFGINSTCOMBINE-NEXT:    ret i1 [[UMUL_OV]]
 ;
 bb:
   %t0 = icmp eq i64 %arg, 0
   br i1 %t0, label %bb5, label %bb2
 
 bb2:                                              ; preds = %bb

 ; INSTCOMBINESIMPLIFYCFGONLY-NEXT:    [[UMUL:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 [[ARG]], i64 [[ARG1:%.*]])
 ; INSTCOMBINESIMPLIFYCFGONLY-NEXT:    [[UMUL_OV:%.*]] = extractvalue { i64, i1 } [[UMUL]], 1
 ; INSTCOMBINESIMPLIFYCFGONLY-NEXT:    [[PHI_BO:%.*]] = xor i1 [[UMUL_OV]], true
 ; INSTCOMBINESIMPLIFYCFGONLY-NEXT:    [[T6:%.*]] = select i1 [[T0]], i1 true, i1 [[PHI_BO]]
 ; INSTCOMBINESIMPLIFYCFGONLY-NEXT:    ret i1 [[T6]]
 ;
 ; INSTCOMBINESIMPLIFYCFGINSTCOMBINE-LABEL: @will_overflow(
 ; INSTCOMBINESIMPLIFYCFGINSTCOMBINE-NEXT:  bb:
-; INSTCOMBINESIMPLIFYCFGINSTCOMBINE-NEXT:    [[UMUL:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 [[ARG:%.*]], i64 [[ARG1:%.*]])
+; INSTCOMBINESIMPLIFYCFGINSTCOMBINE-NEXT:    [[ARG1_FR:%.*]] = freeze i64 [[ARG1:%.*]]
+; INSTCOMBINESIMPLIFYCFGINSTCOMBINE-NEXT:    [[UMUL:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 [[ARG:%.*]], i64 [[ARG1_FR]])
 ; INSTCOMBINESIMPLIFYCFGINSTCOMBINE-NEXT:    [[UMUL_OV:%.*]] = extractvalue { i64, i1 } [[UMUL]], 1
 ; INSTCOMBINESIMPLIFYCFGINSTCOMBINE-NEXT:    [[PHI_BO:%.*]] = xor i1 [[UMUL_OV]], true
 ; INSTCOMBINESIMPLIFYCFGINSTCOMBINE-NEXT:    ret i1 [[PHI_BO]]
 ;
 bb:
   %t0 = icmp eq i64 %arg, 0
   br i1 %t0, label %bb5, label %bb2