[InstCombine] Support one-hot merge for logical and/or

[nikic]

Summary

If a logical and/or is used, we need to be careful not to propagate a potential poison value from the RHS by inserting a freeze instruction. Otherwise it works the same way as bitwise and/or.

This is intended to address the regression reported at https://reviews.llvm.org/D101191#2751002.

[nikic]

llvm/test/Transforms/InstCombine/onehot_merge.ll

69–73

As a side-note, it would probably make sense to push freeze instructions through one-use non-canCreateUndefOrPoison instructions. 1 << freeze(x) is better than freeze(1 << x).

[spatel]

LGTM

[sanwou01]

@nikic this fixed the regression, thank you!

llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp

foldAndOrOfEqualityCmpsWithConstants(ICmpInst *LHS, ICmpInst *RHS,
   return nullptr;
 }
 
 // Fold (iszero(A & K1) | iszero(A & K2)) -> (A & (K1 | K2)) != (K1 | K2)
 // Fold (!iszero(A & K1) & !iszero(A & K2)) -> (A & (K1 | K2)) == (K1 | K2)
 Value *InstCombinerImpl::foldAndOrOfICmpsOfAndWithPow2(ICmpInst *LHS,
                                                        ICmpInst *RHS,
                                                        Instruction *CxtI,
-                                                       bool IsAnd) {
+                                                       bool IsAnd,
+                                                       bool IsLogical) {
   CmpInst::Predicate Pred = IsAnd ? CmpInst::ICMP_NE : CmpInst::ICMP_EQ;
   if (LHS->getPredicate() != Pred || RHS->getPredicate() != Pred)
     return nullptr;
 
   if (!match(LHS->getOperand(1), m_Zero()) ||
       !match(RHS->getOperand(1), m_Zero()))
     return nullptr;
 
   Value *L1, *L2, *R1, *R2;
   if (match(LHS->getOperand(0), m_And(m_Value(L1), m_Value(L2))) &&
       match(RHS->getOperand(0), m_And(m_Value(R1), m_Value(R2)))) {
     if (L1 == R2 || L2 == R2)
       std::swap(R1, R2);
     if (L2 == R1)
       std::swap(L1, L2);
 
     if (L1 == R1 &&
         isKnownToBeAPowerOfTwo(L2, false, 0, CxtI) &&
         isKnownToBeAPowerOfTwo(R2, false, 0, CxtI)) {
+      // If this is a logical and/or, then we must prevent propagation of a
+      // poison value from the RHS by inserting freeze.
+      if (IsLogical)
+        R2 = Builder.CreateFreeze(R2);
       Value *Mask = Builder.CreateOr(L2, R2);
       Value *Masked = Builder.CreateAnd(L1, Mask);
       auto NewPred = IsAnd ? CmpInst::ICMP_EQ : CmpInst::ICMP_NE;
       return Builder.CreateICmp(NewPred, Masked, Mask);
     }
   }
 
   return nullptr;

llvm/lib/Transforms/InstCombine/InstCombineInternal.h

private:
   Value *foldXorOfICmps(ICmpInst *LHS, ICmpInst *RHS, BinaryOperator &Xor);
 
   /// Optimize (fcmp)&(fcmp) or (fcmp)|(fcmp).
   /// NOTE: Unlike most of instcombine, this returns a Value which should
   /// already be inserted into the function.
   Value *foldLogicOfFCmps(FCmpInst *LHS, FCmpInst *RHS, bool IsAnd);
 
   Value *foldAndOrOfICmpsOfAndWithPow2(ICmpInst *LHS, ICmpInst *RHS,
-                                       Instruction *CxtI, bool IsAnd);
+                                       Instruction *CxtI, bool IsAnd,
+                                       bool IsLogical = false);
   Value *matchSelectFromAndOr(Value *A, Value *B, Value *C, Value *D);
   Value *getSelectCondition(Value *A, Value *B);
 
   Instruction *foldIntrinsicWithOverflowCommon(IntrinsicInst *II);
   Instruction *foldFPSignBitOps(BinaryOperator &I);
 
   // Optimize one of these forms:
   //   and i1 Op, SI / select i1 Op, i1 SI, i1 false (if IsAnd = true)

llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp

if (match(FalseVal, m_Zero()) || match(TrueVal, m_One())) {
         replaceUse(*Y, FI);
         return replaceInstUsesWith(SI, Op1);
       }
 
       if (auto *Op1SI = dyn_cast<SelectInst>(Op1))
         if (auto *I = foldAndOrOfSelectUsingImpliedCond(CondVal, *Op1SI,
                                                         /* IsAnd */ IsAnd))
           return I;
+
+      if (auto *ICmp0 = dyn_cast<ICmpInst>(CondVal))
+        if (auto *ICmp1 = dyn_cast<ICmpInst>(Op1))
+          if (auto *V = foldAndOrOfICmpsOfAndWithPow2(ICmp0, ICmp1, &SI, IsAnd,
+                                                      /* IsLogical */ true))
+            return replaceInstUsesWith(SI, V);
     }
 
     // select (select a, true, b), c, false -> select a, c, false
     // select c, (select a, true, b), false -> select c, a, false
     //   if c implies that b is false.
     if (match(CondVal, m_Select(m_Value(A), m_One(), m_Value(B))) &&
         match(FalseVal, m_Zero())) {
       Optional<bool> Res = isImpliedCondition(TrueVal, B, DL);

llvm/test/Transforms/InstCombine/onehot_merge.ll

;
   %or = or i1 %t2, %t6
   ret i1 %or
 }
 
 define i1 @foo1_and_logical(i32 %k, i32 %c1, i32 %c2) {
 ; CHECK-LABEL: @foo1_and_logical(
 ; CHECK-NEXT:    [[T:%.*]] = shl i32 1, [[C1:%.*]]
 ; CHECK-NEXT:    [[T4:%.*]] = shl i32 1, [[C2:%.*]]
-; CHECK-NEXT:    [[T1:%.*]] = and i32 [[T]], [[K:%.*]]
-; CHECK-NEXT:    [[T2:%.*]] = icmp eq i32 [[T1]], 0
-; CHECK-NEXT:    [[T5:%.*]] = and i32 [[T4]], [[K]]
-; CHECK-NEXT:    [[T6:%.*]] = icmp eq i32 [[T5]], 0
-; CHECK-NEXT:    [[OR:%.*]] = select i1 [[T2]], i1 true, i1 [[T6]]
-; CHECK-NEXT:    ret i1 [[OR]]
+; CHECK-NEXT:    [[TMP1:%.*]] = freeze i32 [[T4]]
+; CHECK-NEXT:    [[TMP2:%.*]] = or i32 [[T]], [[TMP1]]
+; CHECK-NEXT:    [[TMP3:%.*]] = and i32 [[TMP2]], [[K:%.*]]
+; CHECK-NEXT:    [[TMP4:%.*]] = icmp ne i32 [[TMP3]], [[TMP2]]
+; CHECK-NEXT:    ret i1 [[TMP4]]
 ;
   %t = shl i32 1, %c1
   %t4 = shl i32 1, %c2
   %t1 = and i32 %t, %k
   %t2 = icmp eq i32 %t1, 0
   %t5 = and i32 %t4, %k
   %t6 = icmp eq i32 %t5, 0
   %or = select i1 %t2, i1 true, i1 %t6
;
   ret i1 %or
 }
 
 define i1 @foo1_and_commuted_logical(i32 %k, i32 %c1, i32 %c2) {
 ; CHECK-LABEL: @foo1_and_commuted_logical(
 ; CHECK-NEXT:    [[K2:%.*]] = mul i32 [[K:%.*]], [[K]]
 ; CHECK-NEXT:    [[T:%.*]] = shl i32 1, [[C1:%.*]]
 ; CHECK-NEXT:    [[T4:%.*]] = shl i32 1, [[C2:%.*]]
-; CHECK-NEXT:    [[T1:%.*]] = and i32 [[K2]], [[T]]
-; CHECK-NEXT:    [[T2:%.*]] = icmp eq i32 [[T1]], 0
-; CHECK-NEXT:    [[T5:%.*]] = and i32 [[T4]], [[K2]]
-; CHECK-NEXT:    [[T6:%.*]] = icmp eq i32 [[T5]], 0
-; CHECK-NEXT:    [[OR:%.*]] = select i1 [[T2]], i1 true, i1 [[T6]]
-; CHECK-NEXT:    ret i1 [[OR]]
+; CHECK-NEXT:    [[TMP1:%.*]] = freeze i32 [[T4]]
+; CHECK-NEXT:    [[TMP2:%.*]] = or i32 [[T]], [[TMP1]]
+; CHECK-NEXT:    [[TMP3:%.*]] = and i32 [[K2]], [[TMP2]]
+; CHECK-NEXT:    [[TMP4:%.*]] = icmp ne i32 [[TMP3]], [[TMP2]]
+; CHECK-NEXT:    ret i1 [[TMP4]]
 ;
   %k2 = mul i32 %k, %k ; to trick the complexity sorting
   %t = shl i32 1, %c1
   %t4 = shl i32 1, %c2
   %t1 = and i32 %k2, %t
   %t2 = icmp eq i32 %t1, 0
   %t5 = and i32 %t4, %k2
   %t6 = icmp eq i32 %t5, 0
;
   %or = and i1 %t2, %t6
   ret i1 %or
 }
 
 define i1 @foo1_or_logical(i32 %k, i32 %c1, i32 %c2) {
 ; CHECK-LABEL: @foo1_or_logical(
 ; CHECK-NEXT:    [[T:%.*]] = shl i32 1, [[C1:%.*]]
 ; CHECK-NEXT:    [[T4:%.*]] = shl i32 1, [[C2:%.*]]
-; CHECK-NEXT:    [[T1:%.*]] = and i32 [[T]], [[K:%.*]]
-; CHECK-NEXT:    [[T2:%.*]] = icmp ne i32 [[T1]], 0
-; CHECK-NEXT:    [[T5:%.*]] = and i32 [[T4]], [[K]]
-; CHECK-NEXT:    [[T6:%.*]] = icmp ne i32 [[T5]], 0
-; CHECK-NEXT:    [[OR:%.*]] = select i1 [[T2]], i1 [[T6]], i1 false
-; CHECK-NEXT:    ret i1 [[OR]]
+; CHECK-NEXT:    [[TMP1:%.*]] = freeze i32 [[T4]]
+; CHECK-NEXT:    [[TMP2:%.*]] = or i32 [[T]], [[TMP1]]
+; CHECK-NEXT:    [[TMP3:%.*]] = and i32 [[TMP2]], [[K:%.*]]
+; CHECK-NEXT:    [[TMP4:%.*]] = icmp eq i32 [[TMP3]], [[TMP2]]
+; CHECK-NEXT:    ret i1 [[TMP4]]
 ;
   %t = shl i32 1, %c1
   %t4 = shl i32 1, %c2
   %t1 = and i32 %t, %k
   %t2 = icmp ne i32 %t1, 0
   %t5 = and i32 %t4, %k
   %t6 = icmp ne i32 %t5, 0
   %or = select i1 %t2, i1 %t6, i1 false
;
   ret i1 %or
 }
 
 define i1 @foo1_or_commuted_logical(i32 %k, i32 %c1, i32 %c2) {
 ; CHECK-LABEL: @foo1_or_commuted_logical(
 ; CHECK-NEXT:    [[K2:%.*]] = mul i32 [[K:%.*]], [[K]]
 ; CHECK-NEXT:    [[T:%.*]] = shl i32 1, [[C1:%.*]]
 ; CHECK-NEXT:    [[T4:%.*]] = shl i32 1, [[C2:%.*]]
-; CHECK-NEXT:    [[T1:%.*]] = and i32 [[K2]], [[T]]
-; CHECK-NEXT:    [[T2:%.*]] = icmp ne i32 [[T1]], 0
-; CHECK-NEXT:    [[T5:%.*]] = and i32 [[T4]], [[K2]]
-; CHECK-NEXT:    [[T6:%.*]] = icmp ne i32 [[T5]], 0
-; CHECK-NEXT:    [[OR:%.*]] = select i1 [[T2]], i1 [[T6]], i1 false
-; CHECK-NEXT:    ret i1 [[OR]]
+; CHECK-NEXT:    [[TMP1:%.*]] = freeze i32 [[T4]]
+; CHECK-NEXT:    [[TMP2:%.*]] = or i32 [[T]], [[TMP1]]
+; CHECK-NEXT:    [[TMP3:%.*]] = and i32 [[K2]], [[TMP2]]
+; CHECK-NEXT:    [[TMP4:%.*]] = icmp eq i32 [[TMP3]], [[TMP2]]
+; CHECK-NEXT:    ret i1 [[TMP4]]
 ;
   %k2 = mul i32 %k, %k ; to trick the complexity sorting
   %t = shl i32 1, %c1
   %t4 = shl i32 1, %c2
   %t1 = and i32 %k2, %t
   %t2 = icmp ne i32 %t1, 0
   %t5 = and i32 %t4, %k2
   %t6 = icmp ne i32 %t5, 0
;
   %or = or i1 %t2, %t6
   ret i1 %or
 }
 
 define i1 @foo1_and_signbit_lshr_logical(i32 %k, i32 %c1, i32 %c2) {
 ; CHECK-LABEL: @foo1_and_signbit_lshr_logical(
 ; CHECK-NEXT:    [[T:%.*]] = shl i32 1, [[C1:%.*]]
 ; CHECK-NEXT:    [[T4:%.*]] = lshr i32 -2147483648, [[C2:%.*]]
-; CHECK-NEXT:    [[T1:%.*]] = and i32 [[T]], [[K:%.*]]
-; CHECK-NEXT:    [[T2:%.*]] = icmp eq i32 [[T1]], 0
-; CHECK-NEXT:    [[T5:%.*]] = and i32 [[T4]], [[K]]
-; CHECK-NEXT:    [[T6:%.*]] = icmp eq i32 [[T5]], 0
-; CHECK-NEXT:    [[OR:%.*]] = select i1 [[T2]], i1 true, i1 [[T6]]
-; CHECK-NEXT:    ret i1 [[OR]]
+; CHECK-NEXT:    [[TMP1:%.*]] = freeze i32 [[T4]]
+; CHECK-NEXT:    [[TMP2:%.*]] = or i32 [[T]], [[TMP1]]
+; CHECK-NEXT:    [[TMP3:%.*]] = and i32 [[TMP2]], [[K:%.*]]
+; CHECK-NEXT:    [[TMP4:%.*]] = icmp ne i32 [[TMP3]], [[TMP2]]
+; CHECK-NEXT:    ret i1 [[TMP4]]
 ;
   %t = shl i32 1, %c1
   %t4 = lshr i32 -2147483648, %c2
   %t1 = and i32 %t, %k
   %t2 = icmp eq i32 %t1, 0
   %t5 = and i32 %t4, %k
   %t6 = icmp eq i32 %t5, 0
   %or = select i1 %t2, i1 true, i1 %t6
;
   %or = and i1 %t2, %t6
   ret i1 %or
 }
 
 define i1 @foo1_or_signbit_lshr_logical(i32 %k, i32 %c1, i32 %c2) {
 ; CHECK-LABEL: @foo1_or_signbit_lshr_logical(
 ; CHECK-NEXT:    [[T:%.*]] = shl i32 1, [[C1:%.*]]
 ; CHECK-NEXT:    [[T4:%.*]] = lshr i32 -2147483648, [[C2:%.*]]
-; CHECK-NEXT:    [[T1:%.*]] = and i32 [[T]], [[K:%.*]]
-; CHECK-NEXT:    [[T2:%.*]] = icmp ne i32 [[T1]], 0
-; CHECK-NEXT:    [[T5:%.*]] = and i32 [[T4]], [[K]]
-; CHECK-NEXT:    [[T6:%.*]] = icmp ne i32 [[T5]], 0
-; CHECK-NEXT:    [[OR:%.*]] = select i1 [[T2]], i1 [[T6]], i1 false
-; CHECK-NEXT:    ret i1 [[OR]]
+; CHECK-NEXT:    [[TMP1:%.*]] = freeze i32 [[T4]]
+; CHECK-NEXT:    [[TMP2:%.*]] = or i32 [[T]], [[TMP1]]
+; CHECK-NEXT:    [[TMP3:%.*]] = and i32 [[TMP2]], [[K:%.*]]
+; CHECK-NEXT:    [[TMP4:%.*]] = icmp eq i32 [[TMP3]], [[TMP2]]
+; CHECK-NEXT:    ret i1 [[TMP4]]
 ;
   %t = shl i32 1, %c1
   %t4 = lshr i32 -2147483648, %c2
   %t1 = and i32 %t, %k
   %t2 = icmp ne i32 %t1, 0
   %t5 = and i32 %t4, %k
   %t6 = icmp ne i32 %t5, 0
   %or = select i1 %t2, i1 %t6, i1 false
;
   ret i1 %or
 }
 
 define i1 @foo1_and_extra_use_shl_logical(i32 %k, i32 %c1, i32 %c2, i32* %p) {
 ; CHECK-LABEL: @foo1_and_extra_use_shl_logical(
 ; CHECK-NEXT:    [[T0:%.*]] = shl i32 1, [[C1:%.*]]
 ; CHECK-NEXT:    store i32 [[T0]], i32* [[P:%.*]], align 4
 ; CHECK-NEXT:    [[T1:%.*]] = shl i32 1, [[C2:%.*]]
-; CHECK-NEXT:    [[T2:%.*]] = and i32 [[T0]], [[K:%.*]]
-; CHECK-NEXT:    [[T3:%.*]] = icmp eq i32 [[T2]], 0
-; CHECK-NEXT:    [[T4:%.*]] = and i32 [[T1]], [[K]]
-; CHECK-NEXT:    [[T5:%.*]] = icmp eq i32 [[T4]], 0
-; CHECK-NEXT:    [[OR:%.*]] = select i1 [[T3]], i1 true, i1 [[T5]]
-; CHECK-NEXT:    ret i1 [[OR]]
+; CHECK-NEXT:    [[TMP1:%.*]] = freeze i32 [[T1]]
+; CHECK-NEXT:    [[TMP2:%.*]] = or i32 [[T0]], [[TMP1]]
+; CHECK-NEXT:    [[TMP3:%.*]] = and i32 [[TMP2]], [[K:%.*]]
+; CHECK-NEXT:    [[TMP4:%.*]] = icmp ne i32 [[TMP3]], [[TMP2]]
+; CHECK-NEXT:    ret i1 [[TMP4]]
 ;
   %t0 = shl i32 1, %c1
   store i32 %t0, i32* %p  ; extra use of shl
   %t1 = shl i32 1, %c2
   %t2 = and i32 %t0, %k
   %t3 = icmp eq i32 %t2, 0
   %t4 = and i32 %t1, %k
   %t5 = icmp eq i32 %t4, 0

 }
 
 define i1 @foo1_and_extra_use_and_logical(i32 %k, i32 %c1, i32 %c2, i32* %p) {
 ; CHECK-LABEL: @foo1_and_extra_use_and_logical(
 ; CHECK-NEXT:    [[T0:%.*]] = shl i32 1, [[C1:%.*]]
 ; CHECK-NEXT:    [[T1:%.*]] = shl i32 1, [[C2:%.*]]
 ; CHECK-NEXT:    [[T2:%.*]] = and i32 [[T0]], [[K:%.*]]
 ; CHECK-NEXT:    store i32 [[T2]], i32* [[P:%.*]], align 4
-; CHECK-NEXT:    [[T3:%.*]] = icmp eq i32 [[T2]], 0
-; CHECK-NEXT:    [[T4:%.*]] = and i32 [[T1]], [[K]]
-; CHECK-NEXT:    [[T5:%.*]] = icmp eq i32 [[T4]], 0
-; CHECK-NEXT:    [[OR:%.*]] = select i1 [[T3]], i1 true, i1 [[T5]]
-; CHECK-NEXT:    ret i1 [[OR]]
+; CHECK-NEXT:    [[TMP1:%.*]] = freeze i32 [[T1]]
+; CHECK-NEXT:    [[TMP2:%.*]] = or i32 [[T0]], [[TMP1]]
+; CHECK-NEXT:    [[TMP3:%.*]] = and i32 [[TMP2]], [[K]]
+; CHECK-NEXT:    [[TMP4:%.*]] = icmp ne i32 [[TMP3]], [[TMP2]]
+; CHECK-NEXT:    ret i1 [[TMP4]]
 ;
   %t0 = shl i32 1, %c1
   %t1 = shl i32 1, %c2
   %t2 = and i32 %t0, %k
   store i32 %t2, i32* %p  ; extra use of and
   %t3 = icmp eq i32 %t2, 0
   %t4 = and i32 %t1, %k
   %t5 = icmp eq i32 %t4, 0

 
 define i1 @foo1_and_extra_use_cmp_logical(i32 %k, i32 %c1, i32 %c2, i1* %p) {
 ; CHECK-LABEL: @foo1_and_extra_use_cmp_logical(
 ; CHECK-NEXT:    [[T0:%.*]] = shl i32 1, [[C1:%.*]]
 ; CHECK-NEXT:    [[T1:%.*]] = shl i32 1, [[C2:%.*]]
 ; CHECK-NEXT:    [[T2:%.*]] = and i32 [[T0]], [[K:%.*]]
 ; CHECK-NEXT:    [[T3:%.*]] = icmp eq i32 [[T2]], 0
 ; CHECK-NEXT:    store i1 [[T3]], i1* [[P:%.*]], align 1
-; CHECK-NEXT:    [[T4:%.*]] = and i32 [[T1]], [[K]]
-; CHECK-NEXT:    [[T5:%.*]] = icmp eq i32 [[T4]], 0
-; CHECK-NEXT:    [[OR:%.*]] = select i1 [[T3]], i1 true, i1 [[T5]]
-; CHECK-NEXT:    ret i1 [[OR]]
+; CHECK-NEXT:    [[TMP1:%.*]] = freeze i32 [[T1]]
+; CHECK-NEXT:    [[TMP2:%.*]] = or i32 [[T0]], [[TMP1]]
+; CHECK-NEXT:    [[TMP3:%.*]] = and i32 [[TMP2]], [[K]]
+; CHECK-NEXT:    [[TMP4:%.*]] = icmp ne i32 [[TMP3]], [[TMP2]]
+; CHECK-NEXT:    ret i1 [[TMP4]]
 ;
   %t0 = shl i32 1, %c1
   %t1 = shl i32 1, %c2
   %t2 = and i32 %t0, %k
   %t3 = icmp eq i32 %t2, 0
   store i1 %t3, i1* %p  ; extra use of cmp
   %t4 = and i32 %t1, %k
   %t5 = icmp eq i32 %t4, 0
;
   ret i1 %or
 }
 
 define i1 @foo1_and_extra_use_shl2_logical(i32 %k, i32 %c1, i32 %c2, i32* %p) {
 ; CHECK-LABEL: @foo1_and_extra_use_shl2_logical(
 ; CHECK-NEXT:    [[T0:%.*]] = shl i32 1, [[C1:%.*]]
 ; CHECK-NEXT:    [[T1:%.*]] = shl i32 1, [[C2:%.*]]
 ; CHECK-NEXT:    store i32 [[T1]], i32* [[P:%.*]], align 4
-; CHECK-NEXT:    [[T2:%.*]] = and i32 [[T0]], [[K:%.*]]
-; CHECK-NEXT:    [[T3:%.*]] = icmp eq i32 [[T2]], 0
-; CHECK-NEXT:    [[T4:%.*]] = and i32 [[T1]], [[K]]
-; CHECK-NEXT:    [[T5:%.*]] = icmp eq i32 [[T4]], 0
-; CHECK-NEXT:    [[OR:%.*]] = select i1 [[T3]], i1 true, i1 [[T5]]
-; CHECK-NEXT:    ret i1 [[OR]]
+; CHECK-NEXT:    [[TMP1:%.*]] = freeze i32 [[T1]]
+; CHECK-NEXT:    [[TMP2:%.*]] = or i32 [[T0]], [[TMP1]]
+; CHECK-NEXT:    [[TMP3:%.*]] = and i32 [[TMP2]], [[K:%.*]]
+; CHECK-NEXT:    [[TMP4:%.*]] = icmp ne i32 [[TMP3]], [[TMP2]]
+; CHECK-NEXT:    ret i1 [[TMP4]]
 ;
   %t0 = shl i32 1, %c1
   %t1 = shl i32 1, %c2
   store i32 %t1, i32* %p  ; extra use of shl
   %t2 = and i32 %t0, %k
   %t3 = icmp eq i32 %t2, 0
   %t4 = and i32 %t1, %k
   %t5 = icmp eq i32 %t4, 0
;
   %or = or i1 %t3, %t5
   ret i1 %or
 }
 
 define i1 @foo1_and_extra_use_and2_logical(i32 %k, i32 %c1, i32 %c2, i32* %p) {
 ; CHECK-LABEL: @foo1_and_extra_use_and2_logical(
 ; CHECK-NEXT:    [[T0:%.*]] = shl i32 1, [[C1:%.*]]
 ; CHECK-NEXT:    [[T1:%.*]] = shl i32 1, [[C2:%.*]]
-; CHECK-NEXT:    [[T2:%.*]] = and i32 [[T0]], [[K:%.*]]
-; CHECK-NEXT:    [[T3:%.*]] = icmp eq i32 [[T2]], 0
-; CHECK-NEXT:    [[T4:%.*]] = and i32 [[T1]], [[K]]
+; CHECK-NEXT:    [[T4:%.*]] = and i32 [[T1]], [[K:%.*]]
 ; CHECK-NEXT:    store i32 [[T4]], i32* [[P:%.*]], align 4
-; CHECK-NEXT:    [[T5:%.*]] = icmp eq i32 [[T4]], 0
-; CHECK-NEXT:    [[OR:%.*]] = select i1 [[T3]], i1 true, i1 [[T5]]
-; CHECK-NEXT:    ret i1 [[OR]]
+; CHECK-NEXT:    [[TMP1:%.*]] = freeze i32 [[T1]]
+; CHECK-NEXT:    [[TMP2:%.*]] = or i32 [[T0]], [[TMP1]]
+; CHECK-NEXT:    [[TMP3:%.*]] = and i32 [[TMP2]], [[K]]
+; CHECK-NEXT:    [[TMP4:%.*]] = icmp ne i32 [[TMP3]], [[TMP2]]
+; CHECK-NEXT:    ret i1 [[TMP4]]
 ;
   %t0 = shl i32 1, %c1
   %t1 = shl i32 1, %c2
   %t2 = and i32 %t0, %k
   %t3 = icmp eq i32 %t2, 0
   %t4 = and i32 %t1, %k
   store i32 %t4, i32* %p  ; extra use of and
   %t5 = icmp eq i32 %t4, 0
;
   %or = or i1 %t3, %t5
   ret i1 %or
 }
 
 define i1 @foo1_and_extra_use_cmp2_logical(i32 %k, i32 %c1, i32 %c2, i1* %p) {
 ; CHECK-LABEL: @foo1_and_extra_use_cmp2_logical(
 ; CHECK-NEXT:    [[T0:%.*]] = shl i32 1, [[C1:%.*]]
 ; CHECK-NEXT:    [[T1:%.*]] = shl i32 1, [[C2:%.*]]
-; CHECK-NEXT:    [[T2:%.*]] = and i32 [[T0]], [[K:%.*]]
-; CHECK-NEXT:    [[T3:%.*]] = icmp eq i32 [[T2]], 0
-; CHECK-NEXT:    [[T4:%.*]] = and i32 [[T1]], [[K]]
+; CHECK-NEXT:    [[T4:%.*]] = and i32 [[T1]], [[K:%.*]]
 ; CHECK-NEXT:    [[T5:%.*]] = icmp eq i32 [[T4]], 0
 ; CHECK-NEXT:    store i1 [[T5]], i1* [[P:%.*]], align 1
-; CHECK-NEXT:    [[OR:%.*]] = select i1 [[T3]], i1 true, i1 [[T5]]
-; CHECK-NEXT:    ret i1 [[OR]]
+; CHECK-NEXT:    [[TMP1:%.*]] = freeze i32 [[T1]]
+; CHECK-NEXT:    [[TMP2:%.*]] = or i32 [[T0]], [[TMP1]]
+; CHECK-NEXT:    [[TMP3:%.*]] = and i32 [[TMP2]], [[K]]
+; CHECK-NEXT:    [[TMP4:%.*]] = icmp ne i32 [[TMP3]], [[TMP2]]
+; CHECK-NEXT:    ret i1 [[TMP4]]
 ;
   %t0 = shl i32 1, %c1
   %t1 = shl i32 1, %c2
   %t2 = and i32 %t0, %k
   %t3 = icmp eq i32 %t2, 0
   %t4 = and i32 %t1, %k
   %t5 = icmp eq i32 %t4, 0
   store i1 %t5, i1* %p  ; extra use of cmp